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authorAuke Kok <auke-jan.h.kok@intel.com>2006-06-27 12:08:03 -0400
committerAuke Kok <juke-jan.h.kok@intel.com>2006-06-27 12:08:03 -0400
commitee04022a21764a12e29eee144b72344ebfe0a55c (patch)
tree88744e14d2df93fe287abc39b0d4446ae159a7ae /drivers/net/e1000
parentf1b3a85354d3877fae45ef448e7e49c2efd692d5 (diff)
e1000: M88 PHY workaround
M88 rev 2 PHY needs a longer downshift to function properly. This adds a much longer downshift counter for this specific device. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/e1000_hw.c46
-rw-r--r--drivers/net/e1000/e1000_hw.h11
2 files changed, 40 insertions, 17 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 1c5b18478fb2..37eb351b4c9b 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -1565,28 +1565,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1565 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1565 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1566 if(hw->disable_polarity_correction == 1) 1566 if(hw->disable_polarity_correction == 1)
1567 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1567 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1568 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1568 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1569 if(ret_val) 1569 if (ret_val)
1570 return ret_val;
1571
1572 /* Force TX_CLK in the Extended PHY Specific Control Register
1573 * to 25MHz clock.
1574 */
1575 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1576 if(ret_val)
1577 return ret_val; 1570 return ret_val;
1578 1571
1579 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1580
1581 if (hw->phy_revision < M88E1011_I_REV_4) { 1572 if (hw->phy_revision < M88E1011_I_REV_4) {
1582 /* Configure Master and Slave downshift values */ 1573 /* Force TX_CLK in the Extended PHY Specific Control Register
1583 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1574 * to 25MHz clock.
1575 */
1576 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1577 if (ret_val)
1578 return ret_val;
1579
1580 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1581
1582 if ((hw->phy_revision == E1000_REVISION_2) &&
1583 (hw->phy_id == M88E1111_I_PHY_ID)) {
1584 /* Vidalia Phy, set the downshift counter to 5x */
1585 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1586 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1587 ret_val = e1000_write_phy_reg(hw,
1588 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1589 if (ret_val)
1590 return ret_val;
1591 } else {
1592 /* Configure Master and Slave downshift values */
1593 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1584 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1594 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1585 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1595 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1586 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1596 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1587 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1597 ret_val = e1000_write_phy_reg(hw,
1588 if(ret_val) 1598 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1589 return ret_val; 1599 if (ret_val)
1600 return ret_val;
1601 }
1590 } 1602 }
1591 1603
1592 /* SW Reset the PHY so all changes take effect */ 1604 /* SW Reset the PHY so all changes take effect */
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 941b47d61674..1908e0d3110c 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -2765,6 +2765,17 @@ struct e1000_host_command_info {
2765#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2765#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2766#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2766#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2767 2767
2768/* M88EC018 Rev 2 specific DownShift settings */
2769#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2770#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2771#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2772#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2773#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2774#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2775#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2776#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2777#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2778
2768/* IGP01E1000 Specific Port Config Register - R/W */ 2779/* IGP01E1000 Specific Port Config Register - R/W */
2769#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2780#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2770#define IGP01E1000_PSCFR_PRE_EN 0x0020 2781#define IGP01E1000_PSCFR_PRE_EN 0x0020