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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/e1000
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/LICENSE339
-rw-r--r--drivers/net/e1000/Makefile35
-rw-r--r--drivers/net/e1000/e1000.h261
-rw-r--r--drivers/net/e1000/e1000_ethtool.c1673
-rw-r--r--drivers/net/e1000/e1000_hw.c5405
-rw-r--r--drivers/net/e1000/e1000_hw.h2144
-rw-r--r--drivers/net/e1000/e1000_main.c3162
-rw-r--r--drivers/net/e1000/e1000_osdep.h101
-rw-r--r--drivers/net/e1000/e1000_param.c744
9 files changed, 13864 insertions, 0 deletions
diff --git a/drivers/net/e1000/LICENSE b/drivers/net/e1000/LICENSE
new file mode 100644
index 000000000000..5f297e5bb465
--- /dev/null
+++ b/drivers/net/e1000/LICENSE
@@ -0,0 +1,339 @@
1
2"This software program is licensed subject to the GNU General Public License
3(GPL). Version 2, June 1991, available at
4<http://www.fsf.org/copyleft/gpl.html>"
5
6GNU General Public License
7
8Version 2, June 1991
9
10Copyright (C) 1989, 1991 Free Software Foundation, Inc.
1159 Temple Place - Suite 330, Boston, MA 02111-1307, USA
12
13Everyone is permitted to copy and distribute verbatim copies of this license
14document, but changing it is not allowed.
15
16Preamble
17
18The licenses for most software are designed to take away your freedom to
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64TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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660. This License applies to any program or other work which contains a notice
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258 NO WARRANTY
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26011. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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277 THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR
278 OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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280END OF TERMS AND CONDITIONS
281
282How to Apply These Terms to Your New Programs
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284If you develop a new program, and you want it to be of the greatest
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288To do so, attach the following notices to the program. It is safest to
289attach them to the start of each source file to most effectively convey the
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291line and a pointer to where the full notice is found.
292
293one line to give the program's name and an idea of what it does.
294Copyright (C) yyyy name of author
295
296This program is free software; you can redistribute it and/or modify it
297under the terms of the GNU General Public License as published by the Free
298Software Foundation; either version 2 of the License, or (at your option)
299any later version.
300
301This program is distributed in the hope that it will be useful, but WITHOUT
302ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
303FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
304more details.
305
306You should have received a copy of the GNU General Public License along with
307this program; if not, write to the Free Software Foundation, Inc., 59
308Temple Place - Suite 330, Boston, MA 02111-1307, USA.
309
310Also add information on how to contact you by electronic and paper mail.
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312If the program is interactive, make it output a short notice like this when
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315Gnomovision version 69, Copyright (C) year name of author Gnomovision comes
316with ABSOLUTELY NO WARRANTY; for details type 'show w'. This is free
317software, and you are welcome to redistribute it under certain conditions;
318type 'show c' for details.
319
320The hypothetical commands 'show w' and 'show c' should show the appropriate
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323mouse-clicks or menu items--whatever suits your program.
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325You should also get your employer (if you work as a programmer) or your
326school, if any, to sign a "copyright disclaimer" for the program, if
327necessary. Here is a sample; alter the names:
328
329Yoyodyne, Inc., hereby disclaims all copyright interest in the program
330'Gnomovision' (which makes passes at compilers) written by James Hacker.
331
332signature of Ty Coon, 1 April 1989
333Ty Coon, President of Vice
334
335This General Public License does not permit incorporating your program into
336proprietary programs. If your program is a subroutine library, you may
337consider it more useful to permit linking proprietary applications with the
338library. If this is what you want to do, use the GNU Library General Public
339License instead of this License.
diff --git a/drivers/net/e1000/Makefile b/drivers/net/e1000/Makefile
new file mode 100644
index 000000000000..ca9f89552da3
--- /dev/null
+++ b/drivers/net/e1000/Makefile
@@ -0,0 +1,35 @@
1################################################################################
2#
3#
4# Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms of the GNU General Public License as published by the Free
8# Software Foundation; either version 2 of the License, or (at your option)
9# any later version.
10#
11# This program is distributed in the hope that it will be useful, but WITHOUT
12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14# more details.
15#
16# You should have received a copy of the GNU General Public License along with
17# this program; if not, write to the Free Software Foundation, Inc., 59
18# Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19#
20# The full GNU General Public License is included in this distribution in the
21# file called LICENSE.
22#
23# Contact Information:
24# Linux NICS <linux.nics@intel.com>
25# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26#
27################################################################################
28
29#
30# Makefile for the Intel(R) PRO/1000 ethernet driver
31#
32
33obj-$(CONFIG_E1000) += e1000.o
34
35e1000-objs := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
new file mode 100644
index 000000000000..148930d4e9bd
--- /dev/null
+++ b/drivers/net/e1000/e1000.h
@@ -0,0 +1,261 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29
30/* Linux PRO/1000 Ethernet Driver main header file */
31
32#ifndef _E1000_H_
33#define _E1000_H_
34
35#include <linux/stddef.h>
36#include <linux/config.h>
37#include <linux/module.h>
38#include <linux/types.h>
39#include <asm/byteorder.h>
40#include <linux/init.h>
41#include <linux/mm.h>
42#include <linux/errno.h>
43#include <linux/ioport.h>
44#include <linux/pci.h>
45#include <linux/kernel.h>
46#include <linux/netdevice.h>
47#include <linux/etherdevice.h>
48#include <linux/skbuff.h>
49#include <linux/delay.h>
50#include <linux/timer.h>
51#include <linux/slab.h>
52#include <linux/vmalloc.h>
53#include <linux/interrupt.h>
54#include <linux/string.h>
55#include <linux/pagemap.h>
56#include <linux/dma-mapping.h>
57#include <linux/bitops.h>
58#include <asm/io.h>
59#include <asm/irq.h>
60#include <linux/capability.h>
61#include <linux/in.h>
62#include <linux/ip.h>
63#include <linux/tcp.h>
64#include <linux/udp.h>
65#include <net/pkt_sched.h>
66#include <linux/list.h>
67#include <linux/reboot.h>
68#ifdef NETIF_F_TSO
69#include <net/checksum.h>
70#endif
71#include <linux/workqueue.h>
72#include <linux/mii.h>
73#include <linux/ethtool.h>
74#include <linux/if_vlan.h>
75
76#define BAR_0 0
77#define BAR_1 1
78#define BAR_5 5
79
80#define INTEL_E1000_ETHERNET_DEVICE(device_id) {\
81 PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
82
83struct e1000_adapter;
84
85#include "e1000_hw.h"
86
87#ifdef DBG
88#define E1000_DBG(args...) printk(KERN_DEBUG "e1000: " args)
89#else
90#define E1000_DBG(args...)
91#endif
92
93#define E1000_ERR(args...) printk(KERN_ERR "e1000: " args)
94
95#define PFX "e1000: "
96#define DPRINTK(nlevel, klevel, fmt, args...) \
97 (void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
98 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
99 __FUNCTION__ , ## args))
100
101#define E1000_MAX_INTR 10
102
103/* TX/RX descriptor defines */
104#define E1000_DEFAULT_TXD 256
105#define E1000_MAX_TXD 256
106#define E1000_MIN_TXD 80
107#define E1000_MAX_82544_TXD 4096
108
109#define E1000_DEFAULT_RXD 256
110#define E1000_MAX_RXD 256
111#define E1000_MIN_RXD 80
112#define E1000_MAX_82544_RXD 4096
113
114/* Supported Rx Buffer Sizes */
115#define E1000_RXBUFFER_2048 2048
116#define E1000_RXBUFFER_4096 4096
117#define E1000_RXBUFFER_8192 8192
118#define E1000_RXBUFFER_16384 16384
119
120/* SmartSpeed delimiters */
121#define E1000_SMARTSPEED_DOWNSHIFT 3
122#define E1000_SMARTSPEED_MAX 15
123
124/* Packet Buffer allocations */
125#define E1000_PBA_BYTES_SHIFT 0xA
126#define E1000_TX_HEAD_ADDR_SHIFT 7
127#define E1000_PBA_TX_MASK 0xFFFF0000
128
129/* Flow Control Watermarks */
130#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
131#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
132
133#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
134
135/* How many Tx Descriptors do we need to call netif_wake_queue ? */
136#define E1000_TX_QUEUE_WAKE 16
137/* How many Rx Buffers do we bundle into one write to the hardware ? */
138#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
139
140#define AUTO_ALL_MODES 0
141#define E1000_EEPROM_82544_APM 0x0004
142#define E1000_EEPROM_APME 0x0400
143
144#ifndef E1000_MASTER_SLAVE
145/* Switch to override PHY master/slave setting */
146#define E1000_MASTER_SLAVE e1000_ms_hw_default
147#endif
148
149/* only works for sizes that are powers of 2 */
150#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
151
152/* wrapper around a pointer to a socket buffer,
153 * so a DMA handle can be stored along with the buffer */
154struct e1000_buffer {
155 struct sk_buff *skb;
156 uint64_t dma;
157 unsigned long time_stamp;
158 uint16_t length;
159 uint16_t next_to_watch;
160};
161
162struct e1000_desc_ring {
163 /* pointer to the descriptor ring memory */
164 void *desc;
165 /* physical address of the descriptor ring */
166 dma_addr_t dma;
167 /* length of descriptor ring in bytes */
168 unsigned int size;
169 /* number of descriptors in the ring */
170 unsigned int count;
171 /* next descriptor to associate a buffer with */
172 unsigned int next_to_use;
173 /* next descriptor to check for DD status bit */
174 unsigned int next_to_clean;
175 /* array of buffer information structs */
176 struct e1000_buffer *buffer_info;
177};
178
179#define E1000_DESC_UNUSED(R) \
180 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
181 (R)->next_to_clean - (R)->next_to_use - 1)
182
183#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
184#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
185#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
186#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
187
188/* board specific private data structure */
189
190struct e1000_adapter {
191 struct timer_list tx_fifo_stall_timer;
192 struct timer_list watchdog_timer;
193 struct timer_list phy_info_timer;
194 struct vlan_group *vlgrp;
195 uint32_t bd_number;
196 uint32_t rx_buffer_len;
197 uint32_t part_num;
198 uint32_t wol;
199 uint32_t smartspeed;
200 uint32_t en_mng_pt;
201 uint16_t link_speed;
202 uint16_t link_duplex;
203 spinlock_t stats_lock;
204 atomic_t irq_sem;
205 struct work_struct tx_timeout_task;
206 struct work_struct watchdog_task;
207 uint8_t fc_autoneg;
208
209 struct timer_list blink_timer;
210 unsigned long led_status;
211
212 /* TX */
213 struct e1000_desc_ring tx_ring;
214 struct e1000_buffer previous_buffer_info;
215 spinlock_t tx_lock;
216 uint32_t txd_cmd;
217 uint32_t tx_int_delay;
218 uint32_t tx_abs_int_delay;
219 uint32_t gotcl;
220 uint64_t gotcl_old;
221 uint64_t tpt_old;
222 uint64_t colc_old;
223 uint32_t tx_fifo_head;
224 uint32_t tx_head_addr;
225 uint32_t tx_fifo_size;
226 atomic_t tx_fifo_stall;
227 boolean_t pcix_82544;
228 boolean_t detect_tx_hung;
229
230 /* RX */
231 struct e1000_desc_ring rx_ring;
232 uint64_t hw_csum_err;
233 uint64_t hw_csum_good;
234 uint32_t rx_int_delay;
235 uint32_t rx_abs_int_delay;
236 boolean_t rx_csum;
237 uint32_t gorcl;
238 uint64_t gorcl_old;
239
240 /* Interrupt Throttle Rate */
241 uint32_t itr;
242
243 /* OS defined structs */
244 struct net_device *netdev;
245 struct pci_dev *pdev;
246 struct net_device_stats net_stats;
247
248 /* structs defined in e1000_hw.h */
249 struct e1000_hw hw;
250 struct e1000_hw_stats stats;
251 struct e1000_phy_info phy_info;
252 struct e1000_phy_stats phy_stats;
253
254 uint32_t test_icr;
255 struct e1000_desc_ring test_tx_ring;
256 struct e1000_desc_ring test_rx_ring;
257
258
259 int msg_enable;
260};
261#endif /* _E1000_H_ */
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
new file mode 100644
index 000000000000..0a2ca7c73a41
--- /dev/null
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -0,0 +1,1673 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for e1000 */
30
31#include "e1000.h"
32
33#include <asm/uaccess.h>
34
35extern char e1000_driver_name[];
36extern char e1000_driver_version[];
37
38extern int e1000_up(struct e1000_adapter *adapter);
39extern void e1000_down(struct e1000_adapter *adapter);
40extern void e1000_reset(struct e1000_adapter *adapter);
41extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
42extern int e1000_setup_rx_resources(struct e1000_adapter *adapter);
43extern int e1000_setup_tx_resources(struct e1000_adapter *adapter);
44extern void e1000_free_rx_resources(struct e1000_adapter *adapter);
45extern void e1000_free_tx_resources(struct e1000_adapter *adapter);
46extern void e1000_update_stats(struct e1000_adapter *adapter);
47
48struct e1000_stats {
49 char stat_string[ETH_GSTRING_LEN];
50 int sizeof_stat;
51 int stat_offset;
52};
53
54#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
55 offsetof(struct e1000_adapter, m)
56static const struct e1000_stats e1000_gstrings_stats[] = {
57 { "rx_packets", E1000_STAT(net_stats.rx_packets) },
58 { "tx_packets", E1000_STAT(net_stats.tx_packets) },
59 { "rx_bytes", E1000_STAT(net_stats.rx_bytes) },
60 { "tx_bytes", E1000_STAT(net_stats.tx_bytes) },
61 { "rx_errors", E1000_STAT(net_stats.rx_errors) },
62 { "tx_errors", E1000_STAT(net_stats.tx_errors) },
63 { "rx_dropped", E1000_STAT(net_stats.rx_dropped) },
64 { "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
65 { "multicast", E1000_STAT(net_stats.multicast) },
66 { "collisions", E1000_STAT(net_stats.collisions) },
67 { "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
68 { "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
69 { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) },
70 { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
71 { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) },
72 { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) },
73 { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) },
74 { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) },
75 { "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
76 { "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
77 { "tx_window_errors", E1000_STAT(net_stats.tx_window_errors) },
78 { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
79 { "tx_deferred_ok", E1000_STAT(stats.dc) },
80 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
81 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
82 { "rx_long_length_errors", E1000_STAT(stats.roc) },
83 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
84 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
85 { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
86 { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
87 { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
88 { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
89 { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
90 { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
91 { "rx_long_byte_count", E1000_STAT(stats.gorcl) },
92 { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
93 { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }
94};
95#define E1000_STATS_LEN \
96 sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
97static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
98 "Register test (offline)", "Eeprom test (offline)",
99 "Interrupt test (offline)", "Loopback test (offline)",
100 "Link test (on/offline)"
101};
102#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN
103
104static int
105e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
106{
107 struct e1000_adapter *adapter = netdev->priv;
108 struct e1000_hw *hw = &adapter->hw;
109
110 if(hw->media_type == e1000_media_type_copper) {
111
112 ecmd->supported = (SUPPORTED_10baseT_Half |
113 SUPPORTED_10baseT_Full |
114 SUPPORTED_100baseT_Half |
115 SUPPORTED_100baseT_Full |
116 SUPPORTED_1000baseT_Full|
117 SUPPORTED_Autoneg |
118 SUPPORTED_TP);
119
120 ecmd->advertising = ADVERTISED_TP;
121
122 if(hw->autoneg == 1) {
123 ecmd->advertising |= ADVERTISED_Autoneg;
124
125 /* the e1000 autoneg seems to match ethtool nicely */
126
127 ecmd->advertising |= hw->autoneg_advertised;
128 }
129
130 ecmd->port = PORT_TP;
131 ecmd->phy_address = hw->phy_addr;
132
133 if(hw->mac_type == e1000_82543)
134 ecmd->transceiver = XCVR_EXTERNAL;
135 else
136 ecmd->transceiver = XCVR_INTERNAL;
137
138 } else {
139 ecmd->supported = (SUPPORTED_1000baseT_Full |
140 SUPPORTED_FIBRE |
141 SUPPORTED_Autoneg);
142
143 ecmd->advertising = (SUPPORTED_1000baseT_Full |
144 SUPPORTED_FIBRE |
145 SUPPORTED_Autoneg);
146
147 ecmd->port = PORT_FIBRE;
148
149 if(hw->mac_type >= e1000_82545)
150 ecmd->transceiver = XCVR_INTERNAL;
151 else
152 ecmd->transceiver = XCVR_EXTERNAL;
153 }
154
155 if(netif_carrier_ok(adapter->netdev)) {
156
157 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
158 &adapter->link_duplex);
159 ecmd->speed = adapter->link_speed;
160
161 /* unfortunatly FULL_DUPLEX != DUPLEX_FULL
162 * and HALF_DUPLEX != DUPLEX_HALF */
163
164 if(adapter->link_duplex == FULL_DUPLEX)
165 ecmd->duplex = DUPLEX_FULL;
166 else
167 ecmd->duplex = DUPLEX_HALF;
168 } else {
169 ecmd->speed = -1;
170 ecmd->duplex = -1;
171 }
172
173 ecmd->autoneg = ((hw->media_type == e1000_media_type_fiber) ||
174 hw->autoneg) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
175 return 0;
176}
177
178static int
179e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
180{
181 struct e1000_adapter *adapter = netdev->priv;
182 struct e1000_hw *hw = &adapter->hw;
183
184 if(ecmd->autoneg == AUTONEG_ENABLE) {
185 hw->autoneg = 1;
186 hw->autoneg_advertised = 0x002F;
187 ecmd->advertising = 0x002F;
188 } else
189 if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex))
190 return -EINVAL;
191
192 /* reset the link */
193
194 if(netif_running(adapter->netdev)) {
195 e1000_down(adapter);
196 e1000_reset(adapter);
197 e1000_up(adapter);
198 } else
199 e1000_reset(adapter);
200
201 return 0;
202}
203
204static void
205e1000_get_pauseparam(struct net_device *netdev,
206 struct ethtool_pauseparam *pause)
207{
208 struct e1000_adapter *adapter = netdev->priv;
209 struct e1000_hw *hw = &adapter->hw;
210
211 pause->autoneg =
212 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
213
214 if(hw->fc == e1000_fc_rx_pause)
215 pause->rx_pause = 1;
216 else if(hw->fc == e1000_fc_tx_pause)
217 pause->tx_pause = 1;
218 else if(hw->fc == e1000_fc_full) {
219 pause->rx_pause = 1;
220 pause->tx_pause = 1;
221 }
222}
223
224static int
225e1000_set_pauseparam(struct net_device *netdev,
226 struct ethtool_pauseparam *pause)
227{
228 struct e1000_adapter *adapter = netdev->priv;
229 struct e1000_hw *hw = &adapter->hw;
230
231 adapter->fc_autoneg = pause->autoneg;
232
233 if(pause->rx_pause && pause->tx_pause)
234 hw->fc = e1000_fc_full;
235 else if(pause->rx_pause && !pause->tx_pause)
236 hw->fc = e1000_fc_rx_pause;
237 else if(!pause->rx_pause && pause->tx_pause)
238 hw->fc = e1000_fc_tx_pause;
239 else if(!pause->rx_pause && !pause->tx_pause)
240 hw->fc = e1000_fc_none;
241
242 hw->original_fc = hw->fc;
243
244 if(adapter->fc_autoneg == AUTONEG_ENABLE) {
245 if(netif_running(adapter->netdev)) {
246 e1000_down(adapter);
247 e1000_up(adapter);
248 } else
249 e1000_reset(adapter);
250 }
251 else
252 return ((hw->media_type == e1000_media_type_fiber) ?
253 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
254
255 return 0;
256}
257
258static uint32_t
259e1000_get_rx_csum(struct net_device *netdev)
260{
261 struct e1000_adapter *adapter = netdev->priv;
262 return adapter->rx_csum;
263}
264
265static int
266e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
267{
268 struct e1000_adapter *adapter = netdev->priv;
269 adapter->rx_csum = data;
270
271 if(netif_running(netdev)) {
272 e1000_down(adapter);
273 e1000_up(adapter);
274 } else
275 e1000_reset(adapter);
276 return 0;
277}
278
279static uint32_t
280e1000_get_tx_csum(struct net_device *netdev)
281{
282 return (netdev->features & NETIF_F_HW_CSUM) != 0;
283}
284
285static int
286e1000_set_tx_csum(struct net_device *netdev, uint32_t data)
287{
288 struct e1000_adapter *adapter = netdev->priv;
289
290 if(adapter->hw.mac_type < e1000_82543) {
291 if (!data)
292 return -EINVAL;
293 return 0;
294 }
295
296 if (data)
297 netdev->features |= NETIF_F_HW_CSUM;
298 else
299 netdev->features &= ~NETIF_F_HW_CSUM;
300
301 return 0;
302}
303
304#ifdef NETIF_F_TSO
305static int
306e1000_set_tso(struct net_device *netdev, uint32_t data)
307{
308 struct e1000_adapter *adapter = netdev->priv;
309 if ((adapter->hw.mac_type < e1000_82544) ||
310 (adapter->hw.mac_type == e1000_82547))
311 return data ? -EINVAL : 0;
312
313 if (data)
314 netdev->features |= NETIF_F_TSO;
315 else
316 netdev->features &= ~NETIF_F_TSO;
317 return 0;
318}
319#endif /* NETIF_F_TSO */
320
321static uint32_t
322e1000_get_msglevel(struct net_device *netdev)
323{
324 struct e1000_adapter *adapter = netdev->priv;
325 return adapter->msg_enable;
326}
327
328static void
329e1000_set_msglevel(struct net_device *netdev, uint32_t data)
330{
331 struct e1000_adapter *adapter = netdev->priv;
332 adapter->msg_enable = data;
333}
334
335static int
336e1000_get_regs_len(struct net_device *netdev)
337{
338#define E1000_REGS_LEN 32
339 return E1000_REGS_LEN * sizeof(uint32_t);
340}
341
342static void
343e1000_get_regs(struct net_device *netdev,
344 struct ethtool_regs *regs, void *p)
345{
346 struct e1000_adapter *adapter = netdev->priv;
347 struct e1000_hw *hw = &adapter->hw;
348 uint32_t *regs_buff = p;
349 uint16_t phy_data;
350
351 memset(p, 0, E1000_REGS_LEN * sizeof(uint32_t));
352
353 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
354
355 regs_buff[0] = E1000_READ_REG(hw, CTRL);
356 regs_buff[1] = E1000_READ_REG(hw, STATUS);
357
358 regs_buff[2] = E1000_READ_REG(hw, RCTL);
359 regs_buff[3] = E1000_READ_REG(hw, RDLEN);
360 regs_buff[4] = E1000_READ_REG(hw, RDH);
361 regs_buff[5] = E1000_READ_REG(hw, RDT);
362 regs_buff[6] = E1000_READ_REG(hw, RDTR);
363
364 regs_buff[7] = E1000_READ_REG(hw, TCTL);
365 regs_buff[8] = E1000_READ_REG(hw, TDLEN);
366 regs_buff[9] = E1000_READ_REG(hw, TDH);
367 regs_buff[10] = E1000_READ_REG(hw, TDT);
368 regs_buff[11] = E1000_READ_REG(hw, TIDV);
369
370 regs_buff[12] = adapter->hw.phy_type; /* PHY type (IGP=1, M88=0) */
371 if(hw->phy_type == e1000_phy_igp) {
372 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
373 IGP01E1000_PHY_AGC_A);
374 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
375 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
376 regs_buff[13] = (uint32_t)phy_data; /* cable length */
377 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
378 IGP01E1000_PHY_AGC_B);
379 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B &
380 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
381 regs_buff[14] = (uint32_t)phy_data; /* cable length */
382 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
383 IGP01E1000_PHY_AGC_C);
384 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C &
385 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
386 regs_buff[15] = (uint32_t)phy_data; /* cable length */
387 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
388 IGP01E1000_PHY_AGC_D);
389 e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D &
390 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
391 regs_buff[16] = (uint32_t)phy_data; /* cable length */
392 regs_buff[17] = 0; /* extended 10bt distance (not needed) */
393 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
394 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS &
395 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
396 regs_buff[18] = (uint32_t)phy_data; /* cable polarity */
397 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
398 IGP01E1000_PHY_PCS_INIT_REG);
399 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
400 IGP01E1000_PHY_PAGE_SELECT, &phy_data);
401 regs_buff[19] = (uint32_t)phy_data; /* cable polarity */
402 regs_buff[20] = 0; /* polarity correction enabled (always) */
403 regs_buff[22] = 0; /* phy receive errors (unavailable) */
404 regs_buff[23] = regs_buff[18]; /* mdix mode */
405 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
406 } else {
407 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
408 regs_buff[13] = (uint32_t)phy_data; /* cable length */
409 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
410 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
411 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
412 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
413 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
414 regs_buff[18] = regs_buff[13]; /* cable polarity */
415 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
416 regs_buff[20] = regs_buff[17]; /* polarity correction */
417 /* phy receive errors */
418 regs_buff[22] = adapter->phy_stats.receive_errors;
419 regs_buff[23] = regs_buff[13]; /* mdix mode */
420 }
421 regs_buff[21] = adapter->phy_stats.idle_errors; /* phy idle errors */
422 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
423 regs_buff[24] = (uint32_t)phy_data; /* phy local receiver status */
424 regs_buff[25] = regs_buff[24]; /* phy remote receiver status */
425 if(hw->mac_type >= e1000_82540 &&
426 hw->media_type == e1000_media_type_copper) {
427 regs_buff[26] = E1000_READ_REG(hw, MANC);
428 }
429}
430
431static int
432e1000_get_eeprom_len(struct net_device *netdev)
433{
434 struct e1000_adapter *adapter = netdev->priv;
435 return adapter->hw.eeprom.word_size * 2;
436}
437
438static int
439e1000_get_eeprom(struct net_device *netdev,
440 struct ethtool_eeprom *eeprom, uint8_t *bytes)
441{
442 struct e1000_adapter *adapter = netdev->priv;
443 struct e1000_hw *hw = &adapter->hw;
444 uint16_t *eeprom_buff;
445 int first_word, last_word;
446 int ret_val = 0;
447 uint16_t i;
448
449 if(eeprom->len == 0)
450 return -EINVAL;
451
452 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
453
454 first_word = eeprom->offset >> 1;
455 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
456
457 eeprom_buff = kmalloc(sizeof(uint16_t) *
458 (last_word - first_word + 1), GFP_KERNEL);
459 if(!eeprom_buff)
460 return -ENOMEM;
461
462 if(hw->eeprom.type == e1000_eeprom_spi)
463 ret_val = e1000_read_eeprom(hw, first_word,
464 last_word - first_word + 1,
465 eeprom_buff);
466 else {
467 for (i = 0; i < last_word - first_word + 1; i++)
468 if((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
469 &eeprom_buff[i])))
470 break;
471 }
472
473 /* Device's eeprom is always little-endian, word addressable */
474 for (i = 0; i < last_word - first_word + 1; i++)
475 le16_to_cpus(&eeprom_buff[i]);
476
477 memcpy(bytes, (uint8_t *)eeprom_buff + (eeprom->offset & 1),
478 eeprom->len);
479 kfree(eeprom_buff);
480
481 return ret_val;
482}
483
484static int
485e1000_set_eeprom(struct net_device *netdev,
486 struct ethtool_eeprom *eeprom, uint8_t *bytes)
487{
488 struct e1000_adapter *adapter = netdev->priv;
489 struct e1000_hw *hw = &adapter->hw;
490 uint16_t *eeprom_buff;
491 void *ptr;
492 int max_len, first_word, last_word, ret_val = 0;
493 uint16_t i;
494
495 if(eeprom->len == 0)
496 return -EOPNOTSUPP;
497
498 if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
499 return -EFAULT;
500
501 max_len = hw->eeprom.word_size * 2;
502
503 first_word = eeprom->offset >> 1;
504 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
505 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
506 if(!eeprom_buff)
507 return -ENOMEM;
508
509 ptr = (void *)eeprom_buff;
510
511 if(eeprom->offset & 1) {
512 /* need read/modify/write of first changed EEPROM word */
513 /* only the second byte of the word is being modified */
514 ret_val = e1000_read_eeprom(hw, first_word, 1,
515 &eeprom_buff[0]);
516 ptr++;
517 }
518 if(((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
519 /* need read/modify/write of last changed EEPROM word */
520 /* only the first byte of the word is being modified */
521 ret_val = e1000_read_eeprom(hw, last_word, 1,
522 &eeprom_buff[last_word - first_word]);
523 }
524
525 /* Device's eeprom is always little-endian, word addressable */
526 for (i = 0; i < last_word - first_word + 1; i++)
527 le16_to_cpus(&eeprom_buff[i]);
528
529 memcpy(ptr, bytes, eeprom->len);
530
531 for (i = 0; i < last_word - first_word + 1; i++)
532 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
533
534 ret_val = e1000_write_eeprom(hw, first_word,
535 last_word - first_word + 1, eeprom_buff);
536
537 /* Update the checksum over the first part of the EEPROM if needed */
538 if((ret_val == 0) && first_word <= EEPROM_CHECKSUM_REG)
539 e1000_update_eeprom_checksum(hw);
540
541 kfree(eeprom_buff);
542 return ret_val;
543}
544
545static void
546e1000_get_drvinfo(struct net_device *netdev,
547 struct ethtool_drvinfo *drvinfo)
548{
549 struct e1000_adapter *adapter = netdev->priv;
550
551 strncpy(drvinfo->driver, e1000_driver_name, 32);
552 strncpy(drvinfo->version, e1000_driver_version, 32);
553 strncpy(drvinfo->fw_version, "N/A", 32);
554 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
555 drvinfo->n_stats = E1000_STATS_LEN;
556 drvinfo->testinfo_len = E1000_TEST_LEN;
557 drvinfo->regdump_len = e1000_get_regs_len(netdev);
558 drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
559}
560
561static void
562e1000_get_ringparam(struct net_device *netdev,
563 struct ethtool_ringparam *ring)
564{
565 struct e1000_adapter *adapter = netdev->priv;
566 e1000_mac_type mac_type = adapter->hw.mac_type;
567 struct e1000_desc_ring *txdr = &adapter->tx_ring;
568 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
569
570 ring->rx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_RXD :
571 E1000_MAX_82544_RXD;
572 ring->tx_max_pending = (mac_type < e1000_82544) ? E1000_MAX_TXD :
573 E1000_MAX_82544_TXD;
574 ring->rx_mini_max_pending = 0;
575 ring->rx_jumbo_max_pending = 0;
576 ring->rx_pending = rxdr->count;
577 ring->tx_pending = txdr->count;
578 ring->rx_mini_pending = 0;
579 ring->rx_jumbo_pending = 0;
580}
581
582static int
583e1000_set_ringparam(struct net_device *netdev,
584 struct ethtool_ringparam *ring)
585{
586 struct e1000_adapter *adapter = netdev->priv;
587 e1000_mac_type mac_type = adapter->hw.mac_type;
588 struct e1000_desc_ring *txdr = &adapter->tx_ring;
589 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
590 struct e1000_desc_ring tx_old, tx_new, rx_old, rx_new;
591 int err;
592
593 tx_old = adapter->tx_ring;
594 rx_old = adapter->rx_ring;
595
596 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
597 return -EINVAL;
598
599 if(netif_running(adapter->netdev))
600 e1000_down(adapter);
601
602 rxdr->count = max(ring->rx_pending,(uint32_t)E1000_MIN_RXD);
603 rxdr->count = min(rxdr->count,(uint32_t)(mac_type < e1000_82544 ?
604 E1000_MAX_RXD : E1000_MAX_82544_RXD));
605 E1000_ROUNDUP(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
606
607 txdr->count = max(ring->tx_pending,(uint32_t)E1000_MIN_TXD);
608 txdr->count = min(txdr->count,(uint32_t)(mac_type < e1000_82544 ?
609 E1000_MAX_TXD : E1000_MAX_82544_TXD));
610 E1000_ROUNDUP(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
611
612 if(netif_running(adapter->netdev)) {
613 /* Try to get new resources before deleting old */
614 if((err = e1000_setup_rx_resources(adapter)))
615 goto err_setup_rx;
616 if((err = e1000_setup_tx_resources(adapter)))
617 goto err_setup_tx;
618
619 /* save the new, restore the old in order to free it,
620 * then restore the new back again */
621
622 rx_new = adapter->rx_ring;
623 tx_new = adapter->tx_ring;
624 adapter->rx_ring = rx_old;
625 adapter->tx_ring = tx_old;
626 e1000_free_rx_resources(adapter);
627 e1000_free_tx_resources(adapter);
628 adapter->rx_ring = rx_new;
629 adapter->tx_ring = tx_new;
630 if((err = e1000_up(adapter)))
631 return err;
632 }
633
634 return 0;
635err_setup_tx:
636 e1000_free_rx_resources(adapter);
637err_setup_rx:
638 adapter->rx_ring = rx_old;
639 adapter->tx_ring = tx_old;
640 e1000_up(adapter);
641 return err;
642}
643
644#define REG_PATTERN_TEST(R, M, W) \
645{ \
646 uint32_t pat, value; \
647 uint32_t test[] = \
648 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
649 for(pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) { \
650 E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W)); \
651 value = E1000_READ_REG(&adapter->hw, R); \
652 if(value != (test[pat] & W & M)) { \
653 *data = (adapter->hw.mac_type < e1000_82543) ? \
654 E1000_82542_##R : E1000_##R; \
655 return 1; \
656 } \
657 } \
658}
659
660#define REG_SET_AND_CHECK(R, M, W) \
661{ \
662 uint32_t value; \
663 E1000_WRITE_REG(&adapter->hw, R, W & M); \
664 value = E1000_READ_REG(&adapter->hw, R); \
665 if ((W & M) != (value & M)) { \
666 *data = (adapter->hw.mac_type < e1000_82543) ? \
667 E1000_82542_##R : E1000_##R; \
668 return 1; \
669 } \
670}
671
672static int
673e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
674{
675 uint32_t value;
676 uint32_t i;
677
678 /* The status register is Read Only, so a write should fail.
679 * Some bits that get toggled are ignored.
680 */
681 value = (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833));
682 E1000_WRITE_REG(&adapter->hw, STATUS, (0xFFFFFFFF));
683 if(value != (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833))) {
684 *data = 1;
685 return 1;
686 }
687
688 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
689 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
690 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
691 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
692 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
693 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
694 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
695 REG_PATTERN_TEST(RDH, 0x0000FFFF, 0x0000FFFF);
696 REG_PATTERN_TEST(RDT, 0x0000FFFF, 0x0000FFFF);
697 REG_PATTERN_TEST(FCRTH, 0x0000FFF8, 0x0000FFF8);
698 REG_PATTERN_TEST(FCTTV, 0x0000FFFF, 0x0000FFFF);
699 REG_PATTERN_TEST(TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
700 REG_PATTERN_TEST(TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
701 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
702
703 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
704 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB);
705 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
706
707 if(adapter->hw.mac_type >= e1000_82543) {
708
709 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF);
710 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
711 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
712 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
713 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
714
715 for(i = 0; i < E1000_RAR_ENTRIES; i++) {
716 REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF,
717 0xFFFFFFFF);
718 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
719 0xFFFFFFFF);
720 }
721
722 } else {
723
724 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF);
725 REG_PATTERN_TEST(RDBAL, 0xFFFFF000, 0xFFFFFFFF);
726 REG_PATTERN_TEST(TXCW, 0x0000FFFF, 0x0000FFFF);
727 REG_PATTERN_TEST(TDBAL, 0xFFFFF000, 0xFFFFFFFF);
728
729 }
730
731 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
732 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
733
734 *data = 0;
735 return 0;
736}
737
738static int
739e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
740{
741 uint16_t temp;
742 uint16_t checksum = 0;
743 uint16_t i;
744
745 *data = 0;
746 /* Read and add up the contents of the EEPROM */
747 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
748 if((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
749 *data = 1;
750 break;
751 }
752 checksum += temp;
753 }
754
755 /* If Checksum is not Correct return error else test passed */
756 if((checksum != (uint16_t) EEPROM_SUM) && !(*data))
757 *data = 2;
758
759 return *data;
760}
761
762static irqreturn_t
763e1000_test_intr(int irq,
764 void *data,
765 struct pt_regs *regs)
766{
767 struct net_device *netdev = (struct net_device *) data;
768 struct e1000_adapter *adapter = netdev->priv;
769
770 adapter->test_icr |= E1000_READ_REG(&adapter->hw, ICR);
771
772 return IRQ_HANDLED;
773}
774
775static int
776e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
777{
778 struct net_device *netdev = adapter->netdev;
779 uint32_t mask, i=0, shared_int = TRUE;
780 uint32_t irq = adapter->pdev->irq;
781
782 *data = 0;
783
784 /* Hook up test interrupt handler just for this test */
785 if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) {
786 shared_int = FALSE;
787 } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ,
788 netdev->name, netdev)){
789 *data = 1;
790 return -1;
791 }
792
793 /* Disable all the interrupts */
794 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
795 msec_delay(10);
796
797 /* Test each interrupt */
798 for(; i < 10; i++) {
799
800 /* Interrupt to test */
801 mask = 1 << i;
802
803 if(!shared_int) {
804 /* Disable the interrupt to be reported in
805 * the cause register and then force the same
806 * interrupt and see if one gets posted. If
807 * an interrupt was posted to the bus, the
808 * test failed.
809 */
810 adapter->test_icr = 0;
811 E1000_WRITE_REG(&adapter->hw, IMC, mask);
812 E1000_WRITE_REG(&adapter->hw, ICS, mask);
813 msec_delay(10);
814
815 if(adapter->test_icr & mask) {
816 *data = 3;
817 break;
818 }
819 }
820
821 /* Enable the interrupt to be reported in
822 * the cause register and then force the same
823 * interrupt and see if one gets posted. If
824 * an interrupt was not posted to the bus, the
825 * test failed.
826 */
827 adapter->test_icr = 0;
828 E1000_WRITE_REG(&adapter->hw, IMS, mask);
829 E1000_WRITE_REG(&adapter->hw, ICS, mask);
830 msec_delay(10);
831
832 if(!(adapter->test_icr & mask)) {
833 *data = 4;
834 break;
835 }
836
837 if(!shared_int) {
838 /* Disable the other interrupts to be reported in
839 * the cause register and then force the other
840 * interrupts and see if any get posted. If
841 * an interrupt was posted to the bus, the
842 * test failed.
843 */
844 adapter->test_icr = 0;
845 E1000_WRITE_REG(&adapter->hw, IMC,
846 (~mask & 0x00007FFF));
847 E1000_WRITE_REG(&adapter->hw, ICS,
848 (~mask & 0x00007FFF));
849 msec_delay(10);
850
851 if(adapter->test_icr) {
852 *data = 5;
853 break;
854 }
855 }
856 }
857
858 /* Disable all the interrupts */
859 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
860 msec_delay(10);
861
862 /* Unhook test interrupt handler */
863 free_irq(irq, netdev);
864
865 return *data;
866}
867
868static void
869e1000_free_desc_rings(struct e1000_adapter *adapter)
870{
871 struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
872 struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
873 struct pci_dev *pdev = adapter->pdev;
874 int i;
875
876 if(txdr->desc && txdr->buffer_info) {
877 for(i = 0; i < txdr->count; i++) {
878 if(txdr->buffer_info[i].dma)
879 pci_unmap_single(pdev, txdr->buffer_info[i].dma,
880 txdr->buffer_info[i].length,
881 PCI_DMA_TODEVICE);
882 if(txdr->buffer_info[i].skb)
883 dev_kfree_skb(txdr->buffer_info[i].skb);
884 }
885 }
886
887 if(rxdr->desc && rxdr->buffer_info) {
888 for(i = 0; i < rxdr->count; i++) {
889 if(rxdr->buffer_info[i].dma)
890 pci_unmap_single(pdev, rxdr->buffer_info[i].dma,
891 rxdr->buffer_info[i].length,
892 PCI_DMA_FROMDEVICE);
893 if(rxdr->buffer_info[i].skb)
894 dev_kfree_skb(rxdr->buffer_info[i].skb);
895 }
896 }
897
898 if(txdr->desc)
899 pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma);
900 if(rxdr->desc)
901 pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
902
903 if(txdr->buffer_info)
904 kfree(txdr->buffer_info);
905 if(rxdr->buffer_info)
906 kfree(rxdr->buffer_info);
907
908 return;
909}
910
911static int
912e1000_setup_desc_rings(struct e1000_adapter *adapter)
913{
914 struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
915 struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
916 struct pci_dev *pdev = adapter->pdev;
917 uint32_t rctl;
918 int size, i, ret_val;
919
920 /* Setup Tx descriptor ring and Tx buffers */
921
922 txdr->count = 80;
923
924 size = txdr->count * sizeof(struct e1000_buffer);
925 if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
926 ret_val = 1;
927 goto err_nomem;
928 }
929 memset(txdr->buffer_info, 0, size);
930
931 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
932 E1000_ROUNDUP(txdr->size, 4096);
933 if(!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
934 ret_val = 2;
935 goto err_nomem;
936 }
937 memset(txdr->desc, 0, txdr->size);
938 txdr->next_to_use = txdr->next_to_clean = 0;
939
940 E1000_WRITE_REG(&adapter->hw, TDBAL,
941 ((uint64_t) txdr->dma & 0x00000000FFFFFFFF));
942 E1000_WRITE_REG(&adapter->hw, TDBAH, ((uint64_t) txdr->dma >> 32));
943 E1000_WRITE_REG(&adapter->hw, TDLEN,
944 txdr->count * sizeof(struct e1000_tx_desc));
945 E1000_WRITE_REG(&adapter->hw, TDH, 0);
946 E1000_WRITE_REG(&adapter->hw, TDT, 0);
947 E1000_WRITE_REG(&adapter->hw, TCTL,
948 E1000_TCTL_PSP | E1000_TCTL_EN |
949 E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
950 E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
951
952 for(i = 0; i < txdr->count; i++) {
953 struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i);
954 struct sk_buff *skb;
955 unsigned int size = 1024;
956
957 if(!(skb = alloc_skb(size, GFP_KERNEL))) {
958 ret_val = 3;
959 goto err_nomem;
960 }
961 skb_put(skb, size);
962 txdr->buffer_info[i].skb = skb;
963 txdr->buffer_info[i].length = skb->len;
964 txdr->buffer_info[i].dma =
965 pci_map_single(pdev, skb->data, skb->len,
966 PCI_DMA_TODEVICE);
967 tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
968 tx_desc->lower.data = cpu_to_le32(skb->len);
969 tx_desc->lower.data |= cpu_to_le32(E1000_TXD_CMD_EOP |
970 E1000_TXD_CMD_IFCS |
971 E1000_TXD_CMD_RPS);
972 tx_desc->upper.data = 0;
973 }
974
975 /* Setup Rx descriptor ring and Rx buffers */
976
977 rxdr->count = 80;
978
979 size = rxdr->count * sizeof(struct e1000_buffer);
980 if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
981 ret_val = 4;
982 goto err_nomem;
983 }
984 memset(rxdr->buffer_info, 0, size);
985
986 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
987 if(!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
988 ret_val = 5;
989 goto err_nomem;
990 }
991 memset(rxdr->desc, 0, rxdr->size);
992 rxdr->next_to_use = rxdr->next_to_clean = 0;
993
994 rctl = E1000_READ_REG(&adapter->hw, RCTL);
995 E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
996 E1000_WRITE_REG(&adapter->hw, RDBAL,
997 ((uint64_t) rxdr->dma & 0xFFFFFFFF));
998 E1000_WRITE_REG(&adapter->hw, RDBAH, ((uint64_t) rxdr->dma >> 32));
999 E1000_WRITE_REG(&adapter->hw, RDLEN, rxdr->size);
1000 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1001 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1002 rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
1003 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1004 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1005 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1006
1007 for(i = 0; i < rxdr->count; i++) {
1008 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
1009 struct sk_buff *skb;
1010
1011 if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN,
1012 GFP_KERNEL))) {
1013 ret_val = 6;
1014 goto err_nomem;
1015 }
1016 skb_reserve(skb, NET_IP_ALIGN);
1017 rxdr->buffer_info[i].skb = skb;
1018 rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
1019 rxdr->buffer_info[i].dma =
1020 pci_map_single(pdev, skb->data, E1000_RXBUFFER_2048,
1021 PCI_DMA_FROMDEVICE);
1022 rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
1023 memset(skb->data, 0x00, skb->len);
1024 }
1025
1026 return 0;
1027
1028err_nomem:
1029 e1000_free_desc_rings(adapter);
1030 return ret_val;
1031}
1032
1033static void
1034e1000_phy_disable_receiver(struct e1000_adapter *adapter)
1035{
1036 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1037 e1000_write_phy_reg(&adapter->hw, 29, 0x001F);
1038 e1000_write_phy_reg(&adapter->hw, 30, 0x8FFC);
1039 e1000_write_phy_reg(&adapter->hw, 29, 0x001A);
1040 e1000_write_phy_reg(&adapter->hw, 30, 0x8FF0);
1041}
1042
1043static void
1044e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
1045{
1046 uint16_t phy_reg;
1047
1048 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1049 * Extended PHY Specific Control Register to 25MHz clock. This
1050 * value defaults back to a 2.5MHz clock when the PHY is reset.
1051 */
1052 e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1053 phy_reg |= M88E1000_EPSCR_TX_CLK_25;
1054 e1000_write_phy_reg(&adapter->hw,
1055 M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
1056
1057 /* In addition, because of the s/w reset above, we need to enable
1058 * CRS on TX. This must be set for both full and half duplex
1059 * operation.
1060 */
1061 e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1062 phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1063 e1000_write_phy_reg(&adapter->hw,
1064 M88E1000_PHY_SPEC_CTRL, phy_reg);
1065}
1066
1067static int
1068e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
1069{
1070 uint32_t ctrl_reg;
1071 uint16_t phy_reg;
1072
1073 /* Setup the Device Control Register for PHY loopback test. */
1074
1075 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1076 ctrl_reg |= (E1000_CTRL_ILOS | /* Invert Loss-Of-Signal */
1077 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1078 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1079 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */
1080 E1000_CTRL_FD); /* Force Duplex to FULL */
1081
1082 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl_reg);
1083
1084 /* Read the PHY Specific Control Register (0x10) */
1085 e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
1086
1087 /* Clear Auto-Crossover bits in PHY Specific Control Register
1088 * (bits 6:5).
1089 */
1090 phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
1091 e1000_write_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
1092
1093 /* Perform software reset on the PHY */
1094 e1000_phy_reset(&adapter->hw);
1095
1096 /* Have to setup TX_CLK and TX_CRS after software reset */
1097 e1000_phy_reset_clk_and_crs(adapter);
1098
1099 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8100);
1100
1101 /* Wait for reset to complete. */
1102 udelay(500);
1103
1104 /* Have to setup TX_CLK and TX_CRS after software reset */
1105 e1000_phy_reset_clk_and_crs(adapter);
1106
1107 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1108 e1000_phy_disable_receiver(adapter);
1109
1110 /* Set the loopback bit in the PHY control register. */
1111 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1112 phy_reg |= MII_CR_LOOPBACK;
1113 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
1114
1115 /* Setup TX_CLK and TX_CRS one more time. */
1116 e1000_phy_reset_clk_and_crs(adapter);
1117
1118 /* Check Phy Configuration */
1119 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1120 if(phy_reg != 0x4100)
1121 return 9;
1122
1123 e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
1124 if(phy_reg != 0x0070)
1125 return 10;
1126
1127 e1000_read_phy_reg(&adapter->hw, 29, &phy_reg);
1128 if(phy_reg != 0x001A)
1129 return 11;
1130
1131 return 0;
1132}
1133
1134static int
1135e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1136{
1137 uint32_t ctrl_reg = 0;
1138 uint32_t stat_reg = 0;
1139
1140 adapter->hw.autoneg = FALSE;
1141
1142 if(adapter->hw.phy_type == e1000_phy_m88) {
1143 /* Auto-MDI/MDIX Off */
1144 e1000_write_phy_reg(&adapter->hw,
1145 M88E1000_PHY_SPEC_CTRL, 0x0808);
1146 /* reset to update Auto-MDI/MDIX */
1147 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
1148 /* autoneg off */
1149 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1150 }
1151 /* force 1000, set loopback */
1152 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1153
1154 /* Now set up the MAC to the same speed/duplex as the PHY. */
1155 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1156 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1157 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1158 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1159 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1160 E1000_CTRL_FD); /* Force Duplex to FULL */
1161
1162 if(adapter->hw.media_type == e1000_media_type_copper &&
1163 adapter->hw.phy_type == e1000_phy_m88) {
1164 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1165 } else {
1166 /* Set the ILOS bit on the fiber Nic is half
1167 * duplex link is detected. */
1168 stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
1169 if((stat_reg & E1000_STATUS_FD) == 0)
1170 ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
1171 }
1172
1173 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl_reg);
1174
1175 /* Disable the receiver on the PHY so when a cable is plugged in, the
1176 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1177 */
1178 if(adapter->hw.phy_type == e1000_phy_m88)
1179 e1000_phy_disable_receiver(adapter);
1180
1181 udelay(500);
1182
1183 return 0;
1184}
1185
1186static int
1187e1000_set_phy_loopback(struct e1000_adapter *adapter)
1188{
1189 uint16_t phy_reg = 0;
1190 uint16_t count = 0;
1191
1192 switch (adapter->hw.mac_type) {
1193 case e1000_82543:
1194 if(adapter->hw.media_type == e1000_media_type_copper) {
1195 /* Attempt to setup Loopback mode on Non-integrated PHY.
1196 * Some PHY registers get corrupted at random, so
1197 * attempt this 10 times.
1198 */
1199 while(e1000_nonintegrated_phy_loopback(adapter) &&
1200 count++ < 10);
1201 if(count < 11)
1202 return 0;
1203 }
1204 break;
1205
1206 case e1000_82544:
1207 case e1000_82540:
1208 case e1000_82545:
1209 case e1000_82545_rev_3:
1210 case e1000_82546:
1211 case e1000_82546_rev_3:
1212 case e1000_82541:
1213 case e1000_82541_rev_2:
1214 case e1000_82547:
1215 case e1000_82547_rev_2:
1216 return e1000_integrated_phy_loopback(adapter);
1217 break;
1218
1219 default:
1220 /* Default PHY loopback work is to read the MII
1221 * control register and assert bit 14 (loopback mode).
1222 */
1223 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1224 phy_reg |= MII_CR_LOOPBACK;
1225 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
1226 return 0;
1227 break;
1228 }
1229
1230 return 8;
1231}
1232
1233static int
1234e1000_setup_loopback_test(struct e1000_adapter *adapter)
1235{
1236 uint32_t rctl;
1237
1238 if(adapter->hw.media_type == e1000_media_type_fiber ||
1239 adapter->hw.media_type == e1000_media_type_internal_serdes) {
1240 if(adapter->hw.mac_type == e1000_82545 ||
1241 adapter->hw.mac_type == e1000_82546 ||
1242 adapter->hw.mac_type == e1000_82545_rev_3 ||
1243 adapter->hw.mac_type == e1000_82546_rev_3)
1244 return e1000_set_phy_loopback(adapter);
1245 else {
1246 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1247 rctl |= E1000_RCTL_LBM_TCVR;
1248 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1249 return 0;
1250 }
1251 } else if(adapter->hw.media_type == e1000_media_type_copper)
1252 return e1000_set_phy_loopback(adapter);
1253
1254 return 7;
1255}
1256
1257static void
1258e1000_loopback_cleanup(struct e1000_adapter *adapter)
1259{
1260 uint32_t rctl;
1261 uint16_t phy_reg;
1262
1263 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1264 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1265 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1266
1267 if(adapter->hw.media_type == e1000_media_type_copper ||
1268 ((adapter->hw.media_type == e1000_media_type_fiber ||
1269 adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1270 (adapter->hw.mac_type == e1000_82545 ||
1271 adapter->hw.mac_type == e1000_82546 ||
1272 adapter->hw.mac_type == e1000_82545_rev_3 ||
1273 adapter->hw.mac_type == e1000_82546_rev_3))) {
1274 adapter->hw.autoneg = TRUE;
1275 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
1276 if(phy_reg & MII_CR_LOOPBACK) {
1277 phy_reg &= ~MII_CR_LOOPBACK;
1278 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
1279 e1000_phy_reset(&adapter->hw);
1280 }
1281 }
1282}
1283
1284static void
1285e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1286{
1287 memset(skb->data, 0xFF, frame_size);
1288 frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
1289 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1290 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1291 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1292}
1293
1294static int
1295e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1296{
1297 frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
1298 if(*(skb->data + 3) == 0xFF) {
1299 if((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1300 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1301 return 0;
1302 }
1303 }
1304 return 13;
1305}
1306
1307static int
1308e1000_run_loopback_test(struct e1000_adapter *adapter)
1309{
1310 struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
1311 struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
1312 struct pci_dev *pdev = adapter->pdev;
1313 int i, ret_val;
1314
1315 E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1);
1316
1317 for(i = 0; i < 64; i++) {
1318 e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024);
1319 pci_dma_sync_single_for_device(pdev, txdr->buffer_info[i].dma,
1320 txdr->buffer_info[i].length,
1321 PCI_DMA_TODEVICE);
1322 }
1323 E1000_WRITE_REG(&adapter->hw, TDT, i);
1324
1325 msec_delay(200);
1326
1327 i = 0;
1328 do {
1329 pci_dma_sync_single_for_cpu(pdev, rxdr->buffer_info[i].dma,
1330 rxdr->buffer_info[i].length,
1331 PCI_DMA_FROMDEVICE);
1332
1333 ret_val = e1000_check_lbtest_frame(rxdr->buffer_info[i].skb,
1334 1024);
1335 i++;
1336 } while (ret_val != 0 && i < 64);
1337
1338 return ret_val;
1339}
1340
1341static int
1342e1000_loopback_test(struct e1000_adapter *adapter, uint64_t *data)
1343{
1344 if((*data = e1000_setup_desc_rings(adapter))) goto err_loopback;
1345 if((*data = e1000_setup_loopback_test(adapter))) goto err_loopback;
1346 *data = e1000_run_loopback_test(adapter);
1347 e1000_loopback_cleanup(adapter);
1348 e1000_free_desc_rings(adapter);
1349err_loopback:
1350 return *data;
1351}
1352
1353static int
1354e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
1355{
1356 *data = 0;
1357
1358 if (adapter->hw.media_type == e1000_media_type_internal_serdes) {
1359 int i = 0;
1360 adapter->hw.serdes_link_down = TRUE;
1361
1362 /* on some blade server designs link establishment */
1363 /* could take as long as 2-3 minutes. */
1364 do {
1365 e1000_check_for_link(&adapter->hw);
1366 if (adapter->hw.serdes_link_down == FALSE)
1367 return *data;
1368 msec_delay(20);
1369 } while (i++ < 3750);
1370
1371 *data = 1;
1372 } else {
1373 e1000_check_for_link(&adapter->hw);
1374
1375 if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
1376 *data = 1;
1377 }
1378 }
1379 return *data;
1380}
1381
1382static int
1383e1000_diag_test_count(struct net_device *netdev)
1384{
1385 return E1000_TEST_LEN;
1386}
1387
1388static void
1389e1000_diag_test(struct net_device *netdev,
1390 struct ethtool_test *eth_test, uint64_t *data)
1391{
1392 struct e1000_adapter *adapter = netdev->priv;
1393 boolean_t if_running = netif_running(netdev);
1394
1395 if(eth_test->flags == ETH_TEST_FL_OFFLINE) {
1396 /* Offline tests */
1397
1398 /* save speed, duplex, autoneg settings */
1399 uint16_t autoneg_advertised = adapter->hw.autoneg_advertised;
1400 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex;
1401 uint8_t autoneg = adapter->hw.autoneg;
1402
1403 /* Link test performed before hardware reset so autoneg doesn't
1404 * interfere with test result */
1405 if(e1000_link_test(adapter, &data[4]))
1406 eth_test->flags |= ETH_TEST_FL_FAILED;
1407
1408 if(if_running)
1409 e1000_down(adapter);
1410 else
1411 e1000_reset(adapter);
1412
1413 if(e1000_reg_test(adapter, &data[0]))
1414 eth_test->flags |= ETH_TEST_FL_FAILED;
1415
1416 e1000_reset(adapter);
1417 if(e1000_eeprom_test(adapter, &data[1]))
1418 eth_test->flags |= ETH_TEST_FL_FAILED;
1419
1420 e1000_reset(adapter);
1421 if(e1000_intr_test(adapter, &data[2]))
1422 eth_test->flags |= ETH_TEST_FL_FAILED;
1423
1424 e1000_reset(adapter);
1425 if(e1000_loopback_test(adapter, &data[3]))
1426 eth_test->flags |= ETH_TEST_FL_FAILED;
1427
1428 /* restore speed, duplex, autoneg settings */
1429 adapter->hw.autoneg_advertised = autoneg_advertised;
1430 adapter->hw.forced_speed_duplex = forced_speed_duplex;
1431 adapter->hw.autoneg = autoneg;
1432
1433 e1000_reset(adapter);
1434 if(if_running)
1435 e1000_up(adapter);
1436 } else {
1437 /* Online tests */
1438 if(e1000_link_test(adapter, &data[4]))
1439 eth_test->flags |= ETH_TEST_FL_FAILED;
1440
1441 /* Offline tests aren't run; pass by default */
1442 data[0] = 0;
1443 data[1] = 0;
1444 data[2] = 0;
1445 data[3] = 0;
1446 }
1447}
1448
1449static void
1450e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1451{
1452 struct e1000_adapter *adapter = netdev->priv;
1453 struct e1000_hw *hw = &adapter->hw;
1454
1455 switch(adapter->hw.device_id) {
1456 case E1000_DEV_ID_82542:
1457 case E1000_DEV_ID_82543GC_FIBER:
1458 case E1000_DEV_ID_82543GC_COPPER:
1459 case E1000_DEV_ID_82544EI_FIBER:
1460 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1461 case E1000_DEV_ID_82545EM_FIBER:
1462 case E1000_DEV_ID_82545EM_COPPER:
1463 wol->supported = 0;
1464 wol->wolopts = 0;
1465 return;
1466
1467 case E1000_DEV_ID_82546EB_FIBER:
1468 case E1000_DEV_ID_82546GB_FIBER:
1469 /* Wake events only supported on port A for dual fiber */
1470 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1471 wol->supported = 0;
1472 wol->wolopts = 0;
1473 return;
1474 }
1475 /* Fall Through */
1476
1477 default:
1478 wol->supported = WAKE_UCAST | WAKE_MCAST |
1479 WAKE_BCAST | WAKE_MAGIC;
1480
1481 wol->wolopts = 0;
1482 if(adapter->wol & E1000_WUFC_EX)
1483 wol->wolopts |= WAKE_UCAST;
1484 if(adapter->wol & E1000_WUFC_MC)
1485 wol->wolopts |= WAKE_MCAST;
1486 if(adapter->wol & E1000_WUFC_BC)
1487 wol->wolopts |= WAKE_BCAST;
1488 if(adapter->wol & E1000_WUFC_MAG)
1489 wol->wolopts |= WAKE_MAGIC;
1490 return;
1491 }
1492}
1493
1494static int
1495e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1496{
1497 struct e1000_adapter *adapter = netdev->priv;
1498 struct e1000_hw *hw = &adapter->hw;
1499
1500 switch(adapter->hw.device_id) {
1501 case E1000_DEV_ID_82542:
1502 case E1000_DEV_ID_82543GC_FIBER:
1503 case E1000_DEV_ID_82543GC_COPPER:
1504 case E1000_DEV_ID_82544EI_FIBER:
1505 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1506 case E1000_DEV_ID_82545EM_FIBER:
1507 case E1000_DEV_ID_82545EM_COPPER:
1508 return wol->wolopts ? -EOPNOTSUPP : 0;
1509
1510 case E1000_DEV_ID_82546EB_FIBER:
1511 case E1000_DEV_ID_82546GB_FIBER:
1512 /* Wake events only supported on port A for dual fiber */
1513 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1514 return wol->wolopts ? -EOPNOTSUPP : 0;
1515 /* Fall Through */
1516
1517 default:
1518 if(wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1519 return -EOPNOTSUPP;
1520
1521 adapter->wol = 0;
1522
1523 if(wol->wolopts & WAKE_UCAST)
1524 adapter->wol |= E1000_WUFC_EX;
1525 if(wol->wolopts & WAKE_MCAST)
1526 adapter->wol |= E1000_WUFC_MC;
1527 if(wol->wolopts & WAKE_BCAST)
1528 adapter->wol |= E1000_WUFC_BC;
1529 if(wol->wolopts & WAKE_MAGIC)
1530 adapter->wol |= E1000_WUFC_MAG;
1531 }
1532
1533 return 0;
1534}
1535
1536/* toggle LED 4 times per second = 2 "blinks" per second */
1537#define E1000_ID_INTERVAL (HZ/4)
1538
1539/* bit defines for adapter->led_status */
1540#define E1000_LED_ON 0
1541
1542static void
1543e1000_led_blink_callback(unsigned long data)
1544{
1545 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1546
1547 if(test_and_change_bit(E1000_LED_ON, &adapter->led_status))
1548 e1000_led_off(&adapter->hw);
1549 else
1550 e1000_led_on(&adapter->hw);
1551
1552 mod_timer(&adapter->blink_timer, jiffies + E1000_ID_INTERVAL);
1553}
1554
1555static int
1556e1000_phys_id(struct net_device *netdev, uint32_t data)
1557{
1558 struct e1000_adapter *adapter = netdev->priv;
1559
1560 if(!data || data > (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ))
1561 data = (uint32_t)(MAX_SCHEDULE_TIMEOUT / HZ);
1562
1563 if(!adapter->blink_timer.function) {
1564 init_timer(&adapter->blink_timer);
1565 adapter->blink_timer.function = e1000_led_blink_callback;
1566 adapter->blink_timer.data = (unsigned long) adapter;
1567 }
1568
1569 e1000_setup_led(&adapter->hw);
1570 mod_timer(&adapter->blink_timer, jiffies);
1571
1572 msleep_interruptible(data * 1000);
1573 del_timer_sync(&adapter->blink_timer);
1574 e1000_led_off(&adapter->hw);
1575 clear_bit(E1000_LED_ON, &adapter->led_status);
1576 e1000_cleanup_led(&adapter->hw);
1577
1578 return 0;
1579}
1580
1581static int
1582e1000_nway_reset(struct net_device *netdev)
1583{
1584 struct e1000_adapter *adapter = netdev->priv;
1585 if(netif_running(netdev)) {
1586 e1000_down(adapter);
1587 e1000_up(adapter);
1588 }
1589 return 0;
1590}
1591
1592static int
1593e1000_get_stats_count(struct net_device *netdev)
1594{
1595 return E1000_STATS_LEN;
1596}
1597
1598static void
1599e1000_get_ethtool_stats(struct net_device *netdev,
1600 struct ethtool_stats *stats, uint64_t *data)
1601{
1602 struct e1000_adapter *adapter = netdev->priv;
1603 int i;
1604
1605 e1000_update_stats(adapter);
1606 for(i = 0; i < E1000_STATS_LEN; i++) {
1607 char *p = (char *)adapter+e1000_gstrings_stats[i].stat_offset;
1608 data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
1609 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1610 }
1611}
1612
1613static void
1614e1000_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
1615{
1616 int i;
1617
1618 switch(stringset) {
1619 case ETH_SS_TEST:
1620 memcpy(data, *e1000_gstrings_test,
1621 E1000_TEST_LEN*ETH_GSTRING_LEN);
1622 break;
1623 case ETH_SS_STATS:
1624 for (i=0; i < E1000_STATS_LEN; i++) {
1625 memcpy(data + i * ETH_GSTRING_LEN,
1626 e1000_gstrings_stats[i].stat_string,
1627 ETH_GSTRING_LEN);
1628 }
1629 break;
1630 }
1631}
1632
1633struct ethtool_ops e1000_ethtool_ops = {
1634 .get_settings = e1000_get_settings,
1635 .set_settings = e1000_set_settings,
1636 .get_drvinfo = e1000_get_drvinfo,
1637 .get_regs_len = e1000_get_regs_len,
1638 .get_regs = e1000_get_regs,
1639 .get_wol = e1000_get_wol,
1640 .set_wol = e1000_set_wol,
1641 .get_msglevel = e1000_get_msglevel,
1642 .set_msglevel = e1000_set_msglevel,
1643 .nway_reset = e1000_nway_reset,
1644 .get_link = ethtool_op_get_link,
1645 .get_eeprom_len = e1000_get_eeprom_len,
1646 .get_eeprom = e1000_get_eeprom,
1647 .set_eeprom = e1000_set_eeprom,
1648 .get_ringparam = e1000_get_ringparam,
1649 .set_ringparam = e1000_set_ringparam,
1650 .get_pauseparam = e1000_get_pauseparam,
1651 .set_pauseparam = e1000_set_pauseparam,
1652 .get_rx_csum = e1000_get_rx_csum,
1653 .set_rx_csum = e1000_set_rx_csum,
1654 .get_tx_csum = e1000_get_tx_csum,
1655 .set_tx_csum = e1000_set_tx_csum,
1656 .get_sg = ethtool_op_get_sg,
1657 .set_sg = ethtool_op_set_sg,
1658#ifdef NETIF_F_TSO
1659 .get_tso = ethtool_op_get_tso,
1660 .set_tso = e1000_set_tso,
1661#endif
1662 .self_test_count = e1000_diag_test_count,
1663 .self_test = e1000_diag_test,
1664 .get_strings = e1000_get_strings,
1665 .phys_id = e1000_phys_id,
1666 .get_stats_count = e1000_get_stats_count,
1667 .get_ethtool_stats = e1000_get_ethtool_stats,
1668};
1669
1670void e1000_set_ethtool_ops(struct net_device *netdev)
1671{
1672 SET_ETHTOOL_OPS(netdev, &e1000_ethtool_ops);
1673}
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
new file mode 100644
index 000000000000..786a9b935659
--- /dev/null
+++ b/drivers/net/e1000/e1000_hw.c
@@ -0,0 +1,5405 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33#include "e1000_hw.h"
34
35static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36static void e1000_phy_init_script(struct e1000_hw *hw);
37static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
45 uint16_t count);
46static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
52 uint16_t *data);
53static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
57 uint16_t count);
58static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
59 uint16_t phy_data);
60static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
61 uint16_t *phy_data);
62static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70
71/* IGP cable length table */
72static const
73uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
74 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
75 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
76 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
77 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
78 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
79 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82
83
84/******************************************************************************
85 * Set the phy type member in the hw struct.
86 *
87 * hw - Struct containing variables accessed by shared code
88 *****************************************************************************/
89int32_t
90e1000_set_phy_type(struct e1000_hw *hw)
91{
92 DEBUGFUNC("e1000_set_phy_type");
93
94 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88;
99 break;
100 case IGP01E1000_I_PHY_ID:
101 if(hw->mac_type == e1000_82541 ||
102 hw->mac_type == e1000_82541_rev_2 ||
103 hw->mac_type == e1000_82547 ||
104 hw->mac_type == e1000_82547_rev_2) {
105 hw->phy_type = e1000_phy_igp;
106 break;
107 }
108 /* Fall Through */
109 default:
110 /* Should never have loaded on this device */
111 hw->phy_type = e1000_phy_undefined;
112 return -E1000_ERR_PHY_TYPE;
113 }
114
115 return E1000_SUCCESS;
116}
117
118/******************************************************************************
119 * IGP phy init script - initializes the GbE PHY
120 *
121 * hw - Struct containing variables accessed by shared code
122 *****************************************************************************/
123static void
124e1000_phy_init_script(struct e1000_hw *hw)
125{
126 uint32_t ret_val;
127 uint16_t phy_saved_data;
128
129 DEBUGFUNC("e1000_phy_init_script");
130
131
132 if(hw->phy_init_script) {
133 msec_delay(20);
134
135 /* Save off the current value of register 0x2F5B to be restored at
136 * the end of this routine. */
137 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
138
139 /* Disabled the PHY transmitter */
140 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
141
142 msec_delay(20);
143
144 e1000_write_phy_reg(hw,0x0000,0x0140);
145
146 msec_delay(5);
147
148 switch(hw->mac_type) {
149 case e1000_82541:
150 case e1000_82547:
151 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
152
153 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
154
155 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
156
157 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
158
159 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
160
161 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
162
163 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
164
165 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
166
167 e1000_write_phy_reg(hw, 0x2010, 0x0008);
168 break;
169
170 case e1000_82541_rev_2:
171 case e1000_82547_rev_2:
172 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
173 break;
174 default:
175 break;
176 }
177
178 e1000_write_phy_reg(hw, 0x0000, 0x3300);
179
180 msec_delay(20);
181
182 /* Now enable the transmitter */
183 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
184
185 if(hw->mac_type == e1000_82547) {
186 uint16_t fused, fine, coarse;
187
188 /* Move to analog registers page */
189 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
190
191 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
192 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
193
194 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
195 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
196
197 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
198 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202
203 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
204 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
205 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
206
207 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
208 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
209 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
210 }
211 }
212 }
213}
214
215/******************************************************************************
216 * Set the mac type member in the hw struct.
217 *
218 * hw - Struct containing variables accessed by shared code
219 *****************************************************************************/
220int32_t
221e1000_set_mac_type(struct e1000_hw *hw)
222{
223 DEBUGFUNC("e1000_set_mac_type");
224
225 switch (hw->device_id) {
226 case E1000_DEV_ID_82542:
227 switch (hw->revision_id) {
228 case E1000_82542_2_0_REV_ID:
229 hw->mac_type = e1000_82542_rev2_0;
230 break;
231 case E1000_82542_2_1_REV_ID:
232 hw->mac_type = e1000_82542_rev2_1;
233 break;
234 default:
235 /* Invalid 82542 revision ID */
236 return -E1000_ERR_MAC_TYPE;
237 }
238 break;
239 case E1000_DEV_ID_82543GC_FIBER:
240 case E1000_DEV_ID_82543GC_COPPER:
241 hw->mac_type = e1000_82543;
242 break;
243 case E1000_DEV_ID_82544EI_COPPER:
244 case E1000_DEV_ID_82544EI_FIBER:
245 case E1000_DEV_ID_82544GC_COPPER:
246 case E1000_DEV_ID_82544GC_LOM:
247 hw->mac_type = e1000_82544;
248 break;
249 case E1000_DEV_ID_82540EM:
250 case E1000_DEV_ID_82540EM_LOM:
251 case E1000_DEV_ID_82540EP:
252 case E1000_DEV_ID_82540EP_LOM:
253 case E1000_DEV_ID_82540EP_LP:
254 hw->mac_type = e1000_82540;
255 break;
256 case E1000_DEV_ID_82545EM_COPPER:
257 case E1000_DEV_ID_82545EM_FIBER:
258 hw->mac_type = e1000_82545;
259 break;
260 case E1000_DEV_ID_82545GM_COPPER:
261 case E1000_DEV_ID_82545GM_FIBER:
262 case E1000_DEV_ID_82545GM_SERDES:
263 hw->mac_type = e1000_82545_rev_3;
264 break;
265 case E1000_DEV_ID_82546EB_COPPER:
266 case E1000_DEV_ID_82546EB_FIBER:
267 case E1000_DEV_ID_82546EB_QUAD_COPPER:
268 hw->mac_type = e1000_82546;
269 break;
270 case E1000_DEV_ID_82546GB_COPPER:
271 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE:
274 hw->mac_type = e1000_82546_rev_3;
275 break;
276 case E1000_DEV_ID_82541EI:
277 case E1000_DEV_ID_82541EI_MOBILE:
278 hw->mac_type = e1000_82541;
279 break;
280 case E1000_DEV_ID_82541ER:
281 case E1000_DEV_ID_82541GI:
282 case E1000_DEV_ID_82541GI_LF:
283 case E1000_DEV_ID_82541GI_MOBILE:
284 hw->mac_type = e1000_82541_rev_2;
285 break;
286 case E1000_DEV_ID_82547EI:
287 hw->mac_type = e1000_82547;
288 break;
289 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2;
291 break;
292 default:
293 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE;
295 }
296
297 switch(hw->mac_type) {
298 case e1000_82541:
299 case e1000_82547:
300 case e1000_82541_rev_2:
301 case e1000_82547_rev_2:
302 hw->asf_firmware_present = TRUE;
303 break;
304 default:
305 break;
306 }
307
308 return E1000_SUCCESS;
309}
310
311/*****************************************************************************
312 * Set media type and TBI compatibility.
313 *
314 * hw - Struct containing variables accessed by shared code
315 * **************************************************************************/
316void
317e1000_set_media_type(struct e1000_hw *hw)
318{
319 uint32_t status;
320
321 DEBUGFUNC("e1000_set_media_type");
322
323 if(hw->mac_type != e1000_82543) {
324 /* tbi_compatibility is only valid on 82543 */
325 hw->tbi_compatibility_en = FALSE;
326 }
327
328 switch (hw->device_id) {
329 case E1000_DEV_ID_82545GM_SERDES:
330 case E1000_DEV_ID_82546GB_SERDES:
331 hw->media_type = e1000_media_type_internal_serdes;
332 break;
333 default:
334 if(hw->mac_type >= e1000_82543) {
335 status = E1000_READ_REG(hw, STATUS);
336 if(status & E1000_STATUS_TBIMODE) {
337 hw->media_type = e1000_media_type_fiber;
338 /* tbi_compatibility not valid on fiber */
339 hw->tbi_compatibility_en = FALSE;
340 } else {
341 hw->media_type = e1000_media_type_copper;
342 }
343 } else {
344 /* This is an 82542 (fiber only) */
345 hw->media_type = e1000_media_type_fiber;
346 }
347 }
348}
349
350/******************************************************************************
351 * Reset the transmit and receive units; mask and clear all interrupts.
352 *
353 * hw - Struct containing variables accessed by shared code
354 *****************************************************************************/
355int32_t
356e1000_reset_hw(struct e1000_hw *hw)
357{
358 uint32_t ctrl;
359 uint32_t ctrl_ext;
360 uint32_t icr;
361 uint32_t manc;
362 uint32_t led_ctrl;
363
364 DEBUGFUNC("e1000_reset_hw");
365
366 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
367 if(hw->mac_type == e1000_82542_rev2_0) {
368 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
369 e1000_pci_clear_mwi(hw);
370 }
371
372 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff);
375
376 /* Disable the Transmit and Receive units. Then delay to allow
377 * any pending transactions to complete before we hit the MAC with
378 * the global reset.
379 */
380 E1000_WRITE_REG(hw, RCTL, 0);
381 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
382 E1000_WRITE_FLUSH(hw);
383
384 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
385 hw->tbi_compatibility_on = FALSE;
386
387 /* Delay to allow any outstanding PCI transactions to complete before
388 * resetting the device
389 */
390 msec_delay(10);
391
392 ctrl = E1000_READ_REG(hw, CTRL);
393
394 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5);
398 }
399
400 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self-
403 * clearing, and should clear within a microsecond.
404 */
405 DEBUGOUT("Issuing a global reset to MAC\n");
406
407 switch(hw->mac_type) {
408 case e1000_82544:
409 case e1000_82540:
410 case e1000_82545:
411 case e1000_82546:
412 case e1000_82541:
413 case e1000_82541_rev_2:
414 /* These controllers can't ack the 64-bit write when issuing the
415 * reset, so use IO-mapping as a workaround to issue the reset */
416 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
417 break;
418 case e1000_82545_rev_3:
419 case e1000_82546_rev_3:
420 /* Reset is performed on a shadow of the control register */
421 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
422 break;
423 default:
424 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
425 break;
426 }
427
428 /* After MAC reset, force reload of EEPROM to restore power-on settings to
429 * device. Later controllers reload the EEPROM automatically, so just wait
430 * for reload to complete.
431 */
432 switch(hw->mac_type) {
433 case e1000_82542_rev2_0:
434 case e1000_82542_rev2_1:
435 case e1000_82543:
436 case e1000_82544:
437 /* Wait for reset to complete */
438 udelay(10);
439 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
440 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
441 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
442 E1000_WRITE_FLUSH(hw);
443 /* Wait for EEPROM reload */
444 msec_delay(2);
445 break;
446 case e1000_82541:
447 case e1000_82541_rev_2:
448 case e1000_82547:
449 case e1000_82547_rev_2:
450 /* Wait for EEPROM reload */
451 msec_delay(20);
452 break;
453 default:
454 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5);
456 break;
457 }
458
459 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) {
461 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc);
464 }
465
466 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
467 e1000_phy_init_script(hw);
468
469 /* Configure activity LED after PHY reset */
470 led_ctrl = E1000_READ_REG(hw, LEDCTL);
471 led_ctrl &= IGP_ACTIVITY_LED_MASK;
472 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
473 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
474 }
475
476 /* Clear interrupt mask to stop board from generating interrupts */
477 DEBUGOUT("Masking off all interrupts\n");
478 E1000_WRITE_REG(hw, IMC, 0xffffffff);
479
480 /* Clear any pending interrupt events. */
481 icr = E1000_READ_REG(hw, ICR);
482
483 /* If MWI was previously enabled, reenable it. */
484 if(hw->mac_type == e1000_82542_rev2_0) {
485 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
486 e1000_pci_set_mwi(hw);
487 }
488
489 return E1000_SUCCESS;
490}
491
492/******************************************************************************
493 * Performs basic configuration of the adapter.
494 *
495 * hw - Struct containing variables accessed by shared code
496 *
497 * Assumes that the controller has previously been reset and is in a
498 * post-reset uninitialized state. Initializes the receive address registers,
499 * multicast table, and VLAN filter table. Calls routines to setup link
500 * configuration and flow control settings. Clears all on-chip counters. Leaves
501 * the transmit and receive units disabled and uninitialized.
502 *****************************************************************************/
503int32_t
504e1000_init_hw(struct e1000_hw *hw)
505{
506 uint32_t ctrl;
507 uint32_t i;
508 int32_t ret_val;
509 uint16_t pcix_cmd_word;
510 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc;
513 DEBUGFUNC("e1000_init_hw");
514
515 /* Initialize Identification LED */
516 ret_val = e1000_id_led_init(hw);
517 if(ret_val) {
518 DEBUGOUT("Error Initializing Identification LED\n");
519 return ret_val;
520 }
521
522 /* Set the media type and TBI compatibility */
523 e1000_set_media_type(hw);
524
525 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0);
528
529 e1000_clear_vfta(hw);
530
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
532 if(hw->mac_type == e1000_82542_rev2_0) {
533 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
534 e1000_pci_clear_mwi(hw);
535 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
536 E1000_WRITE_FLUSH(hw);
537 msec_delay(5);
538 }
539
540 /* Setup the receive address. This involves initializing all of the Receive
541 * Address Registers (RARs 0 - 15).
542 */
543 e1000_init_rx_addrs(hw);
544
545 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
546 if(hw->mac_type == e1000_82542_rev2_0) {
547 E1000_WRITE_REG(hw, RCTL, 0);
548 E1000_WRITE_FLUSH(hw);
549 msec_delay(1);
550 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
551 e1000_pci_set_mwi(hw);
552 }
553
554 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558
559 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives.
562 */
563 if(hw->dma_fairness) {
564 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 }
567
568 switch(hw->mac_type) {
569 case e1000_82545_rev_3:
570 case e1000_82546_rev_3:
571 break;
572 default:
573 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
574 if(hw->bus_type == e1000_bus_type_pcix) {
575 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
576 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
577 &pcix_stat_hi_word);
578 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
579 PCIX_COMMAND_MMRBC_SHIFT;
580 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
581 PCIX_STATUS_HI_MMRBC_SHIFT;
582 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
583 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
584 if(cmd_mmrbc > stat_mmrbc) {
585 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
586 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
587 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
588 &pcix_cmd_word);
589 }
590 }
591 break;
592 }
593
594 /* Call a subroutine to configure the link and setup flow control. */
595 ret_val = e1000_setup_link(hw);
596
597 /* Set the transmit descriptor write-back policy */
598 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
601 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 }
603
604 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there
607 * is no link.
608 */
609 e1000_clear_hw_cntrs(hw);
610
611 return ret_val;
612}
613
614/******************************************************************************
615 * Adjust SERDES output amplitude based on EEPROM setting.
616 *
617 * hw - Struct containing variables accessed by shared code.
618 *****************************************************************************/
619static int32_t
620e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
621{
622 uint16_t eeprom_data;
623 int32_t ret_val;
624
625 DEBUGFUNC("e1000_adjust_serdes_amplitude");
626
627 if(hw->media_type != e1000_media_type_internal_serdes)
628 return E1000_SUCCESS;
629
630 switch(hw->mac_type) {
631 case e1000_82545_rev_3:
632 case e1000_82546_rev_3:
633 break;
634 default:
635 return E1000_SUCCESS;
636 }
637
638 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
639 if (ret_val) {
640 return ret_val;
641 }
642
643 if(eeprom_data != EEPROM_RESERVED_WORD) {
644 /* Adjust SERDES output amplitude only. */
645 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
646 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
647 if(ret_val)
648 return ret_val;
649 }
650
651 return E1000_SUCCESS;
652}
653
654/******************************************************************************
655 * Configures flow control and link settings.
656 *
657 * hw - Struct containing variables accessed by shared code
658 *
659 * Determines which flow control settings to use. Calls the apropriate media-
660 * specific link configuration function. Configures the flow control settings.
661 * Assuming the adapter has a valid link partner, a valid link should be
662 * established. Assumes the hardware has previously been reset and the
663 * transmitter and receiver are not enabled.
664 *****************************************************************************/
665int32_t
666e1000_setup_link(struct e1000_hw *hw)
667{
668 uint32_t ctrl_ext;
669 int32_t ret_val;
670 uint16_t eeprom_data;
671
672 DEBUGFUNC("e1000_setup_link");
673
674 /* Read and store word 0x0F of the EEPROM. This word contains bits
675 * that determine the hardware's default PAUSE (flow control) mode,
676 * a bit that determines whether the HW defaults to enabling or
677 * disabling auto-negotiation, and the direction of the
678 * SW defined pins. If there is no SW over-ride of the flow
679 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM.
681 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
683 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM;
685 }
686
687 if(hw->fc == e1000_fc_default) {
688 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
689 hw->fc = e1000_fc_none;
690 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
691 EEPROM_WORD0F_ASM_DIR)
692 hw->fc = e1000_fc_tx_pause;
693 else
694 hw->fc = e1000_fc_full;
695 }
696
697 /* We want to save off the original Flow Control configuration just
698 * in case we get disconnected and then reconnected into a different
699 * hub or switch with different Flow Control capabilities.
700 */
701 if(hw->mac_type == e1000_82542_rev2_0)
702 hw->fc &= (~e1000_fc_tx_pause);
703
704 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
705 hw->fc &= (~e1000_fc_rx_pause);
706
707 hw->original_fc = hw->fc;
708
709 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
710
711 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
712 * polarity value for the SW controlled pins, and setup the
713 * Extended Device Control reg with that info.
714 * This is needed because one of the SW controlled pins is used for
715 * signal detection. So this should be done before e1000_setup_pcs_link()
716 * or e1000_phy_setup() is called.
717 */
718 if(hw->mac_type == e1000_82543) {
719 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
720 SWDPIO__EXT_SHIFT);
721 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
722 }
723
724 /* Call the necessary subroutine to configure the link. */
725 ret_val = (hw->media_type == e1000_media_type_copper) ?
726 e1000_setup_copper_link(hw) :
727 e1000_setup_fiber_serdes_link(hw);
728
729 /* Initialize the flow control address, type, and PAUSE timer
730 * registers to their default values. This is done even if flow
731 * control is disabled, because it does not hurt anything to
732 * initialize these registers.
733 */
734 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
735
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740
741 /* Set the flow control receive threshold registers. Normally,
742 * these registers will be set to a default threshold that may be
743 * adjusted later by the driver's runtime code. However, if the
744 * ability to transmit pause frames in not enabled, then these
745 * registers will be set to 0.
746 */
747 if(!(hw->fc & e1000_fc_tx_pause)) {
748 E1000_WRITE_REG(hw, FCRTL, 0);
749 E1000_WRITE_REG(hw, FCRTH, 0);
750 } else {
751 /* We need to set up the Receive Threshold high and low water marks
752 * as well as (optionally) enabling the transmission of XON frames.
753 */
754 if(hw->fc_send_xon) {
755 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
756 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
757 } else {
758 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
759 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
760 }
761 }
762 return ret_val;
763}
764
765/******************************************************************************
766 * Sets up link for a fiber based or serdes based adapter
767 *
768 * hw - Struct containing variables accessed by shared code
769 *
770 * Manipulates Physical Coding Sublayer functions in order to configure
771 * link. Assumes the hardware has been previously reset and the transmitter
772 * and receiver are not enabled.
773 *****************************************************************************/
774static int32_t
775e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
776{
777 uint32_t ctrl;
778 uint32_t status;
779 uint32_t txcw = 0;
780 uint32_t i;
781 uint32_t signal = 0;
782 int32_t ret_val;
783
784 DEBUGFUNC("e1000_setup_fiber_serdes_link");
785
786 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
787 * set when the optics detect a signal. On older adapters, it will be
788 * cleared when there is a signal. This applies to fiber media only.
789 * If we're on serdes media, adjust the output amplitude to value set in
790 * the EEPROM.
791 */
792 ctrl = E1000_READ_REG(hw, CTRL);
793 if(hw->media_type == e1000_media_type_fiber)
794 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
795
796 ret_val = e1000_adjust_serdes_amplitude(hw);
797 if(ret_val)
798 return ret_val;
799
800 /* Take the link out of reset */
801 ctrl &= ~(E1000_CTRL_LRST);
802
803 /* Adjust VCO speed to improve BER performance */
804 ret_val = e1000_set_vco_speed(hw);
805 if(ret_val)
806 return ret_val;
807
808 e1000_config_collision_dist(hw);
809
810 /* Check for a software override of the flow control settings, and setup
811 * the device accordingly. If auto-negotiation is enabled, then software
812 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
813 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
814 * auto-negotiation is disabled, then software will have to manually
815 * configure the two flow control enable bits in the CTRL register.
816 *
817 * The possible values of the "fc" parameter are:
818 * 0: Flow control is completely disabled
819 * 1: Rx flow control is enabled (we can receive pause frames, but
820 * not send pause frames).
821 * 2: Tx flow control is enabled (we can send pause frames but we do
822 * not support receiving pause frames).
823 * 3: Both Rx and TX flow control (symmetric) are enabled.
824 */
825 switch (hw->fc) {
826 case e1000_fc_none:
827 /* Flow control is completely disabled by a software over-ride. */
828 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
829 break;
830 case e1000_fc_rx_pause:
831 /* RX Flow control is enabled and TX Flow control is disabled by a
832 * software over-ride. Since there really isn't a way to advertise
833 * that we are capable of RX Pause ONLY, we will advertise that we
834 * support both symmetric and asymmetric RX PAUSE. Later, we will
835 * disable the adapter's ability to send PAUSE frames.
836 */
837 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
838 break;
839 case e1000_fc_tx_pause:
840 /* TX Flow control is enabled, and RX Flow control is disabled, by a
841 * software over-ride.
842 */
843 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
844 break;
845 case e1000_fc_full:
846 /* Flow control (both RX and TX) is enabled by a software over-ride. */
847 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
848 break;
849 default:
850 DEBUGOUT("Flow control param set incorrectly\n");
851 return -E1000_ERR_CONFIG;
852 break;
853 }
854
855 /* Since auto-negotiation is enabled, take the link out of reset (the link
856 * will be in reset, because we previously reset the chip). This will
857 * restart auto-negotiation. If auto-neogtiation is successful then the
858 * link-up status bit will be set and the flow control enable bits (RFCE
859 * and TFCE) will be set according to their negotiated value.
860 */
861 DEBUGOUT("Auto-negotiation enabled\n");
862
863 E1000_WRITE_REG(hw, TXCW, txcw);
864 E1000_WRITE_REG(hw, CTRL, ctrl);
865 E1000_WRITE_FLUSH(hw);
866
867 hw->txcw = txcw;
868 msec_delay(1);
869
870 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
871 * indication in the Device Status Register. Time-out if a link isn't
872 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
873 * less than 500 milliseconds even if the other end is doing it in SW).
874 * For internal serdes, we just assume a signal is present, then poll.
875 */
876 if(hw->media_type == e1000_media_type_internal_serdes ||
877 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
878 DEBUGOUT("Looking for Link\n");
879 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
880 msec_delay(10);
881 status = E1000_READ_REG(hw, STATUS);
882 if(status & E1000_STATUS_LU) break;
883 }
884 if(i == (LINK_UP_TIMEOUT / 10)) {
885 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
886 hw->autoneg_failed = 1;
887 /* AutoNeg failed to achieve a link, so we'll call
888 * e1000_check_for_link. This routine will force the link up if
889 * we detect a signal. This will allow us to communicate with
890 * non-autonegotiating link partners.
891 */
892 ret_val = e1000_check_for_link(hw);
893 if(ret_val) {
894 DEBUGOUT("Error while checking for link\n");
895 return ret_val;
896 }
897 hw->autoneg_failed = 0;
898 } else {
899 hw->autoneg_failed = 0;
900 DEBUGOUT("Valid Link Found\n");
901 }
902 } else {
903 DEBUGOUT("No Signal Detected\n");
904 }
905 return E1000_SUCCESS;
906}
907
908/******************************************************************************
909* Detects which PHY is present and the speed and duplex
910*
911* hw - Struct containing variables accessed by shared code
912******************************************************************************/
913static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw)
915{
916 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data;
921
922 DEBUGFUNC("e1000_setup_copper_link");
923
924 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what
926 * the PHY speed and duplex configuration is. In addition, we need to
927 * perform a hardware reset on the PHY to take it out of reset.
928 */
929 if(hw->mac_type > e1000_82543) {
930 ctrl |= E1000_CTRL_SLU;
931 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
932 E1000_WRITE_REG(hw, CTRL, ctrl);
933 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw);
937 }
938
939 /* Make sure we have a valid PHY */
940 ret_val = e1000_detect_gig_phy(hw);
941 if(ret_val) {
942 DEBUGOUT("Error, did not detect valid phy.\n");
943 return ret_val;
944 }
945 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
946
947 /* Set PHY to class A mode (if necessary) */
948 ret_val = e1000_set_phy_mode(hw);
949 if(ret_val)
950 return ret_val;
951
952 if((hw->mac_type == e1000_82545_rev_3) ||
953 (hw->mac_type == e1000_82546_rev_3)) {
954 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
955 phy_data |= 0x00000008;
956 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
957 }
958
959 if(hw->mac_type <= e1000_82543 ||
960 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE;
963
964 if(!hw->phy_reset_disable) {
965 if (hw->phy_type == e1000_phy_igp) {
966
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */
974 msec_delay(15);
975
976 /* Configure activity LED after PHY reset */
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981
982 /* disable lplu d3 during driver init */
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
984 if(ret_val) {
985 DEBUGOUT("Error Disabling LPLU D3\n");
986 return ret_val;
987 }
988
989 /* Configure mdi-mdix settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
996 hw->dsp_config_state = e1000_dsp_config_disabled;
997 /* Force MDI for earlier revs of the IGP PHY */
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
999 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1000 hw->mdix = 1;
1001
1002 } else {
1003 hw->dsp_config_state = e1000_dsp_config_enabled;
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1005
1006 switch (hw->mdix) {
1007 case 1:
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023
1024 /* set auto-master slave resolution settings */
1025 if(hw->autoneg) {
1026 e1000_ms_type phy_ms_setting = hw->master_slave;
1027
1028 if(hw->ffe_config_state == e1000_ffe_config_active)
1029 hw->ffe_config_state = e1000_ffe_config_enabled;
1030
1031 if(hw->dsp_config_state == e1000_dsp_config_activated)
1032 hw->dsp_config_state = e1000_dsp_config_enabled;
1033
1034 /* when autonegotiation advertisment is only 1000Mbps then we
1035 * should disable SmartSpeed and enable Auto MasterSlave
1036 * resolution as hardware default. */
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1038 /* Disable SmartSpeed */
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1040 &phy_data);
1041 if(ret_val)
1042 return ret_val;
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1044 ret_val = e1000_write_phy_reg(hw,
1045 IGP01E1000_PHY_PORT_CONFIG,
1046 phy_data);
1047 if(ret_val)
1048 return ret_val;
1049 /* Set auto Master/Slave resolution process */
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1060 if(ret_val)
1061 return ret_val;
1062
1063 /* load defaults for future use */
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1065 ((phy_data & CR_1000T_MS_VALUE) ?
1066 e1000_ms_force_master :
1067 e1000_ms_force_slave) :
1068 e1000_ms_auto;
1069
1070 switch (phy_ms_setting) {
1071 case e1000_ms_force_master:
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1073 break;
1074 case e1000_ms_force_slave:
1075 phy_data |= CR_1000T_MS_ENABLE;
1076 phy_data &= ~(CR_1000T_MS_VALUE);
1077 break;
1078 case e1000_ms_auto:
1079 phy_data &= ~CR_1000T_MS_ENABLE;
1080 default:
1081 break;
1082 }
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084 if(ret_val)
1085 return ret_val;
1086 }
1087 } else {
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val)
1092 return ret_val;
1093
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1095
1096 /* Options:
1097 * MDI/MDI-X = 0 (default)
1098 * 0 - Auto for all speeds
1099 * 1 - MDI mode
1100 * 2 - MDI-X mode
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104
1105 switch (hw->mdix) {
1106 case 1:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1108 break;
1109 case 2:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1111 break;
1112 case 3:
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1114 break;
1115 case 0:
1116 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1118 break;
1119 }
1120
1121 /* Options:
1122 * disable_polarity_correction = 0 (default)
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1144
1145 if (hw->phy_revision < M88E1011_I_REV_4) {
1146 /* Configure Master and Slave downshift values */
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152 phy_data);
1153 if(ret_val)
1154 return ret_val;
1155 }
1156
1157 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val;
1162 }
1163 }
1164
1165 /* Options:
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173
1174 /* Is autoneg enabled? This is enabled by default or by software
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1193 ret_val = e1000_phy_setup_autoneg(hw);
1194 if(ret_val) {
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1196 return ret_val;
1197 }
1198 DEBUGOUT("Restarting Auto-Neg\n");
1199
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1201 * the Auto Neg Restart bit in the PHY control register.
1202 */
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1204 if(ret_val)
1205 return ret_val;
1206
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1209 if(ret_val)
1210 return ret_val;
1211
1212 /* Does the user want to wait for Auto-Neg to complete here, or
1213 * check at a later time (for example, callback routine).
1214 */
1215 if(hw->wait_autoneg_complete) {
1216 ret_val = e1000_wait_autoneg(hw);
1217 if(ret_val) {
1218 DEBUGOUT("Error while waiting for autoneg to complete\n");
1219 return ret_val;
1220 }
1221 }
1222 hw->get_link_status = TRUE;
1223 } else {
1224 DEBUGOUT("Forcing speed and duplex\n");
1225 ret_val = e1000_phy_force_speed_duplex(hw);
1226 if(ret_val) {
1227 DEBUGOUT("Error Forcing Speed and Duplex\n");
1228 return ret_val;
1229 }
1230 }
1231 } /* !hw->phy_reset_disable */
1232
1233 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid.
1235 */
1236 for(i = 0; i < 10; i++) {
1237 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1238 if(ret_val)
1239 return ret_val;
1240 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1241 if(ret_val)
1242 return ret_val;
1243
1244 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process:
1246 * 1) Set up the MAC to the current PHY speed/duplex
1247 * if we are on 82543. If we
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val;
1266 }
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS;
1278 }
1279 udelay(10);
1280 }
1281
1282 DEBUGOUT("Unable to establish link!!!\n");
1283 return E1000_SUCCESS;
1284}
1285
1286/******************************************************************************
1287* Configures PHY autoneg and flow control advertisement settings
1288*
1289* hw - Struct containing variables accessed by shared code
1290******************************************************************************/
1291int32_t
1292e1000_phy_setup_autoneg(struct e1000_hw *hw)
1293{
1294 int32_t ret_val;
1295 uint16_t mii_autoneg_adv_reg;
1296 uint16_t mii_1000t_ctrl_reg;
1297
1298 DEBUGFUNC("e1000_phy_setup_autoneg");
1299
1300 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1301 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1302 if(ret_val)
1303 return ret_val;
1304
1305 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val)
1308 return ret_val;
1309
1310 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for
1312 * autoneg_advertised software override. Since we can advertise
1313 * a plethora of combinations, we need to check each bit
1314 * individually.
1315 */
1316
1317 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1318 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1319 * the 1000Base-T Control Register (Address 9).
1320 */
1321 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1322 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1323
1324 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1325
1326 /* Do we want to advertise 10 Mb Half Duplex? */
1327 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1328 DEBUGOUT("Advertise 10mb Half duplex\n");
1329 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1330 }
1331
1332 /* Do we want to advertise 10 Mb Full Duplex? */
1333 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1334 DEBUGOUT("Advertise 10mb Full duplex\n");
1335 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1336 }
1337
1338 /* Do we want to advertise 100 Mb Half Duplex? */
1339 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1340 DEBUGOUT("Advertise 100mb Half duplex\n");
1341 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1342 }
1343
1344 /* Do we want to advertise 100 Mb Full Duplex? */
1345 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1346 DEBUGOUT("Advertise 100mb Full duplex\n");
1347 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1348 }
1349
1350 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1351 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1352 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1353 }
1354
1355 /* Do we want to advertise 1000 Mb Full Duplex? */
1356 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1357 DEBUGOUT("Advertise 1000mb Full duplex\n");
1358 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1359 }
1360
1361 /* Check for a software override of the flow control settings, and
1362 * setup the PHY advertisement registers accordingly. If
1363 * auto-negotiation is enabled, then software will have to set the
1364 * "PAUSE" bits to the correct value in the Auto-Negotiation
1365 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1366 *
1367 * The possible values of the "fc" parameter are:
1368 * 0: Flow control is completely disabled
1369 * 1: Rx flow control is enabled (we can receive pause frames
1370 * but not send pause frames).
1371 * 2: Tx flow control is enabled (we can send pause frames
1372 * but we do not support receiving pause frames).
1373 * 3: Both Rx and TX flow control (symmetric) are enabled.
1374 * other: No software override. The flow control configuration
1375 * in the EEPROM is used.
1376 */
1377 switch (hw->fc) {
1378 case e1000_fc_none: /* 0 */
1379 /* Flow control (RX & TX) is completely disabled by a
1380 * software over-ride.
1381 */
1382 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1383 break;
1384 case e1000_fc_rx_pause: /* 1 */
1385 /* RX Flow control is enabled, and TX Flow control is
1386 * disabled, by a software over-ride.
1387 */
1388 /* Since there really isn't a way to advertise that we are
1389 * capable of RX Pause ONLY, we will advertise that we
1390 * support both symmetric and asymmetric RX PAUSE. Later
1391 * (in e1000_config_fc_after_link_up) we will disable the
1392 *hw's ability to send PAUSE frames.
1393 */
1394 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1395 break;
1396 case e1000_fc_tx_pause: /* 2 */
1397 /* TX Flow control is enabled, and RX Flow control is
1398 * disabled, by a software over-ride.
1399 */
1400 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1401 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1402 break;
1403 case e1000_fc_full: /* 3 */
1404 /* Flow control (both RX and TX) is enabled by a software
1405 * over-ride.
1406 */
1407 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1408 break;
1409 default:
1410 DEBUGOUT("Flow control param set incorrectly\n");
1411 return -E1000_ERR_CONFIG;
1412 }
1413
1414 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1415 if(ret_val)
1416 return ret_val;
1417
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val)
1422 return ret_val;
1423
1424 return E1000_SUCCESS;
1425}
1426
1427/******************************************************************************
1428* Force PHY speed and duplex settings to hw->forced_speed_duplex
1429*
1430* hw - Struct containing variables accessed by shared code
1431******************************************************************************/
1432static int32_t
1433e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1434{
1435 uint32_t ctrl;
1436 int32_t ret_val;
1437 uint16_t mii_ctrl_reg;
1438 uint16_t mii_status_reg;
1439 uint16_t phy_data;
1440 uint16_t i;
1441
1442 DEBUGFUNC("e1000_phy_force_speed_duplex");
1443
1444 /* Turn off Flow control if we are forcing speed and duplex. */
1445 hw->fc = e1000_fc_none;
1446
1447 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1448
1449 /* Read the Device Control Register. */
1450 ctrl = E1000_READ_REG(hw, CTRL);
1451
1452 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1453 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1454 ctrl &= ~(DEVICE_SPEED_MASK);
1455
1456 /* Clear the Auto Speed Detect Enable bit. */
1457 ctrl &= ~E1000_CTRL_ASDE;
1458
1459 /* Read the MII Control Register. */
1460 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1461 if(ret_val)
1462 return ret_val;
1463
1464 /* We need to disable autoneg in order to force link and duplex. */
1465
1466 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1467
1468 /* Are we forcing Full or Half Duplex? */
1469 if(hw->forced_speed_duplex == e1000_100_full ||
1470 hw->forced_speed_duplex == e1000_10_full) {
1471 /* We want to force full duplex so we SET the full duplex bits in the
1472 * Device and MII Control Registers.
1473 */
1474 ctrl |= E1000_CTRL_FD;
1475 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1476 DEBUGOUT("Full Duplex\n");
1477 } else {
1478 /* We want to force half duplex so we CLEAR the full duplex bits in
1479 * the Device and MII Control Registers.
1480 */
1481 ctrl &= ~E1000_CTRL_FD;
1482 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1483 DEBUGOUT("Half Duplex\n");
1484 }
1485
1486 /* Are we forcing 100Mbps??? */
1487 if(hw->forced_speed_duplex == e1000_100_full ||
1488 hw->forced_speed_duplex == e1000_100_half) {
1489 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1490 ctrl |= E1000_CTRL_SPD_100;
1491 mii_ctrl_reg |= MII_CR_SPEED_100;
1492 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1493 DEBUGOUT("Forcing 100mb ");
1494 } else {
1495 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1496 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1497 mii_ctrl_reg |= MII_CR_SPEED_10;
1498 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1499 DEBUGOUT("Forcing 10mb ");
1500 }
1501
1502 e1000_config_collision_dist(hw);
1503
1504 /* Write the configured values back to the Device Control Reg. */
1505 E1000_WRITE_REG(hw, CTRL, ctrl);
1506
1507 if (hw->phy_type == e1000_phy_m88) {
1508 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1509 if(ret_val)
1510 return ret_val;
1511
1512 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1513 * forced whenever speed are duplex are forced.
1514 */
1515 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1516 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1517 if(ret_val)
1518 return ret_val;
1519
1520 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1521
1522 /* Need to reset the PHY or these changes will be ignored */
1523 mii_ctrl_reg |= MII_CR_RESET;
1524 } else {
1525 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1526 * forced whenever speed or duplex are forced.
1527 */
1528 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1529 if(ret_val)
1530 return ret_val;
1531
1532 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1533 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1534
1535 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1536 if(ret_val)
1537 return ret_val;
1538 }
1539
1540 /* Write back the modified PHY MII control register. */
1541 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1542 if(ret_val)
1543 return ret_val;
1544
1545 udelay(1);
1546
1547 /* The wait_autoneg_complete flag may be a little misleading here.
1548 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1549 * But we do want to delay for a period while forcing only so we
1550 * don't generate false No Link messages. So we will wait here
1551 * only if the user has set wait_autoneg_complete to 1, which is
1552 * the default.
1553 */
1554 if(hw->wait_autoneg_complete) {
1555 /* We will wait for autoneg to complete. */
1556 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1557 mii_status_reg = 0;
1558
1559 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1560 for(i = PHY_FORCE_TIME; i > 0; i--) {
1561 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1562 * to be set.
1563 */
1564 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1565 if(ret_val)
1566 return ret_val;
1567
1568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1569 if(ret_val)
1570 return ret_val;
1571
1572 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1573 msec_delay(100);
1574 }
1575 if((i == 0) &&
1576 (hw->phy_type == e1000_phy_m88)) {
1577 /* We didn't get link. Reset the DSP and wait again for link. */
1578 ret_val = e1000_phy_reset_dsp(hw);
1579 if(ret_val) {
1580 DEBUGOUT("Error Resetting PHY DSP\n");
1581 return ret_val;
1582 }
1583 }
1584 /* This loop will early-out if the link condition has been met. */
1585 for(i = PHY_FORCE_TIME; i > 0; i--) {
1586 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1587 msec_delay(100);
1588 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1589 * to be set.
1590 */
1591 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1592 if(ret_val)
1593 return ret_val;
1594
1595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1596 if(ret_val)
1597 return ret_val;
1598 }
1599 }
1600
1601 if (hw->phy_type == e1000_phy_m88) {
1602 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1603 * Extended PHY Specific Control Register to 25MHz clock. This value
1604 * defaults back to a 2.5MHz clock when the PHY is reset.
1605 */
1606 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1607 if(ret_val)
1608 return ret_val;
1609
1610 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1611 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1612 if(ret_val)
1613 return ret_val;
1614
1615 /* In addition, because of the s/w reset above, we need to enable CRS on
1616 * TX. This must be set for both full and half duplex operation.
1617 */
1618 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1619 if(ret_val)
1620 return ret_val;
1621
1622 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1623 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1624 if(ret_val)
1625 return ret_val;
1626
1627 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
1628 (!hw->autoneg) &&
1629 (hw->forced_speed_duplex == e1000_10_full ||
1630 hw->forced_speed_duplex == e1000_10_half)) {
1631 ret_val = e1000_polarity_reversal_workaround(hw);
1632 if(ret_val)
1633 return ret_val;
1634 }
1635 }
1636 return E1000_SUCCESS;
1637}
1638
1639/******************************************************************************
1640* Sets the collision distance in the Transmit Control register
1641*
1642* hw - Struct containing variables accessed by shared code
1643*
1644* Link should have been established previously. Reads the speed and duplex
1645* information from the Device Status register.
1646******************************************************************************/
1647void
1648e1000_config_collision_dist(struct e1000_hw *hw)
1649{
1650 uint32_t tctl;
1651
1652 DEBUGFUNC("e1000_config_collision_dist");
1653
1654 tctl = E1000_READ_REG(hw, TCTL);
1655
1656 tctl &= ~E1000_TCTL_COLD;
1657 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1658
1659 E1000_WRITE_REG(hw, TCTL, tctl);
1660 E1000_WRITE_FLUSH(hw);
1661}
1662
1663/******************************************************************************
1664* Sets MAC speed and duplex settings to reflect the those in the PHY
1665*
1666* hw - Struct containing variables accessed by shared code
1667* mii_reg - data to write to the MII control register
1668*
1669* The contents of the PHY register containing the needed information need to
1670* be passed in.
1671******************************************************************************/
1672static int32_t
1673e1000_config_mac_to_phy(struct e1000_hw *hw)
1674{
1675 uint32_t ctrl;
1676 int32_t ret_val;
1677 uint16_t phy_data;
1678
1679 DEBUGFUNC("e1000_config_mac_to_phy");
1680
1681 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex.
1683 */
1684 ctrl = E1000_READ_REG(hw, CTRL);
1685 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1686 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1687
1688 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values.
1690 */
1691 if (hw->phy_type == e1000_phy_igp) {
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1693 &phy_data);
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701
1702 /* Set up speed in the Device Control register depending on
1703 * negotiated values.
1704 */
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1718 else ctrl &= ~E1000_CTRL_FD;
1719
1720 e1000_config_collision_dist(hw);
1721
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS;
1733}
1734
1735/******************************************************************************
1736 * Forces the MAC's flow control settings.
1737 *
1738 * hw - Struct containing variables accessed by shared code
1739 *
1740 * Sets the TFCE and RFCE bits in the device control register to reflect
1741 * the adapter settings. TFCE and RFCE need to be explicitly set by
1742 * software when a Copper PHY is used because autonegotiation is managed
1743 * by the PHY rather than the MAC. Software must also configure these
1744 * bits when link is forced on a fiber connection.
1745 *****************************************************************************/
1746int32_t
1747e1000_force_mac_fc(struct e1000_hw *hw)
1748{
1749 uint32_t ctrl;
1750
1751 DEBUGFUNC("e1000_force_mac_fc");
1752
1753 /* Get the current configuration of the Device Control Register */
1754 ctrl = E1000_READ_REG(hw, CTRL);
1755
1756 /* Because we didn't get link via the internal auto-negotiation
1757 * mechanism (we either forced link or we got link via PHY
1758 * auto-neg), we have to manually enable/disable transmit an
1759 * receive flow control.
1760 *
1761 * The "Case" statement below enables/disable flow control
1762 * according to the "hw->fc" parameter.
1763 *
1764 * The possible values of the "fc" parameter are:
1765 * 0: Flow control is completely disabled
1766 * 1: Rx flow control is enabled (we can receive pause
1767 * frames but not send pause frames).
1768 * 2: Tx flow control is enabled (we can send pause frames
1769 * frames but we do not receive pause frames).
1770 * 3: Both Rx and TX flow control (symmetric) is enabled.
1771 * other: No other values should be possible at this point.
1772 */
1773
1774 switch (hw->fc) {
1775 case e1000_fc_none:
1776 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1777 break;
1778 case e1000_fc_rx_pause:
1779 ctrl &= (~E1000_CTRL_TFCE);
1780 ctrl |= E1000_CTRL_RFCE;
1781 break;
1782 case e1000_fc_tx_pause:
1783 ctrl &= (~E1000_CTRL_RFCE);
1784 ctrl |= E1000_CTRL_TFCE;
1785 break;
1786 case e1000_fc_full:
1787 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1788 break;
1789 default:
1790 DEBUGOUT("Flow control param set incorrectly\n");
1791 return -E1000_ERR_CONFIG;
1792 }
1793
1794 /* Disable TX Flow Control for 82542 (rev 2.0) */
1795 if(hw->mac_type == e1000_82542_rev2_0)
1796 ctrl &= (~E1000_CTRL_TFCE);
1797
1798 E1000_WRITE_REG(hw, CTRL, ctrl);
1799 return E1000_SUCCESS;
1800}
1801
1802/******************************************************************************
1803 * Configures flow control settings after link is established
1804 *
1805 * hw - Struct containing variables accessed by shared code
1806 *
1807 * Should be called immediately after a valid link has been established.
1808 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1809 * and autonegotiation is enabled, the MAC flow control settings will be set
1810 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1811 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1812 *****************************************************************************/
1813int32_t
1814e1000_config_fc_after_link_up(struct e1000_hw *hw)
1815{
1816 int32_t ret_val;
1817 uint16_t mii_status_reg;
1818 uint16_t mii_nway_adv_reg;
1819 uint16_t mii_nway_lp_ability_reg;
1820 uint16_t speed;
1821 uint16_t duplex;
1822
1823 DEBUGFUNC("e1000_config_fc_after_link_up");
1824
1825 /* Check for the case where we have fiber media and auto-neg failed
1826 * so we had to force link. In this case, we need to force the
1827 * configuration of the MAC to match the "fc" parameter.
1828 */
1829 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1830 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1831 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1832 ret_val = e1000_force_mac_fc(hw);
1833 if(ret_val) {
1834 DEBUGOUT("Error forcing flow control settings\n");
1835 return ret_val;
1836 }
1837 }
1838
1839 /* Check for the case where we have copper media and auto-neg is
1840 * enabled. In this case, we need to check and see if Auto-Neg
1841 * has completed, and if so, how the PHY and link partner has
1842 * flow control configured.
1843 */
1844 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1845 /* Read the MII Status Register and check to see if AutoNeg
1846 * has completed. We read this twice because this reg has
1847 * some "sticky" (latched) bits.
1848 */
1849 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1850 if(ret_val)
1851 return ret_val;
1852 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1853 if(ret_val)
1854 return ret_val;
1855
1856 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1857 /* The AutoNeg process has completed, so we now need to
1858 * read both the Auto Negotiation Advertisement Register
1859 * (Address 4) and the Auto_Negotiation Base Page Ability
1860 * Register (Address 5) to determine how flow control was
1861 * negotiated.
1862 */
1863 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1864 &mii_nway_adv_reg);
1865 if(ret_val)
1866 return ret_val;
1867 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1868 &mii_nway_lp_ability_reg);
1869 if(ret_val)
1870 return ret_val;
1871
1872 /* Two bits in the Auto Negotiation Advertisement Register
1873 * (Address 4) and two bits in the Auto Negotiation Base
1874 * Page Ability Register (Address 5) determine flow control
1875 * for both the PHY and the link partner. The following
1876 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1877 * 1999, describes these PAUSE resolution bits and how flow
1878 * control is determined based upon these settings.
1879 * NOTE: DC = Don't Care
1880 *
1881 * LOCAL DEVICE | LINK PARTNER
1882 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1883 *-------|---------|-------|---------|--------------------
1884 * 0 | 0 | DC | DC | e1000_fc_none
1885 * 0 | 1 | 0 | DC | e1000_fc_none
1886 * 0 | 1 | 1 | 0 | e1000_fc_none
1887 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1888 * 1 | 0 | 0 | DC | e1000_fc_none
1889 * 1 | DC | 1 | DC | e1000_fc_full
1890 * 1 | 1 | 0 | 0 | e1000_fc_none
1891 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1892 *
1893 */
1894 /* Are both PAUSE bits set to 1? If so, this implies
1895 * Symmetric Flow Control is enabled at both ends. The
1896 * ASM_DIR bits are irrelevant per the spec.
1897 *
1898 * For Symmetric Flow Control:
1899 *
1900 * LOCAL DEVICE | LINK PARTNER
1901 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1902 *-------|---------|-------|---------|--------------------
1903 * 1 | DC | 1 | DC | e1000_fc_full
1904 *
1905 */
1906 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1907 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1908 /* Now we need to check if the user selected RX ONLY
1909 * of pause frames. In this case, we had to advertise
1910 * FULL flow control because we could not advertise RX
1911 * ONLY. Hence, we must now check to see if we need to
1912 * turn OFF the TRANSMISSION of PAUSE frames.
1913 */
1914 if(hw->original_fc == e1000_fc_full) {
1915 hw->fc = e1000_fc_full;
1916 DEBUGOUT("Flow Control = FULL.\r\n");
1917 } else {
1918 hw->fc = e1000_fc_rx_pause;
1919 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1920 }
1921 }
1922 /* For receiving PAUSE frames ONLY.
1923 *
1924 * LOCAL DEVICE | LINK PARTNER
1925 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1926 *-------|---------|-------|---------|--------------------
1927 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1928 *
1929 */
1930 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1931 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1932 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1933 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1934 hw->fc = e1000_fc_tx_pause;
1935 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1936 }
1937 /* For transmitting PAUSE frames ONLY.
1938 *
1939 * LOCAL DEVICE | LINK PARTNER
1940 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1941 *-------|---------|-------|---------|--------------------
1942 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1943 *
1944 */
1945 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1946 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1947 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1948 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1949 hw->fc = e1000_fc_rx_pause;
1950 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1951 }
1952 /* Per the IEEE spec, at this point flow control should be
1953 * disabled. However, we want to consider that we could
1954 * be connected to a legacy switch that doesn't advertise
1955 * desired flow control, but can be forced on the link
1956 * partner. So if we advertised no flow control, that is
1957 * what we will resolve to. If we advertised some kind of
1958 * receive capability (Rx Pause Only or Full Flow Control)
1959 * and the link partner advertised none, we will configure
1960 * ourselves to enable Rx Flow Control only. We can do
1961 * this safely for two reasons: If the link partner really
1962 * didn't want flow control enabled, and we enable Rx, no
1963 * harm done since we won't be receiving any PAUSE frames
1964 * anyway. If the intent on the link partner was to have
1965 * flow control enabled, then by us enabling RX only, we
1966 * can at least receive pause frames and process them.
1967 * This is a good idea because in most cases, since we are
1968 * predominantly a server NIC, more times than not we will
1969 * be asked to delay transmission of packets than asking
1970 * our link partner to pause transmission of frames.
1971 */
1972 else if((hw->original_fc == e1000_fc_none ||
1973 hw->original_fc == e1000_fc_tx_pause) ||
1974 hw->fc_strict_ieee) {
1975 hw->fc = e1000_fc_none;
1976 DEBUGOUT("Flow Control = NONE.\r\n");
1977 } else {
1978 hw->fc = e1000_fc_rx_pause;
1979 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1980 }
1981
1982 /* Now we need to do one last check... If we auto-
1983 * negotiated to HALF DUPLEX, flow control should not be
1984 * enabled per IEEE 802.3 spec.
1985 */
1986 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1987 if(ret_val) {
1988 DEBUGOUT("Error getting link speed and duplex\n");
1989 return ret_val;
1990 }
1991
1992 if(duplex == HALF_DUPLEX)
1993 hw->fc = e1000_fc_none;
1994
1995 /* Now we call a subroutine to actually force the MAC
1996 * controller to use the correct flow control settings.
1997 */
1998 ret_val = e1000_force_mac_fc(hw);
1999 if(ret_val) {
2000 DEBUGOUT("Error forcing flow control settings\n");
2001 return ret_val;
2002 }
2003 } else {
2004 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2005 }
2006 }
2007 return E1000_SUCCESS;
2008}
2009
2010/******************************************************************************
2011 * Checks to see if the link status of the hardware has changed.
2012 *
2013 * hw - Struct containing variables accessed by shared code
2014 *
2015 * Called by any function that needs to check the link status of the adapter.
2016 *****************************************************************************/
2017int32_t
2018e1000_check_for_link(struct e1000_hw *hw)
2019{
2020 uint32_t rxcw = 0;
2021 uint32_t ctrl;
2022 uint32_t status;
2023 uint32_t rctl;
2024 uint32_t icr;
2025 uint32_t signal = 0;
2026 int32_t ret_val;
2027 uint16_t phy_data;
2028
2029 DEBUGFUNC("e1000_check_for_link");
2030
2031 ctrl = E1000_READ_REG(hw, CTRL);
2032 status = E1000_READ_REG(hw, STATUS);
2033
2034 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2035 * set when the optics detect a signal. On older adapters, it will be
2036 * cleared when there is a signal. This applies to fiber media only.
2037 */
2038 if((hw->media_type == e1000_media_type_fiber) ||
2039 (hw->media_type == e1000_media_type_internal_serdes)) {
2040 rxcw = E1000_READ_REG(hw, RXCW);
2041
2042 if(hw->media_type == e1000_media_type_fiber) {
2043 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2044 if(status & E1000_STATUS_LU)
2045 hw->get_link_status = FALSE;
2046 }
2047 }
2048
2049 /* If we have a copper PHY then we only want to go out to the PHY
2050 * registers to see if Auto-Neg has completed and/or if our link
2051 * status has changed. The get_link_status flag will be set if we
2052 * receive a Link Status Change interrupt or we have Rx Sequence
2053 * Errors.
2054 */
2055 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2056 /* First we want to see if the MII Status Register reports
2057 * link. If so, then we want to get the current speed/duplex
2058 * of the PHY.
2059 * Read the register twice since the link bit is sticky.
2060 */
2061 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2062 if(ret_val)
2063 return ret_val;
2064 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2065 if(ret_val)
2066 return ret_val;
2067
2068 if(phy_data & MII_SR_LINK_STATUS) {
2069 hw->get_link_status = FALSE;
2070 /* Check if there was DownShift, must be checked immediately after
2071 * link-up */
2072 e1000_check_downshift(hw);
2073
2074 /* If we are on 82544 or 82543 silicon and speed/duplex
2075 * are forced to 10H or 10F, then we will implement the polarity
2076 * reversal workaround. We disable interrupts first, and upon
2077 * returning, place the devices interrupt state to its previous
2078 * value except for the link status change interrupt which will
2079 * happen due to the execution of this workaround.
2080 */
2081
2082 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2083 (!hw->autoneg) &&
2084 (hw->forced_speed_duplex == e1000_10_full ||
2085 hw->forced_speed_duplex == e1000_10_half)) {
2086 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2087 ret_val = e1000_polarity_reversal_workaround(hw);
2088 icr = E1000_READ_REG(hw, ICR);
2089 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2090 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2091 }
2092
2093 } else {
2094 /* No link detected */
2095 e1000_config_dsp_after_link_change(hw, FALSE);
2096 return 0;
2097 }
2098
2099 /* If we are forcing speed/duplex, then we simply return since
2100 * we have already determined whether we have link or not.
2101 */
2102 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2103
2104 /* optimize the dsp settings for the igp phy */
2105 e1000_config_dsp_after_link_change(hw, TRUE);
2106
2107 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2108 * have Si on board that is 82544 or newer, Auto
2109 * Speed Detection takes care of MAC speed/duplex
2110 * configuration. So we only need to configure Collision
2111 * Distance in the MAC. Otherwise, we need to force
2112 * speed/duplex on the MAC to the current PHY speed/duplex
2113 * settings.
2114 */
2115 if(hw->mac_type >= e1000_82544)
2116 e1000_config_collision_dist(hw);
2117 else {
2118 ret_val = e1000_config_mac_to_phy(hw);
2119 if(ret_val) {
2120 DEBUGOUT("Error configuring MAC to PHY settings\n");
2121 return ret_val;
2122 }
2123 }
2124
2125 /* Configure Flow Control now that Auto-Neg has completed. First, we
2126 * need to restore the desired flow control settings because we may
2127 * have had to re-autoneg with a different link partner.
2128 */
2129 ret_val = e1000_config_fc_after_link_up(hw);
2130 if(ret_val) {
2131 DEBUGOUT("Error configuring flow control\n");
2132 return ret_val;
2133 }
2134
2135 /* At this point we know that we are on copper and we have
2136 * auto-negotiated link. These are conditions for checking the link
2137 * partner capability register. We use the link speed to determine if
2138 * TBI compatibility needs to be turned on or off. If the link is not
2139 * at gigabit speed, then TBI compatibility is not needed. If we are
2140 * at gigabit speed, we turn on TBI compatibility.
2141 */
2142 if(hw->tbi_compatibility_en) {
2143 uint16_t speed, duplex;
2144 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2145 if(speed != SPEED_1000) {
2146 /* If link speed is not set to gigabit speed, we do not need
2147 * to enable TBI compatibility.
2148 */
2149 if(hw->tbi_compatibility_on) {
2150 /* If we previously were in the mode, turn it off. */
2151 rctl = E1000_READ_REG(hw, RCTL);
2152 rctl &= ~E1000_RCTL_SBP;
2153 E1000_WRITE_REG(hw, RCTL, rctl);
2154 hw->tbi_compatibility_on = FALSE;
2155 }
2156 } else {
2157 /* If TBI compatibility is was previously off, turn it on. For
2158 * compatibility with a TBI link partner, we will store bad
2159 * packets. Some frames have an additional byte on the end and
2160 * will look like CRC errors to to the hardware.
2161 */
2162 if(!hw->tbi_compatibility_on) {
2163 hw->tbi_compatibility_on = TRUE;
2164 rctl = E1000_READ_REG(hw, RCTL);
2165 rctl |= E1000_RCTL_SBP;
2166 E1000_WRITE_REG(hw, RCTL, rctl);
2167 }
2168 }
2169 }
2170 }
2171 /* If we don't have link (auto-negotiation failed or link partner cannot
2172 * auto-negotiate), the cable is plugged in (we have signal), and our
2173 * link partner is not trying to auto-negotiate with us (we are receiving
2174 * idles or data), we need to force link up. We also need to give
2175 * auto-negotiation time to complete, in case the cable was just plugged
2176 * in. The autoneg_failed flag does this.
2177 */
2178 else if((((hw->media_type == e1000_media_type_fiber) &&
2179 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2180 (hw->media_type == e1000_media_type_internal_serdes)) &&
2181 (!(status & E1000_STATUS_LU)) &&
2182 (!(rxcw & E1000_RXCW_C))) {
2183 if(hw->autoneg_failed == 0) {
2184 hw->autoneg_failed = 1;
2185 return 0;
2186 }
2187 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2188
2189 /* Disable auto-negotiation in the TXCW register */
2190 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2191
2192 /* Force link-up and also force full-duplex. */
2193 ctrl = E1000_READ_REG(hw, CTRL);
2194 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2195 E1000_WRITE_REG(hw, CTRL, ctrl);
2196
2197 /* Configure Flow Control after forcing link up. */
2198 ret_val = e1000_config_fc_after_link_up(hw);
2199 if(ret_val) {
2200 DEBUGOUT("Error configuring flow control\n");
2201 return ret_val;
2202 }
2203 }
2204 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2205 * auto-negotiation in the TXCW register and disable forced link in the
2206 * Device Control register in an attempt to auto-negotiate with our link
2207 * partner.
2208 */
2209 else if(((hw->media_type == e1000_media_type_fiber) ||
2210 (hw->media_type == e1000_media_type_internal_serdes)) &&
2211 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2212 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2213 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2214 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2215
2216 hw->serdes_link_down = FALSE;
2217 }
2218 /* If we force link for non-auto-negotiation switch, check link status
2219 * based on MAC synchronization for internal serdes media type.
2220 */
2221 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2222 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2223 /* SYNCH bit and IV bit are sticky. */
2224 udelay(10);
2225 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2226 if(!(rxcw & E1000_RXCW_IV)) {
2227 hw->serdes_link_down = FALSE;
2228 DEBUGOUT("SERDES: Link is up.\n");
2229 }
2230 } else {
2231 hw->serdes_link_down = TRUE;
2232 DEBUGOUT("SERDES: Link is down.\n");
2233 }
2234 }
2235 if((hw->media_type == e1000_media_type_internal_serdes) &&
2236 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2237 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2238 }
2239 return E1000_SUCCESS;
2240}
2241
2242/******************************************************************************
2243 * Detects the current speed and duplex settings of the hardware.
2244 *
2245 * hw - Struct containing variables accessed by shared code
2246 * speed - Speed of the connection
2247 * duplex - Duplex setting of the connection
2248 *****************************************************************************/
2249int32_t
2250e1000_get_speed_and_duplex(struct e1000_hw *hw,
2251 uint16_t *speed,
2252 uint16_t *duplex)
2253{
2254 uint32_t status;
2255 int32_t ret_val;
2256 uint16_t phy_data;
2257
2258 DEBUGFUNC("e1000_get_speed_and_duplex");
2259
2260 if(hw->mac_type >= e1000_82543) {
2261 status = E1000_READ_REG(hw, STATUS);
2262 if(status & E1000_STATUS_SPEED_1000) {
2263 *speed = SPEED_1000;
2264 DEBUGOUT("1000 Mbs, ");
2265 } else if(status & E1000_STATUS_SPEED_100) {
2266 *speed = SPEED_100;
2267 DEBUGOUT("100 Mbs, ");
2268 } else {
2269 *speed = SPEED_10;
2270 DEBUGOUT("10 Mbs, ");
2271 }
2272
2273 if(status & E1000_STATUS_FD) {
2274 *duplex = FULL_DUPLEX;
2275 DEBUGOUT("Full Duplex\r\n");
2276 } else {
2277 *duplex = HALF_DUPLEX;
2278 DEBUGOUT(" Half Duplex\r\n");
2279 }
2280 } else {
2281 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2282 *speed = SPEED_1000;
2283 *duplex = FULL_DUPLEX;
2284 }
2285
2286 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2287 * if it is operating at half duplex. Here we set the duplex settings to
2288 * match the duplex in the link partner's capabilities.
2289 */
2290 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2291 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2292 if(ret_val)
2293 return ret_val;
2294
2295 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2296 *duplex = HALF_DUPLEX;
2297 else {
2298 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2299 if(ret_val)
2300 return ret_val;
2301 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2302 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2303 *duplex = HALF_DUPLEX;
2304 }
2305 }
2306
2307 return E1000_SUCCESS;
2308}
2309
2310/******************************************************************************
2311* Blocks until autoneg completes or times out (~4.5 seconds)
2312*
2313* hw - Struct containing variables accessed by shared code
2314******************************************************************************/
2315int32_t
2316e1000_wait_autoneg(struct e1000_hw *hw)
2317{
2318 int32_t ret_val;
2319 uint16_t i;
2320 uint16_t phy_data;
2321
2322 DEBUGFUNC("e1000_wait_autoneg");
2323 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2324
2325 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2326 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2327 /* Read the MII Status Register and wait for Auto-Neg
2328 * Complete bit to be set.
2329 */
2330 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2331 if(ret_val)
2332 return ret_val;
2333 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2334 if(ret_val)
2335 return ret_val;
2336 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2337 return E1000_SUCCESS;
2338 }
2339 msec_delay(100);
2340 }
2341 return E1000_SUCCESS;
2342}
2343
2344/******************************************************************************
2345* Raises the Management Data Clock
2346*
2347* hw - Struct containing variables accessed by shared code
2348* ctrl - Device control register's current value
2349******************************************************************************/
2350static void
2351e1000_raise_mdi_clk(struct e1000_hw *hw,
2352 uint32_t *ctrl)
2353{
2354 /* Raise the clock input to the Management Data Clock (by setting the MDC
2355 * bit), and then delay 10 microseconds.
2356 */
2357 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2358 E1000_WRITE_FLUSH(hw);
2359 udelay(10);
2360}
2361
2362/******************************************************************************
2363* Lowers the Management Data Clock
2364*
2365* hw - Struct containing variables accessed by shared code
2366* ctrl - Device control register's current value
2367******************************************************************************/
2368static void
2369e1000_lower_mdi_clk(struct e1000_hw *hw,
2370 uint32_t *ctrl)
2371{
2372 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2373 * bit), and then delay 10 microseconds.
2374 */
2375 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2376 E1000_WRITE_FLUSH(hw);
2377 udelay(10);
2378}
2379
2380/******************************************************************************
2381* Shifts data bits out to the PHY
2382*
2383* hw - Struct containing variables accessed by shared code
2384* data - Data to send out to the PHY
2385* count - Number of bits to shift out
2386*
2387* Bits are shifted out in MSB to LSB order.
2388******************************************************************************/
2389static void
2390e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2391 uint32_t data,
2392 uint16_t count)
2393{
2394 uint32_t ctrl;
2395 uint32_t mask;
2396
2397 /* We need to shift "count" number of bits out to the PHY. So, the value
2398 * in the "data" parameter will be shifted out to the PHY one bit at a
2399 * time. In order to do this, "data" must be broken down into bits.
2400 */
2401 mask = 0x01;
2402 mask <<= (count - 1);
2403
2404 ctrl = E1000_READ_REG(hw, CTRL);
2405
2406 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2407 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2408
2409 while(mask) {
2410 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2411 * then raising and lowering the Management Data Clock. A "0" is
2412 * shifted out to the PHY by setting the MDIO bit to "0" and then
2413 * raising and lowering the clock.
2414 */
2415 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2416 else ctrl &= ~E1000_CTRL_MDIO;
2417
2418 E1000_WRITE_REG(hw, CTRL, ctrl);
2419 E1000_WRITE_FLUSH(hw);
2420
2421 udelay(10);
2422
2423 e1000_raise_mdi_clk(hw, &ctrl);
2424 e1000_lower_mdi_clk(hw, &ctrl);
2425
2426 mask = mask >> 1;
2427 }
2428}
2429
2430/******************************************************************************
2431* Shifts data bits in from the PHY
2432*
2433* hw - Struct containing variables accessed by shared code
2434*
2435* Bits are shifted in in MSB to LSB order.
2436******************************************************************************/
2437static uint16_t
2438e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2439{
2440 uint32_t ctrl;
2441 uint16_t data = 0;
2442 uint8_t i;
2443
2444 /* In order to read a register from the PHY, we need to shift in a total
2445 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2446 * to avoid contention on the MDIO pin when a read operation is performed.
2447 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2448 * by raising the input to the Management Data Clock (setting the MDC bit),
2449 * and then reading the value of the MDIO bit.
2450 */
2451 ctrl = E1000_READ_REG(hw, CTRL);
2452
2453 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2454 ctrl &= ~E1000_CTRL_MDIO_DIR;
2455 ctrl &= ~E1000_CTRL_MDIO;
2456
2457 E1000_WRITE_REG(hw, CTRL, ctrl);
2458 E1000_WRITE_FLUSH(hw);
2459
2460 /* Raise and Lower the clock before reading in the data. This accounts for
2461 * the turnaround bits. The first clock occurred when we clocked out the
2462 * last bit of the Register Address.
2463 */
2464 e1000_raise_mdi_clk(hw, &ctrl);
2465 e1000_lower_mdi_clk(hw, &ctrl);
2466
2467 for(data = 0, i = 0; i < 16; i++) {
2468 data = data << 1;
2469 e1000_raise_mdi_clk(hw, &ctrl);
2470 ctrl = E1000_READ_REG(hw, CTRL);
2471 /* Check to see if we shifted in a "1". */
2472 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2473 e1000_lower_mdi_clk(hw, &ctrl);
2474 }
2475
2476 e1000_raise_mdi_clk(hw, &ctrl);
2477 e1000_lower_mdi_clk(hw, &ctrl);
2478
2479 return data;
2480}
2481
2482/*****************************************************************************
2483* Reads the value from a PHY register, if the value is on a specific non zero
2484* page, sets the page first.
2485* hw - Struct containing variables accessed by shared code
2486* reg_addr - address of the PHY register to read
2487******************************************************************************/
2488int32_t
2489e1000_read_phy_reg(struct e1000_hw *hw,
2490 uint32_t reg_addr,
2491 uint16_t *phy_data)
2492{
2493 uint32_t ret_val;
2494
2495 DEBUGFUNC("e1000_read_phy_reg");
2496
2497
2498 if(hw->phy_type == e1000_phy_igp &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr);
2502 if(ret_val) {
2503 return ret_val;
2504 }
2505 }
2506
2507 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2508 phy_data);
2509
2510 return ret_val;
2511}
2512
2513int32_t
2514e1000_read_phy_reg_ex(struct e1000_hw *hw,
2515 uint32_t reg_addr,
2516 uint16_t *phy_data)
2517{
2518 uint32_t i;
2519 uint32_t mdic = 0;
2520 const uint32_t phy_addr = 1;
2521
2522 DEBUGFUNC("e1000_read_phy_reg_ex");
2523
2524 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2525 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2526 return -E1000_ERR_PARAM;
2527 }
2528
2529 if(hw->mac_type > e1000_82543) {
2530 /* Set up Op-code, Phy Address, and register address in the MDI
2531 * Control register. The MAC will take care of interfacing with the
2532 * PHY to retrieve the desired data.
2533 */
2534 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2535 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2536 (E1000_MDIC_OP_READ));
2537
2538 E1000_WRITE_REG(hw, MDIC, mdic);
2539
2540 /* Poll the ready bit to see if the MDI read completed */
2541 for(i = 0; i < 64; i++) {
2542 udelay(50);
2543 mdic = E1000_READ_REG(hw, MDIC);
2544 if(mdic & E1000_MDIC_READY) break;
2545 }
2546 if(!(mdic & E1000_MDIC_READY)) {
2547 DEBUGOUT("MDI Read did not complete\n");
2548 return -E1000_ERR_PHY;
2549 }
2550 if(mdic & E1000_MDIC_ERROR) {
2551 DEBUGOUT("MDI Error\n");
2552 return -E1000_ERR_PHY;
2553 }
2554 *phy_data = (uint16_t) mdic;
2555 } else {
2556 /* We must first send a preamble through the MDIO pin to signal the
2557 * beginning of an MII instruction. This is done by sending 32
2558 * consecutive "1" bits.
2559 */
2560 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2561
2562 /* Now combine the next few fields that are required for a read
2563 * operation. We use this method instead of calling the
2564 * e1000_shift_out_mdi_bits routine five different times. The format of
2565 * a MII read instruction consists of a shift out of 14 bits and is
2566 * defined as follows:
2567 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2568 * followed by a shift in of 18 bits. This first two bits shifted in
2569 * are TurnAround bits used to avoid contention on the MDIO pin when a
2570 * READ operation is performed. These two bits are thrown away
2571 * followed by a shift in of 16 bits which contains the desired data.
2572 */
2573 mdic = ((reg_addr) | (phy_addr << 5) |
2574 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2575
2576 e1000_shift_out_mdi_bits(hw, mdic, 14);
2577
2578 /* Now that we've shifted out the read command to the MII, we need to
2579 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2580 * register address.
2581 */
2582 *phy_data = e1000_shift_in_mdi_bits(hw);
2583 }
2584 return E1000_SUCCESS;
2585}
2586
2587/******************************************************************************
2588* Writes a value to a PHY register
2589*
2590* hw - Struct containing variables accessed by shared code
2591* reg_addr - address of the PHY register to write
2592* data - data to write to the PHY
2593******************************************************************************/
2594int32_t
2595e1000_write_phy_reg(struct e1000_hw *hw,
2596 uint32_t reg_addr,
2597 uint16_t phy_data)
2598{
2599 uint32_t ret_val;
2600
2601 DEBUGFUNC("e1000_write_phy_reg");
2602
2603
2604 if(hw->phy_type == e1000_phy_igp &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr);
2608 if(ret_val) {
2609 return ret_val;
2610 }
2611 }
2612
2613 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2614 phy_data);
2615
2616 return ret_val;
2617}
2618
2619int32_t
2620e1000_write_phy_reg_ex(struct e1000_hw *hw,
2621 uint32_t reg_addr,
2622 uint16_t phy_data)
2623{
2624 uint32_t i;
2625 uint32_t mdic = 0;
2626 const uint32_t phy_addr = 1;
2627
2628 DEBUGFUNC("e1000_write_phy_reg_ex");
2629
2630 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2631 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2632 return -E1000_ERR_PARAM;
2633 }
2634
2635 if(hw->mac_type > e1000_82543) {
2636 /* Set up Op-code, Phy Address, register address, and data intended
2637 * for the PHY register in the MDI Control register. The MAC will take
2638 * care of interfacing with the PHY to send the desired data.
2639 */
2640 mdic = (((uint32_t) phy_data) |
2641 (reg_addr << E1000_MDIC_REG_SHIFT) |
2642 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2643 (E1000_MDIC_OP_WRITE));
2644
2645 E1000_WRITE_REG(hw, MDIC, mdic);
2646
2647 /* Poll the ready bit to see if the MDI read completed */
2648 for(i = 0; i < 640; i++) {
2649 udelay(5);
2650 mdic = E1000_READ_REG(hw, MDIC);
2651 if(mdic & E1000_MDIC_READY) break;
2652 }
2653 if(!(mdic & E1000_MDIC_READY)) {
2654 DEBUGOUT("MDI Write did not complete\n");
2655 return -E1000_ERR_PHY;
2656 }
2657 } else {
2658 /* We'll need to use the SW defined pins to shift the write command
2659 * out to the PHY. We first send a preamble to the PHY to signal the
2660 * beginning of the MII instruction. This is done by sending 32
2661 * consecutive "1" bits.
2662 */
2663 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2664
2665 /* Now combine the remaining required fields that will indicate a
2666 * write operation. We use this method instead of calling the
2667 * e1000_shift_out_mdi_bits routine for each field in the command. The
2668 * format of a MII write instruction is as follows:
2669 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2670 */
2671 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2672 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2673 mdic <<= 16;
2674 mdic |= (uint32_t) phy_data;
2675
2676 e1000_shift_out_mdi_bits(hw, mdic, 32);
2677 }
2678
2679 return E1000_SUCCESS;
2680}
2681
2682/******************************************************************************
2683* Returns the PHY to the power-on reset state
2684*
2685* hw - Struct containing variables accessed by shared code
2686******************************************************************************/
2687void
2688e1000_phy_hw_reset(struct e1000_hw *hw)
2689{
2690 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl;
2692
2693 DEBUGFUNC("e1000_phy_hw_reset");
2694
2695 DEBUGOUT("Resetting Phy...\n");
2696
2697 if(hw->mac_type > e1000_82543) {
2698 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2699 * bit. Then, take it out of reset.
2700 */
2701 ctrl = E1000_READ_REG(hw, CTRL);
2702 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2703 E1000_WRITE_FLUSH(hw);
2704 msec_delay(10);
2705 E1000_WRITE_REG(hw, CTRL, ctrl);
2706 E1000_WRITE_FLUSH(hw);
2707 } else {
2708 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2709 * bit to put the PHY into reset. Then, take it out of reset.
2710 */
2711 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2712 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2713 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2714 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2715 E1000_WRITE_FLUSH(hw);
2716 msec_delay(10);
2717 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2718 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2719 E1000_WRITE_FLUSH(hw);
2720 }
2721 udelay(150);
2722
2723 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2724 /* Configure activity LED after PHY reset */
2725 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2726 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 }
2730}
2731
2732/******************************************************************************
2733* Resets the PHY
2734*
2735* hw - Struct containing variables accessed by shared code
2736*
2737* Sets bit 15 of the MII Control regiser
2738******************************************************************************/
2739int32_t
2740e1000_phy_reset(struct e1000_hw *hw)
2741{
2742 int32_t ret_val;
2743 uint16_t phy_data;
2744
2745 DEBUGFUNC("e1000_phy_reset");
2746
2747 if(hw->mac_type != e1000_82541_rev_2) {
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val)
2750 return ret_val;
2751
2752 phy_data |= MII_CR_RESET;
2753 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2754 if(ret_val)
2755 return ret_val;
2756
2757 udelay(1);
2758 } else e1000_phy_hw_reset(hw);
2759
2760 if(hw->phy_type == e1000_phy_igp)
2761 e1000_phy_init_script(hw);
2762
2763 return E1000_SUCCESS;
2764}
2765
2766/******************************************************************************
2767* Probes the expected PHY address for known PHY IDs
2768*
2769* hw - Struct containing variables accessed by shared code
2770******************************************************************************/
2771int32_t
2772e1000_detect_gig_phy(struct e1000_hw *hw)
2773{
2774 int32_t phy_init_status, ret_val;
2775 uint16_t phy_id_high, phy_id_low;
2776 boolean_t match = FALSE;
2777
2778 DEBUGFUNC("e1000_detect_gig_phy");
2779
2780 /* Read the PHY ID Registers to identify which PHY is onboard. */
2781 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2782 if(ret_val)
2783 return ret_val;
2784
2785 hw->phy_id = (uint32_t) (phy_id_high << 16);
2786 udelay(20);
2787 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2788 if(ret_val)
2789 return ret_val;
2790
2791 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2792 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2793
2794 switch(hw->mac_type) {
2795 case e1000_82543:
2796 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2797 break;
2798 case e1000_82544:
2799 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2800 break;
2801 case e1000_82540:
2802 case e1000_82545:
2803 case e1000_82545_rev_3:
2804 case e1000_82546:
2805 case e1000_82546_rev_3:
2806 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2807 break;
2808 case e1000_82541:
2809 case e1000_82541_rev_2:
2810 case e1000_82547:
2811 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break;
2814 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG;
2817 }
2818 phy_init_status = e1000_set_phy_type(hw);
2819
2820 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2821 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2822 return E1000_SUCCESS;
2823 }
2824 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2825 return -E1000_ERR_PHY;
2826}
2827
2828/******************************************************************************
2829* Resets the PHY's DSP
2830*
2831* hw - Struct containing variables accessed by shared code
2832******************************************************************************/
2833static int32_t
2834e1000_phy_reset_dsp(struct e1000_hw *hw)
2835{
2836 int32_t ret_val;
2837 DEBUGFUNC("e1000_phy_reset_dsp");
2838
2839 do {
2840 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2841 if(ret_val) break;
2842 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2843 if(ret_val) break;
2844 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2845 if(ret_val) break;
2846 ret_val = E1000_SUCCESS;
2847 } while(0);
2848
2849 return ret_val;
2850}
2851
2852/******************************************************************************
2853* Get PHY information from various PHY registers for igp PHY only.
2854*
2855* hw - Struct containing variables accessed by shared code
2856* phy_info - PHY information structure
2857******************************************************************************/
2858int32_t
2859e1000_phy_igp_get_info(struct e1000_hw *hw,
2860 struct e1000_phy_info *phy_info)
2861{
2862 int32_t ret_val;
2863 uint16_t phy_data, polarity, min_length, max_length, average;
2864
2865 DEBUGFUNC("e1000_phy_igp_get_info");
2866
2867 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded;
2870
2871 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
2873
2874 /* IGP01E1000 always correct polarity reversal */
2875 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
2876
2877 /* Check polarity status */
2878 ret_val = e1000_check_polarity(hw, &polarity);
2879 if(ret_val)
2880 return ret_val;
2881
2882 phy_info->cable_polarity = polarity;
2883
2884 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2885 if(ret_val)
2886 return ret_val;
2887
2888 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2889 IGP01E1000_PSSR_MDIX_SHIFT;
2890
2891 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2892 IGP01E1000_PSSR_SPEED_1000MBPS) {
2893 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2894 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2895 if(ret_val)
2896 return ret_val;
2897
2898 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2899 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2900 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2901 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2902
2903 /* Get cable length */
2904 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2905 if(ret_val)
2906 return ret_val;
2907
2908 /* transalte to old method */
2909 average = (max_length + min_length) / 2;
2910
2911 if(average <= e1000_igp_cable_length_50)
2912 phy_info->cable_length = e1000_cable_length_50;
2913 else if(average <= e1000_igp_cable_length_80)
2914 phy_info->cable_length = e1000_cable_length_50_80;
2915 else if(average <= e1000_igp_cable_length_110)
2916 phy_info->cable_length = e1000_cable_length_80_110;
2917 else if(average <= e1000_igp_cable_length_140)
2918 phy_info->cable_length = e1000_cable_length_110_140;
2919 else
2920 phy_info->cable_length = e1000_cable_length_140;
2921 }
2922
2923 return E1000_SUCCESS;
2924}
2925
2926/******************************************************************************
2927* Get PHY information from various PHY registers fot m88 PHY only.
2928*
2929* hw - Struct containing variables accessed by shared code
2930* phy_info - PHY information structure
2931******************************************************************************/
2932int32_t
2933e1000_phy_m88_get_info(struct e1000_hw *hw,
2934 struct e1000_phy_info *phy_info)
2935{
2936 int32_t ret_val;
2937 uint16_t phy_data, polarity;
2938
2939 DEBUGFUNC("e1000_phy_m88_get_info");
2940
2941 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded;
2944
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val)
2947 return ret_val;
2948
2949 phy_info->extended_10bt_distance =
2950 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2951 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2952 phy_info->polarity_correction =
2953 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2954 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2955
2956 /* Check polarity status */
2957 ret_val = e1000_check_polarity(hw, &polarity);
2958 if(ret_val)
2959 return ret_val;
2960 phy_info->cable_polarity = polarity;
2961
2962 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2963 if(ret_val)
2964 return ret_val;
2965
2966 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2967 M88E1000_PSSR_MDIX_SHIFT;
2968
2969 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2970 /* Cable Length Estimation and Local/Remote Receiver Information
2971 * are only valid at 1000 Mbps.
2972 */
2973 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2974 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2975
2976 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2977 if(ret_val)
2978 return ret_val;
2979
2980 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2981 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2982
2983 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2984 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2985 }
2986
2987 return E1000_SUCCESS;
2988}
2989
2990/******************************************************************************
2991* Get PHY information from various PHY registers
2992*
2993* hw - Struct containing variables accessed by shared code
2994* phy_info - PHY information structure
2995******************************************************************************/
2996int32_t
2997e1000_phy_get_info(struct e1000_hw *hw,
2998 struct e1000_phy_info *phy_info)
2999{
3000 int32_t ret_val;
3001 uint16_t phy_data;
3002
3003 DEBUGFUNC("e1000_phy_get_info");
3004
3005 phy_info->cable_length = e1000_cable_length_undefined;
3006 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3007 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3008 phy_info->downshift = e1000_downshift_undefined;
3009 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3010 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3011 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3012 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3013
3014 if(hw->media_type != e1000_media_type_copper) {
3015 DEBUGOUT("PHY info is only valid for copper media\n");
3016 return -E1000_ERR_CONFIG;
3017 }
3018
3019 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3020 if(ret_val)
3021 return ret_val;
3022
3023 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3024 if(ret_val)
3025 return ret_val;
3026
3027 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3028 DEBUGOUT("PHY info is only valid if link is up\n");
3029 return -E1000_ERR_CONFIG;
3030 }
3031
3032 if(hw->phy_type == e1000_phy_igp)
3033 return e1000_phy_igp_get_info(hw, phy_info);
3034 else
3035 return e1000_phy_m88_get_info(hw, phy_info);
3036}
3037
3038int32_t
3039e1000_validate_mdi_setting(struct e1000_hw *hw)
3040{
3041 DEBUGFUNC("e1000_validate_mdi_settings");
3042
3043 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3044 DEBUGOUT("Invalid MDI setting detected\n");
3045 hw->mdix = 1;
3046 return -E1000_ERR_CONFIG;
3047 }
3048 return E1000_SUCCESS;
3049}
3050
3051
3052/******************************************************************************
3053 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3054 * is configured.
3055 *
3056 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/
3058void
3059e1000_init_eeprom_params(struct e1000_hw *hw)
3060{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD);
3063 uint16_t eeprom_size;
3064
3065 DEBUGFUNC("e1000_init_eeprom_params");
3066
3067 switch (hw->mac_type) {
3068 case e1000_82542_rev2_0:
3069 case e1000_82542_rev2_1:
3070 case e1000_82543:
3071 case e1000_82544:
3072 eeprom->type = e1000_eeprom_microwire;
3073 eeprom->word_size = 64;
3074 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50;
3077 break;
3078 case e1000_82540:
3079 case e1000_82545:
3080 case e1000_82545_rev_3:
3081 case e1000_82546:
3082 case e1000_82546_rev_3:
3083 eeprom->type = e1000_eeprom_microwire;
3084 eeprom->opcode_bits = 3;
3085 eeprom->delay_usec = 50;
3086 if(eecd & E1000_EECD_SIZE) {
3087 eeprom->word_size = 256;
3088 eeprom->address_bits = 8;
3089 } else {
3090 eeprom->word_size = 64;
3091 eeprom->address_bits = 6;
3092 }
3093 break;
3094 case e1000_82541:
3095 case e1000_82541_rev_2:
3096 case e1000_82547:
3097 case e1000_82547_rev_2:
3098 if (eecd & E1000_EECD_TYPE) {
3099 eeprom->type = e1000_eeprom_spi;
3100 eeprom->opcode_bits = 8;
3101 eeprom->delay_usec = 1;
3102 if (eecd & E1000_EECD_ADDR_BITS) {
3103 eeprom->page_size = 32;
3104 eeprom->address_bits = 16;
3105 } else {
3106 eeprom->page_size = 8;
3107 eeprom->address_bits = 8;
3108 }
3109 } else {
3110 eeprom->type = e1000_eeprom_microwire;
3111 eeprom->opcode_bits = 3;
3112 eeprom->delay_usec = 50;
3113 if (eecd & E1000_EECD_ADDR_BITS) {
3114 eeprom->word_size = 256;
3115 eeprom->address_bits = 8;
3116 } else {
3117 eeprom->word_size = 64;
3118 eeprom->address_bits = 6;
3119 }
3120 }
3121 break;
3122 default:
3123 break;
3124 }
3125
3126 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64;
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3129 eeprom_size &= EEPROM_SIZE_MASK;
3130
3131 switch (eeprom_size) {
3132 case EEPROM_SIZE_16KB:
3133 eeprom->word_size = 8192;
3134 break;
3135 case EEPROM_SIZE_8KB:
3136 eeprom->word_size = 4096;
3137 break;
3138 case EEPROM_SIZE_4KB:
3139 eeprom->word_size = 2048;
3140 break;
3141 case EEPROM_SIZE_2KB:
3142 eeprom->word_size = 1024;
3143 break;
3144 case EEPROM_SIZE_1KB:
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 }
3156 }
3157}
3158
3159/******************************************************************************
3160 * Raises the EEPROM's clock input.
3161 *
3162 * hw - Struct containing variables accessed by shared code
3163 * eecd - EECD's current value
3164 *****************************************************************************/
3165static void
3166e1000_raise_ee_clk(struct e1000_hw *hw,
3167 uint32_t *eecd)
3168{
3169 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3170 * wait <delay> microseconds.
3171 */
3172 *eecd = *eecd | E1000_EECD_SK;
3173 E1000_WRITE_REG(hw, EECD, *eecd);
3174 E1000_WRITE_FLUSH(hw);
3175 udelay(hw->eeprom.delay_usec);
3176}
3177
3178/******************************************************************************
3179 * Lowers the EEPROM's clock input.
3180 *
3181 * hw - Struct containing variables accessed by shared code
3182 * eecd - EECD's current value
3183 *****************************************************************************/
3184static void
3185e1000_lower_ee_clk(struct e1000_hw *hw,
3186 uint32_t *eecd)
3187{
3188 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3189 * wait 50 microseconds.
3190 */
3191 *eecd = *eecd & ~E1000_EECD_SK;
3192 E1000_WRITE_REG(hw, EECD, *eecd);
3193 E1000_WRITE_FLUSH(hw);
3194 udelay(hw->eeprom.delay_usec);
3195}
3196
3197/******************************************************************************
3198 * Shift data bits out to the EEPROM.
3199 *
3200 * hw - Struct containing variables accessed by shared code
3201 * data - data to send to the EEPROM
3202 * count - number of bits to shift out
3203 *****************************************************************************/
3204static void
3205e1000_shift_out_ee_bits(struct e1000_hw *hw,
3206 uint16_t data,
3207 uint16_t count)
3208{
3209 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3210 uint32_t eecd;
3211 uint32_t mask;
3212
3213 /* We need to shift "count" bits out to the EEPROM. So, value in the
3214 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3215 * In order to do this, "data" must be broken down into bits.
3216 */
3217 mask = 0x01 << (count - 1);
3218 eecd = E1000_READ_REG(hw, EECD);
3219 if (eeprom->type == e1000_eeprom_microwire) {
3220 eecd &= ~E1000_EECD_DO;
3221 } else if (eeprom->type == e1000_eeprom_spi) {
3222 eecd |= E1000_EECD_DO;
3223 }
3224 do {
3225 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3226 * and then raising and then lowering the clock (the SK bit controls
3227 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3228 * by setting "DI" to "0" and then raising and then lowering the clock.
3229 */
3230 eecd &= ~E1000_EECD_DI;
3231
3232 if(data & mask)
3233 eecd |= E1000_EECD_DI;
3234
3235 E1000_WRITE_REG(hw, EECD, eecd);
3236 E1000_WRITE_FLUSH(hw);
3237
3238 udelay(eeprom->delay_usec);
3239
3240 e1000_raise_ee_clk(hw, &eecd);
3241 e1000_lower_ee_clk(hw, &eecd);
3242
3243 mask = mask >> 1;
3244
3245 } while(mask);
3246
3247 /* We leave the "DI" bit set to "0" when we leave this routine. */
3248 eecd &= ~E1000_EECD_DI;
3249 E1000_WRITE_REG(hw, EECD, eecd);
3250}
3251
3252/******************************************************************************
3253 * Shift data bits in from the EEPROM
3254 *
3255 * hw - Struct containing variables accessed by shared code
3256 *****************************************************************************/
3257static uint16_t
3258e1000_shift_in_ee_bits(struct e1000_hw *hw,
3259 uint16_t count)
3260{
3261 uint32_t eecd;
3262 uint32_t i;
3263 uint16_t data;
3264
3265 /* In order to read a register from the EEPROM, we need to shift 'count'
3266 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3267 * input to the EEPROM (setting the SK bit), and then reading the value of
3268 * the "DO" bit. During this "shifting in" process the "DI" bit should
3269 * always be clear.
3270 */
3271
3272 eecd = E1000_READ_REG(hw, EECD);
3273
3274 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3275 data = 0;
3276
3277 for(i = 0; i < count; i++) {
3278 data = data << 1;
3279 e1000_raise_ee_clk(hw, &eecd);
3280
3281 eecd = E1000_READ_REG(hw, EECD);
3282
3283 eecd &= ~(E1000_EECD_DI);
3284 if(eecd & E1000_EECD_DO)
3285 data |= 1;
3286
3287 e1000_lower_ee_clk(hw, &eecd);
3288 }
3289
3290 return data;
3291}
3292
3293/******************************************************************************
3294 * Prepares EEPROM for access
3295 *
3296 * hw - Struct containing variables accessed by shared code
3297 *
3298 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3299 * function should be called before issuing a command to the EEPROM.
3300 *****************************************************************************/
3301static int32_t
3302e1000_acquire_eeprom(struct e1000_hw *hw)
3303{
3304 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3305 uint32_t eecd, i=0;
3306
3307 DEBUGFUNC("e1000_acquire_eeprom");
3308
3309 eecd = E1000_READ_REG(hw, EECD);
3310
3311 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ;
3314 E1000_WRITE_REG(hw, EECD, eecd);
3315 eecd = E1000_READ_REG(hw, EECD);
3316 while((!(eecd & E1000_EECD_GNT)) &&
3317 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3318 i++;
3319 udelay(5);
3320 eecd = E1000_READ_REG(hw, EECD);
3321 }
3322 if(!(eecd & E1000_EECD_GNT)) {
3323 eecd &= ~E1000_EECD_REQ;
3324 E1000_WRITE_REG(hw, EECD, eecd);
3325 DEBUGOUT("Could not acquire EEPROM grant\n");
3326 return -E1000_ERR_EEPROM;
3327 }
3328 }
3329
3330 /* Setup EEPROM for Read/Write */
3331
3332 if (eeprom->type == e1000_eeprom_microwire) {
3333 /* Clear SK and DI */
3334 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3335 E1000_WRITE_REG(hw, EECD, eecd);
3336
3337 /* Set CS */
3338 eecd |= E1000_EECD_CS;
3339 E1000_WRITE_REG(hw, EECD, eecd);
3340 } else if (eeprom->type == e1000_eeprom_spi) {
3341 /* Clear SK and CS */
3342 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3343 E1000_WRITE_REG(hw, EECD, eecd);
3344 udelay(1);
3345 }
3346
3347 return E1000_SUCCESS;
3348}
3349
3350/******************************************************************************
3351 * Returns EEPROM to a "standby" state
3352 *
3353 * hw - Struct containing variables accessed by shared code
3354 *****************************************************************************/
3355static void
3356e1000_standby_eeprom(struct e1000_hw *hw)
3357{
3358 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3359 uint32_t eecd;
3360
3361 eecd = E1000_READ_REG(hw, EECD);
3362
3363 if(eeprom->type == e1000_eeprom_microwire) {
3364 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3365 E1000_WRITE_REG(hw, EECD, eecd);
3366 E1000_WRITE_FLUSH(hw);
3367 udelay(eeprom->delay_usec);
3368
3369 /* Clock high */
3370 eecd |= E1000_EECD_SK;
3371 E1000_WRITE_REG(hw, EECD, eecd);
3372 E1000_WRITE_FLUSH(hw);
3373 udelay(eeprom->delay_usec);
3374
3375 /* Select EEPROM */
3376 eecd |= E1000_EECD_CS;
3377 E1000_WRITE_REG(hw, EECD, eecd);
3378 E1000_WRITE_FLUSH(hw);
3379 udelay(eeprom->delay_usec);
3380
3381 /* Clock low */
3382 eecd &= ~E1000_EECD_SK;
3383 E1000_WRITE_REG(hw, EECD, eecd);
3384 E1000_WRITE_FLUSH(hw);
3385 udelay(eeprom->delay_usec);
3386 } else if(eeprom->type == e1000_eeprom_spi) {
3387 /* Toggle CS to flush commands */
3388 eecd |= E1000_EECD_CS;
3389 E1000_WRITE_REG(hw, EECD, eecd);
3390 E1000_WRITE_FLUSH(hw);
3391 udelay(eeprom->delay_usec);
3392 eecd &= ~E1000_EECD_CS;
3393 E1000_WRITE_REG(hw, EECD, eecd);
3394 E1000_WRITE_FLUSH(hw);
3395 udelay(eeprom->delay_usec);
3396 }
3397}
3398
3399/******************************************************************************
3400 * Terminates a command by inverting the EEPROM's chip select pin
3401 *
3402 * hw - Struct containing variables accessed by shared code
3403 *****************************************************************************/
3404static void
3405e1000_release_eeprom(struct e1000_hw *hw)
3406{
3407 uint32_t eecd;
3408
3409 DEBUGFUNC("e1000_release_eeprom");
3410
3411 eecd = E1000_READ_REG(hw, EECD);
3412
3413 if (hw->eeprom.type == e1000_eeprom_spi) {
3414 eecd |= E1000_EECD_CS; /* Pull CS high */
3415 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3416
3417 E1000_WRITE_REG(hw, EECD, eecd);
3418
3419 udelay(hw->eeprom.delay_usec);
3420 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3421 /* cleanup eeprom */
3422
3423 /* CS on Microwire is active-high */
3424 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3425
3426 E1000_WRITE_REG(hw, EECD, eecd);
3427
3428 /* Rising edge of clock */
3429 eecd |= E1000_EECD_SK;
3430 E1000_WRITE_REG(hw, EECD, eecd);
3431 E1000_WRITE_FLUSH(hw);
3432 udelay(hw->eeprom.delay_usec);
3433
3434 /* Falling edge of clock */
3435 eecd &= ~E1000_EECD_SK;
3436 E1000_WRITE_REG(hw, EECD, eecd);
3437 E1000_WRITE_FLUSH(hw);
3438 udelay(hw->eeprom.delay_usec);
3439 }
3440
3441 /* Stop requesting EEPROM access */
3442 if(hw->mac_type > e1000_82544) {
3443 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd);
3445 }
3446}
3447
3448/******************************************************************************
3449 * Reads a 16 bit word from the EEPROM.
3450 *
3451 * hw - Struct containing variables accessed by shared code
3452 *****************************************************************************/
3453int32_t
3454e1000_spi_eeprom_ready(struct e1000_hw *hw)
3455{
3456 uint16_t retry_count = 0;
3457 uint8_t spi_stat_reg;
3458
3459 DEBUGFUNC("e1000_spi_eeprom_ready");
3460
3461 /* Read "Status Register" repeatedly until the LSB is cleared. The
3462 * EEPROM will signal that the command has been completed by clearing
3463 * bit 0 of the internal status register. If it's not cleared within
3464 * 5 milliseconds, then error out.
3465 */
3466 retry_count = 0;
3467 do {
3468 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3469 hw->eeprom.opcode_bits);
3470 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3471 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3472 break;
3473
3474 udelay(5);
3475 retry_count += 5;
3476
3477 e1000_standby_eeprom(hw);
3478 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3479
3480 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3481 * only 0-5mSec on 5V devices)
3482 */
3483 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3484 DEBUGOUT("SPI EEPROM Status error\n");
3485 return -E1000_ERR_EEPROM;
3486 }
3487
3488 return E1000_SUCCESS;
3489}
3490
3491/******************************************************************************
3492 * Reads a 16 bit word from the EEPROM.
3493 *
3494 * hw - Struct containing variables accessed by shared code
3495 * offset - offset of word in the EEPROM to read
3496 * data - word read from the EEPROM
3497 * words - number of words to read
3498 *****************************************************************************/
3499int32_t
3500e1000_read_eeprom(struct e1000_hw *hw,
3501 uint16_t offset,
3502 uint16_t words,
3503 uint16_t *data)
3504{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0;
3507
3508 DEBUGFUNC("e1000_read_eeprom");
3509 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words.
3511 */
3512 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3513 (words == 0)) {
3514 DEBUGOUT("\"words\" parameter out of bounds\n");
3515 return -E1000_ERR_EEPROM;
3516 }
3517
3518 /* Prepare the EEPROM for reading */
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3520 return -E1000_ERR_EEPROM;
3521
3522 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in;
3524 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3525
3526 if(e1000_spi_eeprom_ready(hw)) {
3527 e1000_release_eeprom(hw);
3528 return -E1000_ERR_EEPROM;
3529 }
3530
3531 e1000_standby_eeprom(hw);
3532
3533 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3534 if((eeprom->address_bits == 8) && (offset >= 128))
3535 read_opcode |= EEPROM_A8_OPCODE_SPI;
3536
3537 /* Send the READ command (opcode + addr) */
3538 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3539 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3540
3541 /* Read the data. The address of the eeprom internally increments with
3542 * each byte (spi) being read, saving on the overhead of eeprom setup
3543 * and tear-down. The address counter will roll over if reading beyond
3544 * the size of the eeprom, thus allowing the entire memory to be read
3545 * starting from any offset. */
3546 for (i = 0; i < words; i++) {
3547 word_in = e1000_shift_in_ee_bits(hw, 16);
3548 data[i] = (word_in >> 8) | (word_in << 8);
3549 }
3550 } else if(eeprom->type == e1000_eeprom_microwire) {
3551 for (i = 0; i < words; i++) {
3552 /* Send the READ command (opcode + addr) */
3553 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3554 eeprom->opcode_bits);
3555 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3556 eeprom->address_bits);
3557
3558 /* Read the data. For microwire, each word requires the overhead
3559 * of eeprom setup and tear-down. */
3560 data[i] = e1000_shift_in_ee_bits(hw, 16);
3561 e1000_standby_eeprom(hw);
3562 }
3563 }
3564
3565 /* End this read operation */
3566 e1000_release_eeprom(hw);
3567
3568 return E1000_SUCCESS;
3569}
3570
3571/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum
3573 *
3574 * hw - Struct containing variables accessed by shared code
3575 *
3576 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3577 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3578 * valid.
3579 *****************************************************************************/
3580int32_t
3581e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3582{
3583 uint16_t checksum = 0;
3584 uint16_t i, eeprom_data;
3585
3586 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n");
3591 return -E1000_ERR_EEPROM;
3592 }
3593 checksum += eeprom_data;
3594 }
3595
3596 if(checksum == (uint16_t) EEPROM_SUM)
3597 return E1000_SUCCESS;
3598 else {
3599 DEBUGOUT("EEPROM Checksum Invalid\n");
3600 return -E1000_ERR_EEPROM;
3601 }
3602}
3603
3604/******************************************************************************
3605 * Calculates the EEPROM checksum and writes it to the EEPROM
3606 *
3607 * hw - Struct containing variables accessed by shared code
3608 *
3609 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3610 * Writes the difference to word offset 63 of the EEPROM.
3611 *****************************************************************************/
3612int32_t
3613e1000_update_eeprom_checksum(struct e1000_hw *hw)
3614{
3615 uint16_t checksum = 0;
3616 uint16_t i, eeprom_data;
3617
3618 DEBUGFUNC("e1000_update_eeprom_checksum");
3619
3620 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3621 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3622 DEBUGOUT("EEPROM Read Error\n");
3623 return -E1000_ERR_EEPROM;
3624 }
3625 checksum += eeprom_data;
3626 }
3627 checksum = (uint16_t) EEPROM_SUM - checksum;
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM;
3631 }
3632 return E1000_SUCCESS;
3633}
3634
3635/******************************************************************************
3636 * Parent function for writing words to the different EEPROM types.
3637 *
3638 * hw - Struct containing variables accessed by shared code
3639 * offset - offset within the EEPROM to be written to
3640 * words - number of words to write
3641 * data - 16 bit word to be written to the EEPROM
3642 *
3643 * If e1000_update_eeprom_checksum is not called after this function, the
3644 * EEPROM will most likely contain an invalid checksum.
3645 *****************************************************************************/
3646int32_t
3647e1000_write_eeprom(struct e1000_hw *hw,
3648 uint16_t offset,
3649 uint16_t words,
3650 uint16_t *data)
3651{
3652 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3653 int32_t status = 0;
3654
3655 DEBUGFUNC("e1000_write_eeprom");
3656
3657 /* A check for invalid values: offset too large, too many words, and not
3658 * enough words.
3659 */
3660 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3661 (words == 0)) {
3662 DEBUGOUT("\"words\" parameter out of bounds\n");
3663 return -E1000_ERR_EEPROM;
3664 }
3665
3666 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM;
3669
3670 if(eeprom->type == e1000_eeprom_microwire) {
3671 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3672 } else {
3673 status = e1000_write_eeprom_spi(hw, offset, words, data);
3674 msec_delay(10);
3675 }
3676
3677 /* Done with writing */
3678 e1000_release_eeprom(hw);
3679
3680 return status;
3681}
3682
3683/******************************************************************************
3684 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3685 *
3686 * hw - Struct containing variables accessed by shared code
3687 * offset - offset within the EEPROM to be written to
3688 * words - number of words to write
3689 * data - pointer to array of 8 bit words to be written to the EEPROM
3690 *
3691 *****************************************************************************/
3692int32_t
3693e1000_write_eeprom_spi(struct e1000_hw *hw,
3694 uint16_t offset,
3695 uint16_t words,
3696 uint16_t *data)
3697{
3698 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3699 uint16_t widx = 0;
3700
3701 DEBUGFUNC("e1000_write_eeprom_spi");
3702
3703 while (widx < words) {
3704 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3705
3706 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3707
3708 e1000_standby_eeprom(hw);
3709
3710 /* Send the WRITE ENABLE command (8 bit opcode ) */
3711 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3712 eeprom->opcode_bits);
3713
3714 e1000_standby_eeprom(hw);
3715
3716 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3717 if((eeprom->address_bits == 8) && (offset >= 128))
3718 write_opcode |= EEPROM_A8_OPCODE_SPI;
3719
3720 /* Send the Write command (8-bit opcode + addr) */
3721 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3722
3723 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3724 eeprom->address_bits);
3725
3726 /* Send the data */
3727
3728 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3729 while (widx < words) {
3730 uint16_t word_out = data[widx];
3731 word_out = (word_out >> 8) | (word_out << 8);
3732 e1000_shift_out_ee_bits(hw, word_out, 16);
3733 widx++;
3734
3735 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3736 * operation, while the smaller eeproms are capable of an 8-byte
3737 * PAGE WRITE operation. Break the inner loop to pass new address
3738 */
3739 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3740 e1000_standby_eeprom(hw);
3741 break;
3742 }
3743 }
3744 }
3745
3746 return E1000_SUCCESS;
3747}
3748
3749/******************************************************************************
3750 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3751 *
3752 * hw - Struct containing variables accessed by shared code
3753 * offset - offset within the EEPROM to be written to
3754 * words - number of words to write
3755 * data - pointer to array of 16 bit words to be written to the EEPROM
3756 *
3757 *****************************************************************************/
3758int32_t
3759e1000_write_eeprom_microwire(struct e1000_hw *hw,
3760 uint16_t offset,
3761 uint16_t words,
3762 uint16_t *data)
3763{
3764 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3765 uint32_t eecd;
3766 uint16_t words_written = 0;
3767 uint16_t i = 0;
3768
3769 DEBUGFUNC("e1000_write_eeprom_microwire");
3770
3771 /* Send the write enable command to the EEPROM (3-bit opcode plus
3772 * 6/8-bit dummy address beginning with 11). It's less work to include
3773 * the 11 of the dummy address as part of the opcode than it is to shift
3774 * it over the correct number of bits for the address. This puts the
3775 * EEPROM into write/erase mode.
3776 */
3777 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3778 (uint16_t)(eeprom->opcode_bits + 2));
3779
3780 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3781
3782 /* Prepare the EEPROM */
3783 e1000_standby_eeprom(hw);
3784
3785 while (words_written < words) {
3786 /* Send the Write command (3-bit opcode + addr) */
3787 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3788 eeprom->opcode_bits);
3789
3790 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3791 eeprom->address_bits);
3792
3793 /* Send the data */
3794 e1000_shift_out_ee_bits(hw, data[words_written], 16);
3795
3796 /* Toggle the CS line. This in effect tells the EEPROM to execute
3797 * the previous command.
3798 */
3799 e1000_standby_eeprom(hw);
3800
3801 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3802 * signal that the command has been completed by raising the DO signal.
3803 * If DO does not go high in 10 milliseconds, then error out.
3804 */
3805 for(i = 0; i < 200; i++) {
3806 eecd = E1000_READ_REG(hw, EECD);
3807 if(eecd & E1000_EECD_DO) break;
3808 udelay(50);
3809 }
3810 if(i == 200) {
3811 DEBUGOUT("EEPROM Write did not complete\n");
3812 return -E1000_ERR_EEPROM;
3813 }
3814
3815 /* Recover from write */
3816 e1000_standby_eeprom(hw);
3817
3818 words_written++;
3819 }
3820
3821 /* Send the write disable command to the EEPROM (3-bit opcode plus
3822 * 6/8-bit dummy address beginning with 10). It's less work to include
3823 * the 10 of the dummy address as part of the opcode than it is to shift
3824 * it over the correct number of bits for the address. This takes the
3825 * EEPROM out of write/erase mode.
3826 */
3827 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3828 (uint16_t)(eeprom->opcode_bits + 2));
3829
3830 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3831
3832 return E1000_SUCCESS;
3833}
3834
3835/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM
3837 *
3838 * hw - Struct containing variables accessed by shared code
3839 * part_num - Adapter's part number
3840 *****************************************************************************/
3841int32_t
3842e1000_read_part_num(struct e1000_hw *hw,
3843 uint32_t *part_num)
3844{
3845 uint16_t offset = EEPROM_PBA_BYTE_1;
3846 uint16_t eeprom_data;
3847
3848 DEBUGFUNC("e1000_read_part_num");
3849
3850 /* Get word 0 from EEPROM */
3851 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3852 DEBUGOUT("EEPROM Read Error\n");
3853 return -E1000_ERR_EEPROM;
3854 }
3855 /* Save word 0 in upper half of part_num */
3856 *part_num = (uint32_t) (eeprom_data << 16);
3857
3858 /* Get word 1 from EEPROM */
3859 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3860 DEBUGOUT("EEPROM Read Error\n");
3861 return -E1000_ERR_EEPROM;
3862 }
3863 /* Save word 1 in lower half of part_num */
3864 *part_num |= eeprom_data;
3865
3866 return E1000_SUCCESS;
3867}
3868
3869/******************************************************************************
3870 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3871 * second function of dual function devices
3872 *
3873 * hw - Struct containing variables accessed by shared code
3874 *****************************************************************************/
3875int32_t
3876e1000_read_mac_addr(struct e1000_hw * hw)
3877{
3878 uint16_t offset;
3879 uint16_t eeprom_data, i;
3880
3881 DEBUGFUNC("e1000_read_mac_addr");
3882
3883 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3884 offset = i >> 1;
3885 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3886 DEBUGOUT("EEPROM Read Error\n");
3887 return -E1000_ERR_EEPROM;
3888 }
3889 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3890 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3891 }
3892 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3893 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3894 hw->perm_mac_addr[5] ^= 0x01;
3895
3896 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3897 hw->mac_addr[i] = hw->perm_mac_addr[i];
3898 return E1000_SUCCESS;
3899}
3900
3901/******************************************************************************
3902 * Initializes receive address filters.
3903 *
3904 * hw - Struct containing variables accessed by shared code
3905 *
3906 * Places the MAC address in receive address register 0 and clears the rest
3907 * of the receive addresss registers. Clears the multicast table. Assumes
3908 * the receiver is in reset when the routine is called.
3909 *****************************************************************************/
3910void
3911e1000_init_rx_addrs(struct e1000_hw *hw)
3912{
3913 uint32_t i;
3914
3915 DEBUGFUNC("e1000_init_rx_addrs");
3916
3917 /* Setup the receive address. */
3918 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3919
3920 e1000_rar_set(hw, hw->mac_addr, 0);
3921
3922 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 }
3928}
3929
3930/******************************************************************************
3931 * Updates the MAC's list of multicast addresses.
3932 *
3933 * hw - Struct containing variables accessed by shared code
3934 * mc_addr_list - the list of new multicast addresses
3935 * mc_addr_count - number of addresses
3936 * pad - number of bytes between addresses in the list
3937 * rar_used_count - offset where to start adding mc addresses into the RAR's
3938 *
3939 * The given list replaces any existing list. Clears the last 15 receive
3940 * address registers and the multicast table. Uses receive address registers
3941 * for the first 15 multicast addresses, and hashes the rest into the
3942 * multicast table.
3943 *****************************************************************************/
3944void
3945e1000_mc_addr_list_update(struct e1000_hw *hw,
3946 uint8_t *mc_addr_list,
3947 uint32_t mc_addr_count,
3948 uint32_t pad,
3949 uint32_t rar_used_count)
3950{
3951 uint32_t hash_value;
3952 uint32_t i;
3953
3954 DEBUGFUNC("e1000_mc_addr_list_update");
3955
3956 /* Set the new number of MC addresses that we are being requested to use. */
3957 hw->num_mc_addrs = mc_addr_count;
3958
3959 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 }
3965
3966 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 }
3971
3972 /* Add the new addresses */
3973 for(i = 0; i < mc_addr_count; i++) {
3974 DEBUGOUT(" Adding the multicast addresses:\n");
3975 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3976 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3977 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3978 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3979 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3980 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3981 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3982
3983 hash_value = e1000_hash_mc_addr(hw,
3984 mc_addr_list +
3985 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3986
3987 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3988
3989 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA
3991 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) {
3993 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count);
3996 rar_used_count++;
3997 } else {
3998 e1000_mta_set(hw, hash_value);
3999 }
4000 }
4001 DEBUGOUT("MC Update Complete\n");
4002}
4003
4004/******************************************************************************
4005 * Hashes an address to determine its location in the multicast table
4006 *
4007 * hw - Struct containing variables accessed by shared code
4008 * mc_addr - the multicast address to hash
4009 *****************************************************************************/
4010uint32_t
4011e1000_hash_mc_addr(struct e1000_hw *hw,
4012 uint8_t *mc_addr)
4013{
4014 uint32_t hash_value = 0;
4015
4016 /* The portion of the address that is used for the hash table is
4017 * determined by the mc_filter_type setting.
4018 */
4019 switch (hw->mc_filter_type) {
4020 /* [0] [1] [2] [3] [4] [5]
4021 * 01 AA 00 12 34 56
4022 * LSB MSB
4023 */
4024 case 0:
4025 /* [47:36] i.e. 0x563 for above example address */
4026 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
4027 break;
4028 case 1:
4029 /* [46:35] i.e. 0xAC6 for above example address */
4030 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
4031 break;
4032 case 2:
4033 /* [45:34] i.e. 0x5D8 for above example address */
4034 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
4035 break;
4036 case 3:
4037 /* [43:32] i.e. 0x634 for above example address */
4038 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
4039 break;
4040 }
4041
4042 hash_value &= 0xFFF;
4043 return hash_value;
4044}
4045
4046/******************************************************************************
4047 * Sets the bit in the multicast table corresponding to the hash value.
4048 *
4049 * hw - Struct containing variables accessed by shared code
4050 * hash_value - Multicast address hash value
4051 *****************************************************************************/
4052void
4053e1000_mta_set(struct e1000_hw *hw,
4054 uint32_t hash_value)
4055{
4056 uint32_t hash_bit, hash_reg;
4057 uint32_t mta;
4058 uint32_t temp;
4059
4060 /* The MTA is a register array of 128 32-bit registers.
4061 * It is treated like an array of 4096 bits. We want to set
4062 * bit BitArray[hash_value]. So we figure out what register
4063 * the bit is in, read it, OR in the new bit, then write
4064 * back the new value. The register is determined by the
4065 * upper 7 bits of the hash value and the bit within that
4066 * register are determined by the lower 5 bits of the value.
4067 */
4068 hash_reg = (hash_value >> 5) & 0x7F;
4069 hash_bit = hash_value & 0x1F;
4070
4071 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4072
4073 mta |= (1 << hash_bit);
4074
4075 /* If we are on an 82544 and we are trying to write an odd offset
4076 * in the MTA, save off the previous entry before writing and
4077 * restore the old value after writing.
4078 */
4079 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4080 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4081 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4082 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4083 } else {
4084 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4085 }
4086}
4087
4088/******************************************************************************
4089 * Puts an ethernet address into a receive address register.
4090 *
4091 * hw - Struct containing variables accessed by shared code
4092 * addr - Address to put into receive address register
4093 * index - Receive address register to write
4094 *****************************************************************************/
4095void
4096e1000_rar_set(struct e1000_hw *hw,
4097 uint8_t *addr,
4098 uint32_t index)
4099{
4100 uint32_t rar_low, rar_high;
4101
4102 /* HW expects these in little endian so we reverse the byte order
4103 * from network order (big endian) to little endian
4104 */
4105 rar_low = ((uint32_t) addr[0] |
4106 ((uint32_t) addr[1] << 8) |
4107 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4108
4109 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4110
4111 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4112 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4113}
4114
4115/******************************************************************************
4116 * Writes a value to the specified offset in the VLAN filter table.
4117 *
4118 * hw - Struct containing variables accessed by shared code
4119 * offset - Offset in VLAN filer table to write
4120 * value - Value to write into VLAN filter table
4121 *****************************************************************************/
4122void
4123e1000_write_vfta(struct e1000_hw *hw,
4124 uint32_t offset,
4125 uint32_t value)
4126{
4127 uint32_t temp;
4128
4129 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4130 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4131 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4132 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4133 } else {
4134 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4135 }
4136}
4137
4138/******************************************************************************
4139 * Clears the VLAN filer table
4140 *
4141 * hw - Struct containing variables accessed by shared code
4142 *****************************************************************************/
4143void
4144e1000_clear_vfta(struct e1000_hw *hw)
4145{
4146 uint32_t offset;
4147
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4150}
4151
4152static int32_t
4153e1000_id_led_init(struct e1000_hw * hw)
4154{
4155 uint32_t ledctl;
4156 const uint32_t ledctl_mask = 0x000000FF;
4157 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4158 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4159 uint16_t eeprom_data, i, temp;
4160 const uint16_t led_mask = 0x0F;
4161
4162 DEBUGFUNC("e1000_id_led_init");
4163
4164 if(hw->mac_type < e1000_82540) {
4165 /* Nothing to do */
4166 return E1000_SUCCESS;
4167 }
4168
4169 ledctl = E1000_READ_REG(hw, LEDCTL);
4170 hw->ledctl_default = ledctl;
4171 hw->ledctl_mode1 = hw->ledctl_default;
4172 hw->ledctl_mode2 = hw->ledctl_default;
4173
4174 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4175 DEBUGOUT("EEPROM Read Error\n");
4176 return -E1000_ERR_EEPROM;
4177 }
4178 if((eeprom_data== ID_LED_RESERVED_0000) ||
4179 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4180 for(i = 0; i < 4; i++) {
4181 temp = (eeprom_data >> (i << 2)) & led_mask;
4182 switch(temp) {
4183 case ID_LED_ON1_DEF2:
4184 case ID_LED_ON1_ON2:
4185 case ID_LED_ON1_OFF2:
4186 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4187 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4188 break;
4189 case ID_LED_OFF1_DEF2:
4190 case ID_LED_OFF1_ON2:
4191 case ID_LED_OFF1_OFF2:
4192 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4193 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4194 break;
4195 default:
4196 /* Do nothing */
4197 break;
4198 }
4199 switch(temp) {
4200 case ID_LED_DEF1_ON2:
4201 case ID_LED_ON1_ON2:
4202 case ID_LED_OFF1_ON2:
4203 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4204 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4205 break;
4206 case ID_LED_DEF1_OFF2:
4207 case ID_LED_ON1_OFF2:
4208 case ID_LED_OFF1_OFF2:
4209 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4210 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4211 break;
4212 default:
4213 /* Do nothing */
4214 break;
4215 }
4216 }
4217 return E1000_SUCCESS;
4218}
4219
4220/******************************************************************************
4221 * Prepares SW controlable LED for use and saves the current state of the LED.
4222 *
4223 * hw - Struct containing variables accessed by shared code
4224 *****************************************************************************/
4225int32_t
4226e1000_setup_led(struct e1000_hw *hw)
4227{
4228 uint32_t ledctl;
4229 int32_t ret_val = E1000_SUCCESS;
4230
4231 DEBUGFUNC("e1000_setup_led");
4232
4233 switch(hw->mac_type) {
4234 case e1000_82542_rev2_0:
4235 case e1000_82542_rev2_1:
4236 case e1000_82543:
4237 case e1000_82544:
4238 /* No setup necessary */
4239 break;
4240 case e1000_82541:
4241 case e1000_82547:
4242 case e1000_82541_rev_2:
4243 case e1000_82547_rev_2:
4244 /* Turn off PHY Smart Power Down (if enabled) */
4245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4246 &hw->phy_spd_default);
4247 if(ret_val)
4248 return ret_val;
4249 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4250 (uint16_t)(hw->phy_spd_default &
4251 ~IGP01E1000_GMII_SPD));
4252 if(ret_val)
4253 return ret_val;
4254 /* Fall Through */
4255 default:
4256 if(hw->media_type == e1000_media_type_fiber) {
4257 ledctl = E1000_READ_REG(hw, LEDCTL);
4258 /* Save current LEDCTL settings */
4259 hw->ledctl_default = ledctl;
4260 /* Turn off LED0 */
4261 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4262 E1000_LEDCTL_LED0_BLINK |
4263 E1000_LEDCTL_LED0_MODE_MASK);
4264 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4265 E1000_LEDCTL_LED0_MODE_SHIFT);
4266 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4267 } else if(hw->media_type == e1000_media_type_copper)
4268 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4269 break;
4270 }
4271
4272 return E1000_SUCCESS;
4273}
4274
4275/******************************************************************************
4276 * Restores the saved state of the SW controlable LED.
4277 *
4278 * hw - Struct containing variables accessed by shared code
4279 *****************************************************************************/
4280int32_t
4281e1000_cleanup_led(struct e1000_hw *hw)
4282{
4283 int32_t ret_val = E1000_SUCCESS;
4284
4285 DEBUGFUNC("e1000_cleanup_led");
4286
4287 switch(hw->mac_type) {
4288 case e1000_82542_rev2_0:
4289 case e1000_82542_rev2_1:
4290 case e1000_82543:
4291 case e1000_82544:
4292 /* No cleanup necessary */
4293 break;
4294 case e1000_82541:
4295 case e1000_82547:
4296 case e1000_82541_rev_2:
4297 case e1000_82547_rev_2:
4298 /* Turn on PHY Smart Power Down (if previously enabled) */
4299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4300 hw->phy_spd_default);
4301 if(ret_val)
4302 return ret_val;
4303 /* Fall Through */
4304 default:
4305 /* Restore LEDCTL settings */
4306 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4307 break;
4308 }
4309
4310 return E1000_SUCCESS;
4311}
4312
4313/******************************************************************************
4314 * Turns on the software controllable LED
4315 *
4316 * hw - Struct containing variables accessed by shared code
4317 *****************************************************************************/
4318int32_t
4319e1000_led_on(struct e1000_hw *hw)
4320{
4321 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4322
4323 DEBUGFUNC("e1000_led_on");
4324
4325 switch(hw->mac_type) {
4326 case e1000_82542_rev2_0:
4327 case e1000_82542_rev2_1:
4328 case e1000_82543:
4329 /* Set SW Defineable Pin 0 to turn on the LED */
4330 ctrl |= E1000_CTRL_SWDPIN0;
4331 ctrl |= E1000_CTRL_SWDPIO0;
4332 break;
4333 case e1000_82544:
4334 if(hw->media_type == e1000_media_type_fiber) {
4335 /* Set SW Defineable Pin 0 to turn on the LED */
4336 ctrl |= E1000_CTRL_SWDPIN0;
4337 ctrl |= E1000_CTRL_SWDPIO0;
4338 } else {
4339 /* Clear SW Defineable Pin 0 to turn on the LED */
4340 ctrl &= ~E1000_CTRL_SWDPIN0;
4341 ctrl |= E1000_CTRL_SWDPIO0;
4342 }
4343 break;
4344 default:
4345 if(hw->media_type == e1000_media_type_fiber) {
4346 /* Clear SW Defineable Pin 0 to turn on the LED */
4347 ctrl &= ~E1000_CTRL_SWDPIN0;
4348 ctrl |= E1000_CTRL_SWDPIO0;
4349 } else if(hw->media_type == e1000_media_type_copper) {
4350 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4351 return E1000_SUCCESS;
4352 }
4353 break;
4354 }
4355
4356 E1000_WRITE_REG(hw, CTRL, ctrl);
4357
4358 return E1000_SUCCESS;
4359}
4360
4361/******************************************************************************
4362 * Turns off the software controllable LED
4363 *
4364 * hw - Struct containing variables accessed by shared code
4365 *****************************************************************************/
4366int32_t
4367e1000_led_off(struct e1000_hw *hw)
4368{
4369 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4370
4371 DEBUGFUNC("e1000_led_off");
4372
4373 switch(hw->mac_type) {
4374 case e1000_82542_rev2_0:
4375 case e1000_82542_rev2_1:
4376 case e1000_82543:
4377 /* Clear SW Defineable Pin 0 to turn off the LED */
4378 ctrl &= ~E1000_CTRL_SWDPIN0;
4379 ctrl |= E1000_CTRL_SWDPIO0;
4380 break;
4381 case e1000_82544:
4382 if(hw->media_type == e1000_media_type_fiber) {
4383 /* Clear SW Defineable Pin 0 to turn off the LED */
4384 ctrl &= ~E1000_CTRL_SWDPIN0;
4385 ctrl |= E1000_CTRL_SWDPIO0;
4386 } else {
4387 /* Set SW Defineable Pin 0 to turn off the LED */
4388 ctrl |= E1000_CTRL_SWDPIN0;
4389 ctrl |= E1000_CTRL_SWDPIO0;
4390 }
4391 break;
4392 default:
4393 if(hw->media_type == e1000_media_type_fiber) {
4394 /* Set SW Defineable Pin 0 to turn off the LED */
4395 ctrl |= E1000_CTRL_SWDPIN0;
4396 ctrl |= E1000_CTRL_SWDPIO0;
4397 } else if(hw->media_type == e1000_media_type_copper) {
4398 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4399 return E1000_SUCCESS;
4400 }
4401 break;
4402 }
4403
4404 E1000_WRITE_REG(hw, CTRL, ctrl);
4405
4406 return E1000_SUCCESS;
4407}
4408
4409/******************************************************************************
4410 * Clears all hardware statistics counters.
4411 *
4412 * hw - Struct containing variables accessed by shared code
4413 *****************************************************************************/
4414void
4415e1000_clear_hw_cntrs(struct e1000_hw *hw)
4416{
4417 volatile uint32_t temp;
4418
4419 temp = E1000_READ_REG(hw, CRCERRS);
4420 temp = E1000_READ_REG(hw, SYMERRS);
4421 temp = E1000_READ_REG(hw, MPC);
4422 temp = E1000_READ_REG(hw, SCC);
4423 temp = E1000_READ_REG(hw, ECOL);
4424 temp = E1000_READ_REG(hw, MCC);
4425 temp = E1000_READ_REG(hw, LATECOL);
4426 temp = E1000_READ_REG(hw, COLC);
4427 temp = E1000_READ_REG(hw, DC);
4428 temp = E1000_READ_REG(hw, SEC);
4429 temp = E1000_READ_REG(hw, RLEC);
4430 temp = E1000_READ_REG(hw, XONRXC);
4431 temp = E1000_READ_REG(hw, XONTXC);
4432 temp = E1000_READ_REG(hw, XOFFRXC);
4433 temp = E1000_READ_REG(hw, XOFFTXC);
4434 temp = E1000_READ_REG(hw, FCRUC);
4435 temp = E1000_READ_REG(hw, PRC64);
4436 temp = E1000_READ_REG(hw, PRC127);
4437 temp = E1000_READ_REG(hw, PRC255);
4438 temp = E1000_READ_REG(hw, PRC511);
4439 temp = E1000_READ_REG(hw, PRC1023);
4440 temp = E1000_READ_REG(hw, PRC1522);
4441 temp = E1000_READ_REG(hw, GPRC);
4442 temp = E1000_READ_REG(hw, BPRC);
4443 temp = E1000_READ_REG(hw, MPRC);
4444 temp = E1000_READ_REG(hw, GPTC);
4445 temp = E1000_READ_REG(hw, GORCL);
4446 temp = E1000_READ_REG(hw, GORCH);
4447 temp = E1000_READ_REG(hw, GOTCL);
4448 temp = E1000_READ_REG(hw, GOTCH);
4449 temp = E1000_READ_REG(hw, RNBC);
4450 temp = E1000_READ_REG(hw, RUC);
4451 temp = E1000_READ_REG(hw, RFC);
4452 temp = E1000_READ_REG(hw, ROC);
4453 temp = E1000_READ_REG(hw, RJC);
4454 temp = E1000_READ_REG(hw, TORL);
4455 temp = E1000_READ_REG(hw, TORH);
4456 temp = E1000_READ_REG(hw, TOTL);
4457 temp = E1000_READ_REG(hw, TOTH);
4458 temp = E1000_READ_REG(hw, TPR);
4459 temp = E1000_READ_REG(hw, TPT);
4460 temp = E1000_READ_REG(hw, PTC64);
4461 temp = E1000_READ_REG(hw, PTC127);
4462 temp = E1000_READ_REG(hw, PTC255);
4463 temp = E1000_READ_REG(hw, PTC511);
4464 temp = E1000_READ_REG(hw, PTC1023);
4465 temp = E1000_READ_REG(hw, PTC1522);
4466 temp = E1000_READ_REG(hw, MPTC);
4467 temp = E1000_READ_REG(hw, BPTC);
4468
4469 if(hw->mac_type < e1000_82543) return;
4470
4471 temp = E1000_READ_REG(hw, ALGNERRC);
4472 temp = E1000_READ_REG(hw, RXERRC);
4473 temp = E1000_READ_REG(hw, TNCRS);
4474 temp = E1000_READ_REG(hw, CEXTERR);
4475 temp = E1000_READ_REG(hw, TSCTC);
4476 temp = E1000_READ_REG(hw, TSCTFC);
4477
4478 if(hw->mac_type <= e1000_82544) return;
4479
4480 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC);
4483}
4484
4485/******************************************************************************
4486 * Resets Adaptive IFS to its default state.
4487 *
4488 * hw - Struct containing variables accessed by shared code
4489 *
4490 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4491 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4492 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4493 * before calling this function.
4494 *****************************************************************************/
4495void
4496e1000_reset_adaptive(struct e1000_hw *hw)
4497{
4498 DEBUGFUNC("e1000_reset_adaptive");
4499
4500 if(hw->adaptive_ifs) {
4501 if(!hw->ifs_params_forced) {
4502 hw->current_ifs_val = 0;
4503 hw->ifs_min_val = IFS_MIN;
4504 hw->ifs_max_val = IFS_MAX;
4505 hw->ifs_step_size = IFS_STEP;
4506 hw->ifs_ratio = IFS_RATIO;
4507 }
4508 hw->in_ifs_mode = FALSE;
4509 E1000_WRITE_REG(hw, AIT, 0);
4510 } else {
4511 DEBUGOUT("Not in Adaptive IFS mode!\n");
4512 }
4513}
4514
4515/******************************************************************************
4516 * Called during the callback/watchdog routine to update IFS value based on
4517 * the ratio of transmits to collisions.
4518 *
4519 * hw - Struct containing variables accessed by shared code
4520 * tx_packets - Number of transmits since last callback
4521 * total_collisions - Number of collisions since last callback
4522 *****************************************************************************/
4523void
4524e1000_update_adaptive(struct e1000_hw *hw)
4525{
4526 DEBUGFUNC("e1000_update_adaptive");
4527
4528 if(hw->adaptive_ifs) {
4529 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4530 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4531 hw->in_ifs_mode = TRUE;
4532 if(hw->current_ifs_val < hw->ifs_max_val) {
4533 if(hw->current_ifs_val == 0)
4534 hw->current_ifs_val = hw->ifs_min_val;
4535 else
4536 hw->current_ifs_val += hw->ifs_step_size;
4537 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4538 }
4539 }
4540 } else {
4541 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4542 hw->current_ifs_val = 0;
4543 hw->in_ifs_mode = FALSE;
4544 E1000_WRITE_REG(hw, AIT, 0);
4545 }
4546 }
4547 } else {
4548 DEBUGOUT("Not in Adaptive IFS mode!\n");
4549 }
4550}
4551
4552/******************************************************************************
4553 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4554 *
4555 * hw - Struct containing variables accessed by shared code
4556 * frame_len - The length of the frame in question
4557 * mac_addr - The Ethernet destination address of the frame in question
4558 *****************************************************************************/
4559void
4560e1000_tbi_adjust_stats(struct e1000_hw *hw,
4561 struct e1000_hw_stats *stats,
4562 uint32_t frame_len,
4563 uint8_t *mac_addr)
4564{
4565 uint64_t carry_bit;
4566
4567 /* First adjust the frame length. */
4568 frame_len--;
4569 /* We need to adjust the statistics counters, since the hardware
4570 * counters overcount this packet as a CRC error and undercount
4571 * the packet as a good packet
4572 */
4573 /* This packet should not be counted as a CRC error. */
4574 stats->crcerrs--;
4575 /* This packet does count as a Good Packet Received. */
4576 stats->gprc++;
4577
4578 /* Adjust the Good Octets received counters */
4579 carry_bit = 0x80000000 & stats->gorcl;
4580 stats->gorcl += frame_len;
4581 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4582 * Received Count) was one before the addition,
4583 * AND it is zero after, then we lost the carry out,
4584 * need to add one to Gorch (Good Octets Received Count High).
4585 * This could be simplified if all environments supported
4586 * 64-bit integers.
4587 */
4588 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4589 stats->gorch++;
4590 /* Is this a broadcast or multicast? Check broadcast first,
4591 * since the test for a multicast frame will test positive on
4592 * a broadcast frame.
4593 */
4594 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4595 /* Broadcast packet */
4596 stats->bprc++;
4597 else if(*mac_addr & 0x01)
4598 /* Multicast packet */
4599 stats->mprc++;
4600
4601 if(frame_len == hw->max_frame_size) {
4602 /* In this case, the hardware has overcounted the number of
4603 * oversize frames.
4604 */
4605 if(stats->roc > 0)
4606 stats->roc--;
4607 }
4608
4609 /* Adjust the bin counters when the extra byte put the frame in the
4610 * wrong bin. Remember that the frame_len was adjusted above.
4611 */
4612 if(frame_len == 64) {
4613 stats->prc64++;
4614 stats->prc127--;
4615 } else if(frame_len == 127) {
4616 stats->prc127++;
4617 stats->prc255--;
4618 } else if(frame_len == 255) {
4619 stats->prc255++;
4620 stats->prc511--;
4621 } else if(frame_len == 511) {
4622 stats->prc511++;
4623 stats->prc1023--;
4624 } else if(frame_len == 1023) {
4625 stats->prc1023++;
4626 stats->prc1522--;
4627 } else if(frame_len == 1522) {
4628 stats->prc1522++;
4629 }
4630}
4631
4632/******************************************************************************
4633 * Gets the current PCI bus type, speed, and width of the hardware
4634 *
4635 * hw - Struct containing variables accessed by shared code
4636 *****************************************************************************/
4637void
4638e1000_get_bus_info(struct e1000_hw *hw)
4639{
4640 uint32_t status;
4641
4642 switch (hw->mac_type) {
4643 case e1000_82542_rev2_0:
4644 case e1000_82542_rev2_1:
4645 hw->bus_type = e1000_bus_type_unknown;
4646 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown;
4648 break;
4649 default:
4650 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4652 e1000_bus_type_pcix : e1000_bus_type_pci;
4653
4654 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4655 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4656 e1000_bus_speed_66 : e1000_bus_speed_120;
4657 } else if(hw->bus_type == e1000_bus_type_pci) {
4658 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4659 e1000_bus_speed_66 : e1000_bus_speed_33;
4660 } else {
4661 switch (status & E1000_STATUS_PCIX_SPEED) {
4662 case E1000_STATUS_PCIX_SPEED_66:
4663 hw->bus_speed = e1000_bus_speed_66;
4664 break;
4665 case E1000_STATUS_PCIX_SPEED_100:
4666 hw->bus_speed = e1000_bus_speed_100;
4667 break;
4668 case E1000_STATUS_PCIX_SPEED_133:
4669 hw->bus_speed = e1000_bus_speed_133;
4670 break;
4671 default:
4672 hw->bus_speed = e1000_bus_speed_reserved;
4673 break;
4674 }
4675 }
4676 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4677 e1000_bus_width_64 : e1000_bus_width_32;
4678 break;
4679 }
4680}
4681/******************************************************************************
4682 * Reads a value from one of the devices registers using port I/O (as opposed
4683 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4684 *
4685 * hw - Struct containing variables accessed by shared code
4686 * offset - offset to read from
4687 *****************************************************************************/
4688uint32_t
4689e1000_read_reg_io(struct e1000_hw *hw,
4690 uint32_t offset)
4691{
4692 unsigned long io_addr = hw->io_base;
4693 unsigned long io_data = hw->io_base + 4;
4694
4695 e1000_io_write(hw, io_addr, offset);
4696 return e1000_io_read(hw, io_data);
4697}
4698
4699/******************************************************************************
4700 * Writes a value to one of the devices registers using port I/O (as opposed to
4701 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4702 *
4703 * hw - Struct containing variables accessed by shared code
4704 * offset - offset to write to
4705 * value - value to write
4706 *****************************************************************************/
4707void
4708e1000_write_reg_io(struct e1000_hw *hw,
4709 uint32_t offset,
4710 uint32_t value)
4711{
4712 unsigned long io_addr = hw->io_base;
4713 unsigned long io_data = hw->io_base + 4;
4714
4715 e1000_io_write(hw, io_addr, offset);
4716 e1000_io_write(hw, io_data, value);
4717}
4718
4719
4720/******************************************************************************
4721 * Estimates the cable length.
4722 *
4723 * hw - Struct containing variables accessed by shared code
4724 * min_length - The estimated minimum length
4725 * max_length - The estimated maximum length
4726 *
4727 * returns: - E1000_ERR_XXX
4728 * E1000_SUCCESS
4729 *
4730 * This function always returns a ranged length (minimum & maximum).
4731 * So for M88 phy's, this function interprets the one value returned from the
4732 * register to the minimum and maximum range.
4733 * For IGP phy's, the function calculates the range by the AGC registers.
4734 *****************************************************************************/
4735int32_t
4736e1000_get_cable_length(struct e1000_hw *hw,
4737 uint16_t *min_length,
4738 uint16_t *max_length)
4739{
4740 int32_t ret_val;
4741 uint16_t agc_value = 0;
4742 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4743 uint16_t i, phy_data;
4744 uint16_t cable_length;
4745
4746 DEBUGFUNC("e1000_get_cable_length");
4747
4748 *min_length = *max_length = 0;
4749
4750 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) {
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data);
4754 if(ret_val)
4755 return ret_val;
4756 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4757 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4758
4759 /* Convert the enum value to ranged values */
4760 switch (cable_length) {
4761 case e1000_cable_length_50:
4762 *min_length = 0;
4763 *max_length = e1000_igp_cable_length_50;
4764 break;
4765 case e1000_cable_length_50_80:
4766 *min_length = e1000_igp_cable_length_50;
4767 *max_length = e1000_igp_cable_length_80;
4768 break;
4769 case e1000_cable_length_80_110:
4770 *min_length = e1000_igp_cable_length_80;
4771 *max_length = e1000_igp_cable_length_110;
4772 break;
4773 case e1000_cable_length_110_140:
4774 *min_length = e1000_igp_cable_length_110;
4775 *max_length = e1000_igp_cable_length_140;
4776 break;
4777 case e1000_cable_length_140:
4778 *min_length = e1000_igp_cable_length_140;
4779 *max_length = e1000_igp_cable_length_170;
4780 break;
4781 default:
4782 return -E1000_ERR_PHY;
4783 break;
4784 }
4785 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4786 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4787 {IGP01E1000_PHY_AGC_A,
4788 IGP01E1000_PHY_AGC_B,
4789 IGP01E1000_PHY_AGC_C,
4790 IGP01E1000_PHY_AGC_D};
4791 /* Read the AGC registers for all channels */
4792 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4793
4794 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4795 if(ret_val)
4796 return ret_val;
4797
4798 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4799
4800 /* Array bound check. */
4801 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4802 (cur_agc == 0))
4803 return -E1000_ERR_PHY;
4804
4805 agc_value += cur_agc;
4806
4807 /* Update minimal AGC value. */
4808 if(min_agc > cur_agc)
4809 min_agc = cur_agc;
4810 }
4811
4812 /* Remove the minimal AGC result for length < 50m */
4813 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4814 agc_value -= min_agc;
4815
4816 /* Get the average length of the remaining 3 channels */
4817 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4818 } else {
4819 /* Get the average length of all the 4 channels. */
4820 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4821 }
4822
4823 /* Set the range of the calculated length. */
4824 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4825 IGP01E1000_AGC_RANGE) > 0) ?
4826 (e1000_igp_cable_length_table[agc_value] -
4827 IGP01E1000_AGC_RANGE) : 0;
4828 *max_length = e1000_igp_cable_length_table[agc_value] +
4829 IGP01E1000_AGC_RANGE;
4830 }
4831
4832 return E1000_SUCCESS;
4833}
4834
4835/******************************************************************************
4836 * Check the cable polarity
4837 *
4838 * hw - Struct containing variables accessed by shared code
4839 * polarity - output parameter : 0 - Polarity is not reversed
4840 * 1 - Polarity is reversed.
4841 *
4842 * returns: - E1000_ERR_XXX
4843 * E1000_SUCCESS
4844 *
4845 * For phy's older then IGP, this function simply reads the polarity bit in the
4846 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4847 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4848 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4849 * IGP01E1000_PHY_PCS_INIT_REG.
4850 *****************************************************************************/
4851int32_t
4852e1000_check_polarity(struct e1000_hw *hw,
4853 uint16_t *polarity)
4854{
4855 int32_t ret_val;
4856 uint16_t phy_data;
4857
4858 DEBUGFUNC("e1000_check_polarity");
4859
4860 if(hw->phy_type == e1000_phy_m88) {
4861 /* return the Polarity bit in the Status register. */
4862 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4863 &phy_data);
4864 if(ret_val)
4865 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) {
4869 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data);
4872 if(ret_val)
4873 return ret_val;
4874
4875 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4876 * find the polarity status */
4877 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4878 IGP01E1000_PSSR_SPEED_1000MBPS) {
4879
4880 /* Read the GIG initialization PCS register (0x00B4) */
4881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4882 &phy_data);
4883 if(ret_val)
4884 return ret_val;
4885
4886 /* Check the polarity bits */
4887 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4888 } else {
4889 /* For 10 Mbps, read the polarity bit in the status register. (for
4890 * 100 Mbps this bit is always 0) */
4891 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4892 }
4893 }
4894 return E1000_SUCCESS;
4895}
4896
4897/******************************************************************************
4898 * Check if Downshift occured
4899 *
4900 * hw - Struct containing variables accessed by shared code
4901 * downshift - output parameter : 0 - No Downshift ocured.
4902 * 1 - Downshift ocured.
4903 *
4904 * returns: - E1000_ERR_XXX
4905 * E1000_SUCCESS
4906 *
4907 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4908 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4909 * Link Health register. In IGP this bit is latched high, so the driver must
4910 * read it immediately after link is established.
4911 *****************************************************************************/
4912int32_t
4913e1000_check_downshift(struct e1000_hw *hw)
4914{
4915 int32_t ret_val;
4916 uint16_t phy_data;
4917
4918 DEBUGFUNC("e1000_check_downshift");
4919
4920 if(hw->phy_type == e1000_phy_igp) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data);
4923 if(ret_val)
4924 return ret_val;
4925
4926 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4927 } else if(hw->phy_type == e1000_phy_m88) {
4928 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4929 &phy_data);
4930 if(ret_val)
4931 return ret_val;
4932
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 }
4936 return E1000_SUCCESS;
4937}
4938
4939/*****************************************************************************
4940 *
4941 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4942 * gigabit link is achieved to improve link quality.
4943 *
4944 * hw: Struct containing variables accessed by shared code
4945 *
4946 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4947 * E1000_SUCCESS at any other case.
4948 *
4949 ****************************************************************************/
4950
4951int32_t
4952e1000_config_dsp_after_link_change(struct e1000_hw *hw,
4953 boolean_t link_up)
4954{
4955 int32_t ret_val;
4956 uint16_t phy_data, phy_saved_data, speed, duplex, i;
4957 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4958 {IGP01E1000_PHY_AGC_PARAM_A,
4959 IGP01E1000_PHY_AGC_PARAM_B,
4960 IGP01E1000_PHY_AGC_PARAM_C,
4961 IGP01E1000_PHY_AGC_PARAM_D};
4962 uint16_t min_length, max_length;
4963
4964 DEBUGFUNC("e1000_config_dsp_after_link_change");
4965
4966 if(hw->phy_type != e1000_phy_igp)
4967 return E1000_SUCCESS;
4968
4969 if(link_up) {
4970 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
4971 if(ret_val) {
4972 DEBUGOUT("Error getting link speed and duplex\n");
4973 return ret_val;
4974 }
4975
4976 if(speed == SPEED_1000) {
4977
4978 e1000_get_cable_length(hw, &min_length, &max_length);
4979
4980 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
4981 min_length >= e1000_igp_cable_length_50) {
4982
4983 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4984 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4985 &phy_data);
4986 if(ret_val)
4987 return ret_val;
4988
4989 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4990
4991 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
4992 phy_data);
4993 if(ret_val)
4994 return ret_val;
4995 }
4996 hw->dsp_config_state = e1000_dsp_config_activated;
4997 }
4998
4999 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
5000 (min_length < e1000_igp_cable_length_50)) {
5001
5002 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5003 uint32_t idle_errs = 0;
5004
5005 /* clear previous idle error counts */
5006 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5007 &phy_data);
5008 if(ret_val)
5009 return ret_val;
5010
5011 for(i = 0; i < ffe_idle_err_timeout; i++) {
5012 udelay(1000);
5013 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5014 &phy_data);
5015 if(ret_val)
5016 return ret_val;
5017
5018 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5019 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5020 hw->ffe_config_state = e1000_ffe_config_active;
5021
5022 ret_val = e1000_write_phy_reg(hw,
5023 IGP01E1000_PHY_DSP_FFE,
5024 IGP01E1000_PHY_DSP_FFE_CM_CP);
5025 if(ret_val)
5026 return ret_val;
5027 break;
5028 }
5029
5030 if(idle_errs)
5031 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5032 }
5033 }
5034 }
5035 } else {
5036 if(hw->dsp_config_state == e1000_dsp_config_activated) {
5037 /* Save off the current value of register 0x2F5B to be restored at
5038 * the end of the routines. */
5039 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5040
5041 if(ret_val)
5042 return ret_val;
5043
5044 /* Disable the PHY transmitter */
5045 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5046
5047 if(ret_val)
5048 return ret_val;
5049
5050 msec_delay(20);
5051
5052 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA);
5054 if(ret_val)
5055 return ret_val;
5056 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5057 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
5058 if(ret_val)
5059 return ret_val;
5060
5061 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5062 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5063
5064 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
5065 if(ret_val)
5066 return ret_val;
5067 }
5068
5069 ret_val = e1000_write_phy_reg(hw, 0x0000,
5070 IGP01E1000_IEEE_RESTART_AUTONEG);
5071 if(ret_val)
5072 return ret_val;
5073
5074 msec_delay(20);
5075
5076 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5078
5079 if(ret_val)
5080 return ret_val;
5081
5082 hw->dsp_config_state = e1000_dsp_config_enabled;
5083 }
5084
5085 if(hw->ffe_config_state == e1000_ffe_config_active) {
5086 /* Save off the current value of register 0x2F5B to be restored at
5087 * the end of the routines. */
5088 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5089
5090 if(ret_val)
5091 return ret_val;
5092
5093 /* Disable the PHY transmitter */
5094 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5095
5096 if(ret_val)
5097 return ret_val;
5098
5099 msec_delay(20);
5100
5101 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA);
5103 if(ret_val)
5104 return ret_val;
5105 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5106 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5107 if(ret_val)
5108 return ret_val;
5109
5110 ret_val = e1000_write_phy_reg(hw, 0x0000,
5111 IGP01E1000_IEEE_RESTART_AUTONEG);
5112 if(ret_val)
5113 return ret_val;
5114
5115 msec_delay(20);
5116
5117 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5119
5120 if(ret_val)
5121 return ret_val;
5122
5123 hw->ffe_config_state = e1000_ffe_config_enabled;
5124 }
5125 }
5126 return E1000_SUCCESS;
5127}
5128
5129/*****************************************************************************
5130 * Set PHY to class A mode
5131 * Assumes the following operations will follow to enable the new class mode.
5132 * 1. Do a PHY soft reset
5133 * 2. Restart auto-negotiation or force link.
5134 *
5135 * hw - Struct containing variables accessed by shared code
5136 ****************************************************************************/
5137static int32_t
5138e1000_set_phy_mode(struct e1000_hw *hw)
5139{
5140 int32_t ret_val;
5141 uint16_t eeprom_data;
5142
5143 DEBUGFUNC("e1000_set_phy_mode");
5144
5145 if((hw->mac_type == e1000_82545_rev_3) &&
5146 (hw->media_type == e1000_media_type_copper)) {
5147 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5148 if(ret_val) {
5149 return ret_val;
5150 }
5151
5152 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5153 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5154 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5155 if(ret_val)
5156 return ret_val;
5157 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5158 if(ret_val)
5159 return ret_val;
5160
5161 hw->phy_reset_disable = FALSE;
5162 }
5163 }
5164
5165 return E1000_SUCCESS;
5166}
5167
5168/*****************************************************************************
5169 *
5170 * This function sets the lplu state according to the active flag. When
5171 * activating lplu this function also disables smart speed and vise versa.
5172 * lplu will not be activated unless the device autonegotiation advertisment
5173 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5174 * hw: Struct containing variables accessed by shared code
5175 * active - true to enable lplu false to disable lplu.
5176 *
5177 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5178 * E1000_SUCCESS at any other case.
5179 *
5180 ****************************************************************************/
5181
5182int32_t
5183e1000_set_d3_lplu_state(struct e1000_hw *hw,
5184 boolean_t active)
5185{
5186 int32_t ret_val;
5187 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state");
5189
5190 if(!((hw->mac_type == e1000_82541_rev_2) ||
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS;
5193
5194 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5198 if(ret_val)
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val)
5205 return ret_val;
5206
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During
5209 * driver activity we should enable SmartSpeed, so performance is
5210 * maintained. */
5211 if (hw->smart_speed == e1000_smart_speed_on) {
5212 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5213 &phy_data);
5214 if(ret_val)
5215 return ret_val;
5216
5217 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5218 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5219 phy_data);
5220 if(ret_val)
5221 return ret_val;
5222 } else if (hw->smart_speed == e1000_smart_speed_off) {
5223 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5224 &phy_data);
5225 if (ret_val)
5226 return ret_val;
5227
5228 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5229 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5230 phy_data);
5231 if(ret_val)
5232 return ret_val;
5233 }
5234
5235 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5241 if(ret_val)
5242 return ret_val;
5243
5244 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val)
5247 return ret_val;
5248
5249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5251 if(ret_val)
5252 return ret_val;
5253
5254 }
5255 return E1000_SUCCESS;
5256}
5257
5258/******************************************************************************
5259 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5260 *
5261 * hw - Struct containing variables accessed by shared code
5262 *****************************************************************************/
5263static int32_t
5264e1000_set_vco_speed(struct e1000_hw *hw)
5265{
5266 int32_t ret_val;
5267 uint16_t default_page = 0;
5268 uint16_t phy_data;
5269
5270 DEBUGFUNC("e1000_set_vco_speed");
5271
5272 switch(hw->mac_type) {
5273 case e1000_82545_rev_3:
5274 case e1000_82546_rev_3:
5275 break;
5276 default:
5277 return E1000_SUCCESS;
5278 }
5279
5280 /* Set PHY register 30, page 5, bit 8 to 0 */
5281
5282 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5283 if(ret_val)
5284 return ret_val;
5285
5286 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5287 if(ret_val)
5288 return ret_val;
5289
5290 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5291 if(ret_val)
5292 return ret_val;
5293
5294 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5295 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5296 if(ret_val)
5297 return ret_val;
5298
5299 /* Set PHY register 30, page 4, bit 11 to 1 */
5300
5301 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5302 if(ret_val)
5303 return ret_val;
5304
5305 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5306 if(ret_val)
5307 return ret_val;
5308
5309 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5310 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5311 if(ret_val)
5312 return ret_val;
5313
5314 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5315 if(ret_val)
5316 return ret_val;
5317
5318 return E1000_SUCCESS;
5319}
5320
5321static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{
5324 int32_t ret_val;
5325 uint16_t mii_status_reg;
5326 uint16_t i;
5327
5328 /* Polarity reversal workaround for forced 10F/10H links. */
5329
5330 /* Disable the transmitter on the PHY */
5331
5332 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5333 if(ret_val)
5334 return ret_val;
5335 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5336 if(ret_val)
5337 return ret_val;
5338
5339 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5340 if(ret_val)
5341 return ret_val;
5342
5343 /* This loop will early-out if the NO link condition has been met. */
5344 for(i = PHY_FORCE_TIME; i > 0; i--) {
5345 /* Read the MII Status Register and wait for Link Status bit
5346 * to be clear.
5347 */
5348
5349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5350 if(ret_val)
5351 return ret_val;
5352
5353 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5354 if(ret_val)
5355 return ret_val;
5356
5357 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
5358 msec_delay_irq(100);
5359 }
5360
5361 /* Recommended delay time after link has been lost */
5362 msec_delay_irq(1000);
5363
5364 /* Now we will re-enable th transmitter on the PHY */
5365
5366 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5367 if(ret_val)
5368 return ret_val;
5369 msec_delay_irq(50);
5370 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5371 if(ret_val)
5372 return ret_val;
5373 msec_delay_irq(50);
5374 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5375 if(ret_val)
5376 return ret_val;
5377 msec_delay_irq(50);
5378 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5379 if(ret_val)
5380 return ret_val;
5381
5382 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5383 if(ret_val)
5384 return ret_val;
5385
5386 /* This loop will early-out if the link condition has been met. */
5387 for(i = PHY_FORCE_TIME; i > 0; i--) {
5388 /* Read the MII Status Register and wait for Link Status bit
5389 * to be set.
5390 */
5391
5392 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5393 if(ret_val)
5394 return ret_val;
5395
5396 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5397 if(ret_val)
5398 return ret_val;
5399
5400 if(mii_status_reg & MII_SR_LINK_STATUS) break;
5401 msec_delay_irq(100);
5402 }
5403 return E1000_SUCCESS;
5404}
5405
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
new file mode 100644
index 000000000000..f397e637a3c5
--- /dev/null
+++ b/drivers/net/e1000/e1000_hw.h
@@ -0,0 +1,2144 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
60 e1000_num_macs
61} e1000_mac_type;
62
63typedef enum {
64 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi,
66 e1000_eeprom_microwire,
67 e1000_num_eeprom_types
68} e1000_eeprom_type;
69
70/* Media Types */
71typedef enum {
72 e1000_media_type_copper = 0,
73 e1000_media_type_fiber = 1,
74 e1000_media_type_internal_serdes = 2,
75 e1000_num_media_types
76} e1000_media_type;
77
78typedef enum {
79 e1000_10_half = 0,
80 e1000_10_full = 1,
81 e1000_100_half = 2,
82 e1000_100_full = 3
83} e1000_speed_duplex_type;
84
85/* Flow Control Settings */
86typedef enum {
87 e1000_fc_none = 0,
88 e1000_fc_rx_pause = 1,
89 e1000_fc_tx_pause = 2,
90 e1000_fc_full = 3,
91 e1000_fc_default = 0xFF
92} e1000_fc_type;
93
94/* PCI bus types */
95typedef enum {
96 e1000_bus_type_unknown = 0,
97 e1000_bus_type_pci,
98 e1000_bus_type_pcix,
99 e1000_bus_type_reserved
100} e1000_bus_type;
101
102/* PCI bus speeds */
103typedef enum {
104 e1000_bus_speed_unknown = 0,
105 e1000_bus_speed_33,
106 e1000_bus_speed_66,
107 e1000_bus_speed_100,
108 e1000_bus_speed_120,
109 e1000_bus_speed_133,
110 e1000_bus_speed_reserved
111} e1000_bus_speed;
112
113/* PCI bus widths */
114typedef enum {
115 e1000_bus_width_unknown = 0,
116 e1000_bus_width_32,
117 e1000_bus_width_64,
118 e1000_bus_width_reserved
119} e1000_bus_width;
120
121/* PHY status info structure and supporting enums */
122typedef enum {
123 e1000_cable_length_50 = 0,
124 e1000_cable_length_50_80,
125 e1000_cable_length_80_110,
126 e1000_cable_length_110_140,
127 e1000_cable_length_140,
128 e1000_cable_length_undefined = 0xFF
129} e1000_cable_length;
130
131typedef enum {
132 e1000_igp_cable_length_10 = 10,
133 e1000_igp_cable_length_20 = 20,
134 e1000_igp_cable_length_30 = 30,
135 e1000_igp_cable_length_40 = 40,
136 e1000_igp_cable_length_50 = 50,
137 e1000_igp_cable_length_60 = 60,
138 e1000_igp_cable_length_70 = 70,
139 e1000_igp_cable_length_80 = 80,
140 e1000_igp_cable_length_90 = 90,
141 e1000_igp_cable_length_100 = 100,
142 e1000_igp_cable_length_110 = 110,
143 e1000_igp_cable_length_120 = 120,
144 e1000_igp_cable_length_130 = 130,
145 e1000_igp_cable_length_140 = 140,
146 e1000_igp_cable_length_150 = 150,
147 e1000_igp_cable_length_160 = 160,
148 e1000_igp_cable_length_170 = 170,
149 e1000_igp_cable_length_180 = 180
150} e1000_igp_cable_length;
151
152typedef enum {
153 e1000_10bt_ext_dist_enable_normal = 0,
154 e1000_10bt_ext_dist_enable_lower,
155 e1000_10bt_ext_dist_enable_undefined = 0xFF
156} e1000_10bt_ext_dist_enable;
157
158typedef enum {
159 e1000_rev_polarity_normal = 0,
160 e1000_rev_polarity_reversed,
161 e1000_rev_polarity_undefined = 0xFF
162} e1000_rev_polarity;
163
164typedef enum {
165 e1000_downshift_normal = 0,
166 e1000_downshift_activated,
167 e1000_downshift_undefined = 0xFF
168} e1000_downshift;
169
170typedef enum {
171 e1000_smart_speed_default = 0,
172 e1000_smart_speed_on,
173 e1000_smart_speed_off
174} e1000_smart_speed;
175
176typedef enum {
177 e1000_polarity_reversal_enabled = 0,
178 e1000_polarity_reversal_disabled,
179 e1000_polarity_reversal_undefined = 0xFF
180} e1000_polarity_reversal;
181
182typedef enum {
183 e1000_auto_x_mode_manual_mdi = 0,
184 e1000_auto_x_mode_manual_mdix,
185 e1000_auto_x_mode_auto1,
186 e1000_auto_x_mode_auto2,
187 e1000_auto_x_mode_undefined = 0xFF
188} e1000_auto_x_mode;
189
190typedef enum {
191 e1000_1000t_rx_status_not_ok = 0,
192 e1000_1000t_rx_status_ok,
193 e1000_1000t_rx_status_undefined = 0xFF
194} e1000_1000t_rx_status;
195
196typedef enum {
197 e1000_phy_m88 = 0,
198 e1000_phy_igp,
199 e1000_phy_undefined = 0xFF
200} e1000_phy_type;
201
202typedef enum {
203 e1000_ms_hw_default = 0,
204 e1000_ms_force_master,
205 e1000_ms_force_slave,
206 e1000_ms_auto
207} e1000_ms_type;
208
209typedef enum {
210 e1000_ffe_config_enabled = 0,
211 e1000_ffe_config_active,
212 e1000_ffe_config_blocked
213} e1000_ffe_config;
214
215typedef enum {
216 e1000_dsp_config_disabled = 0,
217 e1000_dsp_config_enabled,
218 e1000_dsp_config_activated,
219 e1000_dsp_config_undefined = 0xFF
220} e1000_dsp_config;
221
222struct e1000_phy_info {
223 e1000_cable_length cable_length;
224 e1000_10bt_ext_dist_enable extended_10bt_distance;
225 e1000_rev_polarity cable_polarity;
226 e1000_downshift downshift;
227 e1000_polarity_reversal polarity_correction;
228 e1000_auto_x_mode mdix_mode;
229 e1000_1000t_rx_status local_rx;
230 e1000_1000t_rx_status remote_rx;
231};
232
233struct e1000_phy_stats {
234 uint32_t idle_errors;
235 uint32_t receive_errors;
236};
237
238struct e1000_eeprom_info {
239 e1000_eeprom_type type;
240 uint16_t word_size;
241 uint16_t opcode_bits;
242 uint16_t address_bits;
243 uint16_t delay_usec;
244 uint16_t page_size;
245};
246
247
248
249/* Error Codes */
250#define E1000_SUCCESS 0
251#define E1000_ERR_EEPROM 1
252#define E1000_ERR_PHY 2
253#define E1000_ERR_CONFIG 3
254#define E1000_ERR_PARAM 4
255#define E1000_ERR_MAC_TYPE 5
256#define E1000_ERR_PHY_TYPE 6
257
258/* Function prototypes */
259/* Initialization */
260int32_t e1000_reset_hw(struct e1000_hw *hw);
261int32_t e1000_init_hw(struct e1000_hw *hw);
262int32_t e1000_set_mac_type(struct e1000_hw *hw);
263void e1000_set_media_type(struct e1000_hw *hw);
264
265/* Link Configuration */
266int32_t e1000_setup_link(struct e1000_hw *hw);
267int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
268void e1000_config_collision_dist(struct e1000_hw *hw);
269int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
270int32_t e1000_check_for_link(struct e1000_hw *hw);
271int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
272int32_t e1000_wait_autoneg(struct e1000_hw *hw);
273int32_t e1000_force_mac_fc(struct e1000_hw *hw);
274
275/* PHY */
276int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
277int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
278void e1000_phy_hw_reset(struct e1000_hw *hw);
279int32_t e1000_phy_reset(struct e1000_hw *hw);
280int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
281int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
282int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
283int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
284int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
285int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
286int32_t e1000_check_downshift(struct e1000_hw *hw);
287int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
288
289/* EEPROM Functions */
290void e1000_init_eeprom_params(struct e1000_hw *hw);
291int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
292int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
293int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
294int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
295int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
296int32_t e1000_read_mac_addr(struct e1000_hw * hw);
297
298/* Filters (multicast, vlan, receive) */
299void e1000_init_rx_addrs(struct e1000_hw *hw);
300void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
301uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
302void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
303void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
304void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
305void e1000_clear_vfta(struct e1000_hw *hw);
306
307/* LED functions */
308int32_t e1000_setup_led(struct e1000_hw *hw);
309int32_t e1000_cleanup_led(struct e1000_hw *hw);
310int32_t e1000_led_on(struct e1000_hw *hw);
311int32_t e1000_led_off(struct e1000_hw *hw);
312
313/* Adaptive IFS Functions */
314
315/* Everything else */
316uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
317void e1000_clear_hw_cntrs(struct e1000_hw *hw);
318void e1000_reset_adaptive(struct e1000_hw *hw);
319void e1000_update_adaptive(struct e1000_hw *hw);
320void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
321void e1000_get_bus_info(struct e1000_hw *hw);
322void e1000_pci_set_mwi(struct e1000_hw *hw);
323void e1000_pci_clear_mwi(struct e1000_hw *hw);
324void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
325void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
326/* Port I/O is only supported on 82544 and newer */
327uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
328uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
329void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
330void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
331int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
332int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
333
334#define E1000_READ_REG_IO(a, reg) \
335 e1000_read_reg_io((a), E1000_##reg)
336#define E1000_WRITE_REG_IO(a, reg, val) \
337 e1000_write_reg_io((a), E1000_##reg, val)
338
339/* PCI Device IDs */
340#define E1000_DEV_ID_82542 0x1000
341#define E1000_DEV_ID_82543GC_FIBER 0x1001
342#define E1000_DEV_ID_82543GC_COPPER 0x1004
343#define E1000_DEV_ID_82544EI_COPPER 0x1008
344#define E1000_DEV_ID_82544EI_FIBER 0x1009
345#define E1000_DEV_ID_82544GC_COPPER 0x100C
346#define E1000_DEV_ID_82544GC_LOM 0x100D
347#define E1000_DEV_ID_82540EM 0x100E
348#define E1000_DEV_ID_82540EM_LOM 0x1015
349#define E1000_DEV_ID_82540EP_LOM 0x1016
350#define E1000_DEV_ID_82540EP 0x1017
351#define E1000_DEV_ID_82540EP_LP 0x101E
352#define E1000_DEV_ID_82545EM_COPPER 0x100F
353#define E1000_DEV_ID_82545EM_FIBER 0x1011
354#define E1000_DEV_ID_82545GM_COPPER 0x1026
355#define E1000_DEV_ID_82545GM_FIBER 0x1027
356#define E1000_DEV_ID_82545GM_SERDES 0x1028
357#define E1000_DEV_ID_82546EB_COPPER 0x1010
358#define E1000_DEV_ID_82546EB_FIBER 0x1012
359#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
360#define E1000_DEV_ID_82541EI 0x1013
361#define E1000_DEV_ID_82541EI_MOBILE 0x1018
362#define E1000_DEV_ID_82541ER 0x1078
363#define E1000_DEV_ID_82547GI 0x1075
364#define E1000_DEV_ID_82541GI 0x1076
365#define E1000_DEV_ID_82541GI_MOBILE 0x1077
366#define E1000_DEV_ID_82541GI_LF 0x107C
367#define E1000_DEV_ID_82546GB_COPPER 0x1079
368#define E1000_DEV_ID_82546GB_FIBER 0x107A
369#define E1000_DEV_ID_82546GB_SERDES 0x107B
370#define E1000_DEV_ID_82546GB_PCIE 0x108A
371#define E1000_DEV_ID_82547EI 0x1019
372
373#define NODE_ADDRESS_SIZE 6
374#define ETH_LENGTH_OF_ADDRESS 6
375
376/* MAC decode size is 128K - This is the size of BAR0 */
377#define MAC_DECODE_SIZE (128 * 1024)
378
379#define E1000_82542_2_0_REV_ID 2
380#define E1000_82542_2_1_REV_ID 3
381#define E1000_REVISION_0 0
382#define E1000_REVISION_1 1
383#define E1000_REVISION_2 2
384
385#define SPEED_10 10
386#define SPEED_100 100
387#define SPEED_1000 1000
388#define HALF_DUPLEX 1
389#define FULL_DUPLEX 2
390
391/* The sizes (in bytes) of a ethernet packet */
392#define ENET_HEADER_SIZE 14
393#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
394#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
395#define ETHERNET_FCS_SIZE 4
396#define MAXIMUM_ETHERNET_PACKET_SIZE \
397 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
398#define MINIMUM_ETHERNET_PACKET_SIZE \
399 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
400#define CRC_LENGTH ETHERNET_FCS_SIZE
401#define MAX_JUMBO_FRAME_SIZE 0x3F00
402
403
404/* 802.1q VLAN Packet Sizes */
405#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
406
407/* Ethertype field values */
408#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
409#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
410#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
411
412/* Packet Header defines */
413#define IP_PROTOCOL_TCP 6
414#define IP_PROTOCOL_UDP 0x11
415
416/* This defines the bits that are set in the Interrupt Mask
417 * Set/Read Register. Each bit is documented below:
418 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
419 * o RXSEQ = Receive Sequence Error
420 */
421#define POLL_IMS_ENABLE_MASK ( \
422 E1000_IMS_RXDMT0 | \
423 E1000_IMS_RXSEQ)
424
425/* This defines the bits that are set in the Interrupt Mask
426 * Set/Read Register. Each bit is documented below:
427 * o RXT0 = Receiver Timer Interrupt (ring 0)
428 * o TXDW = Transmit Descriptor Written Back
429 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
430 * o RXSEQ = Receive Sequence Error
431 * o LSC = Link Status Change
432 */
433#define IMS_ENABLE_MASK ( \
434 E1000_IMS_RXT0 | \
435 E1000_IMS_TXDW | \
436 E1000_IMS_RXDMT0 | \
437 E1000_IMS_RXSEQ | \
438 E1000_IMS_LSC)
439
440/* Number of high/low register pairs in the RAR. The RAR (Receive Address
441 * Registers) holds the directed and multicast addresses that we monitor. We
442 * reserve one of these spots for our directed address, allowing us room for
443 * E1000_RAR_ENTRIES - 1 multicast addresses.
444 */
445#define E1000_RAR_ENTRIES 15
446
447#define MIN_NUMBER_OF_DESCRIPTORS 8
448#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
449
450/* Receive Descriptor */
451struct e1000_rx_desc {
452 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
453 uint16_t length; /* Length of data DMAed into data buffer */
454 uint16_t csum; /* Packet checksum */
455 uint8_t status; /* Descriptor status */
456 uint8_t errors; /* Descriptor Errors */
457 uint16_t special;
458};
459
460/* Receive Decriptor bit definitions */
461#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
462#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
463#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
464#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
465#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
466#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
467#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
468#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
469#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
470#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
471#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
472#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
473#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
474#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
475#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
476#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
477#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
478#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
479#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
480
481/* mask to determine if packets should be dropped due to frame errors */
482#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
483 E1000_RXD_ERR_CE | \
484 E1000_RXD_ERR_SE | \
485 E1000_RXD_ERR_SEQ | \
486 E1000_RXD_ERR_CXE | \
487 E1000_RXD_ERR_RXE)
488
489/* Transmit Descriptor */
490struct e1000_tx_desc {
491 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
492 union {
493 uint32_t data;
494 struct {
495 uint16_t length; /* Data buffer length */
496 uint8_t cso; /* Checksum offset */
497 uint8_t cmd; /* Descriptor control */
498 } flags;
499 } lower;
500 union {
501 uint32_t data;
502 struct {
503 uint8_t status; /* Descriptor status */
504 uint8_t css; /* Checksum start */
505 uint16_t special;
506 } fields;
507 } upper;
508};
509
510/* Transmit Descriptor bit definitions */
511#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
512#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
513#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
514#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
515#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
516#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
517#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
518#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
519#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
520#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
521#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
522#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
523#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
524#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
525#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
526#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
527#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
528#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
529#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
530#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
531
532/* Offload Context Descriptor */
533struct e1000_context_desc {
534 union {
535 uint32_t ip_config;
536 struct {
537 uint8_t ipcss; /* IP checksum start */
538 uint8_t ipcso; /* IP checksum offset */
539 uint16_t ipcse; /* IP checksum end */
540 } ip_fields;
541 } lower_setup;
542 union {
543 uint32_t tcp_config;
544 struct {
545 uint8_t tucss; /* TCP checksum start */
546 uint8_t tucso; /* TCP checksum offset */
547 uint16_t tucse; /* TCP checksum end */
548 } tcp_fields;
549 } upper_setup;
550 uint32_t cmd_and_length; /* */
551 union {
552 uint32_t data;
553 struct {
554 uint8_t status; /* Descriptor status */
555 uint8_t hdr_len; /* Header length */
556 uint16_t mss; /* Maximum segment size */
557 } fields;
558 } tcp_seg_setup;
559};
560
561/* Offload data descriptor */
562struct e1000_data_desc {
563 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
564 union {
565 uint32_t data;
566 struct {
567 uint16_t length; /* Data buffer length */
568 uint8_t typ_len_ext; /* */
569 uint8_t cmd; /* */
570 } flags;
571 } lower;
572 union {
573 uint32_t data;
574 struct {
575 uint8_t status; /* Descriptor status */
576 uint8_t popts; /* Packet Options */
577 uint16_t special; /* */
578 } fields;
579 } upper;
580};
581
582/* Filters */
583#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
584#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
585#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
586
587
588/* Receive Address Register */
589struct e1000_rar {
590 volatile uint32_t low; /* receive address low */
591 volatile uint32_t high; /* receive address high */
592};
593
594/* Number of entries in the Multicast Table Array (MTA). */
595#define E1000_NUM_MTA_REGISTERS 128
596
597/* IPv4 Address Table Entry */
598struct e1000_ipv4_at_entry {
599 volatile uint32_t ipv4_addr; /* IP Address (RW) */
600 volatile uint32_t reserved;
601};
602
603/* Four wakeup IP addresses are supported */
604#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
605#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
606#define E1000_IP6AT_SIZE 1
607
608/* IPv6 Address Table Entry */
609struct e1000_ipv6_at_entry {
610 volatile uint8_t ipv6_addr[16];
611};
612
613/* Flexible Filter Length Table Entry */
614struct e1000_fflt_entry {
615 volatile uint32_t length; /* Flexible Filter Length (RW) */
616 volatile uint32_t reserved;
617};
618
619/* Flexible Filter Mask Table Entry */
620struct e1000_ffmt_entry {
621 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
622 volatile uint32_t reserved;
623};
624
625/* Flexible Filter Value Table Entry */
626struct e1000_ffvt_entry {
627 volatile uint32_t value; /* Flexible Filter Value (RW) */
628 volatile uint32_t reserved;
629};
630
631/* Four Flexible Filters are supported */
632#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
633
634/* Each Flexible Filter is at most 128 (0x80) bytes in length */
635#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
636
637#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
638#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
639#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
640
641/* Register Set. (82543, 82544)
642 *
643 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
644 * These registers are physically located on the NIC, but are mapped into the
645 * host memory address space.
646 *
647 * RW - register is both readable and writable
648 * RO - register is read only
649 * WO - register is write only
650 * R/clr - register is read only and is cleared when read
651 * A - register array
652 */
653#define E1000_CTRL 0x00000 /* Device Control - RW */
654#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
655#define E1000_STATUS 0x00008 /* Device Status - RO */
656#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
657#define E1000_EERD 0x00014 /* EEPROM Read - RW */
658#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
659#define E1000_FLA 0x0001C /* Flash Access - RW */
660#define E1000_MDIC 0x00020 /* MDI Control - RW */
661#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
662#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
663#define E1000_FCT 0x00030 /* Flow Control Type - RW */
664#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
665#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
666#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
667#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
668#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
669#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
670#define E1000_RCTL 0x00100 /* RX Control - RW */
671#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
672#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
673#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
674#define E1000_TCTL 0x00400 /* TX Control - RW */
675#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
676#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
677#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
678#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
679#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
680#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
681#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
682#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
683#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
684#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
685#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
686#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
687#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
688#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
689#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
690#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
691#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
692#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
693#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
694#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
695#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
696#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
697#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
698#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
699#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
700#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
701#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
702#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
703#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
704#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
705#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
706#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
707#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
708#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
709#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
710#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
711#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
712#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
713#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
714#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
715#define E1000_COLC 0x04028 /* Collision Count - R/clr */
716#define E1000_DC 0x04030 /* Defer Count - R/clr */
717#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
718#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
719#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
720#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
721#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
722#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
723#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
724#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
725#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
726#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
727#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
728#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
729#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
730#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
731#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
732#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
733#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
734#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
735#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
736#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
737#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
738#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
739#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
740#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
741#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
742#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
743#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
744#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
745#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
746#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
747#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
748#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
749#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
750#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
751#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
752#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
753#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
754#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
755#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
756#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
757#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
758#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
759#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
760#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
761#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
762#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
763#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
764#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
765#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
766#define E1000_RA 0x05400 /* Receive Address - RW Array */
767#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
768#define E1000_WUC 0x05800 /* Wakeup Control - RW */
769#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
770#define E1000_WUS 0x05810 /* Wakeup Status - RO */
771#define E1000_MANC 0x05820 /* Management Control - RW */
772#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
773#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
774#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
775#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
776#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
777#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
778#define E1000_HOST_IF 0x08800 /* Host Interface */
779#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
780#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
781
782/* Register Set (82542)
783 *
784 * Some of the 82542 registers are located at different offsets than they are
785 * in more current versions of the 8254x. Despite the difference in location,
786 * the registers function in the same manner.
787 */
788#define E1000_82542_CTRL E1000_CTRL
789#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
790#define E1000_82542_STATUS E1000_STATUS
791#define E1000_82542_EECD E1000_EECD
792#define E1000_82542_EERD E1000_EERD
793#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
794#define E1000_82542_FLA E1000_FLA
795#define E1000_82542_MDIC E1000_MDIC
796#define E1000_82542_FCAL E1000_FCAL
797#define E1000_82542_FCAH E1000_FCAH
798#define E1000_82542_FCT E1000_FCT
799#define E1000_82542_VET E1000_VET
800#define E1000_82542_RA 0x00040
801#define E1000_82542_ICR E1000_ICR
802#define E1000_82542_ITR E1000_ITR
803#define E1000_82542_ICS E1000_ICS
804#define E1000_82542_IMS E1000_IMS
805#define E1000_82542_IMC E1000_IMC
806#define E1000_82542_RCTL E1000_RCTL
807#define E1000_82542_RDTR 0x00108
808#define E1000_82542_RDBAL 0x00110
809#define E1000_82542_RDBAH 0x00114
810#define E1000_82542_RDLEN 0x00118
811#define E1000_82542_RDH 0x00120
812#define E1000_82542_RDT 0x00128
813#define E1000_82542_FCRTH 0x00160
814#define E1000_82542_FCRTL 0x00168
815#define E1000_82542_FCTTV E1000_FCTTV
816#define E1000_82542_TXCW E1000_TXCW
817#define E1000_82542_RXCW E1000_RXCW
818#define E1000_82542_MTA 0x00200
819#define E1000_82542_TCTL E1000_TCTL
820#define E1000_82542_TIPG E1000_TIPG
821#define E1000_82542_TDBAL 0x00420
822#define E1000_82542_TDBAH 0x00424
823#define E1000_82542_TDLEN 0x00428
824#define E1000_82542_TDH 0x00430
825#define E1000_82542_TDT 0x00438
826#define E1000_82542_TIDV 0x00440
827#define E1000_82542_TBT E1000_TBT
828#define E1000_82542_AIT E1000_AIT
829#define E1000_82542_VFTA 0x00600
830#define E1000_82542_LEDCTL E1000_LEDCTL
831#define E1000_82542_PBA E1000_PBA
832#define E1000_82542_RXDCTL E1000_RXDCTL
833#define E1000_82542_RADV E1000_RADV
834#define E1000_82542_RSRPD E1000_RSRPD
835#define E1000_82542_TXDMAC E1000_TXDMAC
836#define E1000_82542_TDFHS E1000_TDFHS
837#define E1000_82542_TDFTS E1000_TDFTS
838#define E1000_82542_TDFPC E1000_TDFPC
839#define E1000_82542_TXDCTL E1000_TXDCTL
840#define E1000_82542_TADV E1000_TADV
841#define E1000_82542_TSPMT E1000_TSPMT
842#define E1000_82542_CRCERRS E1000_CRCERRS
843#define E1000_82542_ALGNERRC E1000_ALGNERRC
844#define E1000_82542_SYMERRS E1000_SYMERRS
845#define E1000_82542_RXERRC E1000_RXERRC
846#define E1000_82542_MPC E1000_MPC
847#define E1000_82542_SCC E1000_SCC
848#define E1000_82542_ECOL E1000_ECOL
849#define E1000_82542_MCC E1000_MCC
850#define E1000_82542_LATECOL E1000_LATECOL
851#define E1000_82542_COLC E1000_COLC
852#define E1000_82542_DC E1000_DC
853#define E1000_82542_TNCRS E1000_TNCRS
854#define E1000_82542_SEC E1000_SEC
855#define E1000_82542_CEXTERR E1000_CEXTERR
856#define E1000_82542_RLEC E1000_RLEC
857#define E1000_82542_XONRXC E1000_XONRXC
858#define E1000_82542_XONTXC E1000_XONTXC
859#define E1000_82542_XOFFRXC E1000_XOFFRXC
860#define E1000_82542_XOFFTXC E1000_XOFFTXC
861#define E1000_82542_FCRUC E1000_FCRUC
862#define E1000_82542_PRC64 E1000_PRC64
863#define E1000_82542_PRC127 E1000_PRC127
864#define E1000_82542_PRC255 E1000_PRC255
865#define E1000_82542_PRC511 E1000_PRC511
866#define E1000_82542_PRC1023 E1000_PRC1023
867#define E1000_82542_PRC1522 E1000_PRC1522
868#define E1000_82542_GPRC E1000_GPRC
869#define E1000_82542_BPRC E1000_BPRC
870#define E1000_82542_MPRC E1000_MPRC
871#define E1000_82542_GPTC E1000_GPTC
872#define E1000_82542_GORCL E1000_GORCL
873#define E1000_82542_GORCH E1000_GORCH
874#define E1000_82542_GOTCL E1000_GOTCL
875#define E1000_82542_GOTCH E1000_GOTCH
876#define E1000_82542_RNBC E1000_RNBC
877#define E1000_82542_RUC E1000_RUC
878#define E1000_82542_RFC E1000_RFC
879#define E1000_82542_ROC E1000_ROC
880#define E1000_82542_RJC E1000_RJC
881#define E1000_82542_MGTPRC E1000_MGTPRC
882#define E1000_82542_MGTPDC E1000_MGTPDC
883#define E1000_82542_MGTPTC E1000_MGTPTC
884#define E1000_82542_TORL E1000_TORL
885#define E1000_82542_TORH E1000_TORH
886#define E1000_82542_TOTL E1000_TOTL
887#define E1000_82542_TOTH E1000_TOTH
888#define E1000_82542_TPR E1000_TPR
889#define E1000_82542_TPT E1000_TPT
890#define E1000_82542_PTC64 E1000_PTC64
891#define E1000_82542_PTC127 E1000_PTC127
892#define E1000_82542_PTC255 E1000_PTC255
893#define E1000_82542_PTC511 E1000_PTC511
894#define E1000_82542_PTC1023 E1000_PTC1023
895#define E1000_82542_PTC1522 E1000_PTC1522
896#define E1000_82542_MPTC E1000_MPTC
897#define E1000_82542_BPTC E1000_BPTC
898#define E1000_82542_TSCTC E1000_TSCTC
899#define E1000_82542_TSCTFC E1000_TSCTFC
900#define E1000_82542_RXCSUM E1000_RXCSUM
901#define E1000_82542_WUC E1000_WUC
902#define E1000_82542_WUFC E1000_WUFC
903#define E1000_82542_WUS E1000_WUS
904#define E1000_82542_MANC E1000_MANC
905#define E1000_82542_IPAV E1000_IPAV
906#define E1000_82542_IP4AT E1000_IP4AT
907#define E1000_82542_IP6AT E1000_IP6AT
908#define E1000_82542_WUPL E1000_WUPL
909#define E1000_82542_WUPM E1000_WUPM
910#define E1000_82542_FFLT E1000_FFLT
911#define E1000_82542_TDFH 0x08010
912#define E1000_82542_TDFT 0x08018
913#define E1000_82542_FFMT E1000_FFMT
914#define E1000_82542_FFVT E1000_FFVT
915#define E1000_82542_HOST_IF E1000_HOST_IF
916
917/* Statistics counters collected by the MAC */
918struct e1000_hw_stats {
919 uint64_t crcerrs;
920 uint64_t algnerrc;
921 uint64_t symerrs;
922 uint64_t rxerrc;
923 uint64_t mpc;
924 uint64_t scc;
925 uint64_t ecol;
926 uint64_t mcc;
927 uint64_t latecol;
928 uint64_t colc;
929 uint64_t dc;
930 uint64_t tncrs;
931 uint64_t sec;
932 uint64_t cexterr;
933 uint64_t rlec;
934 uint64_t xonrxc;
935 uint64_t xontxc;
936 uint64_t xoffrxc;
937 uint64_t xofftxc;
938 uint64_t fcruc;
939 uint64_t prc64;
940 uint64_t prc127;
941 uint64_t prc255;
942 uint64_t prc511;
943 uint64_t prc1023;
944 uint64_t prc1522;
945 uint64_t gprc;
946 uint64_t bprc;
947 uint64_t mprc;
948 uint64_t gptc;
949 uint64_t gorcl;
950 uint64_t gorch;
951 uint64_t gotcl;
952 uint64_t gotch;
953 uint64_t rnbc;
954 uint64_t ruc;
955 uint64_t rfc;
956 uint64_t roc;
957 uint64_t rjc;
958 uint64_t mgprc;
959 uint64_t mgpdc;
960 uint64_t mgptc;
961 uint64_t torl;
962 uint64_t torh;
963 uint64_t totl;
964 uint64_t toth;
965 uint64_t tpr;
966 uint64_t tpt;
967 uint64_t ptc64;
968 uint64_t ptc127;
969 uint64_t ptc255;
970 uint64_t ptc511;
971 uint64_t ptc1023;
972 uint64_t ptc1522;
973 uint64_t mptc;
974 uint64_t bptc;
975 uint64_t tsctc;
976 uint64_t tsctfc;
977};
978
979/* Structure containing variables used by the shared code (e1000_hw.c) */
980struct e1000_hw {
981 uint8_t __iomem *hw_addr;
982 e1000_mac_type mac_type;
983 e1000_phy_type phy_type;
984 uint32_t phy_init_script;
985 e1000_media_type media_type;
986 void *back;
987 e1000_fc_type fc;
988 e1000_bus_speed bus_speed;
989 e1000_bus_width bus_width;
990 e1000_bus_type bus_type;
991 struct e1000_eeprom_info eeprom;
992 e1000_ms_type master_slave;
993 e1000_ms_type original_master_slave;
994 e1000_ffe_config ffe_config_state;
995 uint32_t asf_firmware_present;
996 unsigned long io_base;
997 uint32_t phy_id;
998 uint32_t phy_revision;
999 uint32_t phy_addr;
1000 uint32_t original_fc;
1001 uint32_t txcw;
1002 uint32_t autoneg_failed;
1003 uint32_t max_frame_size;
1004 uint32_t min_frame_size;
1005 uint32_t mc_filter_type;
1006 uint32_t num_mc_addrs;
1007 uint32_t collision_delta;
1008 uint32_t tx_packet_delta;
1009 uint32_t ledctl_default;
1010 uint32_t ledctl_mode1;
1011 uint32_t ledctl_mode2;
1012 uint16_t phy_spd_default;
1013 uint16_t autoneg_advertised;
1014 uint16_t pci_cmd_word;
1015 uint16_t fc_high_water;
1016 uint16_t fc_low_water;
1017 uint16_t fc_pause_time;
1018 uint16_t current_ifs_val;
1019 uint16_t ifs_min_val;
1020 uint16_t ifs_max_val;
1021 uint16_t ifs_step_size;
1022 uint16_t ifs_ratio;
1023 uint16_t device_id;
1024 uint16_t vendor_id;
1025 uint16_t subsystem_id;
1026 uint16_t subsystem_vendor_id;
1027 uint8_t revision_id;
1028 uint8_t autoneg;
1029 uint8_t mdix;
1030 uint8_t forced_speed_duplex;
1031 uint8_t wait_autoneg_complete;
1032 uint8_t dma_fairness;
1033 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1034 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1035 boolean_t disable_polarity_correction;
1036 boolean_t speed_downgraded;
1037 e1000_smart_speed smart_speed;
1038 e1000_dsp_config dsp_config_state;
1039 boolean_t get_link_status;
1040 boolean_t serdes_link_down;
1041 boolean_t tbi_compatibility_en;
1042 boolean_t tbi_compatibility_on;
1043 boolean_t phy_reset_disable;
1044 boolean_t fc_send_xon;
1045 boolean_t fc_strict_ieee;
1046 boolean_t report_tx_early;
1047 boolean_t adaptive_ifs;
1048 boolean_t ifs_params_forced;
1049 boolean_t in_ifs_mode;
1050};
1051
1052
1053#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1054#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1055/* Register Bit Masks */
1056/* Device Control */
1057#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1058#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1059#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1060#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1061#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1062#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1063#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1064#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1065#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1066#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1067#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1068#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1069#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1070#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1071#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1072#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1073#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1074#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1075#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1076#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1077#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1078#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1079#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1080#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1081#define E1000_CTRL_RST 0x04000000 /* Global reset */
1082#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1083#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1084#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1085#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1086#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1087
1088/* Device Status */
1089#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1090#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1091#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1092#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1093#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1094#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1095#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1096#define E1000_STATUS_SPEED_MASK 0x000000C0
1097#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1098#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1099#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1100#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1101#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1102#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1103#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1104#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1105#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1106
1107/* Constants used to intrepret the masked PCI-X bus speed. */
1108#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1109#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1110#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1111
1112/* EEPROM/Flash Control */
1113#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1114#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1115#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1116#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1117#define E1000_EECD_FWE_MASK 0x00000030
1118#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1119#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1120#define E1000_EECD_FWE_SHIFT 4
1121#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1122#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1123#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1124#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1125#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1126 * (0-small, 1-large) */
1127#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1128#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1129#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1130#endif
1131
1132/* EEPROM Read */
1133#define E1000_EERD_START 0x00000001 /* Start Read */
1134#define E1000_EERD_DONE 0x00000010 /* Read Done */
1135#define E1000_EERD_ADDR_SHIFT 8
1136#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1137#define E1000_EERD_DATA_SHIFT 16
1138#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1139
1140/* SPI EEPROM Status Register */
1141#define EEPROM_STATUS_RDY_SPI 0x01
1142#define EEPROM_STATUS_WEN_SPI 0x02
1143#define EEPROM_STATUS_BP0_SPI 0x04
1144#define EEPROM_STATUS_BP1_SPI 0x08
1145#define EEPROM_STATUS_WPEN_SPI 0x80
1146
1147/* Extended Device Control */
1148#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1149#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1150#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1151#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1152#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1153#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1154#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1155#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1156#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1157#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1158#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1159#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1160#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1161#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1162#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1163#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1164#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1165#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1166#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1167#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1168#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1169#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1170#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1171#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1172#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1173#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1174
1175/* MDI Control */
1176#define E1000_MDIC_DATA_MASK 0x0000FFFF
1177#define E1000_MDIC_REG_MASK 0x001F0000
1178#define E1000_MDIC_REG_SHIFT 16
1179#define E1000_MDIC_PHY_MASK 0x03E00000
1180#define E1000_MDIC_PHY_SHIFT 21
1181#define E1000_MDIC_OP_WRITE 0x04000000
1182#define E1000_MDIC_OP_READ 0x08000000
1183#define E1000_MDIC_READY 0x10000000
1184#define E1000_MDIC_INT_EN 0x20000000
1185#define E1000_MDIC_ERROR 0x40000000
1186
1187/* LED Control */
1188#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1189#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1190#define E1000_LEDCTL_LED0_IVRT 0x00000040
1191#define E1000_LEDCTL_LED0_BLINK 0x00000080
1192#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1193#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1194#define E1000_LEDCTL_LED1_IVRT 0x00004000
1195#define E1000_LEDCTL_LED1_BLINK 0x00008000
1196#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1197#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1198#define E1000_LEDCTL_LED2_IVRT 0x00400000
1199#define E1000_LEDCTL_LED2_BLINK 0x00800000
1200#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1201#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1202#define E1000_LEDCTL_LED3_IVRT 0x40000000
1203#define E1000_LEDCTL_LED3_BLINK 0x80000000
1204
1205#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1206#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1207#define E1000_LEDCTL_MODE_LINK_UP 0x2
1208#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1209#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1210#define E1000_LEDCTL_MODE_LINK_10 0x5
1211#define E1000_LEDCTL_MODE_LINK_100 0x6
1212#define E1000_LEDCTL_MODE_LINK_1000 0x7
1213#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1214#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1215#define E1000_LEDCTL_MODE_COLLISION 0xA
1216#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1217#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1218#define E1000_LEDCTL_MODE_PAUSED 0xD
1219#define E1000_LEDCTL_MODE_LED_ON 0xE
1220#define E1000_LEDCTL_MODE_LED_OFF 0xF
1221
1222/* Receive Address */
1223#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1224
1225/* Interrupt Cause Read */
1226#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1227#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1228#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1229#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1230#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1231#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1232#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1233#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1234#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1235#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1236#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1237#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1238#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1239#define E1000_ICR_TXD_LOW 0x00008000
1240#define E1000_ICR_SRPD 0x00010000
1241
1242/* Interrupt Cause Set */
1243#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1244#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1245#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1246#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1247#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1248#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1249#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1250#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1251#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1252#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1253#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1254#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1255#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1256#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1257#define E1000_ICS_SRPD E1000_ICR_SRPD
1258
1259/* Interrupt Mask Set */
1260#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1261#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1262#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1263#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1264#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1265#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1266#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1267#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1268#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1269#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1270#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1271#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1272#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1273#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1274#define E1000_IMS_SRPD E1000_ICR_SRPD
1275
1276/* Interrupt Mask Clear */
1277#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1278#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1279#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1280#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1281#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1282#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1283#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1284#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1285#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1286#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1287#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1288#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1289#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1290#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1291#define E1000_IMC_SRPD E1000_ICR_SRPD
1292
1293/* Receive Control */
1294#define E1000_RCTL_RST 0x00000001 /* Software reset */
1295#define E1000_RCTL_EN 0x00000002 /* enable */
1296#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1297#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1298#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1299#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1300#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1301#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1302#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1303#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1304#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1305#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1306#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1307#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1308#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1309#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1310#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1311#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1312#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1313#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1314/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1315#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1316#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1317#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1318#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1319/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1320#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1321#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1322#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1323#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1324#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1325#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1326#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1327#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1328#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1329#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1330
1331/* Receive Descriptor */
1332#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1333#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1334#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1335#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1336#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1337
1338/* Flow Control */
1339#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1340#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1341#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1342#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1343
1344/* Receive Descriptor Control */
1345#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1346#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1347#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1348#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1349
1350/* Transmit Descriptor Control */
1351#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1352#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1353#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1354#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1355#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1356#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1357
1358/* Transmit Configuration Word */
1359#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1360#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1361#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1362#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1363#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1364#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1365#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1366#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1367#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1368#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1369
1370/* Receive Configuration Word */
1371#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1372#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1373#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1374#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1375#define E1000_RXCW_C 0x20000000 /* Receive config */
1376#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1377#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1378
1379/* Transmit Control */
1380#define E1000_TCTL_RST 0x00000001 /* software reset */
1381#define E1000_TCTL_EN 0x00000002 /* enable tx */
1382#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1383#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1384#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1385#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1386#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1387#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1388#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1389#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1390
1391/* Receive Checksum Control */
1392#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1393#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1394#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1395#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1396
1397/* Definitions for power management and wakeup registers */
1398/* Wake Up Control */
1399#define E1000_WUC_APME 0x00000001 /* APM Enable */
1400#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1401#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1402#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1403#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1404
1405/* Wake Up Filter Control */
1406#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1407#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1408#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1409#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1410#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1411#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1412#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1413#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1414#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1415#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1416#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1417#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1418#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1419#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1420#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1421
1422/* Wake Up Status */
1423#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1424#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1425#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1426#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1427#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1428#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1429#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1430#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1431#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1432#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1433#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1434#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1435#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1436
1437/* Management Control */
1438#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1439#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1440#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1441#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1442#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1443#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1444#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1445#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1446#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1447#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1448 * Filtering */
1449#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1450#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1451#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1452#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1453 * filtering */
1454#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1455 * memory */
1456#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1457#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1458#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1459#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1460#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1461#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1462
1463#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1464#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1465
1466/* Wake Up Packet Length */
1467#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1468
1469#define E1000_MDALIGN 4096
1470
1471/* EEPROM Commands - Microwire */
1472#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1473#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1474#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1475#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1476#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1477
1478/* EEPROM Commands - SPI */
1479#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1480#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */
1481#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */
1482#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
1483#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */
1484#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */
1485#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */
1486#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */
1487
1488/* EEPROM Size definitions */
1489#define EEPROM_SIZE_16KB 0x1800
1490#define EEPROM_SIZE_8KB 0x1400
1491#define EEPROM_SIZE_4KB 0x1000
1492#define EEPROM_SIZE_2KB 0x0C00
1493#define EEPROM_SIZE_1KB 0x0800
1494#define EEPROM_SIZE_512B 0x0400
1495#define EEPROM_SIZE_128B 0x0000
1496#define EEPROM_SIZE_MASK 0x1C00
1497
1498/* EEPROM Word Offsets */
1499#define EEPROM_COMPAT 0x0003
1500#define EEPROM_ID_LED_SETTINGS 0x0004
1501#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1502#define EEPROM_PHY_CLASS_WORD 0x0007
1503#define EEPROM_INIT_CONTROL1_REG 0x000A
1504#define EEPROM_INIT_CONTROL2_REG 0x000F
1505#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1506#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1507#define EEPROM_CFG 0x0012
1508#define EEPROM_FLASH_VERSION 0x0032
1509#define EEPROM_CHECKSUM_REG 0x003F
1510
1511/* Word definitions for ID LED Settings */
1512#define ID_LED_RESERVED_0000 0x0000
1513#define ID_LED_RESERVED_FFFF 0xFFFF
1514#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1515 (ID_LED_OFF1_OFF2 << 8) | \
1516 (ID_LED_DEF1_DEF2 << 4) | \
1517 (ID_LED_DEF1_DEF2))
1518#define ID_LED_DEF1_DEF2 0x1
1519#define ID_LED_DEF1_ON2 0x2
1520#define ID_LED_DEF1_OFF2 0x3
1521#define ID_LED_ON1_DEF2 0x4
1522#define ID_LED_ON1_ON2 0x5
1523#define ID_LED_ON1_OFF2 0x6
1524#define ID_LED_OFF1_DEF2 0x7
1525#define ID_LED_OFF1_ON2 0x8
1526#define ID_LED_OFF1_OFF2 0x9
1527
1528#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1529#define IGP_ACTIVITY_LED_ENABLE 0x0300
1530#define IGP_LED3_MODE 0x07000000
1531
1532
1533/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
1534#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
1535
1536/* Mask bit for PHY class in Word 7 of the EEPROM */
1537#define EEPROM_PHY_CLASS_A 0x8000
1538
1539/* Mask bits for fields in Word 0x0a of the EEPROM */
1540#define EEPROM_WORD0A_ILOS 0x0010
1541#define EEPROM_WORD0A_SWDPIO 0x01E0
1542#define EEPROM_WORD0A_LRST 0x0200
1543#define EEPROM_WORD0A_FD 0x0400
1544#define EEPROM_WORD0A_66MHZ 0x0800
1545
1546/* Mask bits for fields in Word 0x0f of the EEPROM */
1547#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1548#define EEPROM_WORD0F_PAUSE 0x1000
1549#define EEPROM_WORD0F_ASM_DIR 0x2000
1550#define EEPROM_WORD0F_ANE 0x0800
1551#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1552
1553/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1554#define EEPROM_SUM 0xBABA
1555
1556/* EEPROM Map defines (WORD OFFSETS)*/
1557#define EEPROM_NODE_ADDRESS_BYTE_0 0
1558#define EEPROM_PBA_BYTE_1 8
1559
1560#define EEPROM_RESERVED_WORD 0xFFFF
1561
1562/* EEPROM Map Sizes (Byte Counts) */
1563#define PBA_SIZE 4
1564
1565/* Collision related configuration parameters */
1566#define E1000_COLLISION_THRESHOLD 15
1567#define E1000_CT_SHIFT 4
1568#define E1000_COLLISION_DISTANCE 64
1569#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1570#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1571#define E1000_COLD_SHIFT 12
1572
1573/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1574#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1575#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1576
1577/* Default values for the transmit IPG register */
1578#define DEFAULT_82542_TIPG_IPGT 10
1579#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1580#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1581
1582#define E1000_TIPG_IPGT_MASK 0x000003FF
1583#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1584#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1585
1586#define DEFAULT_82542_TIPG_IPGR1 2
1587#define DEFAULT_82543_TIPG_IPGR1 8
1588#define E1000_TIPG_IPGR1_SHIFT 10
1589
1590#define DEFAULT_82542_TIPG_IPGR2 10
1591#define DEFAULT_82543_TIPG_IPGR2 6
1592#define E1000_TIPG_IPGR2_SHIFT 20
1593
1594#define E1000_TXDMAC_DPP 0x00000001
1595
1596/* Adaptive IFS defines */
1597#define TX_THRESHOLD_START 8
1598#define TX_THRESHOLD_INCREMENT 10
1599#define TX_THRESHOLD_DECREMENT 1
1600#define TX_THRESHOLD_STOP 190
1601#define TX_THRESHOLD_DISABLE 0
1602#define TX_THRESHOLD_TIMER_MS 10000
1603#define MIN_NUM_XMITS 1000
1604#define IFS_MAX 80
1605#define IFS_STEP 10
1606#define IFS_MIN 40
1607#define IFS_RATIO 4
1608
1609/* PBA constants */
1610#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1611#define E1000_PBA_22K 0x0016
1612#define E1000_PBA_24K 0x0018
1613#define E1000_PBA_30K 0x001E
1614#define E1000_PBA_40K 0x0028
1615#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1616
1617/* Flow Control Constants */
1618#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1619#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1620#define FLOW_CONTROL_TYPE 0x8808
1621
1622/* The historical defaults for the flow control values are given below. */
1623#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1624#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1625#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1626
1627/* PCIX Config space */
1628#define PCIX_COMMAND_REGISTER 0xE6
1629#define PCIX_STATUS_REGISTER_LO 0xE8
1630#define PCIX_STATUS_REGISTER_HI 0xEA
1631
1632#define PCIX_COMMAND_MMRBC_MASK 0x000C
1633#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1634#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1635#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1636#define PCIX_STATUS_HI_MMRBC_4K 0x3
1637#define PCIX_STATUS_HI_MMRBC_2K 0x2
1638
1639
1640/* Number of bits required to shift right the "pause" bits from the
1641 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
1642 */
1643#define PAUSE_SHIFT 5
1644
1645/* Number of bits required to shift left the "SWDPIO" bits from the
1646 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
1647 */
1648#define SWDPIO_SHIFT 17
1649
1650/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
1651 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
1652 */
1653#define SWDPIO__EXT_SHIFT 4
1654
1655/* Number of bits required to shift left the "ILOS" bit from the EEPROM
1656 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
1657 */
1658#define ILOS_SHIFT 3
1659
1660
1661#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1662
1663/* Number of milliseconds we wait for auto-negotiation to complete */
1664#define LINK_UP_TIMEOUT 500
1665
1666#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1667
1668/* The carrier extension symbol, as received by the NIC. */
1669#define CARRIER_EXTENSION 0x0F
1670
1671/* TBI_ACCEPT macro definition:
1672 *
1673 * This macro requires:
1674 * adapter = a pointer to struct e1000_hw
1675 * status = the 8 bit status field of the RX descriptor with EOP set
1676 * error = the 8 bit error field of the RX descriptor with EOP set
1677 * length = the sum of all the length fields of the RX descriptors that
1678 * make up the current frame
1679 * last_byte = the last byte of the frame DMAed by the hardware
1680 * max_frame_length = the maximum frame length we want to accept.
1681 * min_frame_length = the minimum frame length we want to accept.
1682 *
1683 * This macro is a conditional that should be used in the interrupt
1684 * handler's Rx processing routine when RxErrors have been detected.
1685 *
1686 * Typical use:
1687 * ...
1688 * if (TBI_ACCEPT) {
1689 * accept_frame = TRUE;
1690 * e1000_tbi_adjust_stats(adapter, MacAddress);
1691 * frame_length--;
1692 * } else {
1693 * accept_frame = FALSE;
1694 * }
1695 * ...
1696 */
1697
1698#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1699 ((adapter)->tbi_compatibility_on && \
1700 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1701 ((last_byte) == CARRIER_EXTENSION) && \
1702 (((status) & E1000_RXD_STAT_VP) ? \
1703 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1704 ((length) <= ((adapter)->max_frame_size + 1))) : \
1705 (((length) > (adapter)->min_frame_size) && \
1706 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1707
1708
1709/* Structures, enums, and macros for the PHY */
1710
1711/* Bit definitions for the Management Data IO (MDIO) and Management Data
1712 * Clock (MDC) pins in the Device Control Register.
1713 */
1714#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1715#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1716#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1717#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1718#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1719#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1720#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1721#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1722
1723/* PHY 1000 MII Register/Bit Definitions */
1724/* PHY Registers defined by IEEE */
1725#define PHY_CTRL 0x00 /* Control Register */
1726#define PHY_STATUS 0x01 /* Status Regiser */
1727#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1728#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1729#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1730#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1731#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1732#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1733#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1734#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1735#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1736#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1737
1738#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1739#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
1740
1741/* M88E1000 Specific Registers */
1742#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1743#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1744#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1745#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1746#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1747#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1748
1749#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1750#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1751#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1752#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1753#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1754
1755#define IGP01E1000_IEEE_REGS_PAGE 0x0000
1756#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1757#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1758
1759/* IGP01E1000 Specific Registers */
1760#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1761#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1762#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1763#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1764#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1765#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1766#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1767
1768/* IGP01E1000 AGC Registers - stores the cable length values*/
1769#define IGP01E1000_PHY_AGC_A 0x1172
1770#define IGP01E1000_PHY_AGC_B 0x1272
1771#define IGP01E1000_PHY_AGC_C 0x1472
1772#define IGP01E1000_PHY_AGC_D 0x1872
1773
1774/* IGP01E1000 DSP Reset Register */
1775#define IGP01E1000_PHY_DSP_RESET 0x1F33
1776#define IGP01E1000_PHY_DSP_SET 0x1F71
1777#define IGP01E1000_PHY_DSP_FFE 0x1F35
1778
1779#define IGP01E1000_PHY_CHANNEL_NUM 4
1780#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1781#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1782#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1783#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1784
1785#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1786#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1787
1788#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1789#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1790#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1791#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1792
1793#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
1794/* IGP01E1000 PCS Initialization register - stores the polarity status when
1795 * speed = 1000 Mbps. */
1796#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
1797#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
1798
1799#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
1800
1801
1802/* PHY Control Register */
1803#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1804#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1805#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1806#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1807#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1808#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1809#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1810#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1811#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1812#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1813
1814/* PHY Status Register */
1815#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1816#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1817#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1818#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1819#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1820#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1821#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1822#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1823#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1824#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1825#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1826#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1827#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1828#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1829#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1830
1831/* Autoneg Advertisement Register */
1832#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1833#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1834#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1835#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1836#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1837#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1838#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1839#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1840#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1841#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1842
1843/* Link Partner Ability Register (Base Page) */
1844#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1845#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1846#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1847#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1848#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1849#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1850#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1851#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1852#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1853#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1854#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1855
1856/* Autoneg Expansion Register */
1857#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1858#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1859#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1860#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1861#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1862
1863/* Next Page TX Register */
1864#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1865#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
1866 * of different NP
1867 */
1868#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1869 * 0 = cannot comply with msg
1870 */
1871#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1872#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1873 * 0 = sending last NP
1874 */
1875
1876/* Link Partner Next Page Register */
1877#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1878#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
1879 * of different NP
1880 */
1881#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1882 * 0 = cannot comply with msg
1883 */
1884#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1885#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
1886#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1887 * 0 = sending last NP
1888 */
1889
1890/* 1000BASE-T Control Register */
1891#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1892#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1893#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1894#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1895 /* 0=DTE device */
1896#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1897 /* 0=Configure PHY as Slave */
1898#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1899 /* 0=Automatic Master/Slave config */
1900#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1901#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1902#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1903#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1904#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1905
1906/* 1000BASE-T Status Register */
1907#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1908#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1909#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1910#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1911#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1912#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1913#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1914#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1915#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1916#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
1917#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1918#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
1919#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
1920
1921/* Extended Status Register */
1922#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1923#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1924#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1925#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1926
1927#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
1928#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
1929
1930#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
1931 /* (0=enable, 1=disable) */
1932
1933/* M88E1000 PHY Specific Control Register */
1934#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1935#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1936#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1937#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
1938 * 0=CLK125 toggling
1939 */
1940#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1941 /* Manual MDI configuration */
1942#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1943#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1944 * 100BASE-TX/10BASE-T:
1945 * MDI Mode
1946 */
1947#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1948 * all speeds.
1949 */
1950#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1951 /* 1=Enable Extended 10BASE-T distance
1952 * (Lower 10BASE-T RX Threshold)
1953 * 0=Normal 10BASE-T RX Threshold */
1954#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1955 /* 1=5-Bit interface in 100BASE-TX
1956 * 0=MII interface in 100BASE-TX */
1957#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1958#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1959#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1960
1961#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1962#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
1963#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1964
1965/* M88E1000 PHY Specific Status Register */
1966#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1967#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1968#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1969#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1970#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1971 * 3=110-140M;4=>140M */
1972#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1973#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1974#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1975#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1976#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1977#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1978#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1979#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1980
1981#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1982#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
1983#define M88E1000_PSSR_MDIX_SHIFT 6
1984#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1985
1986/* M88E1000 Extended PHY Specific Control Register */
1987#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1988#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
1989 * Will assert lost lock and bring
1990 * link down if idle not seen
1991 * within 1ms in 1000BASE-T
1992 */
1993/* Number of times we will attempt to autonegotiate before downshifting if we
1994 * are the master */
1995#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1996#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1997#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1998#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1999#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2000/* Number of times we will attempt to autonegotiate before downshifting if we
2001 * are the slave */
2002#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2003#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2004#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2005#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2006#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2007#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2008#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2009#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2010
2011/* IGP01E1000 Specific Port Config Register - R/W */
2012#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2013#define IGP01E1000_PSCFR_PRE_EN 0x0020
2014#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2015#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2016#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2017#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2018
2019/* IGP01E1000 Specific Port Status Register - R/O */
2020#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2021#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2022#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2023#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2024#define IGP01E1000_PSSR_LINK_UP 0x0400
2025#define IGP01E1000_PSSR_MDIX 0x0800
2026#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2027#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2028#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2029#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2030#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2031#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2032
2033/* IGP01E1000 Specific Port Control Register - R/W */
2034#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2035#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2036#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2037#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2038#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2039#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2040
2041/* IGP01E1000 Specific Port Link Health Register */
2042#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2043#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2044#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2045#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2046#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2047#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2048#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2049#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2050#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2051#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2052#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2053#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2054#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2055#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2056
2057/* IGP01E1000 Channel Quality Register */
2058#define IGP01E1000_MSE_CHANNEL_D 0x000F
2059#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2060#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2061#define IGP01E1000_MSE_CHANNEL_A 0xF000
2062
2063/* IGP01E1000 DSP reset macros */
2064#define DSP_RESET_ENABLE 0x0
2065#define DSP_RESET_DISABLE 0x2
2066#define E1000_MAX_DSP_RESETS 10
2067
2068/* IGP01E1000 AGC Registers */
2069
2070#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2071
2072/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2073#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2074
2075/* The precision of the length is +/- 10 meters */
2076#define IGP01E1000_AGC_RANGE 10
2077
2078/* IGP01E1000 PCS Initialization register */
2079/* bits 3:6 in the PCS registers stores the channels polarity */
2080#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2081
2082/* IGP01E1000 GMII FIFO Register */
2083#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2084 * on Link-Up */
2085#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2086
2087/* IGP01E1000 Analog Register */
2088#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2089#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2090#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2091#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2092
2093#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2094#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2095#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2096#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2097#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2098
2099#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2100#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2101#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2102#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2103
2104
2105/* Bit definitions for valid PHY IDs. */
2106/* I = Integrated
2107 * E = External
2108 */
2109#define M88E1000_E_PHY_ID 0x01410C50
2110#define M88E1000_I_PHY_ID 0x01410C30
2111#define M88E1011_I_PHY_ID 0x01410C20
2112#define IGP01E1000_I_PHY_ID 0x02A80380
2113#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2114#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2115#define M88E1011_I_REV_4 0x04
2116
2117/* Miscellaneous PHY bit definitions. */
2118#define PHY_PREAMBLE 0xFFFFFFFF
2119#define PHY_SOF 0x01
2120#define PHY_OP_READ 0x02
2121#define PHY_OP_WRITE 0x01
2122#define PHY_TURNAROUND 0x02
2123#define PHY_PREAMBLE_SIZE 32
2124#define MII_CR_SPEED_1000 0x0040
2125#define MII_CR_SPEED_100 0x2000
2126#define MII_CR_SPEED_10 0x0000
2127#define E1000_PHY_ADDRESS 0x01
2128#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2129#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2130#define PHY_REVISION_MASK 0xFFFFFFF0
2131#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2132#define REG4_SPEED_MASK 0x01E0
2133#define REG9_SPEED_MASK 0x0300
2134#define ADVERTISE_10_HALF 0x0001
2135#define ADVERTISE_10_FULL 0x0002
2136#define ADVERTISE_100_HALF 0x0004
2137#define ADVERTISE_100_FULL 0x0008
2138#define ADVERTISE_1000_HALF 0x0010
2139#define ADVERTISE_1000_FULL 0x0020
2140#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2141#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2142#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2143
2144#endif /* _E1000_HW_H_ */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
new file mode 100644
index 000000000000..82549a6fcfb3
--- /dev/null
+++ b/drivers/net/e1000/e1000_main.c
@@ -0,0 +1,3162 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
32 * 5.3.12 6/7/04
33 * - kcompat NETIF_MSG for older kernels (2.4.9) <sean.p.mcdermott@intel.com>
34 * - if_mii support and associated kcompat for older kernels
35 * - More errlogging support from Jon Mason <jonmason@us.ibm.com>
36 * - Fix TSO issues on PPC64 machines -- Jon Mason <jonmason@us.ibm.com>
37 *
38 * 5.7.1 12/16/04
39 * - Resurrect 82547EI/GI related fix in e1000_intr to avoid deadlocks. This
40 * fix was removed as it caused system instability. The suspected cause of
41 * this is the called to e1000_irq_disable in e1000_intr. Inlined the
42 * required piece of e1000_irq_disable into e1000_intr - Anton Blanchard
43 * 5.7.0 12/10/04
44 * - include fix to the condition that determines when to quit NAPI - Robert Olsson
45 * - use netif_poll_{disable/enable} to synchronize between NAPI and i/f up/down
46 * 5.6.5 11/01/04
47 * - Enabling NETIF_F_SG without checksum offload is illegal -
48 John Mason <jdmason@us.ibm.com>
49 * 5.6.3 10/26/04
50 * - Remove redundant initialization - Jamal Hadi
51 * - Reset buffer_info->dma in tx resource cleanup logic
52 * 5.6.2 10/12/04
53 * - Avoid filling tx_ring completely - shemminger@osdl.org
54 * - Replace schedule_timeout() with msleep()/msleep_interruptible() -
55 * nacc@us.ibm.com
56 * - Sparse cleanup - shemminger@osdl.org
57 * - Fix tx resource cleanup logic
58 * - LLTX support - ak@suse.de and hadi@cyberus.ca
59 */
60
61char e1000_driver_name[] = "e1000";
62char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
63#ifndef CONFIG_E1000_NAPI
64#define DRIVERNAPI
65#else
66#define DRIVERNAPI "-NAPI"
67#endif
68#define DRV_VERSION "5.7.6-k2"DRIVERNAPI
69char e1000_driver_version[] = DRV_VERSION;
70char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation.";
71
72/* e1000_pci_tbl - PCI Device ID Table
73 *
74 * Last entry must be all 0s
75 *
76 * Macro expands to...
77 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
78 */
79static struct pci_device_id e1000_pci_tbl[] = {
80 INTEL_E1000_ETHERNET_DEVICE(0x1000),
81 INTEL_E1000_ETHERNET_DEVICE(0x1001),
82 INTEL_E1000_ETHERNET_DEVICE(0x1004),
83 INTEL_E1000_ETHERNET_DEVICE(0x1008),
84 INTEL_E1000_ETHERNET_DEVICE(0x1009),
85 INTEL_E1000_ETHERNET_DEVICE(0x100C),
86 INTEL_E1000_ETHERNET_DEVICE(0x100D),
87 INTEL_E1000_ETHERNET_DEVICE(0x100E),
88 INTEL_E1000_ETHERNET_DEVICE(0x100F),
89 INTEL_E1000_ETHERNET_DEVICE(0x1010),
90 INTEL_E1000_ETHERNET_DEVICE(0x1011),
91 INTEL_E1000_ETHERNET_DEVICE(0x1012),
92 INTEL_E1000_ETHERNET_DEVICE(0x1013),
93 INTEL_E1000_ETHERNET_DEVICE(0x1014),
94 INTEL_E1000_ETHERNET_DEVICE(0x1015),
95 INTEL_E1000_ETHERNET_DEVICE(0x1016),
96 INTEL_E1000_ETHERNET_DEVICE(0x1017),
97 INTEL_E1000_ETHERNET_DEVICE(0x1018),
98 INTEL_E1000_ETHERNET_DEVICE(0x1019),
99 INTEL_E1000_ETHERNET_DEVICE(0x101D),
100 INTEL_E1000_ETHERNET_DEVICE(0x101E),
101 INTEL_E1000_ETHERNET_DEVICE(0x1026),
102 INTEL_E1000_ETHERNET_DEVICE(0x1027),
103 INTEL_E1000_ETHERNET_DEVICE(0x1028),
104 INTEL_E1000_ETHERNET_DEVICE(0x1075),
105 INTEL_E1000_ETHERNET_DEVICE(0x1076),
106 INTEL_E1000_ETHERNET_DEVICE(0x1077),
107 INTEL_E1000_ETHERNET_DEVICE(0x1078),
108 INTEL_E1000_ETHERNET_DEVICE(0x1079),
109 INTEL_E1000_ETHERNET_DEVICE(0x107A),
110 INTEL_E1000_ETHERNET_DEVICE(0x107B),
111 INTEL_E1000_ETHERNET_DEVICE(0x107C),
112 INTEL_E1000_ETHERNET_DEVICE(0x108A),
113 /* required last entry */
114 {0,}
115};
116
117MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
118
119int e1000_up(struct e1000_adapter *adapter);
120void e1000_down(struct e1000_adapter *adapter);
121void e1000_reset(struct e1000_adapter *adapter);
122int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
123int e1000_setup_tx_resources(struct e1000_adapter *adapter);
124int e1000_setup_rx_resources(struct e1000_adapter *adapter);
125void e1000_free_tx_resources(struct e1000_adapter *adapter);
126void e1000_free_rx_resources(struct e1000_adapter *adapter);
127void e1000_update_stats(struct e1000_adapter *adapter);
128
129/* Local Function Prototypes */
130
131static int e1000_init_module(void);
132static void e1000_exit_module(void);
133static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
134static void __devexit e1000_remove(struct pci_dev *pdev);
135static int e1000_sw_init(struct e1000_adapter *adapter);
136static int e1000_open(struct net_device *netdev);
137static int e1000_close(struct net_device *netdev);
138static void e1000_configure_tx(struct e1000_adapter *adapter);
139static void e1000_configure_rx(struct e1000_adapter *adapter);
140static void e1000_setup_rctl(struct e1000_adapter *adapter);
141static void e1000_clean_tx_ring(struct e1000_adapter *adapter);
142static void e1000_clean_rx_ring(struct e1000_adapter *adapter);
143static void e1000_set_multi(struct net_device *netdev);
144static void e1000_update_phy_info(unsigned long data);
145static void e1000_watchdog(unsigned long data);
146static void e1000_watchdog_task(struct e1000_adapter *adapter);
147static void e1000_82547_tx_fifo_stall(unsigned long data);
148static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
149static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
150static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
151static int e1000_set_mac(struct net_device *netdev, void *p);
152static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
153static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter);
154#ifdef CONFIG_E1000_NAPI
155static int e1000_clean(struct net_device *netdev, int *budget);
156static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
157 int *work_done, int work_to_do);
158#else
159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter);
160#endif
161static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
162static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
163static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
164 int cmd);
165void e1000_set_ethtool_ops(struct net_device *netdev);
166static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
167static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
168static void e1000_tx_timeout(struct net_device *dev);
169static void e1000_tx_timeout_task(struct net_device *dev);
170static void e1000_smartspeed(struct e1000_adapter *adapter);
171static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
172 struct sk_buff *skb);
173
174static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
175static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
176static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
177static void e1000_restore_vlan(struct e1000_adapter *adapter);
178
179static int e1000_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
180static int e1000_suspend(struct pci_dev *pdev, uint32_t state);
181#ifdef CONFIG_PM
182static int e1000_resume(struct pci_dev *pdev);
183#endif
184
185#ifdef CONFIG_NET_POLL_CONTROLLER
186/* for netdump / net console */
187static void e1000_netpoll (struct net_device *netdev);
188#endif
189
190struct notifier_block e1000_notifier_reboot = {
191 .notifier_call = e1000_notify_reboot,
192 .next = NULL,
193 .priority = 0
194};
195
196/* Exported from other modules */
197
198extern void e1000_check_options(struct e1000_adapter *adapter);
199
200static struct pci_driver e1000_driver = {
201 .name = e1000_driver_name,
202 .id_table = e1000_pci_tbl,
203 .probe = e1000_probe,
204 .remove = __devexit_p(e1000_remove),
205 /* Power Managment Hooks */
206#ifdef CONFIG_PM
207 .suspend = e1000_suspend,
208 .resume = e1000_resume
209#endif
210};
211
212MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
213MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
214MODULE_LICENSE("GPL");
215MODULE_VERSION(DRV_VERSION);
216
217static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
218module_param(debug, int, 0);
219MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
220
221/**
222 * e1000_init_module - Driver Registration Routine
223 *
224 * e1000_init_module is the first routine called when the driver is
225 * loaded. All it does is register with the PCI subsystem.
226 **/
227
228static int __init
229e1000_init_module(void)
230{
231 int ret;
232 printk(KERN_INFO "%s - version %s\n",
233 e1000_driver_string, e1000_driver_version);
234
235 printk(KERN_INFO "%s\n", e1000_copyright);
236
237 ret = pci_module_init(&e1000_driver);
238 if(ret >= 0) {
239 register_reboot_notifier(&e1000_notifier_reboot);
240 }
241 return ret;
242}
243
244module_init(e1000_init_module);
245
246/**
247 * e1000_exit_module - Driver Exit Cleanup Routine
248 *
249 * e1000_exit_module is called just before the driver is removed
250 * from memory.
251 **/
252
253static void __exit
254e1000_exit_module(void)
255{
256 unregister_reboot_notifier(&e1000_notifier_reboot);
257 pci_unregister_driver(&e1000_driver);
258}
259
260module_exit(e1000_exit_module);
261
262/**
263 * e1000_irq_disable - Mask off interrupt generation on the NIC
264 * @adapter: board private structure
265 **/
266
267static inline void
268e1000_irq_disable(struct e1000_adapter *adapter)
269{
270 atomic_inc(&adapter->irq_sem);
271 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
272 E1000_WRITE_FLUSH(&adapter->hw);
273 synchronize_irq(adapter->pdev->irq);
274}
275
276/**
277 * e1000_irq_enable - Enable default interrupt generation settings
278 * @adapter: board private structure
279 **/
280
281static inline void
282e1000_irq_enable(struct e1000_adapter *adapter)
283{
284 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
285 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
286 E1000_WRITE_FLUSH(&adapter->hw);
287 }
288}
289
290int
291e1000_up(struct e1000_adapter *adapter)
292{
293 struct net_device *netdev = adapter->netdev;
294 int err;
295
296 /* hardware has been reset, we need to reload some things */
297
298 /* Reset the PHY if it was previously powered down */
299 if(adapter->hw.media_type == e1000_media_type_copper) {
300 uint16_t mii_reg;
301 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
302 if(mii_reg & MII_CR_POWER_DOWN)
303 e1000_phy_reset(&adapter->hw);
304 }
305
306 e1000_set_multi(netdev);
307
308 e1000_restore_vlan(adapter);
309
310 e1000_configure_tx(adapter);
311 e1000_setup_rctl(adapter);
312 e1000_configure_rx(adapter);
313 e1000_alloc_rx_buffers(adapter);
314
315 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
316 SA_SHIRQ | SA_SAMPLE_RANDOM,
317 netdev->name, netdev)))
318 return err;
319
320 mod_timer(&adapter->watchdog_timer, jiffies);
321 e1000_irq_enable(adapter);
322
323#ifdef CONFIG_E1000_NAPI
324 netif_poll_enable(netdev);
325#endif
326 return 0;
327}
328
329void
330e1000_down(struct e1000_adapter *adapter)
331{
332 struct net_device *netdev = adapter->netdev;
333
334 e1000_irq_disable(adapter);
335 free_irq(adapter->pdev->irq, netdev);
336 del_timer_sync(&adapter->tx_fifo_stall_timer);
337 del_timer_sync(&adapter->watchdog_timer);
338 del_timer_sync(&adapter->phy_info_timer);
339
340#ifdef CONFIG_E1000_NAPI
341 netif_poll_disable(netdev);
342#endif
343 adapter->link_speed = 0;
344 adapter->link_duplex = 0;
345 netif_carrier_off(netdev);
346 netif_stop_queue(netdev);
347
348 e1000_reset(adapter);
349 e1000_clean_tx_ring(adapter);
350 e1000_clean_rx_ring(adapter);
351
352 /* If WoL is not enabled
353 * Power down the PHY so no link is implied when interface is down */
354 if(!adapter->wol && adapter->hw.media_type == e1000_media_type_copper) {
355 uint16_t mii_reg;
356 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
357 mii_reg |= MII_CR_POWER_DOWN;
358 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
359 }
360}
361
362void
363e1000_reset(struct e1000_adapter *adapter)
364{
365 uint32_t pba;
366
367 /* Repartition Pba for greater than 9k mtu
368 * To take effect CTRL.RST is required.
369 */
370
371 if(adapter->hw.mac_type < e1000_82547) {
372 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192)
373 pba = E1000_PBA_40K;
374 else
375 pba = E1000_PBA_48K;
376 } else {
377 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192)
378 pba = E1000_PBA_22K;
379 else
380 pba = E1000_PBA_30K;
381 adapter->tx_fifo_head = 0;
382 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
383 adapter->tx_fifo_size =
384 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
385 atomic_set(&adapter->tx_fifo_stall, 0);
386 }
387 E1000_WRITE_REG(&adapter->hw, PBA, pba);
388
389 /* flow control settings */
390 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
391 E1000_FC_HIGH_DIFF;
392 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
393 E1000_FC_LOW_DIFF;
394 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
395 adapter->hw.fc_send_xon = 1;
396 adapter->hw.fc = adapter->hw.original_fc;
397
398 e1000_reset_hw(&adapter->hw);
399 if(adapter->hw.mac_type >= e1000_82544)
400 E1000_WRITE_REG(&adapter->hw, WUC, 0);
401 if(e1000_init_hw(&adapter->hw))
402 DPRINTK(PROBE, ERR, "Hardware Error\n");
403
404 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
405 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
406
407 e1000_reset_adaptive(&adapter->hw);
408 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
409}
410
411/**
412 * e1000_probe - Device Initialization Routine
413 * @pdev: PCI device information struct
414 * @ent: entry in e1000_pci_tbl
415 *
416 * Returns 0 on success, negative on failure
417 *
418 * e1000_probe initializes an adapter identified by a pci_dev structure.
419 * The OS initialization, configuring of the adapter private structure,
420 * and a hardware reset occur.
421 **/
422
423static int __devinit
424e1000_probe(struct pci_dev *pdev,
425 const struct pci_device_id *ent)
426{
427 struct net_device *netdev;
428 struct e1000_adapter *adapter;
429 static int cards_found = 0;
430 unsigned long mmio_start;
431 int mmio_len;
432 int pci_using_dac;
433 int i;
434 int err;
435 uint16_t eeprom_data;
436 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
437
438 if((err = pci_enable_device(pdev)))
439 return err;
440
441 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
442 pci_using_dac = 1;
443 } else {
444 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
445 E1000_ERR("No usable DMA configuration, aborting\n");
446 return err;
447 }
448 pci_using_dac = 0;
449 }
450
451 if((err = pci_request_regions(pdev, e1000_driver_name)))
452 return err;
453
454 pci_set_master(pdev);
455
456 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
457 if(!netdev) {
458 err = -ENOMEM;
459 goto err_alloc_etherdev;
460 }
461
462 SET_MODULE_OWNER(netdev);
463 SET_NETDEV_DEV(netdev, &pdev->dev);
464
465 pci_set_drvdata(pdev, netdev);
466 adapter = netdev->priv;
467 adapter->netdev = netdev;
468 adapter->pdev = pdev;
469 adapter->hw.back = adapter;
470 adapter->msg_enable = (1 << debug) - 1;
471
472 mmio_start = pci_resource_start(pdev, BAR_0);
473 mmio_len = pci_resource_len(pdev, BAR_0);
474
475 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
476 if(!adapter->hw.hw_addr) {
477 err = -EIO;
478 goto err_ioremap;
479 }
480
481 for(i = BAR_1; i <= BAR_5; i++) {
482 if(pci_resource_len(pdev, i) == 0)
483 continue;
484 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
485 adapter->hw.io_base = pci_resource_start(pdev, i);
486 break;
487 }
488 }
489
490 netdev->open = &e1000_open;
491 netdev->stop = &e1000_close;
492 netdev->hard_start_xmit = &e1000_xmit_frame;
493 netdev->get_stats = &e1000_get_stats;
494 netdev->set_multicast_list = &e1000_set_multi;
495 netdev->set_mac_address = &e1000_set_mac;
496 netdev->change_mtu = &e1000_change_mtu;
497 netdev->do_ioctl = &e1000_ioctl;
498 e1000_set_ethtool_ops(netdev);
499 netdev->tx_timeout = &e1000_tx_timeout;
500 netdev->watchdog_timeo = 5 * HZ;
501#ifdef CONFIG_E1000_NAPI
502 netdev->poll = &e1000_clean;
503 netdev->weight = 64;
504#endif
505 netdev->vlan_rx_register = e1000_vlan_rx_register;
506 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
507 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
508#ifdef CONFIG_NET_POLL_CONTROLLER
509 netdev->poll_controller = e1000_netpoll;
510#endif
511 strcpy(netdev->name, pci_name(pdev));
512
513 netdev->mem_start = mmio_start;
514 netdev->mem_end = mmio_start + mmio_len;
515 netdev->base_addr = adapter->hw.io_base;
516
517 adapter->bd_number = cards_found;
518
519 /* setup the private structure */
520
521 if((err = e1000_sw_init(adapter)))
522 goto err_sw_init;
523
524 if(adapter->hw.mac_type >= e1000_82543) {
525 netdev->features = NETIF_F_SG |
526 NETIF_F_HW_CSUM |
527 NETIF_F_HW_VLAN_TX |
528 NETIF_F_HW_VLAN_RX |
529 NETIF_F_HW_VLAN_FILTER;
530 }
531
532#ifdef NETIF_F_TSO
533 if((adapter->hw.mac_type >= e1000_82544) &&
534 (adapter->hw.mac_type != e1000_82547))
535 netdev->features |= NETIF_F_TSO;
536#endif
537 if(pci_using_dac)
538 netdev->features |= NETIF_F_HIGHDMA;
539
540 /* hard_start_xmit is safe against parallel locking */
541 netdev->features |= NETIF_F_LLTX;
542
543 /* before reading the EEPROM, reset the controller to
544 * put the device in a known good starting state */
545
546 e1000_reset_hw(&adapter->hw);
547
548 /* make sure the EEPROM is good */
549
550 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
551 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
552 err = -EIO;
553 goto err_eeprom;
554 }
555
556 /* copy the MAC address out of the EEPROM */
557
558 if (e1000_read_mac_addr(&adapter->hw))
559 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
560 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
561
562 if(!is_valid_ether_addr(netdev->dev_addr)) {
563 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
564 err = -EIO;
565 goto err_eeprom;
566 }
567
568 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
569
570 e1000_get_bus_info(&adapter->hw);
571
572 init_timer(&adapter->tx_fifo_stall_timer);
573 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
574 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
575
576 init_timer(&adapter->watchdog_timer);
577 adapter->watchdog_timer.function = &e1000_watchdog;
578 adapter->watchdog_timer.data = (unsigned long) adapter;
579
580 INIT_WORK(&adapter->watchdog_task,
581 (void (*)(void *))e1000_watchdog_task, adapter);
582
583 init_timer(&adapter->phy_info_timer);
584 adapter->phy_info_timer.function = &e1000_update_phy_info;
585 adapter->phy_info_timer.data = (unsigned long) adapter;
586
587 INIT_WORK(&adapter->tx_timeout_task,
588 (void (*)(void *))e1000_tx_timeout_task, netdev);
589
590 /* we're going to reset, so assume we have no link for now */
591
592 netif_carrier_off(netdev);
593 netif_stop_queue(netdev);
594
595 e1000_check_options(adapter);
596
597 /* Initial Wake on LAN setting
598 * If APM wake is enabled in the EEPROM,
599 * enable the ACPI Magic Packet filter
600 */
601
602 switch(adapter->hw.mac_type) {
603 case e1000_82542_rev2_0:
604 case e1000_82542_rev2_1:
605 case e1000_82543:
606 break;
607 case e1000_82544:
608 e1000_read_eeprom(&adapter->hw,
609 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
610 eeprom_apme_mask = E1000_EEPROM_82544_APM;
611 break;
612 case e1000_82546:
613 case e1000_82546_rev_3:
614 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
615 && (adapter->hw.media_type == e1000_media_type_copper)) {
616 e1000_read_eeprom(&adapter->hw,
617 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
618 break;
619 }
620 /* Fall Through */
621 default:
622 e1000_read_eeprom(&adapter->hw,
623 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
624 break;
625 }
626 if(eeprom_data & eeprom_apme_mask)
627 adapter->wol |= E1000_WUFC_MAG;
628
629 /* reset the hardware with the new settings */
630 e1000_reset(adapter);
631
632 strcpy(netdev->name, "eth%d");
633 if((err = register_netdev(netdev)))
634 goto err_register;
635
636 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
637
638 cards_found++;
639 return 0;
640
641err_register:
642err_sw_init:
643err_eeprom:
644 iounmap(adapter->hw.hw_addr);
645err_ioremap:
646 free_netdev(netdev);
647err_alloc_etherdev:
648 pci_release_regions(pdev);
649 return err;
650}
651
652/**
653 * e1000_remove - Device Removal Routine
654 * @pdev: PCI device information struct
655 *
656 * e1000_remove is called by the PCI subsystem to alert the driver
657 * that it should release a PCI device. The could be caused by a
658 * Hot-Plug event, or because the driver is going to be removed from
659 * memory.
660 **/
661
662static void __devexit
663e1000_remove(struct pci_dev *pdev)
664{
665 struct net_device *netdev = pci_get_drvdata(pdev);
666 struct e1000_adapter *adapter = netdev->priv;
667 uint32_t manc;
668
669 flush_scheduled_work();
670
671 if(adapter->hw.mac_type >= e1000_82540 &&
672 adapter->hw.media_type == e1000_media_type_copper) {
673 manc = E1000_READ_REG(&adapter->hw, MANC);
674 if(manc & E1000_MANC_SMBUS_EN) {
675 manc |= E1000_MANC_ARP_EN;
676 E1000_WRITE_REG(&adapter->hw, MANC, manc);
677 }
678 }
679
680 unregister_netdev(netdev);
681
682 e1000_phy_hw_reset(&adapter->hw);
683
684 iounmap(adapter->hw.hw_addr);
685 pci_release_regions(pdev);
686
687 free_netdev(netdev);
688
689 pci_disable_device(pdev);
690}
691
692/**
693 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
694 * @adapter: board private structure to initialize
695 *
696 * e1000_sw_init initializes the Adapter private data structure.
697 * Fields are initialized based on PCI device information and
698 * OS network device settings (MTU size).
699 **/
700
701static int __devinit
702e1000_sw_init(struct e1000_adapter *adapter)
703{
704 struct e1000_hw *hw = &adapter->hw;
705 struct net_device *netdev = adapter->netdev;
706 struct pci_dev *pdev = adapter->pdev;
707
708 /* PCI config space info */
709
710 hw->vendor_id = pdev->vendor;
711 hw->device_id = pdev->device;
712 hw->subsystem_vendor_id = pdev->subsystem_vendor;
713 hw->subsystem_id = pdev->subsystem_device;
714
715 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
716
717 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
718
719 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
720 hw->max_frame_size = netdev->mtu +
721 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
722 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
723
724 /* identify the MAC */
725
726 if(e1000_set_mac_type(hw)) {
727 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
728 return -EIO;
729 }
730
731 /* initialize eeprom parameters */
732
733 e1000_init_eeprom_params(hw);
734
735 switch(hw->mac_type) {
736 default:
737 break;
738 case e1000_82541:
739 case e1000_82547:
740 case e1000_82541_rev_2:
741 case e1000_82547_rev_2:
742 hw->phy_init_script = 1;
743 break;
744 }
745
746 e1000_set_media_type(hw);
747
748 hw->wait_autoneg_complete = FALSE;
749 hw->tbi_compatibility_en = TRUE;
750 hw->adaptive_ifs = TRUE;
751
752 /* Copper options */
753
754 if(hw->media_type == e1000_media_type_copper) {
755 hw->mdix = AUTO_ALL_MODES;
756 hw->disable_polarity_correction = FALSE;
757 hw->master_slave = E1000_MASTER_SLAVE;
758 }
759
760 atomic_set(&adapter->irq_sem, 1);
761 spin_lock_init(&adapter->stats_lock);
762 spin_lock_init(&adapter->tx_lock);
763
764 return 0;
765}
766
767/**
768 * e1000_open - Called when a network interface is made active
769 * @netdev: network interface device structure
770 *
771 * Returns 0 on success, negative value on failure
772 *
773 * The open entry point is called when a network interface is made
774 * active by the system (IFF_UP). At this point all resources needed
775 * for transmit and receive operations are allocated, the interrupt
776 * handler is registered with the OS, the watchdog timer is started,
777 * and the stack is notified that the interface is ready.
778 **/
779
780static int
781e1000_open(struct net_device *netdev)
782{
783 struct e1000_adapter *adapter = netdev->priv;
784 int err;
785
786 /* allocate transmit descriptors */
787
788 if((err = e1000_setup_tx_resources(adapter)))
789 goto err_setup_tx;
790
791 /* allocate receive descriptors */
792
793 if((err = e1000_setup_rx_resources(adapter)))
794 goto err_setup_rx;
795
796 if((err = e1000_up(adapter)))
797 goto err_up;
798
799 return E1000_SUCCESS;
800
801err_up:
802 e1000_free_rx_resources(adapter);
803err_setup_rx:
804 e1000_free_tx_resources(adapter);
805err_setup_tx:
806 e1000_reset(adapter);
807
808 return err;
809}
810
811/**
812 * e1000_close - Disables a network interface
813 * @netdev: network interface device structure
814 *
815 * Returns 0, this is not allowed to fail
816 *
817 * The close entry point is called when an interface is de-activated
818 * by the OS. The hardware is still under the drivers control, but
819 * needs to be disabled. A global MAC reset is issued to stop the
820 * hardware, and all transmit and receive resources are freed.
821 **/
822
823static int
824e1000_close(struct net_device *netdev)
825{
826 struct e1000_adapter *adapter = netdev->priv;
827
828 e1000_down(adapter);
829
830 e1000_free_tx_resources(adapter);
831 e1000_free_rx_resources(adapter);
832
833 return 0;
834}
835
836/**
837 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
838 * @adapter: address of board private structure
839 * @begin: address of beginning of memory
840 * @end: address of end of memory
841 **/
842static inline boolean_t
843e1000_check_64k_bound(struct e1000_adapter *adapter,
844 void *start, unsigned long len)
845{
846 unsigned long begin = (unsigned long) start;
847 unsigned long end = begin + len;
848
849 /* first rev 82545 and 82546 need to not allow any memory
850 * write location to cross a 64k boundary due to errata 23 */
851 if (adapter->hw.mac_type == e1000_82545 ||
852 adapter->hw.mac_type == e1000_82546 ) {
853
854 /* check buffer doesn't cross 64kB */
855 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
856 }
857
858 return TRUE;
859}
860
861/**
862 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
863 * @adapter: board private structure
864 *
865 * Return 0 on success, negative on failure
866 **/
867
868int
869e1000_setup_tx_resources(struct e1000_adapter *adapter)
870{
871 struct e1000_desc_ring *txdr = &adapter->tx_ring;
872 struct pci_dev *pdev = adapter->pdev;
873 int size;
874
875 size = sizeof(struct e1000_buffer) * txdr->count;
876 txdr->buffer_info = vmalloc(size);
877 if(!txdr->buffer_info) {
878 DPRINTK(PROBE, ERR,
879 "Unable to Allocate Memory for the Transmit descriptor ring\n");
880 return -ENOMEM;
881 }
882 memset(txdr->buffer_info, 0, size);
883
884 /* round up to nearest 4K */
885
886 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
887 E1000_ROUNDUP(txdr->size, 4096);
888
889 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
890 if(!txdr->desc) {
891setup_tx_desc_die:
892 DPRINTK(PROBE, ERR,
893 "Unable to Allocate Memory for the Transmit descriptor ring\n");
894 vfree(txdr->buffer_info);
895 return -ENOMEM;
896 }
897
898 /* fix for errata 23, cant cross 64kB boundary */
899 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
900 void *olddesc = txdr->desc;
901 dma_addr_t olddma = txdr->dma;
902 DPRINTK(TX_ERR,ERR,"txdr align check failed: %u bytes at %p\n",
903 txdr->size, txdr->desc);
904 /* try again, without freeing the previous */
905 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
906 /* failed allocation, critial failure */
907 if(!txdr->desc) {
908 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
909 goto setup_tx_desc_die;
910 }
911
912 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
913 /* give up */
914 pci_free_consistent(pdev, txdr->size,
915 txdr->desc, txdr->dma);
916 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
917 DPRINTK(PROBE, ERR,
918 "Unable to Allocate aligned Memory for the Transmit"
919 " descriptor ring\n");
920 vfree(txdr->buffer_info);
921 return -ENOMEM;
922 } else {
923 /* free old, move on with the new one since its okay */
924 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
925 }
926 }
927 memset(txdr->desc, 0, txdr->size);
928
929 txdr->next_to_use = 0;
930 txdr->next_to_clean = 0;
931
932 return 0;
933}
934
935/**
936 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
937 * @adapter: board private structure
938 *
939 * Configure the Tx unit of the MAC after a reset.
940 **/
941
942static void
943e1000_configure_tx(struct e1000_adapter *adapter)
944{
945 uint64_t tdba = adapter->tx_ring.dma;
946 uint32_t tdlen = adapter->tx_ring.count * sizeof(struct e1000_tx_desc);
947 uint32_t tctl, tipg;
948
949 E1000_WRITE_REG(&adapter->hw, TDBAL, (tdba & 0x00000000ffffffffULL));
950 E1000_WRITE_REG(&adapter->hw, TDBAH, (tdba >> 32));
951
952 E1000_WRITE_REG(&adapter->hw, TDLEN, tdlen);
953
954 /* Setup the HW Tx Head and Tail descriptor pointers */
955
956 E1000_WRITE_REG(&adapter->hw, TDH, 0);
957 E1000_WRITE_REG(&adapter->hw, TDT, 0);
958
959 /* Set the default values for the Tx Inter Packet Gap timer */
960
961 switch (adapter->hw.mac_type) {
962 case e1000_82542_rev2_0:
963 case e1000_82542_rev2_1:
964 tipg = DEFAULT_82542_TIPG_IPGT;
965 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
966 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
967 break;
968 default:
969 if(adapter->hw.media_type == e1000_media_type_fiber ||
970 adapter->hw.media_type == e1000_media_type_internal_serdes)
971 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
972 else
973 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
974 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
975 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
976 }
977 E1000_WRITE_REG(&adapter->hw, TIPG, tipg);
978
979 /* Set the Tx Interrupt Delay register */
980
981 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay);
982 if(adapter->hw.mac_type >= e1000_82540)
983 E1000_WRITE_REG(&adapter->hw, TADV, adapter->tx_abs_int_delay);
984
985 /* Program the Transmit Control Register */
986
987 tctl = E1000_READ_REG(&adapter->hw, TCTL);
988
989 tctl &= ~E1000_TCTL_CT;
990 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
991 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
992
993 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
994
995 e1000_config_collision_dist(&adapter->hw);
996
997 /* Setup Transmit Descriptor Settings for eop descriptor */
998 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
999 E1000_TXD_CMD_IFCS;
1000
1001 if(adapter->hw.mac_type < e1000_82543)
1002 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1003 else
1004 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1005
1006 /* Cache if we're 82544 running in PCI-X because we'll
1007 * need this to apply a workaround later in the send path. */
1008 if(adapter->hw.mac_type == e1000_82544 &&
1009 adapter->hw.bus_type == e1000_bus_type_pcix)
1010 adapter->pcix_82544 = 1;
1011}
1012
1013/**
1014 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1015 * @adapter: board private structure
1016 *
1017 * Returns 0 on success, negative on failure
1018 **/
1019
1020int
1021e1000_setup_rx_resources(struct e1000_adapter *adapter)
1022{
1023 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
1024 struct pci_dev *pdev = adapter->pdev;
1025 int size;
1026
1027 size = sizeof(struct e1000_buffer) * rxdr->count;
1028 rxdr->buffer_info = vmalloc(size);
1029 if(!rxdr->buffer_info) {
1030 DPRINTK(PROBE, ERR,
1031 "Unable to Allocate Memory for the Recieve descriptor ring\n");
1032 return -ENOMEM;
1033 }
1034 memset(rxdr->buffer_info, 0, size);
1035
1036 /* Round up to nearest 4K */
1037
1038 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
1039 E1000_ROUNDUP(rxdr->size, 4096);
1040
1041 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1042
1043 if(!rxdr->desc) {
1044setup_rx_desc_die:
1045 DPRINTK(PROBE, ERR,
1046 "Unble to Allocate Memory for the Recieve descriptor ring\n");
1047 vfree(rxdr->buffer_info);
1048 return -ENOMEM;
1049 }
1050
1051 /* fix for errata 23, cant cross 64kB boundary */
1052 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1053 void *olddesc = rxdr->desc;
1054 dma_addr_t olddma = rxdr->dma;
1055 DPRINTK(RX_ERR,ERR,
1056 "rxdr align check failed: %u bytes at %p\n",
1057 rxdr->size, rxdr->desc);
1058 /* try again, without freeing the previous */
1059 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1060 /* failed allocation, critial failure */
1061 if(!rxdr->desc) {
1062 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1063 goto setup_rx_desc_die;
1064 }
1065
1066 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1067 /* give up */
1068 pci_free_consistent(pdev, rxdr->size,
1069 rxdr->desc, rxdr->dma);
1070 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1071 DPRINTK(PROBE, ERR,
1072 "Unable to Allocate aligned Memory for the"
1073 " Receive descriptor ring\n");
1074 vfree(rxdr->buffer_info);
1075 return -ENOMEM;
1076 } else {
1077 /* free old, move on with the new one since its okay */
1078 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1079 }
1080 }
1081 memset(rxdr->desc, 0, rxdr->size);
1082
1083 rxdr->next_to_clean = 0;
1084 rxdr->next_to_use = 0;
1085
1086 return 0;
1087}
1088
1089/**
1090 * e1000_setup_rctl - configure the receive control register
1091 * @adapter: Board private structure
1092 **/
1093
1094static void
1095e1000_setup_rctl(struct e1000_adapter *adapter)
1096{
1097 uint32_t rctl;
1098
1099 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1100
1101 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1102
1103 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1104 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1105 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1106
1107 if(adapter->hw.tbi_compatibility_on == 1)
1108 rctl |= E1000_RCTL_SBP;
1109 else
1110 rctl &= ~E1000_RCTL_SBP;
1111
1112 /* Setup buffer sizes */
1113 rctl &= ~(E1000_RCTL_SZ_4096);
1114 rctl |= (E1000_RCTL_BSEX | E1000_RCTL_LPE);
1115 switch (adapter->rx_buffer_len) {
1116 case E1000_RXBUFFER_2048:
1117 default:
1118 rctl |= E1000_RCTL_SZ_2048;
1119 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
1120 break;
1121 case E1000_RXBUFFER_4096:
1122 rctl |= E1000_RCTL_SZ_4096;
1123 break;
1124 case E1000_RXBUFFER_8192:
1125 rctl |= E1000_RCTL_SZ_8192;
1126 break;
1127 case E1000_RXBUFFER_16384:
1128 rctl |= E1000_RCTL_SZ_16384;
1129 break;
1130 }
1131
1132 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1133}
1134
1135/**
1136 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1137 * @adapter: board private structure
1138 *
1139 * Configure the Rx unit of the MAC after a reset.
1140 **/
1141
1142static void
1143e1000_configure_rx(struct e1000_adapter *adapter)
1144{
1145 uint64_t rdba = adapter->rx_ring.dma;
1146 uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
1147 uint32_t rctl;
1148 uint32_t rxcsum;
1149
1150 /* disable receives while setting up the descriptors */
1151 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1152 E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
1153
1154 /* set the Receive Delay Timer Register */
1155 E1000_WRITE_REG(&adapter->hw, RDTR, adapter->rx_int_delay);
1156
1157 if(adapter->hw.mac_type >= e1000_82540) {
1158 E1000_WRITE_REG(&adapter->hw, RADV, adapter->rx_abs_int_delay);
1159 if(adapter->itr > 1)
1160 E1000_WRITE_REG(&adapter->hw, ITR,
1161 1000000000 / (adapter->itr * 256));
1162 }
1163
1164 /* Setup the Base and Length of the Rx Descriptor Ring */
1165 E1000_WRITE_REG(&adapter->hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1166 E1000_WRITE_REG(&adapter->hw, RDBAH, (rdba >> 32));
1167
1168 E1000_WRITE_REG(&adapter->hw, RDLEN, rdlen);
1169
1170 /* Setup the HW Rx Head and Tail Descriptor Pointers */
1171 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1172 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1173
1174 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
1175 if((adapter->hw.mac_type >= e1000_82543) &&
1176 (adapter->rx_csum == TRUE)) {
1177 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
1178 rxcsum |= E1000_RXCSUM_TUOFL;
1179 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
1180 }
1181
1182 /* Enable Receives */
1183 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1184}
1185
1186/**
1187 * e1000_free_tx_resources - Free Tx Resources
1188 * @adapter: board private structure
1189 *
1190 * Free all transmit software resources
1191 **/
1192
1193void
1194e1000_free_tx_resources(struct e1000_adapter *adapter)
1195{
1196 struct pci_dev *pdev = adapter->pdev;
1197
1198 e1000_clean_tx_ring(adapter);
1199
1200 vfree(adapter->tx_ring.buffer_info);
1201 adapter->tx_ring.buffer_info = NULL;
1202
1203 pci_free_consistent(pdev, adapter->tx_ring.size,
1204 adapter->tx_ring.desc, adapter->tx_ring.dma);
1205
1206 adapter->tx_ring.desc = NULL;
1207}
1208
1209static inline void
1210e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1211 struct e1000_buffer *buffer_info)
1212{
1213 struct pci_dev *pdev = adapter->pdev;
1214
1215 if(buffer_info->dma) {
1216 pci_unmap_page(pdev,
1217 buffer_info->dma,
1218 buffer_info->length,
1219 PCI_DMA_TODEVICE);
1220 buffer_info->dma = 0;
1221 }
1222 if(buffer_info->skb) {
1223 dev_kfree_skb_any(buffer_info->skb);
1224 buffer_info->skb = NULL;
1225 }
1226}
1227
1228/**
1229 * e1000_clean_tx_ring - Free Tx Buffers
1230 * @adapter: board private structure
1231 **/
1232
1233static void
1234e1000_clean_tx_ring(struct e1000_adapter *adapter)
1235{
1236 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
1237 struct e1000_buffer *buffer_info;
1238 unsigned long size;
1239 unsigned int i;
1240
1241 /* Free all the Tx ring sk_buffs */
1242
1243 if (likely(adapter->previous_buffer_info.skb != NULL)) {
1244 e1000_unmap_and_free_tx_resource(adapter,
1245 &adapter->previous_buffer_info);
1246 }
1247
1248 for(i = 0; i < tx_ring->count; i++) {
1249 buffer_info = &tx_ring->buffer_info[i];
1250 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1251 }
1252
1253 size = sizeof(struct e1000_buffer) * tx_ring->count;
1254 memset(tx_ring->buffer_info, 0, size);
1255
1256 /* Zero out the descriptor ring */
1257
1258 memset(tx_ring->desc, 0, tx_ring->size);
1259
1260 tx_ring->next_to_use = 0;
1261 tx_ring->next_to_clean = 0;
1262
1263 E1000_WRITE_REG(&adapter->hw, TDH, 0);
1264 E1000_WRITE_REG(&adapter->hw, TDT, 0);
1265}
1266
1267/**
1268 * e1000_free_rx_resources - Free Rx Resources
1269 * @adapter: board private structure
1270 *
1271 * Free all receive software resources
1272 **/
1273
1274void
1275e1000_free_rx_resources(struct e1000_adapter *adapter)
1276{
1277 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1278 struct pci_dev *pdev = adapter->pdev;
1279
1280 e1000_clean_rx_ring(adapter);
1281
1282 vfree(rx_ring->buffer_info);
1283 rx_ring->buffer_info = NULL;
1284
1285 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1286
1287 rx_ring->desc = NULL;
1288}
1289
1290/**
1291 * e1000_clean_rx_ring - Free Rx Buffers
1292 * @adapter: board private structure
1293 **/
1294
1295static void
1296e1000_clean_rx_ring(struct e1000_adapter *adapter)
1297{
1298 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1299 struct e1000_buffer *buffer_info;
1300 struct pci_dev *pdev = adapter->pdev;
1301 unsigned long size;
1302 unsigned int i;
1303
1304 /* Free all the Rx ring sk_buffs */
1305
1306 for(i = 0; i < rx_ring->count; i++) {
1307 buffer_info = &rx_ring->buffer_info[i];
1308 if(buffer_info->skb) {
1309
1310 pci_unmap_single(pdev,
1311 buffer_info->dma,
1312 buffer_info->length,
1313 PCI_DMA_FROMDEVICE);
1314
1315 dev_kfree_skb(buffer_info->skb);
1316 buffer_info->skb = NULL;
1317 }
1318 }
1319
1320 size = sizeof(struct e1000_buffer) * rx_ring->count;
1321 memset(rx_ring->buffer_info, 0, size);
1322
1323 /* Zero out the descriptor ring */
1324
1325 memset(rx_ring->desc, 0, rx_ring->size);
1326
1327 rx_ring->next_to_clean = 0;
1328 rx_ring->next_to_use = 0;
1329
1330 E1000_WRITE_REG(&adapter->hw, RDH, 0);
1331 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1332}
1333
1334/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1335 * and memory write and invalidate disabled for certain operations
1336 */
1337static void
1338e1000_enter_82542_rst(struct e1000_adapter *adapter)
1339{
1340 struct net_device *netdev = adapter->netdev;
1341 uint32_t rctl;
1342
1343 e1000_pci_clear_mwi(&adapter->hw);
1344
1345 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1346 rctl |= E1000_RCTL_RST;
1347 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1348 E1000_WRITE_FLUSH(&adapter->hw);
1349 mdelay(5);
1350
1351 if(netif_running(netdev))
1352 e1000_clean_rx_ring(adapter);
1353}
1354
1355static void
1356e1000_leave_82542_rst(struct e1000_adapter *adapter)
1357{
1358 struct net_device *netdev = adapter->netdev;
1359 uint32_t rctl;
1360
1361 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1362 rctl &= ~E1000_RCTL_RST;
1363 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1364 E1000_WRITE_FLUSH(&adapter->hw);
1365 mdelay(5);
1366
1367 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1368 e1000_pci_set_mwi(&adapter->hw);
1369
1370 if(netif_running(netdev)) {
1371 e1000_configure_rx(adapter);
1372 e1000_alloc_rx_buffers(adapter);
1373 }
1374}
1375
1376/**
1377 * e1000_set_mac - Change the Ethernet Address of the NIC
1378 * @netdev: network interface device structure
1379 * @p: pointer to an address structure
1380 *
1381 * Returns 0 on success, negative on failure
1382 **/
1383
1384static int
1385e1000_set_mac(struct net_device *netdev, void *p)
1386{
1387 struct e1000_adapter *adapter = netdev->priv;
1388 struct sockaddr *addr = p;
1389
1390 if(!is_valid_ether_addr(addr->sa_data))
1391 return -EADDRNOTAVAIL;
1392
1393 /* 82542 2.0 needs to be in reset to write receive address registers */
1394
1395 if(adapter->hw.mac_type == e1000_82542_rev2_0)
1396 e1000_enter_82542_rst(adapter);
1397
1398 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1399 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
1400
1401 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
1402
1403 if(adapter->hw.mac_type == e1000_82542_rev2_0)
1404 e1000_leave_82542_rst(adapter);
1405
1406 return 0;
1407}
1408
1409/**
1410 * e1000_set_multi - Multicast and Promiscuous mode set
1411 * @netdev: network interface device structure
1412 *
1413 * The set_multi entry point is called whenever the multicast address
1414 * list or the network interface flags are updated. This routine is
1415 * responsible for configuring the hardware for proper multicast,
1416 * promiscuous mode, and all-multi behavior.
1417 **/
1418
1419static void
1420e1000_set_multi(struct net_device *netdev)
1421{
1422 struct e1000_adapter *adapter = netdev->priv;
1423 struct e1000_hw *hw = &adapter->hw;
1424 struct dev_mc_list *mc_ptr;
1425 uint32_t rctl;
1426 uint32_t hash_value;
1427 int i;
1428 unsigned long flags;
1429
1430 /* Check for Promiscuous and All Multicast modes */
1431
1432 spin_lock_irqsave(&adapter->tx_lock, flags);
1433
1434 rctl = E1000_READ_REG(hw, RCTL);
1435
1436 if(netdev->flags & IFF_PROMISC) {
1437 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1438 } else if(netdev->flags & IFF_ALLMULTI) {
1439 rctl |= E1000_RCTL_MPE;
1440 rctl &= ~E1000_RCTL_UPE;
1441 } else {
1442 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
1443 }
1444
1445 E1000_WRITE_REG(hw, RCTL, rctl);
1446
1447 /* 82542 2.0 needs to be in reset to write receive address registers */
1448
1449 if(hw->mac_type == e1000_82542_rev2_0)
1450 e1000_enter_82542_rst(adapter);
1451
1452 /* load the first 14 multicast address into the exact filters 1-14
1453 * RAR 0 is used for the station MAC adddress
1454 * if there are not 14 addresses, go ahead and clear the filters
1455 */
1456 mc_ptr = netdev->mc_list;
1457
1458 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
1459 if(mc_ptr) {
1460 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
1461 mc_ptr = mc_ptr->next;
1462 } else {
1463 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
1464 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
1465 }
1466 }
1467
1468 /* clear the old settings from the multicast hash table */
1469
1470 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1471 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1472
1473 /* load any remaining addresses into the hash table */
1474
1475 for(; mc_ptr; mc_ptr = mc_ptr->next) {
1476 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
1477 e1000_mta_set(hw, hash_value);
1478 }
1479
1480 if(hw->mac_type == e1000_82542_rev2_0)
1481 e1000_leave_82542_rst(adapter);
1482
1483 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1484}
1485
1486/* Need to wait a few seconds after link up to get diagnostic information from
1487 * the phy */
1488
1489static void
1490e1000_update_phy_info(unsigned long data)
1491{
1492 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1493 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
1494}
1495
1496/**
1497 * e1000_82547_tx_fifo_stall - Timer Call-back
1498 * @data: pointer to adapter cast into an unsigned long
1499 **/
1500
1501static void
1502e1000_82547_tx_fifo_stall(unsigned long data)
1503{
1504 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1505 struct net_device *netdev = adapter->netdev;
1506 uint32_t tctl;
1507
1508 if(atomic_read(&adapter->tx_fifo_stall)) {
1509 if((E1000_READ_REG(&adapter->hw, TDT) ==
1510 E1000_READ_REG(&adapter->hw, TDH)) &&
1511 (E1000_READ_REG(&adapter->hw, TDFT) ==
1512 E1000_READ_REG(&adapter->hw, TDFH)) &&
1513 (E1000_READ_REG(&adapter->hw, TDFTS) ==
1514 E1000_READ_REG(&adapter->hw, TDFHS))) {
1515 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1516 E1000_WRITE_REG(&adapter->hw, TCTL,
1517 tctl & ~E1000_TCTL_EN);
1518 E1000_WRITE_REG(&adapter->hw, TDFT,
1519 adapter->tx_head_addr);
1520 E1000_WRITE_REG(&adapter->hw, TDFH,
1521 adapter->tx_head_addr);
1522 E1000_WRITE_REG(&adapter->hw, TDFTS,
1523 adapter->tx_head_addr);
1524 E1000_WRITE_REG(&adapter->hw, TDFHS,
1525 adapter->tx_head_addr);
1526 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1527 E1000_WRITE_FLUSH(&adapter->hw);
1528
1529 adapter->tx_fifo_head = 0;
1530 atomic_set(&adapter->tx_fifo_stall, 0);
1531 netif_wake_queue(netdev);
1532 } else {
1533 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
1534 }
1535 }
1536}
1537
1538/**
1539 * e1000_watchdog - Timer Call-back
1540 * @data: pointer to adapter cast into an unsigned long
1541 **/
1542static void
1543e1000_watchdog(unsigned long data)
1544{
1545 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1546
1547 /* Do the rest outside of interrupt context */
1548 schedule_work(&adapter->watchdog_task);
1549}
1550
1551static void
1552e1000_watchdog_task(struct e1000_adapter *adapter)
1553{
1554 struct net_device *netdev = adapter->netdev;
1555 struct e1000_desc_ring *txdr = &adapter->tx_ring;
1556 uint32_t link;
1557
1558 e1000_check_for_link(&adapter->hw);
1559
1560 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1561 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
1562 link = !adapter->hw.serdes_link_down;
1563 else
1564 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
1565
1566 if(link) {
1567 if(!netif_carrier_ok(netdev)) {
1568 e1000_get_speed_and_duplex(&adapter->hw,
1569 &adapter->link_speed,
1570 &adapter->link_duplex);
1571
1572 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
1573 adapter->link_speed,
1574 adapter->link_duplex == FULL_DUPLEX ?
1575 "Full Duplex" : "Half Duplex");
1576
1577 netif_carrier_on(netdev);
1578 netif_wake_queue(netdev);
1579 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
1580 adapter->smartspeed = 0;
1581 }
1582 } else {
1583 if(netif_carrier_ok(netdev)) {
1584 adapter->link_speed = 0;
1585 adapter->link_duplex = 0;
1586 DPRINTK(LINK, INFO, "NIC Link is Down\n");
1587 netif_carrier_off(netdev);
1588 netif_stop_queue(netdev);
1589 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
1590 }
1591
1592 e1000_smartspeed(adapter);
1593 }
1594
1595 e1000_update_stats(adapter);
1596
1597 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
1598 adapter->tpt_old = adapter->stats.tpt;
1599 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
1600 adapter->colc_old = adapter->stats.colc;
1601
1602 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
1603 adapter->gorcl_old = adapter->stats.gorcl;
1604 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
1605 adapter->gotcl_old = adapter->stats.gotcl;
1606
1607 e1000_update_adaptive(&adapter->hw);
1608
1609 if(!netif_carrier_ok(netdev)) {
1610 if(E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1611 /* We've lost link, so the controller stops DMA,
1612 * but we've got queued Tx work that's never going
1613 * to get done, so reset controller to flush Tx.
1614 * (Do the reset outside of interrupt context). */
1615 schedule_work(&adapter->tx_timeout_task);
1616 }
1617 }
1618
1619 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
1620 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1621 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
1622 * asymmetrical Tx or Rx gets ITR=8000; everyone
1623 * else is between 2000-8000. */
1624 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
1625 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1626 adapter->gotcl - adapter->gorcl :
1627 adapter->gorcl - adapter->gotcl) / 10000;
1628 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
1629 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
1630 }
1631
1632 /* Cause software interrupt to ensure rx ring is cleaned */
1633 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
1634
1635 /* Force detection of hung controller every watchdog period*/
1636 adapter->detect_tx_hung = TRUE;
1637
1638 /* Reset the timer */
1639 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
1640}
1641
1642#define E1000_TX_FLAGS_CSUM 0x00000001
1643#define E1000_TX_FLAGS_VLAN 0x00000002
1644#define E1000_TX_FLAGS_TSO 0x00000004
1645#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
1646#define E1000_TX_FLAGS_VLAN_SHIFT 16
1647
1648static inline int
1649e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1650{
1651#ifdef NETIF_F_TSO
1652 struct e1000_context_desc *context_desc;
1653 unsigned int i;
1654 uint32_t cmd_length = 0;
1655 uint16_t ipcse, tucse, mss;
1656 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
1657 int err;
1658
1659 if(skb_shinfo(skb)->tso_size) {
1660 if (skb_header_cloned(skb)) {
1661 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1662 if (err)
1663 return err;
1664 }
1665
1666 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1667 mss = skb_shinfo(skb)->tso_size;
1668 skb->nh.iph->tot_len = 0;
1669 skb->nh.iph->check = 0;
1670 skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
1671 skb->nh.iph->daddr,
1672 0,
1673 IPPROTO_TCP,
1674 0);
1675 ipcss = skb->nh.raw - skb->data;
1676 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1677 ipcse = skb->h.raw - skb->data - 1;
1678 tucss = skb->h.raw - skb->data;
1679 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
1680 tucse = 0;
1681
1682 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
1683 E1000_TXD_CMD_IP | E1000_TXD_CMD_TCP |
1684 (skb->len - (hdr_len)));
1685
1686 i = adapter->tx_ring.next_to_use;
1687 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
1688
1689 context_desc->lower_setup.ip_fields.ipcss = ipcss;
1690 context_desc->lower_setup.ip_fields.ipcso = ipcso;
1691 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
1692 context_desc->upper_setup.tcp_fields.tucss = tucss;
1693 context_desc->upper_setup.tcp_fields.tucso = tucso;
1694 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
1695 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
1696 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
1697 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
1698
1699 if(++i == adapter->tx_ring.count) i = 0;
1700 adapter->tx_ring.next_to_use = i;
1701
1702 return 1;
1703 }
1704#endif
1705
1706 return 0;
1707}
1708
1709static inline boolean_t
1710e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
1711{
1712 struct e1000_context_desc *context_desc;
1713 unsigned int i;
1714 uint8_t css;
1715
1716 if(likely(skb->ip_summed == CHECKSUM_HW)) {
1717 css = skb->h.raw - skb->data;
1718
1719 i = adapter->tx_ring.next_to_use;
1720 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
1721
1722 context_desc->upper_setup.tcp_fields.tucss = css;
1723 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
1724 context_desc->upper_setup.tcp_fields.tucse = 0;
1725 context_desc->tcp_seg_setup.data = 0;
1726 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
1727
1728 if(unlikely(++i == adapter->tx_ring.count)) i = 0;
1729 adapter->tx_ring.next_to_use = i;
1730
1731 return TRUE;
1732 }
1733
1734 return FALSE;
1735}
1736
1737#define E1000_MAX_TXD_PWR 12
1738#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
1739
1740static inline int
1741e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb,
1742 unsigned int first, unsigned int max_per_txd,
1743 unsigned int nr_frags, unsigned int mss)
1744{
1745 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
1746 struct e1000_buffer *buffer_info;
1747 unsigned int len = skb->len;
1748 unsigned int offset = 0, size, count = 0, i;
1749 unsigned int f;
1750 len -= skb->data_len;
1751
1752 i = tx_ring->next_to_use;
1753
1754 while(len) {
1755 buffer_info = &tx_ring->buffer_info[i];
1756 size = min(len, max_per_txd);
1757#ifdef NETIF_F_TSO
1758 /* Workaround for premature desc write-backs
1759 * in TSO mode. Append 4-byte sentinel desc */
1760 if(unlikely(mss && !nr_frags && size == len && size > 8))
1761 size -= 4;
1762#endif
1763 /* Workaround for potential 82544 hang in PCI-X. Avoid
1764 * terminating buffers within evenly-aligned dwords. */
1765 if(unlikely(adapter->pcix_82544 &&
1766 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
1767 size > 4))
1768 size -= 4;
1769
1770 buffer_info->length = size;
1771 buffer_info->dma =
1772 pci_map_single(adapter->pdev,
1773 skb->data + offset,
1774 size,
1775 PCI_DMA_TODEVICE);
1776 buffer_info->time_stamp = jiffies;
1777
1778 len -= size;
1779 offset += size;
1780 count++;
1781 if(unlikely(++i == tx_ring->count)) i = 0;
1782 }
1783
1784 for(f = 0; f < nr_frags; f++) {
1785 struct skb_frag_struct *frag;
1786
1787 frag = &skb_shinfo(skb)->frags[f];
1788 len = frag->size;
1789 offset = frag->page_offset;
1790
1791 while(len) {
1792 buffer_info = &tx_ring->buffer_info[i];
1793 size = min(len, max_per_txd);
1794#ifdef NETIF_F_TSO
1795 /* Workaround for premature desc write-backs
1796 * in TSO mode. Append 4-byte sentinel desc */
1797 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1798 size -= 4;
1799#endif
1800 /* Workaround for potential 82544 hang in PCI-X.
1801 * Avoid terminating buffers within evenly-aligned
1802 * dwords. */
1803 if(unlikely(adapter->pcix_82544 &&
1804 !((unsigned long)(frag->page+offset+size-1) & 4) &&
1805 size > 4))
1806 size -= 4;
1807
1808 buffer_info->length = size;
1809 buffer_info->dma =
1810 pci_map_page(adapter->pdev,
1811 frag->page,
1812 offset,
1813 size,
1814 PCI_DMA_TODEVICE);
1815 buffer_info->time_stamp = jiffies;
1816
1817 len -= size;
1818 offset += size;
1819 count++;
1820 if(unlikely(++i == tx_ring->count)) i = 0;
1821 }
1822 }
1823
1824 i = (i == 0) ? tx_ring->count - 1 : i - 1;
1825 tx_ring->buffer_info[i].skb = skb;
1826 tx_ring->buffer_info[first].next_to_watch = i;
1827
1828 return count;
1829}
1830
1831static inline void
1832e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
1833{
1834 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
1835 struct e1000_tx_desc *tx_desc = NULL;
1836 struct e1000_buffer *buffer_info;
1837 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
1838 unsigned int i;
1839
1840 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1841 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
1842 E1000_TXD_CMD_TSE;
1843 txd_upper |= (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
1844 }
1845
1846 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1847 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
1848 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
1849 }
1850
1851 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1852 txd_lower |= E1000_TXD_CMD_VLE;
1853 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
1854 }
1855
1856 i = tx_ring->next_to_use;
1857
1858 while(count--) {
1859 buffer_info = &tx_ring->buffer_info[i];
1860 tx_desc = E1000_TX_DESC(*tx_ring, i);
1861 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1862 tx_desc->lower.data =
1863 cpu_to_le32(txd_lower | buffer_info->length);
1864 tx_desc->upper.data = cpu_to_le32(txd_upper);
1865 if(unlikely(++i == tx_ring->count)) i = 0;
1866 }
1867
1868 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
1869
1870 /* Force memory writes to complete before letting h/w
1871 * know there are new descriptors to fetch. (Only
1872 * applicable for weak-ordered memory model archs,
1873 * such as IA-64). */
1874 wmb();
1875
1876 tx_ring->next_to_use = i;
1877 E1000_WRITE_REG(&adapter->hw, TDT, i);
1878}
1879
1880/**
1881 * 82547 workaround to avoid controller hang in half-duplex environment.
1882 * The workaround is to avoid queuing a large packet that would span
1883 * the internal Tx FIFO ring boundary by notifying the stack to resend
1884 * the packet at a later time. This gives the Tx FIFO an opportunity to
1885 * flush all packets. When that occurs, we reset the Tx FIFO pointers
1886 * to the beginning of the Tx FIFO.
1887 **/
1888
1889#define E1000_FIFO_HDR 0x10
1890#define E1000_82547_PAD_LEN 0x3E0
1891
1892static inline int
1893e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
1894{
1895 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1896 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
1897
1898 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
1899
1900 if(adapter->link_duplex != HALF_DUPLEX)
1901 goto no_fifo_stall_required;
1902
1903 if(atomic_read(&adapter->tx_fifo_stall))
1904 return 1;
1905
1906 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1907 atomic_set(&adapter->tx_fifo_stall, 1);
1908 return 1;
1909 }
1910
1911no_fifo_stall_required:
1912 adapter->tx_fifo_head += skb_fifo_len;
1913 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
1914 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1915 return 0;
1916}
1917
1918#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
1919static int
1920e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1921{
1922 struct e1000_adapter *adapter = netdev->priv;
1923 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
1924 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
1925 unsigned int tx_flags = 0;
1926 unsigned int len = skb->len;
1927 unsigned long flags;
1928 unsigned int nr_frags = 0;
1929 unsigned int mss = 0;
1930 int count = 0;
1931 int tso;
1932 unsigned int f;
1933 len -= skb->data_len;
1934
1935 if(unlikely(skb->len <= 0)) {
1936 dev_kfree_skb_any(skb);
1937 return NETDEV_TX_OK;
1938 }
1939
1940#ifdef NETIF_F_TSO
1941 mss = skb_shinfo(skb)->tso_size;
1942 /* The controller does a simple calculation to
1943 * make sure there is enough room in the FIFO before
1944 * initiating the DMA for each buffer. The calc is:
1945 * 4 = ceil(buffer len/mss). To make sure we don't
1946 * overrun the FIFO, adjust the max buffer len if mss
1947 * drops. */
1948 if(mss) {
1949 max_per_txd = min(mss << 2, max_per_txd);
1950 max_txd_pwr = fls(max_per_txd) - 1;
1951 }
1952
1953 if((mss) || (skb->ip_summed == CHECKSUM_HW))
1954 count++;
1955 count++; /* for sentinel desc */
1956#else
1957 if(skb->ip_summed == CHECKSUM_HW)
1958 count++;
1959#endif
1960 count += TXD_USE_COUNT(len, max_txd_pwr);
1961
1962 if(adapter->pcix_82544)
1963 count++;
1964
1965 nr_frags = skb_shinfo(skb)->nr_frags;
1966 for(f = 0; f < nr_frags; f++)
1967 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
1968 max_txd_pwr);
1969 if(adapter->pcix_82544)
1970 count += nr_frags;
1971
1972 local_irq_save(flags);
1973 if (!spin_trylock(&adapter->tx_lock)) {
1974 /* Collision - tell upper layer to requeue */
1975 local_irq_restore(flags);
1976 return NETDEV_TX_LOCKED;
1977 }
1978
1979 /* need: count + 2 desc gap to keep tail from touching
1980 * head, otherwise try next time */
1981 if(unlikely(E1000_DESC_UNUSED(&adapter->tx_ring) < count + 2)) {
1982 netif_stop_queue(netdev);
1983 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1984 return NETDEV_TX_BUSY;
1985 }
1986
1987 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
1988 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1989 netif_stop_queue(netdev);
1990 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
1991 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1992 return NETDEV_TX_BUSY;
1993 }
1994 }
1995
1996 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1997 tx_flags |= E1000_TX_FLAGS_VLAN;
1998 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
1999 }
2000
2001 first = adapter->tx_ring.next_to_use;
2002
2003 tso = e1000_tso(adapter, skb);
2004 if (tso < 0) {
2005 dev_kfree_skb_any(skb);
2006 return NETDEV_TX_OK;
2007 }
2008
2009 if (likely(tso))
2010 tx_flags |= E1000_TX_FLAGS_TSO;
2011 else if(likely(e1000_tx_csum(adapter, skb)))
2012 tx_flags |= E1000_TX_FLAGS_CSUM;
2013
2014 e1000_tx_queue(adapter,
2015 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss),
2016 tx_flags);
2017
2018 netdev->trans_start = jiffies;
2019
2020 /* Make sure there is space in the ring for the next send. */
2021 if(unlikely(E1000_DESC_UNUSED(&adapter->tx_ring) < MAX_SKB_FRAGS + 2))
2022 netif_stop_queue(netdev);
2023
2024 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2025 return NETDEV_TX_OK;
2026}
2027
2028/**
2029 * e1000_tx_timeout - Respond to a Tx Hang
2030 * @netdev: network interface device structure
2031 **/
2032
2033static void
2034e1000_tx_timeout(struct net_device *netdev)
2035{
2036 struct e1000_adapter *adapter = netdev->priv;
2037
2038 /* Do the reset outside of interrupt context */
2039 schedule_work(&adapter->tx_timeout_task);
2040}
2041
2042static void
2043e1000_tx_timeout_task(struct net_device *netdev)
2044{
2045 struct e1000_adapter *adapter = netdev->priv;
2046
2047 e1000_down(adapter);
2048 e1000_up(adapter);
2049}
2050
2051/**
2052 * e1000_get_stats - Get System Network Statistics
2053 * @netdev: network interface device structure
2054 *
2055 * Returns the address of the device statistics structure.
2056 * The statistics are actually updated from the timer callback.
2057 **/
2058
2059static struct net_device_stats *
2060e1000_get_stats(struct net_device *netdev)
2061{
2062 struct e1000_adapter *adapter = netdev->priv;
2063
2064 e1000_update_stats(adapter);
2065 return &adapter->net_stats;
2066}
2067
2068/**
2069 * e1000_change_mtu - Change the Maximum Transfer Unit
2070 * @netdev: network interface device structure
2071 * @new_mtu: new value for maximum frame size
2072 *
2073 * Returns 0 on success, negative on failure
2074 **/
2075
2076static int
2077e1000_change_mtu(struct net_device *netdev, int new_mtu)
2078{
2079 struct e1000_adapter *adapter = netdev->priv;
2080 int old_mtu = adapter->rx_buffer_len;
2081 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2082
2083 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2084 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2085 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
2086 return -EINVAL;
2087 }
2088
2089 if(max_frame <= MAXIMUM_ETHERNET_FRAME_SIZE) {
2090 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2091
2092 } else if(adapter->hw.mac_type < e1000_82543) {
2093 DPRINTK(PROBE, ERR, "Jumbo Frames not supported on 82542\n");
2094 return -EINVAL;
2095
2096 } else if(max_frame <= E1000_RXBUFFER_4096) {
2097 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2098
2099 } else if(max_frame <= E1000_RXBUFFER_8192) {
2100 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2101
2102 } else {
2103 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2104 }
2105
2106 if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) {
2107 e1000_down(adapter);
2108 e1000_up(adapter);
2109 }
2110
2111 netdev->mtu = new_mtu;
2112 adapter->hw.max_frame_size = max_frame;
2113
2114 return 0;
2115}
2116
2117/**
2118 * e1000_update_stats - Update the board statistics counters
2119 * @adapter: board private structure
2120 **/
2121
2122void
2123e1000_update_stats(struct e1000_adapter *adapter)
2124{
2125 struct e1000_hw *hw = &adapter->hw;
2126 unsigned long flags;
2127 uint16_t phy_tmp;
2128
2129#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2130
2131 spin_lock_irqsave(&adapter->stats_lock, flags);
2132
2133 /* these counters are modified from e1000_adjust_tbi_stats,
2134 * called from the interrupt context, so they must only
2135 * be written while holding adapter->stats_lock
2136 */
2137
2138 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
2139 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
2140 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
2141 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
2142 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
2143 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
2144 adapter->stats.roc += E1000_READ_REG(hw, ROC);
2145 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
2146 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
2147 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
2148 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
2149 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
2150 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
2151
2152 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
2153 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
2154 adapter->stats.scc += E1000_READ_REG(hw, SCC);
2155 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
2156 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
2157 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
2158 adapter->stats.dc += E1000_READ_REG(hw, DC);
2159 adapter->stats.sec += E1000_READ_REG(hw, SEC);
2160 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
2161 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
2162 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
2163 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
2164 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
2165 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
2166 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
2167 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
2168 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
2169 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
2170 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
2171 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
2172 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
2173 adapter->stats.torl += E1000_READ_REG(hw, TORL);
2174 adapter->stats.torh += E1000_READ_REG(hw, TORH);
2175 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
2176 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
2177 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
2178 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
2179 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
2180 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
2181 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
2182 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
2183 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
2184 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
2185 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
2186
2187 /* used for adaptive IFS */
2188
2189 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
2190 adapter->stats.tpt += hw->tx_packet_delta;
2191 hw->collision_delta = E1000_READ_REG(hw, COLC);
2192 adapter->stats.colc += hw->collision_delta;
2193
2194 if(hw->mac_type >= e1000_82543) {
2195 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
2196 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
2197 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
2198 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
2199 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
2200 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
2201 }
2202
2203 /* Fill out the OS statistics structure */
2204
2205 adapter->net_stats.rx_packets = adapter->stats.gprc;
2206 adapter->net_stats.tx_packets = adapter->stats.gptc;
2207 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
2208 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
2209 adapter->net_stats.multicast = adapter->stats.mprc;
2210 adapter->net_stats.collisions = adapter->stats.colc;
2211
2212 /* Rx Errors */
2213
2214 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2215 adapter->stats.crcerrs + adapter->stats.algnerrc +
2216 adapter->stats.rlec + adapter->stats.rnbc +
2217 adapter->stats.mpc + adapter->stats.cexterr;
2218 adapter->net_stats.rx_dropped = adapter->stats.rnbc;
2219 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2220 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2221 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2222 adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
2223 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2224
2225 /* Tx Errors */
2226
2227 adapter->net_stats.tx_errors = adapter->stats.ecol +
2228 adapter->stats.latecol;
2229 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
2230 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
2231 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
2232
2233 /* Tx Dropped needs to be maintained elsewhere */
2234
2235 /* Phy Stats */
2236
2237 if(hw->media_type == e1000_media_type_copper) {
2238 if((adapter->link_speed == SPEED_1000) &&
2239 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
2240 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
2241 adapter->phy_stats.idle_errors += phy_tmp;
2242 }
2243
2244 if((hw->mac_type <= e1000_82546) &&
2245 (hw->phy_type == e1000_phy_m88) &&
2246 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
2247 adapter->phy_stats.receive_errors += phy_tmp;
2248 }
2249
2250 spin_unlock_irqrestore(&adapter->stats_lock, flags);
2251}
2252
2253/**
2254 * e1000_intr - Interrupt Handler
2255 * @irq: interrupt number
2256 * @data: pointer to a network interface device structure
2257 * @pt_regs: CPU registers structure
2258 **/
2259
2260static irqreturn_t
2261e1000_intr(int irq, void *data, struct pt_regs *regs)
2262{
2263 struct net_device *netdev = data;
2264 struct e1000_adapter *adapter = netdev->priv;
2265 struct e1000_hw *hw = &adapter->hw;
2266 uint32_t icr = E1000_READ_REG(hw, ICR);
2267#ifndef CONFIG_E1000_NAPI
2268 unsigned int i;
2269#endif
2270
2271 if(unlikely(!icr))
2272 return IRQ_NONE; /* Not our interrupt */
2273
2274 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
2275 hw->get_link_status = 1;
2276 mod_timer(&adapter->watchdog_timer, jiffies);
2277 }
2278
2279#ifdef CONFIG_E1000_NAPI
2280 if(likely(netif_rx_schedule_prep(netdev))) {
2281
2282 /* Disable interrupts and register for poll. The flush
2283 of the posted write is intentionally left out.
2284 */
2285
2286 atomic_inc(&adapter->irq_sem);
2287 E1000_WRITE_REG(hw, IMC, ~0);
2288 __netif_rx_schedule(netdev);
2289 }
2290#else
2291 /* Writing IMC and IMS is needed for 82547.
2292 Due to Hub Link bus being occupied, an interrupt
2293 de-assertion message is not able to be sent.
2294 When an interrupt assertion message is generated later,
2295 two messages are re-ordered and sent out.
2296 That causes APIC to think 82547 is in de-assertion
2297 state, while 82547 is in assertion state, resulting
2298 in dead lock. Writing IMC forces 82547 into
2299 de-assertion state.
2300 */
2301 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
2302 atomic_inc(&adapter->irq_sem);
2303 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
2304 }
2305
2306 for(i = 0; i < E1000_MAX_INTR; i++)
2307 if(unlikely(!e1000_clean_rx_irq(adapter) &
2308 !e1000_clean_tx_irq(adapter)))
2309 break;
2310
2311 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
2312 e1000_irq_enable(adapter);
2313#endif
2314
2315 return IRQ_HANDLED;
2316}
2317
2318#ifdef CONFIG_E1000_NAPI
2319/**
2320 * e1000_clean - NAPI Rx polling callback
2321 * @adapter: board private structure
2322 **/
2323
2324static int
2325e1000_clean(struct net_device *netdev, int *budget)
2326{
2327 struct e1000_adapter *adapter = netdev->priv;
2328 int work_to_do = min(*budget, netdev->quota);
2329 int tx_cleaned;
2330 int work_done = 0;
2331
2332 tx_cleaned = e1000_clean_tx_irq(adapter);
2333 e1000_clean_rx_irq(adapter, &work_done, work_to_do);
2334
2335 *budget -= work_done;
2336 netdev->quota -= work_done;
2337
2338 /* if no Tx and not enough Rx work done, exit the polling mode */
2339 if((!tx_cleaned && (work_done < work_to_do)) ||
2340 !netif_running(netdev)) {
2341 netif_rx_complete(netdev);
2342 e1000_irq_enable(adapter);
2343 return 0;
2344 }
2345
2346 return 1;
2347}
2348
2349#endif
2350/**
2351 * e1000_clean_tx_irq - Reclaim resources after transmit completes
2352 * @adapter: board private structure
2353 **/
2354
2355static boolean_t
2356e1000_clean_tx_irq(struct e1000_adapter *adapter)
2357{
2358 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
2359 struct net_device *netdev = adapter->netdev;
2360 struct e1000_tx_desc *tx_desc, *eop_desc;
2361 struct e1000_buffer *buffer_info;
2362 unsigned int i, eop;
2363 boolean_t cleaned = FALSE;
2364
2365 i = tx_ring->next_to_clean;
2366 eop = tx_ring->buffer_info[i].next_to_watch;
2367 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2368
2369 while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
2370 /* pre-mature writeback of Tx descriptors */
2371 /* clear (free buffers and unmap pci_mapping) */
2372 /* previous_buffer_info */
2373 if (likely(adapter->previous_buffer_info.skb != NULL)) {
2374 e1000_unmap_and_free_tx_resource(adapter,
2375 &adapter->previous_buffer_info);
2376 }
2377
2378 for(cleaned = FALSE; !cleaned; ) {
2379 tx_desc = E1000_TX_DESC(*tx_ring, i);
2380 buffer_info = &tx_ring->buffer_info[i];
2381 cleaned = (i == eop);
2382
2383 /* pre-mature writeback of Tx descriptors */
2384 /* save the cleaning of the this for the */
2385 /* next iteration */
2386 if (cleaned) {
2387 memcpy(&adapter->previous_buffer_info,
2388 buffer_info,
2389 sizeof(struct e1000_buffer));
2390 memset(buffer_info,
2391 0,
2392 sizeof(struct e1000_buffer));
2393 } else {
2394 e1000_unmap_and_free_tx_resource(adapter,
2395 buffer_info);
2396 }
2397
2398 tx_desc->buffer_addr = 0;
2399 tx_desc->lower.data = 0;
2400 tx_desc->upper.data = 0;
2401
2402 cleaned = (i == eop);
2403 if(unlikely(++i == tx_ring->count)) i = 0;
2404 }
2405
2406 eop = tx_ring->buffer_info[i].next_to_watch;
2407 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2408 }
2409
2410 tx_ring->next_to_clean = i;
2411
2412 spin_lock(&adapter->tx_lock);
2413
2414 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
2415 netif_carrier_ok(netdev)))
2416 netif_wake_queue(netdev);
2417
2418 spin_unlock(&adapter->tx_lock);
2419
2420 if(adapter->detect_tx_hung) {
2421 /* detect a transmit hang in hardware, this serializes the
2422 * check with the clearing of time_stamp and movement of i */
2423 adapter->detect_tx_hung = FALSE;
2424 if(tx_ring->buffer_info[i].dma &&
2425 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ) &&
2426 !(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF))
2427 netif_stop_queue(netdev);
2428 }
2429
2430 return cleaned;
2431}
2432
2433/**
2434 * e1000_rx_checksum - Receive Checksum Offload for 82543
2435 * @adapter: board private structure
2436 * @rx_desc: receive descriptor
2437 * @sk_buff: socket buffer with received data
2438 **/
2439
2440static inline void
2441e1000_rx_checksum(struct e1000_adapter *adapter,
2442 struct e1000_rx_desc *rx_desc,
2443 struct sk_buff *skb)
2444{
2445 /* 82543 or newer only */
2446 if(unlikely((adapter->hw.mac_type < e1000_82543) ||
2447 /* Ignore Checksum bit is set */
2448 (rx_desc->status & E1000_RXD_STAT_IXSM) ||
2449 /* TCP Checksum has not been calculated */
2450 (!(rx_desc->status & E1000_RXD_STAT_TCPCS)))) {
2451 skb->ip_summed = CHECKSUM_NONE;
2452 return;
2453 }
2454
2455 /* At this point we know the hardware did the TCP checksum */
2456 /* now look at the TCP checksum error bit */
2457 if(rx_desc->errors & E1000_RXD_ERR_TCPE) {
2458 /* let the stack verify checksum errors */
2459 skb->ip_summed = CHECKSUM_NONE;
2460 adapter->hw_csum_err++;
2461 } else {
2462 /* TCP checksum is good */
2463 skb->ip_summed = CHECKSUM_UNNECESSARY;
2464 adapter->hw_csum_good++;
2465 }
2466}
2467
2468/**
2469 * e1000_clean_rx_irq - Send received data up the network stack
2470 * @adapter: board private structure
2471 **/
2472
2473static boolean_t
2474#ifdef CONFIG_E1000_NAPI
2475e1000_clean_rx_irq(struct e1000_adapter *adapter, int *work_done,
2476 int work_to_do)
2477#else
2478e1000_clean_rx_irq(struct e1000_adapter *adapter)
2479#endif
2480{
2481 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2482 struct net_device *netdev = adapter->netdev;
2483 struct pci_dev *pdev = adapter->pdev;
2484 struct e1000_rx_desc *rx_desc;
2485 struct e1000_buffer *buffer_info;
2486 struct sk_buff *skb;
2487 unsigned long flags;
2488 uint32_t length;
2489 uint8_t last_byte;
2490 unsigned int i;
2491 boolean_t cleaned = FALSE;
2492
2493 i = rx_ring->next_to_clean;
2494 rx_desc = E1000_RX_DESC(*rx_ring, i);
2495
2496 while(rx_desc->status & E1000_RXD_STAT_DD) {
2497 buffer_info = &rx_ring->buffer_info[i];
2498#ifdef CONFIG_E1000_NAPI
2499 if(*work_done >= work_to_do)
2500 break;
2501 (*work_done)++;
2502#endif
2503 cleaned = TRUE;
2504
2505 pci_unmap_single(pdev,
2506 buffer_info->dma,
2507 buffer_info->length,
2508 PCI_DMA_FROMDEVICE);
2509
2510 skb = buffer_info->skb;
2511 length = le16_to_cpu(rx_desc->length);
2512
2513 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
2514 /* All receives must fit into a single buffer */
2515 E1000_DBG("%s: Receive packet consumed multiple"
2516 " buffers\n", netdev->name);
2517 dev_kfree_skb_irq(skb);
2518 goto next_desc;
2519 }
2520
2521 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
2522 last_byte = *(skb->data + length - 1);
2523 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
2524 rx_desc->errors, length, last_byte)) {
2525 spin_lock_irqsave(&adapter->stats_lock, flags);
2526 e1000_tbi_adjust_stats(&adapter->hw,
2527 &adapter->stats,
2528 length, skb->data);
2529 spin_unlock_irqrestore(&adapter->stats_lock,
2530 flags);
2531 length--;
2532 } else {
2533 dev_kfree_skb_irq(skb);
2534 goto next_desc;
2535 }
2536 }
2537
2538 /* Good Receive */
2539 skb_put(skb, length - ETHERNET_FCS_SIZE);
2540
2541 /* Receive Checksum Offload */
2542 e1000_rx_checksum(adapter, rx_desc, skb);
2543
2544 skb->protocol = eth_type_trans(skb, netdev);
2545#ifdef CONFIG_E1000_NAPI
2546 if(unlikely(adapter->vlgrp &&
2547 (rx_desc->status & E1000_RXD_STAT_VP))) {
2548 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2549 le16_to_cpu(rx_desc->special) &
2550 E1000_RXD_SPC_VLAN_MASK);
2551 } else {
2552 netif_receive_skb(skb);
2553 }
2554#else /* CONFIG_E1000_NAPI */
2555 if(unlikely(adapter->vlgrp &&
2556 (rx_desc->status & E1000_RXD_STAT_VP))) {
2557 vlan_hwaccel_rx(skb, adapter->vlgrp,
2558 le16_to_cpu(rx_desc->special) &
2559 E1000_RXD_SPC_VLAN_MASK);
2560 } else {
2561 netif_rx(skb);
2562 }
2563#endif /* CONFIG_E1000_NAPI */
2564 netdev->last_rx = jiffies;
2565
2566next_desc:
2567 rx_desc->status = 0;
2568 buffer_info->skb = NULL;
2569 if(unlikely(++i == rx_ring->count)) i = 0;
2570
2571 rx_desc = E1000_RX_DESC(*rx_ring, i);
2572 }
2573
2574 rx_ring->next_to_clean = i;
2575
2576 e1000_alloc_rx_buffers(adapter);
2577
2578 return cleaned;
2579}
2580
2581/**
2582 * e1000_alloc_rx_buffers - Replace used receive buffers
2583 * @adapter: address of board private structure
2584 **/
2585
2586static void
2587e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2588{
2589 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2590 struct net_device *netdev = adapter->netdev;
2591 struct pci_dev *pdev = adapter->pdev;
2592 struct e1000_rx_desc *rx_desc;
2593 struct e1000_buffer *buffer_info;
2594 struct sk_buff *skb;
2595 unsigned int i, bufsz;
2596
2597 i = rx_ring->next_to_use;
2598 buffer_info = &rx_ring->buffer_info[i];
2599
2600 while(!buffer_info->skb) {
2601 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
2602
2603 skb = dev_alloc_skb(bufsz);
2604 if(unlikely(!skb)) {
2605 /* Better luck next round */
2606 break;
2607 }
2608
2609 /* fix for errata 23, cant cross 64kB boundary */
2610 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
2611 struct sk_buff *oldskb = skb;
2612 DPRINTK(RX_ERR,ERR,
2613 "skb align check failed: %u bytes at %p\n",
2614 bufsz, skb->data);
2615 /* try again, without freeing the previous */
2616 skb = dev_alloc_skb(bufsz);
2617 if (!skb) {
2618 dev_kfree_skb(oldskb);
2619 break;
2620 }
2621 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
2622 /* give up */
2623 dev_kfree_skb(skb);
2624 dev_kfree_skb(oldskb);
2625 break; /* while !buffer_info->skb */
2626 } else {
2627 /* move on with the new one */
2628 dev_kfree_skb(oldskb);
2629 }
2630 }
2631
2632 /* Make buffer alignment 2 beyond a 16 byte boundary
2633 * this will result in a 16 byte aligned IP header after
2634 * the 14 byte MAC header is removed
2635 */
2636 skb_reserve(skb, NET_IP_ALIGN);
2637
2638 skb->dev = netdev;
2639
2640 buffer_info->skb = skb;
2641 buffer_info->length = adapter->rx_buffer_len;
2642 buffer_info->dma = pci_map_single(pdev,
2643 skb->data,
2644 adapter->rx_buffer_len,
2645 PCI_DMA_FROMDEVICE);
2646
2647 /* fix for errata 23, cant cross 64kB boundary */
2648 if(!e1000_check_64k_bound(adapter,
2649 (void *)(unsigned long)buffer_info->dma,
2650 adapter->rx_buffer_len)) {
2651 DPRINTK(RX_ERR,ERR,
2652 "dma align check failed: %u bytes at %ld\n",
2653 adapter->rx_buffer_len, (unsigned long)buffer_info->dma);
2654
2655 dev_kfree_skb(skb);
2656 buffer_info->skb = NULL;
2657
2658 pci_unmap_single(pdev,
2659 buffer_info->dma,
2660 adapter->rx_buffer_len,
2661 PCI_DMA_FROMDEVICE);
2662
2663 break; /* while !buffer_info->skb */
2664 }
2665
2666 rx_desc = E1000_RX_DESC(*rx_ring, i);
2667 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2668
2669 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
2670 /* Force memory writes to complete before letting h/w
2671 * know there are new descriptors to fetch. (Only
2672 * applicable for weak-ordered memory model archs,
2673 * such as IA-64). */
2674 wmb();
2675
2676 E1000_WRITE_REG(&adapter->hw, RDT, i);
2677 }
2678
2679 if(unlikely(++i == rx_ring->count)) i = 0;
2680 buffer_info = &rx_ring->buffer_info[i];
2681 }
2682
2683 rx_ring->next_to_use = i;
2684}
2685
2686/**
2687 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
2688 * @adapter:
2689 **/
2690
2691static void
2692e1000_smartspeed(struct e1000_adapter *adapter)
2693{
2694 uint16_t phy_status;
2695 uint16_t phy_ctrl;
2696
2697 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
2698 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2699 return;
2700
2701 if(adapter->smartspeed == 0) {
2702 /* If Master/Slave config fault is asserted twice,
2703 * we assume back-to-back */
2704 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
2705 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
2706 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
2707 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
2708 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
2709 if(phy_ctrl & CR_1000T_MS_ENABLE) {
2710 phy_ctrl &= ~CR_1000T_MS_ENABLE;
2711 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
2712 phy_ctrl);
2713 adapter->smartspeed++;
2714 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
2715 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
2716 &phy_ctrl)) {
2717 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
2718 MII_CR_RESTART_AUTO_NEG);
2719 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
2720 phy_ctrl);
2721 }
2722 }
2723 return;
2724 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
2725 /* If still no link, perhaps using 2/3 pair cable */
2726 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
2727 phy_ctrl |= CR_1000T_MS_ENABLE;
2728 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
2729 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
2730 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
2731 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
2732 MII_CR_RESTART_AUTO_NEG);
2733 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
2734 }
2735 }
2736 /* Restart process after E1000_SMARTSPEED_MAX iterations */
2737 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
2738 adapter->smartspeed = 0;
2739}
2740
2741/**
2742 * e1000_ioctl -
2743 * @netdev:
2744 * @ifreq:
2745 * @cmd:
2746 **/
2747
2748static int
2749e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2750{
2751 switch (cmd) {
2752 case SIOCGMIIPHY:
2753 case SIOCGMIIREG:
2754 case SIOCSMIIREG:
2755 return e1000_mii_ioctl(netdev, ifr, cmd);
2756 default:
2757 return -EOPNOTSUPP;
2758 }
2759}
2760
2761/**
2762 * e1000_mii_ioctl -
2763 * @netdev:
2764 * @ifreq:
2765 * @cmd:
2766 **/
2767
2768static int
2769e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2770{
2771 struct e1000_adapter *adapter = netdev->priv;
2772 struct mii_ioctl_data *data = if_mii(ifr);
2773 int retval;
2774 uint16_t mii_reg;
2775 uint16_t spddplx;
2776
2777 if(adapter->hw.media_type != e1000_media_type_copper)
2778 return -EOPNOTSUPP;
2779
2780 switch (cmd) {
2781 case SIOCGMIIPHY:
2782 data->phy_id = adapter->hw.phy_addr;
2783 break;
2784 case SIOCGMIIREG:
2785 if (!capable(CAP_NET_ADMIN))
2786 return -EPERM;
2787 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
2788 &data->val_out))
2789 return -EIO;
2790 break;
2791 case SIOCSMIIREG:
2792 if (!capable(CAP_NET_ADMIN))
2793 return -EPERM;
2794 if (data->reg_num & ~(0x1F))
2795 return -EFAULT;
2796 mii_reg = data->val_in;
2797 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
2798 mii_reg))
2799 return -EIO;
2800 if (adapter->hw.phy_type == e1000_phy_m88) {
2801 switch (data->reg_num) {
2802 case PHY_CTRL:
2803 if(mii_reg & MII_CR_POWER_DOWN)
2804 break;
2805 if(mii_reg & MII_CR_AUTO_NEG_EN) {
2806 adapter->hw.autoneg = 1;
2807 adapter->hw.autoneg_advertised = 0x2F;
2808 } else {
2809 if (mii_reg & 0x40)
2810 spddplx = SPEED_1000;
2811 else if (mii_reg & 0x2000)
2812 spddplx = SPEED_100;
2813 else
2814 spddplx = SPEED_10;
2815 spddplx += (mii_reg & 0x100)
2816 ? FULL_DUPLEX :
2817 HALF_DUPLEX;
2818 retval = e1000_set_spd_dplx(adapter,
2819 spddplx);
2820 if(retval)
2821 return retval;
2822 }
2823 if(netif_running(adapter->netdev)) {
2824 e1000_down(adapter);
2825 e1000_up(adapter);
2826 } else
2827 e1000_reset(adapter);
2828 break;
2829 case M88E1000_PHY_SPEC_CTRL:
2830 case M88E1000_EXT_PHY_SPEC_CTRL:
2831 if (e1000_phy_reset(&adapter->hw))
2832 return -EIO;
2833 break;
2834 }
2835 } else {
2836 switch (data->reg_num) {
2837 case PHY_CTRL:
2838 if(mii_reg & MII_CR_POWER_DOWN)
2839 break;
2840 if(netif_running(adapter->netdev)) {
2841 e1000_down(adapter);
2842 e1000_up(adapter);
2843 } else
2844 e1000_reset(adapter);
2845 break;
2846 }
2847 }
2848 break;
2849 default:
2850 return -EOPNOTSUPP;
2851 }
2852 return E1000_SUCCESS;
2853}
2854
2855void
2856e1000_pci_set_mwi(struct e1000_hw *hw)
2857{
2858 struct e1000_adapter *adapter = hw->back;
2859
2860 int ret;
2861 ret = pci_set_mwi(adapter->pdev);
2862}
2863
2864void
2865e1000_pci_clear_mwi(struct e1000_hw *hw)
2866{
2867 struct e1000_adapter *adapter = hw->back;
2868
2869 pci_clear_mwi(adapter->pdev);
2870}
2871
2872void
2873e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
2874{
2875 struct e1000_adapter *adapter = hw->back;
2876
2877 pci_read_config_word(adapter->pdev, reg, value);
2878}
2879
2880void
2881e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
2882{
2883 struct e1000_adapter *adapter = hw->back;
2884
2885 pci_write_config_word(adapter->pdev, reg, *value);
2886}
2887
2888uint32_t
2889e1000_io_read(struct e1000_hw *hw, unsigned long port)
2890{
2891 return inl(port);
2892}
2893
2894void
2895e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
2896{
2897 outl(value, port);
2898}
2899
2900static void
2901e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2902{
2903 struct e1000_adapter *adapter = netdev->priv;
2904 uint32_t ctrl, rctl;
2905
2906 e1000_irq_disable(adapter);
2907 adapter->vlgrp = grp;
2908
2909 if(grp) {
2910 /* enable VLAN tag insert/strip */
2911 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2912 ctrl |= E1000_CTRL_VME;
2913 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
2914
2915 /* enable VLAN receive filtering */
2916 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2917 rctl |= E1000_RCTL_VFE;
2918 rctl &= ~E1000_RCTL_CFIEN;
2919 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2920 } else {
2921 /* disable VLAN tag insert/strip */
2922 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2923 ctrl &= ~E1000_CTRL_VME;
2924 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
2925
2926 /* disable VLAN filtering */
2927 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2928 rctl &= ~E1000_RCTL_VFE;
2929 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2930 }
2931
2932 e1000_irq_enable(adapter);
2933}
2934
2935static void
2936e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
2937{
2938 struct e1000_adapter *adapter = netdev->priv;
2939 uint32_t vfta, index;
2940
2941 /* add VID to filter table */
2942 index = (vid >> 5) & 0x7F;
2943 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
2944 vfta |= (1 << (vid & 0x1F));
2945 e1000_write_vfta(&adapter->hw, index, vfta);
2946}
2947
2948static void
2949e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
2950{
2951 struct e1000_adapter *adapter = netdev->priv;
2952 uint32_t vfta, index;
2953
2954 e1000_irq_disable(adapter);
2955
2956 if(adapter->vlgrp)
2957 adapter->vlgrp->vlan_devices[vid] = NULL;
2958
2959 e1000_irq_enable(adapter);
2960
2961 /* remove VID from filter table */
2962 index = (vid >> 5) & 0x7F;
2963 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
2964 vfta &= ~(1 << (vid & 0x1F));
2965 e1000_write_vfta(&adapter->hw, index, vfta);
2966}
2967
2968static void
2969e1000_restore_vlan(struct e1000_adapter *adapter)
2970{
2971 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2972
2973 if(adapter->vlgrp) {
2974 uint16_t vid;
2975 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2976 if(!adapter->vlgrp->vlan_devices[vid])
2977 continue;
2978 e1000_vlan_rx_add_vid(adapter->netdev, vid);
2979 }
2980 }
2981}
2982
2983int
2984e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
2985{
2986 adapter->hw.autoneg = 0;
2987
2988 switch(spddplx) {
2989 case SPEED_10 + DUPLEX_HALF:
2990 adapter->hw.forced_speed_duplex = e1000_10_half;
2991 break;
2992 case SPEED_10 + DUPLEX_FULL:
2993 adapter->hw.forced_speed_duplex = e1000_10_full;
2994 break;
2995 case SPEED_100 + DUPLEX_HALF:
2996 adapter->hw.forced_speed_duplex = e1000_100_half;
2997 break;
2998 case SPEED_100 + DUPLEX_FULL:
2999 adapter->hw.forced_speed_duplex = e1000_100_full;
3000 break;
3001 case SPEED_1000 + DUPLEX_FULL:
3002 adapter->hw.autoneg = 1;
3003 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
3004 break;
3005 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3006 default:
3007 DPRINTK(PROBE, ERR,
3008 "Unsupported Speed/Duplexity configuration\n");
3009 return -EINVAL;
3010 }
3011 return 0;
3012}
3013
3014static int
3015e1000_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
3016{
3017 struct pci_dev *pdev = NULL;
3018
3019 switch(event) {
3020 case SYS_DOWN:
3021 case SYS_HALT:
3022 case SYS_POWER_OFF:
3023 while((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
3024 if(pci_dev_driver(pdev) == &e1000_driver)
3025 e1000_suspend(pdev, 3);
3026 }
3027 }
3028 return NOTIFY_DONE;
3029}
3030
3031static int
3032e1000_suspend(struct pci_dev *pdev, uint32_t state)
3033{
3034 struct net_device *netdev = pci_get_drvdata(pdev);
3035 struct e1000_adapter *adapter = netdev->priv;
3036 uint32_t ctrl, ctrl_ext, rctl, manc, status;
3037 uint32_t wufc = adapter->wol;
3038
3039 netif_device_detach(netdev);
3040
3041 if(netif_running(netdev))
3042 e1000_down(adapter);
3043
3044 status = E1000_READ_REG(&adapter->hw, STATUS);
3045 if(status & E1000_STATUS_LU)
3046 wufc &= ~E1000_WUFC_LNKC;
3047
3048 if(wufc) {
3049 e1000_setup_rctl(adapter);
3050 e1000_set_multi(netdev);
3051
3052 /* turn on all-multi mode if wake on multicast is enabled */
3053 if(adapter->wol & E1000_WUFC_MC) {
3054 rctl = E1000_READ_REG(&adapter->hw, RCTL);
3055 rctl |= E1000_RCTL_MPE;
3056 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3057 }
3058
3059 if(adapter->hw.mac_type >= e1000_82540) {
3060 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3061 /* advertise wake from D3Cold */
3062 #define E1000_CTRL_ADVD3WUC 0x00100000
3063 /* phy power management enable */
3064 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3065 ctrl |= E1000_CTRL_ADVD3WUC |
3066 E1000_CTRL_EN_PHY_PWR_MGMT;
3067 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3068 }
3069
3070 if(adapter->hw.media_type == e1000_media_type_fiber ||
3071 adapter->hw.media_type == e1000_media_type_internal_serdes) {
3072 /* keep the laser running in D3 */
3073 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
3074 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3075 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
3076 }
3077
3078 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
3079 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
3080 pci_enable_wake(pdev, 3, 1);
3081 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
3082 } else {
3083 E1000_WRITE_REG(&adapter->hw, WUC, 0);
3084 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
3085 pci_enable_wake(pdev, 3, 0);
3086 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
3087 }
3088
3089 pci_save_state(pdev);
3090
3091 if(adapter->hw.mac_type >= e1000_82540 &&
3092 adapter->hw.media_type == e1000_media_type_copper) {
3093 manc = E1000_READ_REG(&adapter->hw, MANC);
3094 if(manc & E1000_MANC_SMBUS_EN) {
3095 manc |= E1000_MANC_ARP_EN;
3096 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3097 pci_enable_wake(pdev, 3, 1);
3098 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
3099 }
3100 }
3101
3102 pci_disable_device(pdev);
3103
3104 state = (state > 0) ? 3 : 0;
3105 pci_set_power_state(pdev, state);
3106
3107 return 0;
3108}
3109
3110#ifdef CONFIG_PM
3111static int
3112e1000_resume(struct pci_dev *pdev)
3113{
3114 struct net_device *netdev = pci_get_drvdata(pdev);
3115 struct e1000_adapter *adapter = netdev->priv;
3116 uint32_t manc, ret;
3117
3118 pci_set_power_state(pdev, 0);
3119 pci_restore_state(pdev);
3120 ret = pci_enable_device(pdev);
3121 if (pdev->is_busmaster)
3122 pci_set_master(pdev);
3123
3124 pci_enable_wake(pdev, 3, 0);
3125 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
3126
3127 e1000_reset(adapter);
3128 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
3129
3130 if(netif_running(netdev))
3131 e1000_up(adapter);
3132
3133 netif_device_attach(netdev);
3134
3135 if(adapter->hw.mac_type >= e1000_82540 &&
3136 adapter->hw.media_type == e1000_media_type_copper) {
3137 manc = E1000_READ_REG(&adapter->hw, MANC);
3138 manc &= ~(E1000_MANC_ARP_EN);
3139 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3140 }
3141
3142 return 0;
3143}
3144#endif
3145
3146#ifdef CONFIG_NET_POLL_CONTROLLER
3147/*
3148 * Polling 'interrupt' - used by things like netconsole to send skbs
3149 * without having to re-enable interrupts. It's not called while
3150 * the interrupt routine is executing.
3151 */
3152static void
3153e1000_netpoll (struct net_device *netdev)
3154{
3155 struct e1000_adapter *adapter = netdev->priv;
3156 disable_irq(adapter->pdev->irq);
3157 e1000_intr(adapter->pdev->irq, netdev, NULL);
3158 enable_irq(adapter->pdev->irq);
3159}
3160#endif
3161
3162/* e1000_main.c */
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
new file mode 100644
index 000000000000..970c656a517c
--- /dev/null
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -0,0 +1,101 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29
30/* glue for the OS independent part of e1000
31 * includes register access macros
32 */
33
34#ifndef _E1000_OSDEP_H_
35#define _E1000_OSDEP_H_
36
37#include <linux/types.h>
38#include <linux/pci.h>
39#include <linux/delay.h>
40#include <asm/io.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
43
44#ifndef msec_delay
45#define msec_delay(x) msleep(x)
46
47/* Some workarounds require millisecond delays and are run during interrupt
48 * context. Most notably, when establishing link, the phy may need tweaking
49 * but cannot process phy register reads/writes faster than millisecond
50 * intervals...and we establish link due to a "link status change" interrupt.
51 */
52#define msec_delay_irq(x) mdelay(x)
53#endif
54
55#define PCI_COMMAND_REGISTER PCI_COMMAND
56#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
57
58typedef enum {
59#undef FALSE
60 FALSE = 0,
61#undef TRUE
62 TRUE = 1
63} boolean_t;
64
65#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
66
67#ifdef DBG
68#define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
69#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
70#else
71#define DEBUGOUT(S)
72#define DEBUGOUT1(S, A...)
73#endif
74
75#define DEBUGFUNC(F) DEBUGOUT(F)
76#define DEBUGOUT2 DEBUGOUT1
77#define DEBUGOUT3 DEBUGOUT2
78#define DEBUGOUT7 DEBUGOUT3
79
80
81#define E1000_WRITE_REG(a, reg, value) ( \
82 writel((value), ((a)->hw_addr + \
83 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
84
85#define E1000_READ_REG(a, reg) ( \
86 readl((a)->hw_addr + \
87 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
88
89#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
90 writel((value), ((a)->hw_addr + \
91 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
92 ((offset) << 2))))
93
94#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
95 readl((a)->hw_addr + \
96 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
97 ((offset) << 2)))
98
99#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
100
101#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
new file mode 100644
index 000000000000..e914d09fe6f9
--- /dev/null
+++ b/drivers/net/e1000/e1000_param.c
@@ -0,0 +1,744 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* This is the only thing that needs to be changed to adjust the
32 * maximum number of ports that the driver can manage.
33 */
34
35#define E1000_MAX_NIC 32
36
37#define OPTION_UNSET -1
38#define OPTION_DISABLED 0
39#define OPTION_ENABLED 1
40
41/* All parameters are treated the same, as an integer array of values.
42 * This macro just reduces the need to repeat the same declaration code
43 * over and over (plus this helps to avoid typo bugs).
44 */
45
46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
47#define E1000_PARAM(X, desc) \
48 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
49 static int num_##X = 0; \
50 module_param_array_named(X, X, int, &num_##X, 0); \
51 MODULE_PARM_DESC(X, desc);
52
53/* Transmit Descriptor Count
54 *
55 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
56 * Valid Range: 80-4096 for 82544 and newer
57 *
58 * Default Value: 256
59 */
60
61E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
62
63/* Receive Descriptor Count
64 *
65 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
66 * Valid Range: 80-4096 for 82544 and newer
67 *
68 * Default Value: 256
69 */
70
71E1000_PARAM(RxDescriptors, "Number of receive descriptors");
72
73/* User Specified Speed Override
74 *
75 * Valid Range: 0, 10, 100, 1000
76 * - 0 - auto-negotiate at all supported speeds
77 * - 10 - only link at 10 Mbps
78 * - 100 - only link at 100 Mbps
79 * - 1000 - only link at 1000 Mbps
80 *
81 * Default Value: 0
82 */
83
84E1000_PARAM(Speed, "Speed setting");
85
86/* User Specified Duplex Override
87 *
88 * Valid Range: 0-2
89 * - 0 - auto-negotiate for duplex
90 * - 1 - only link at half duplex
91 * - 2 - only link at full duplex
92 *
93 * Default Value: 0
94 */
95
96E1000_PARAM(Duplex, "Duplex setting");
97
98/* Auto-negotiation Advertisement Override
99 *
100 * Valid Range: 0x01-0x0F, 0x20-0x2F (copper); 0x20 (fiber)
101 *
102 * The AutoNeg value is a bit mask describing which speed and duplex
103 * combinations should be advertised during auto-negotiation.
104 * The supported speed and duplex modes are listed below
105 *
106 * Bit 7 6 5 4 3 2 1 0
107 * Speed (Mbps) N/A N/A 1000 N/A 100 100 10 10
108 * Duplex Full Full Half Full Half
109 *
110 * Default Value: 0x2F (copper); 0x20 (fiber)
111 */
112
113E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
114
115/* User Specified Flow Control Override
116 *
117 * Valid Range: 0-3
118 * - 0 - No Flow Control
119 * - 1 - Rx only, respond to PAUSE frames but do not generate them
120 * - 2 - Tx only, generate PAUSE frames but ignore them on receive
121 * - 3 - Full Flow Control Support
122 *
123 * Default Value: Read flow control settings from the EEPROM
124 */
125
126E1000_PARAM(FlowControl, "Flow Control setting");
127
128/* XsumRX - Receive Checksum Offload Enable/Disable
129 *
130 * Valid Range: 0, 1
131 * - 0 - disables all checksum offload
132 * - 1 - enables receive IP/TCP/UDP checksum offload
133 * on 82543 and newer -based NICs
134 *
135 * Default Value: 1
136 */
137
138E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
139
140/* Transmit Interrupt Delay in units of 1.024 microseconds
141 *
142 * Valid Range: 0-65535
143 *
144 * Default Value: 64
145 */
146
147E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
148
149/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
150 *
151 * Valid Range: 0-65535
152 *
153 * Default Value: 0
154 */
155
156E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
157
158/* Receive Interrupt Delay in units of 1.024 microseconds
159 *
160 * Valid Range: 0-65535
161 *
162 * Default Value: 0
163 */
164
165E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
166
167/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
168 *
169 * Valid Range: 0-65535
170 *
171 * Default Value: 128
172 */
173
174E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
175
176/* Interrupt Throttle Rate (interrupts/sec)
177 *
178 * Valid Range: 100-100000 (0=off, 1=dynamic)
179 *
180 * Default Value: 1
181 */
182
183E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
184
185#define AUTONEG_ADV_DEFAULT 0x2F
186#define AUTONEG_ADV_MASK 0x2F
187#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
188
189#define DEFAULT_RDTR 0
190#define MAX_RXDELAY 0xFFFF
191#define MIN_RXDELAY 0
192
193#define DEFAULT_RADV 128
194#define MAX_RXABSDELAY 0xFFFF
195#define MIN_RXABSDELAY 0
196
197#define DEFAULT_TIDV 64
198#define MAX_TXDELAY 0xFFFF
199#define MIN_TXDELAY 0
200
201#define DEFAULT_TADV 64
202#define MAX_TXABSDELAY 0xFFFF
203#define MIN_TXABSDELAY 0
204
205#define DEFAULT_ITR 8000
206#define MAX_ITR 100000
207#define MIN_ITR 100
208
209struct e1000_option {
210 enum { enable_option, range_option, list_option } type;
211 char *name;
212 char *err;
213 int def;
214 union {
215 struct { /* range_option info */
216 int min;
217 int max;
218 } r;
219 struct { /* list_option info */
220 int nr;
221 struct e1000_opt_list { int i; char *str; } *p;
222 } l;
223 } arg;
224};
225
226static int __devinit
227e1000_validate_option(int *value, struct e1000_option *opt,
228 struct e1000_adapter *adapter)
229{
230 if(*value == OPTION_UNSET) {
231 *value = opt->def;
232 return 0;
233 }
234
235 switch (opt->type) {
236 case enable_option:
237 switch (*value) {
238 case OPTION_ENABLED:
239 DPRINTK(PROBE, INFO, "%s Enabled\n", opt->name);
240 return 0;
241 case OPTION_DISABLED:
242 DPRINTK(PROBE, INFO, "%s Disabled\n", opt->name);
243 return 0;
244 }
245 break;
246 case range_option:
247 if(*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
248 DPRINTK(PROBE, INFO,
249 "%s set to %i\n", opt->name, *value);
250 return 0;
251 }
252 break;
253 case list_option: {
254 int i;
255 struct e1000_opt_list *ent;
256
257 for(i = 0; i < opt->arg.l.nr; i++) {
258 ent = &opt->arg.l.p[i];
259 if(*value == ent->i) {
260 if(ent->str[0] != '\0')
261 DPRINTK(PROBE, INFO, "%s\n", ent->str);
262 return 0;
263 }
264 }
265 }
266 break;
267 default:
268 BUG();
269 }
270
271 DPRINTK(PROBE, INFO, "Invalid %s specified (%i) %s\n",
272 opt->name, *value, opt->err);
273 *value = opt->def;
274 return -1;
275}
276
277static void e1000_check_fiber_options(struct e1000_adapter *adapter);
278static void e1000_check_copper_options(struct e1000_adapter *adapter);
279
280/**
281 * e1000_check_options - Range Checking for Command Line Parameters
282 * @adapter: board private structure
283 *
284 * This routine checks all command line parameters for valid user
285 * input. If an invalid value is given, or if no user specified
286 * value exists, a default value is used. The final value is stored
287 * in a variable in the adapter structure.
288 **/
289
290void __devinit
291e1000_check_options(struct e1000_adapter *adapter)
292{
293 int bd = adapter->bd_number;
294 if(bd >= E1000_MAX_NIC) {
295 DPRINTK(PROBE, NOTICE,
296 "Warning: no configuration for board #%i\n", bd);
297 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
298 }
299
300 { /* Transmit Descriptor Count */
301 struct e1000_option opt = {
302 .type = range_option,
303 .name = "Transmit Descriptors",
304 .err = "using default of "
305 __MODULE_STRING(E1000_DEFAULT_TXD),
306 .def = E1000_DEFAULT_TXD,
307 .arg = { .r = { .min = E1000_MIN_TXD }}
308 };
309 struct e1000_desc_ring *tx_ring = &adapter->tx_ring;
310 e1000_mac_type mac_type = adapter->hw.mac_type;
311 opt.arg.r.max = mac_type < e1000_82544 ?
312 E1000_MAX_TXD : E1000_MAX_82544_TXD;
313
314 if (num_TxDescriptors > bd) {
315 tx_ring->count = TxDescriptors[bd];
316 e1000_validate_option(&tx_ring->count, &opt, adapter);
317 E1000_ROUNDUP(tx_ring->count,
318 REQ_TX_DESCRIPTOR_MULTIPLE);
319 } else {
320 tx_ring->count = opt.def;
321 }
322 }
323 { /* Receive Descriptor Count */
324 struct e1000_option opt = {
325 .type = range_option,
326 .name = "Receive Descriptors",
327 .err = "using default of "
328 __MODULE_STRING(E1000_DEFAULT_RXD),
329 .def = E1000_DEFAULT_RXD,
330 .arg = { .r = { .min = E1000_MIN_RXD }}
331 };
332 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
333 e1000_mac_type mac_type = adapter->hw.mac_type;
334 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
335 E1000_MAX_82544_RXD;
336
337 if (num_RxDescriptors > bd) {
338 rx_ring->count = RxDescriptors[bd];
339 e1000_validate_option(&rx_ring->count, &opt, adapter);
340 E1000_ROUNDUP(rx_ring->count,
341 REQ_RX_DESCRIPTOR_MULTIPLE);
342 } else {
343 rx_ring->count = opt.def;
344 }
345 }
346 { /* Checksum Offload Enable/Disable */
347 struct e1000_option opt = {
348 .type = enable_option,
349 .name = "Checksum Offload",
350 .err = "defaulting to Enabled",
351 .def = OPTION_ENABLED
352 };
353
354 if (num_XsumRX > bd) {
355 int rx_csum = XsumRX[bd];
356 e1000_validate_option(&rx_csum, &opt, adapter);
357 adapter->rx_csum = rx_csum;
358 } else {
359 adapter->rx_csum = opt.def;
360 }
361 }
362 { /* Flow Control */
363
364 struct e1000_opt_list fc_list[] =
365 {{ e1000_fc_none, "Flow Control Disabled" },
366 { e1000_fc_rx_pause,"Flow Control Receive Only" },
367 { e1000_fc_tx_pause,"Flow Control Transmit Only" },
368 { e1000_fc_full, "Flow Control Enabled" },
369 { e1000_fc_default, "Flow Control Hardware Default" }};
370
371 struct e1000_option opt = {
372 .type = list_option,
373 .name = "Flow Control",
374 .err = "reading default settings from EEPROM",
375 .def = e1000_fc_default,
376 .arg = { .l = { .nr = ARRAY_SIZE(fc_list),
377 .p = fc_list }}
378 };
379
380 if (num_FlowControl > bd) {
381 int fc = FlowControl[bd];
382 e1000_validate_option(&fc, &opt, adapter);
383 adapter->hw.fc = adapter->hw.original_fc = fc;
384 } else {
385 adapter->hw.fc = opt.def;
386 }
387 }
388 { /* Transmit Interrupt Delay */
389 struct e1000_option opt = {
390 .type = range_option,
391 .name = "Transmit Interrupt Delay",
392 .err = "using default of " __MODULE_STRING(DEFAULT_TIDV),
393 .def = DEFAULT_TIDV,
394 .arg = { .r = { .min = MIN_TXDELAY,
395 .max = MAX_TXDELAY }}
396 };
397
398 if (num_TxIntDelay > bd) {
399 adapter->tx_int_delay = TxIntDelay[bd];
400 e1000_validate_option(&adapter->tx_int_delay, &opt,
401 adapter);
402 } else {
403 adapter->tx_int_delay = opt.def;
404 }
405 }
406 { /* Transmit Absolute Interrupt Delay */
407 struct e1000_option opt = {
408 .type = range_option,
409 .name = "Transmit Absolute Interrupt Delay",
410 .err = "using default of " __MODULE_STRING(DEFAULT_TADV),
411 .def = DEFAULT_TADV,
412 .arg = { .r = { .min = MIN_TXABSDELAY,
413 .max = MAX_TXABSDELAY }}
414 };
415
416 if (num_TxAbsIntDelay > bd) {
417 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
418 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
419 adapter);
420 } else {
421 adapter->tx_abs_int_delay = opt.def;
422 }
423 }
424 { /* Receive Interrupt Delay */
425 struct e1000_option opt = {
426 .type = range_option,
427 .name = "Receive Interrupt Delay",
428 .err = "using default of " __MODULE_STRING(DEFAULT_RDTR),
429 .def = DEFAULT_RDTR,
430 .arg = { .r = { .min = MIN_RXDELAY,
431 .max = MAX_RXDELAY }}
432 };
433
434 if (num_RxIntDelay > bd) {
435 adapter->rx_int_delay = RxIntDelay[bd];
436 e1000_validate_option(&adapter->rx_int_delay, &opt,
437 adapter);
438 } else {
439 adapter->rx_int_delay = opt.def;
440 }
441 }
442 { /* Receive Absolute Interrupt Delay */
443 struct e1000_option opt = {
444 .type = range_option,
445 .name = "Receive Absolute Interrupt Delay",
446 .err = "using default of " __MODULE_STRING(DEFAULT_RADV),
447 .def = DEFAULT_RADV,
448 .arg = { .r = { .min = MIN_RXABSDELAY,
449 .max = MAX_RXABSDELAY }}
450 };
451
452 if (num_RxAbsIntDelay > bd) {
453 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
454 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
455 adapter);
456 } else {
457 adapter->rx_abs_int_delay = opt.def;
458 }
459 }
460 { /* Interrupt Throttling Rate */
461 struct e1000_option opt = {
462 .type = range_option,
463 .name = "Interrupt Throttling Rate (ints/sec)",
464 .err = "using default of " __MODULE_STRING(DEFAULT_ITR),
465 .def = DEFAULT_ITR,
466 .arg = { .r = { .min = MIN_ITR,
467 .max = MAX_ITR }}
468 };
469
470 if (num_InterruptThrottleRate > bd) {
471 adapter->itr = InterruptThrottleRate[bd];
472 switch(adapter->itr) {
473 case 0:
474 DPRINTK(PROBE, INFO, "%s turned off\n",
475 opt.name);
476 break;
477 case 1:
478 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
479 opt.name);
480 break;
481 case -1:
482 default:
483 e1000_validate_option(&adapter->itr, &opt,
484 adapter);
485 break;
486 }
487 } else {
488 adapter->itr = opt.def;
489 }
490 }
491
492 switch(adapter->hw.media_type) {
493 case e1000_media_type_fiber:
494 case e1000_media_type_internal_serdes:
495 e1000_check_fiber_options(adapter);
496 break;
497 case e1000_media_type_copper:
498 e1000_check_copper_options(adapter);
499 break;
500 default:
501 BUG();
502 }
503}
504
505/**
506 * e1000_check_fiber_options - Range Checking for Link Options, Fiber Version
507 * @adapter: board private structure
508 *
509 * Handles speed and duplex options on fiber adapters
510 **/
511
512static void __devinit
513e1000_check_fiber_options(struct e1000_adapter *adapter)
514{
515 int bd = adapter->bd_number;
516 if(num_Speed > bd) {
517 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
518 "parameter ignored\n");
519 }
520
521 if(num_Duplex > bd) {
522 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
523 "parameter ignored\n");
524 }
525
526 if((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) {
527 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
528 "not valid for fiber adapters, "
529 "parameter ignored\n");
530 }
531}
532
533/**
534 * e1000_check_copper_options - Range Checking for Link Options, Copper Version
535 * @adapter: board private structure
536 *
537 * Handles speed and duplex options on copper adapters
538 **/
539
540static void __devinit
541e1000_check_copper_options(struct e1000_adapter *adapter)
542{
543 int speed, dplx;
544 int bd = adapter->bd_number;
545
546 { /* Speed */
547 struct e1000_opt_list speed_list[] = {{ 0, "" },
548 { SPEED_10, "" },
549 { SPEED_100, "" },
550 { SPEED_1000, "" }};
551
552 struct e1000_option opt = {
553 .type = list_option,
554 .name = "Speed",
555 .err = "parameter ignored",
556 .def = 0,
557 .arg = { .l = { .nr = ARRAY_SIZE(speed_list),
558 .p = speed_list }}
559 };
560
561 if (num_Speed > bd) {
562 speed = Speed[bd];
563 e1000_validate_option(&speed, &opt, adapter);
564 } else {
565 speed = opt.def;
566 }
567 }
568 { /* Duplex */
569 struct e1000_opt_list dplx_list[] = {{ 0, "" },
570 { HALF_DUPLEX, "" },
571 { FULL_DUPLEX, "" }};
572
573 struct e1000_option opt = {
574 .type = list_option,
575 .name = "Duplex",
576 .err = "parameter ignored",
577 .def = 0,
578 .arg = { .l = { .nr = ARRAY_SIZE(dplx_list),
579 .p = dplx_list }}
580 };
581
582 if (num_Duplex > bd) {
583 dplx = Duplex[bd];
584 e1000_validate_option(&dplx, &opt, adapter);
585 } else {
586 dplx = opt.def;
587 }
588 }
589
590 if((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) {
591 DPRINTK(PROBE, INFO,
592 "AutoNeg specified along with Speed or Duplex, "
593 "parameter ignored\n");
594 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
595 } else { /* Autoneg */
596 struct e1000_opt_list an_list[] =
597 #define AA "AutoNeg advertising "
598 {{ 0x01, AA "10/HD" },
599 { 0x02, AA "10/FD" },
600 { 0x03, AA "10/FD, 10/HD" },
601 { 0x04, AA "100/HD" },
602 { 0x05, AA "100/HD, 10/HD" },
603 { 0x06, AA "100/HD, 10/FD" },
604 { 0x07, AA "100/HD, 10/FD, 10/HD" },
605 { 0x08, AA "100/FD" },
606 { 0x09, AA "100/FD, 10/HD" },
607 { 0x0a, AA "100/FD, 10/FD" },
608 { 0x0b, AA "100/FD, 10/FD, 10/HD" },
609 { 0x0c, AA "100/FD, 100/HD" },
610 { 0x0d, AA "100/FD, 100/HD, 10/HD" },
611 { 0x0e, AA "100/FD, 100/HD, 10/FD" },
612 { 0x0f, AA "100/FD, 100/HD, 10/FD, 10/HD" },
613 { 0x20, AA "1000/FD" },
614 { 0x21, AA "1000/FD, 10/HD" },
615 { 0x22, AA "1000/FD, 10/FD" },
616 { 0x23, AA "1000/FD, 10/FD, 10/HD" },
617 { 0x24, AA "1000/FD, 100/HD" },
618 { 0x25, AA "1000/FD, 100/HD, 10/HD" },
619 { 0x26, AA "1000/FD, 100/HD, 10/FD" },
620 { 0x27, AA "1000/FD, 100/HD, 10/FD, 10/HD" },
621 { 0x28, AA "1000/FD, 100/FD" },
622 { 0x29, AA "1000/FD, 100/FD, 10/HD" },
623 { 0x2a, AA "1000/FD, 100/FD, 10/FD" },
624 { 0x2b, AA "1000/FD, 100/FD, 10/FD, 10/HD" },
625 { 0x2c, AA "1000/FD, 100/FD, 100/HD" },
626 { 0x2d, AA "1000/FD, 100/FD, 100/HD, 10/HD" },
627 { 0x2e, AA "1000/FD, 100/FD, 100/HD, 10/FD" },
628 { 0x2f, AA "1000/FD, 100/FD, 100/HD, 10/FD, 10/HD" }};
629
630 struct e1000_option opt = {
631 .type = list_option,
632 .name = "AutoNeg",
633 .err = "parameter ignored",
634 .def = AUTONEG_ADV_DEFAULT,
635 .arg = { .l = { .nr = ARRAY_SIZE(an_list),
636 .p = an_list }}
637 };
638
639 int an = AutoNeg[bd];
640 e1000_validate_option(&an, &opt, adapter);
641 adapter->hw.autoneg_advertised = an;
642 }
643
644 switch (speed + dplx) {
645 case 0:
646 adapter->hw.autoneg = adapter->fc_autoneg = 1;
647 if((num_Speed > bd) && (speed != 0 || dplx != 0))
648 DPRINTK(PROBE, INFO,
649 "Speed and duplex autonegotiation enabled\n");
650 break;
651 case HALF_DUPLEX:
652 DPRINTK(PROBE, INFO, "Half Duplex specified without Speed\n");
653 DPRINTK(PROBE, INFO, "Using Autonegotiation at "
654 "Half Duplex only\n");
655 adapter->hw.autoneg = adapter->fc_autoneg = 1;
656 adapter->hw.autoneg_advertised = ADVERTISE_10_HALF |
657 ADVERTISE_100_HALF;
658 break;
659 case FULL_DUPLEX:
660 DPRINTK(PROBE, INFO, "Full Duplex specified without Speed\n");
661 DPRINTK(PROBE, INFO, "Using Autonegotiation at "
662 "Full Duplex only\n");
663 adapter->hw.autoneg = adapter->fc_autoneg = 1;
664 adapter->hw.autoneg_advertised = ADVERTISE_10_FULL |
665 ADVERTISE_100_FULL |
666 ADVERTISE_1000_FULL;
667 break;
668 case SPEED_10:
669 DPRINTK(PROBE, INFO, "10 Mbps Speed specified "
670 "without Duplex\n");
671 DPRINTK(PROBE, INFO, "Using Autonegotiation at 10 Mbps only\n");
672 adapter->hw.autoneg = adapter->fc_autoneg = 1;
673 adapter->hw.autoneg_advertised = ADVERTISE_10_HALF |
674 ADVERTISE_10_FULL;
675 break;
676 case SPEED_10 + HALF_DUPLEX:
677 DPRINTK(PROBE, INFO, "Forcing to 10 Mbps Half Duplex\n");
678 adapter->hw.autoneg = adapter->fc_autoneg = 0;
679 adapter->hw.forced_speed_duplex = e1000_10_half;
680 adapter->hw.autoneg_advertised = 0;
681 break;
682 case SPEED_10 + FULL_DUPLEX:
683 DPRINTK(PROBE, INFO, "Forcing to 10 Mbps Full Duplex\n");
684 adapter->hw.autoneg = adapter->fc_autoneg = 0;
685 adapter->hw.forced_speed_duplex = e1000_10_full;
686 adapter->hw.autoneg_advertised = 0;
687 break;
688 case SPEED_100:
689 DPRINTK(PROBE, INFO, "100 Mbps Speed specified "
690 "without Duplex\n");
691 DPRINTK(PROBE, INFO, "Using Autonegotiation at "
692 "100 Mbps only\n");
693 adapter->hw.autoneg = adapter->fc_autoneg = 1;
694 adapter->hw.autoneg_advertised = ADVERTISE_100_HALF |
695 ADVERTISE_100_FULL;
696 break;
697 case SPEED_100 + HALF_DUPLEX:
698 DPRINTK(PROBE, INFO, "Forcing to 100 Mbps Half Duplex\n");
699 adapter->hw.autoneg = adapter->fc_autoneg = 0;
700 adapter->hw.forced_speed_duplex = e1000_100_half;
701 adapter->hw.autoneg_advertised = 0;
702 break;
703 case SPEED_100 + FULL_DUPLEX:
704 DPRINTK(PROBE, INFO, "Forcing to 100 Mbps Full Duplex\n");
705 adapter->hw.autoneg = adapter->fc_autoneg = 0;
706 adapter->hw.forced_speed_duplex = e1000_100_full;
707 adapter->hw.autoneg_advertised = 0;
708 break;
709 case SPEED_1000:
710 DPRINTK(PROBE, INFO, "1000 Mbps Speed specified without "
711 "Duplex\n");
712 DPRINTK(PROBE, INFO,
713 "Using Autonegotiation at 1000 Mbps "
714 "Full Duplex only\n");
715 adapter->hw.autoneg = adapter->fc_autoneg = 1;
716 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
717 break;
718 case SPEED_1000 + HALF_DUPLEX:
719 DPRINTK(PROBE, INFO,
720 "Half Duplex is not supported at 1000 Mbps\n");
721 DPRINTK(PROBE, INFO,
722 "Using Autonegotiation at 1000 Mbps "
723 "Full Duplex only\n");
724 adapter->hw.autoneg = adapter->fc_autoneg = 1;
725 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
726 break;
727 case SPEED_1000 + FULL_DUPLEX:
728 DPRINTK(PROBE, INFO,
729 "Using Autonegotiation at 1000 Mbps Full Duplex only\n");
730 adapter->hw.autoneg = adapter->fc_autoneg = 1;
731 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
732 break;
733 default:
734 BUG();
735 }
736
737 /* Speed, AutoNeg and MDI/MDI-X must all play nice */
738 if (e1000_validate_mdi_setting(&(adapter->hw)) < 0) {
739 DPRINTK(PROBE, INFO,
740 "Speed, AutoNeg and MDI-X specifications are "
741 "incompatible. Setting MDI-X to a compatible value.\n");
742 }
743}
744
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 21:30:11 -0500