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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-24 13:15:13 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-24 13:15:13 -0400
commita319a2773a13bab56a0d0b3744ba8703324313b5 (patch)
treef02c86acabd1031439fd422a167784007e84ebb1 /drivers/net/e1000
parente18fa700c9a31360bc8f193aa543b7ef7b39a06b (diff)
parent183798799216fad36c7219fe8d4d6dee6b8fa755 (diff)
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (217 commits) net/ieee80211: fix more crypto-related build breakage [PATCH] Spidernet: add ethtool -S (show statistics) [NET] GT96100: Delete bitrotting ethernet driver [PATCH] mv643xx_eth: restrict to 32-bit PPC_MULTIPLATFORM [PATCH] Cirrus Logic ep93xx ethernet driver r8169: the MMIO region of the 8167 stands behin BAR#1 e1000, ixgb: Remove pointless wrappers [PATCH] Remove powerpc specific parts of 3c509 driver [PATCH] s2io: Switch to pci_get_device [PATCH] gt96100: move to pci_get_device API [PATCH] ehea: bugfix for register access functions [PATCH] e1000 disable device on PCI error drivers/net/phy/fixed: #if 0 some incomplete code drivers/net: const-ify ethtool_ops declarations [PATCH] ethtool: allow const ethtool_ops [PATCH] sky2: big endian [PATCH] sky2: fiber support [PATCH] sky2: tx pause bug fix drivers/net: Trim trailing whitespace [PATCH] ehea: IBM eHEA Ethernet Device Driver ... Manually resolved conflicts in drivers/net/ixgb/ixgb_main.c and drivers/net/sky2.c related to CHECKSUM_HW/CHECKSUM_PARTIAL changes by commit 84fa7933a33f806bbbaae6775e87459b1ec584c0 that just happened to be next to unrelated changes in this update.
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/e1000.h6
-rw-r--r--drivers/net/e1000/e1000_ethtool.c279
-rw-r--r--drivers/net/e1000/e1000_hw.c1167
-rw-r--r--drivers/net/e1000/e1000_hw.h26
-rw-r--r--drivers/net/e1000/e1000_main.c154
-rw-r--r--drivers/net/e1000/e1000_osdep.h19
-rw-r--r--drivers/net/e1000/e1000_param.c161
7 files changed, 951 insertions, 861 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index d304297c496c..98afa9c2057e 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -242,12 +242,10 @@ struct e1000_adapter {
242 struct timer_list watchdog_timer; 242 struct timer_list watchdog_timer;
243 struct timer_list phy_info_timer; 243 struct timer_list phy_info_timer;
244 struct vlan_group *vlgrp; 244 struct vlan_group *vlgrp;
245 uint16_t mng_vlan_id; 245 uint16_t mng_vlan_id;
246 uint32_t bd_number; 246 uint32_t bd_number;
247 uint32_t rx_buffer_len; 247 uint32_t rx_buffer_len;
248 uint32_t part_num;
249 uint32_t wol; 248 uint32_t wol;
250 uint32_t ksp3_port_a;
251 uint32_t smartspeed; 249 uint32_t smartspeed;
252 uint32_t en_mng_pt; 250 uint32_t en_mng_pt;
253 uint16_t link_speed; 251 uint16_t link_speed;
@@ -342,7 +340,9 @@ struct e1000_adapter {
342 boolean_t tso_force; 340 boolean_t tso_force;
343#endif 341#endif
344 boolean_t smart_power_down; /* phy smart power down */ 342 boolean_t smart_power_down; /* phy smart power down */
343 boolean_t quad_port_a;
345 unsigned long flags; 344 unsigned long flags;
345 uint32_t eeprom_wol;
346}; 346};
347 347
348enum e1000_state_t { 348enum e1000_state_t {
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 88a82ba88f57..e39aa1fc4d1e 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -183,6 +183,9 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
183 return -EINVAL; 183 return -EINVAL;
184 } 184 }
185 185
186 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
187 msleep(1);
188
186 if (ecmd->autoneg == AUTONEG_ENABLE) { 189 if (ecmd->autoneg == AUTONEG_ENABLE) {
187 hw->autoneg = 1; 190 hw->autoneg = 1;
188 if (hw->media_type == e1000_media_type_fiber) 191 if (hw->media_type == e1000_media_type_fiber)
@@ -199,16 +202,20 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
199 ADVERTISED_TP; 202 ADVERTISED_TP;
200 ecmd->advertising = hw->autoneg_advertised; 203 ecmd->advertising = hw->autoneg_advertised;
201 } else 204 } else
202 if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) 205 if (e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
206 clear_bit(__E1000_RESETTING, &adapter->flags);
203 return -EINVAL; 207 return -EINVAL;
208 }
204 209
205 /* reset the link */ 210 /* reset the link */
206 211
207 if (netif_running(adapter->netdev)) 212 if (netif_running(adapter->netdev)) {
208 e1000_reinit_locked(adapter); 213 e1000_down(adapter);
209 else 214 e1000_up(adapter);
215 } else
210 e1000_reset(adapter); 216 e1000_reset(adapter);
211 217
218 clear_bit(__E1000_RESETTING, &adapter->flags);
212 return 0; 219 return 0;
213} 220}
214 221
@@ -238,9 +245,13 @@ e1000_set_pauseparam(struct net_device *netdev,
238{ 245{
239 struct e1000_adapter *adapter = netdev_priv(netdev); 246 struct e1000_adapter *adapter = netdev_priv(netdev);
240 struct e1000_hw *hw = &adapter->hw; 247 struct e1000_hw *hw = &adapter->hw;
248 int retval = 0;
241 249
242 adapter->fc_autoneg = pause->autoneg; 250 adapter->fc_autoneg = pause->autoneg;
243 251
252 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
253 msleep(1);
254
244 if (pause->rx_pause && pause->tx_pause) 255 if (pause->rx_pause && pause->tx_pause)
245 hw->fc = e1000_fc_full; 256 hw->fc = e1000_fc_full;
246 else if (pause->rx_pause && !pause->tx_pause) 257 else if (pause->rx_pause && !pause->tx_pause)
@@ -253,15 +264,17 @@ e1000_set_pauseparam(struct net_device *netdev,
253 hw->original_fc = hw->fc; 264 hw->original_fc = hw->fc;
254 265
255 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 266 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
256 if (netif_running(adapter->netdev)) 267 if (netif_running(adapter->netdev)) {
257 e1000_reinit_locked(adapter); 268 e1000_down(adapter);
258 else 269 e1000_up(adapter);
270 } else
259 e1000_reset(adapter); 271 e1000_reset(adapter);
260 } else 272 } else
261 return ((hw->media_type == e1000_media_type_fiber) ? 273 retval = ((hw->media_type == e1000_media_type_fiber) ?
262 e1000_setup_link(hw) : e1000_force_mac_fc(hw)); 274 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
263 275
264 return 0; 276 clear_bit(__E1000_RESETTING, &adapter->flags);
277 return retval;
265} 278}
266 279
267static uint32_t 280static uint32_t
@@ -415,12 +428,12 @@ e1000_get_regs(struct net_device *netdev,
415 regs_buff[23] = regs_buff[18]; /* mdix mode */ 428 regs_buff[23] = regs_buff[18]; /* mdix mode */
416 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0); 429 e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
417 } else { 430 } else {
418 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 431 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
419 regs_buff[13] = (uint32_t)phy_data; /* cable length */ 432 regs_buff[13] = (uint32_t)phy_data; /* cable length */
420 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 433 regs_buff[14] = 0; /* Dummy (to align w/ IGP phy reg dump) */
421 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 434 regs_buff[15] = 0; /* Dummy (to align w/ IGP phy reg dump) */
422 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 435 regs_buff[16] = 0; /* Dummy (to align w/ IGP phy reg dump) */
423 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 436 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
424 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */ 437 regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
425 regs_buff[18] = regs_buff[13]; /* cable polarity */ 438 regs_buff[18] = regs_buff[13]; /* cable polarity */
426 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */ 439 regs_buff[19] = 0; /* Dummy (to align w/ IGP phy reg dump) */
@@ -696,7 +709,6 @@ e1000_set_ringparam(struct net_device *netdev,
696 } 709 }
697 710
698 clear_bit(__E1000_RESETTING, &adapter->flags); 711 clear_bit(__E1000_RESETTING, &adapter->flags);
699
700 return 0; 712 return 0;
701err_setup_tx: 713err_setup_tx:
702 e1000_free_all_rx_resources(adapter); 714 e1000_free_all_rx_resources(adapter);
@@ -881,21 +893,22 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
881 893
882 *data = 0; 894 *data = 0;
883 895
896 /* NOTE: we don't test MSI interrupts here, yet */
884 /* Hook up test interrupt handler just for this test */ 897 /* Hook up test interrupt handler just for this test */
885 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, 898 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED,
886 netdev->name, netdev)) { 899 netdev->name, netdev))
887 shared_int = FALSE; 900 shared_int = FALSE;
888 } else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, 901 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
889 netdev->name, netdev)){ 902 netdev->name, netdev)) {
890 *data = 1; 903 *data = 1;
891 return -1; 904 return -1;
892 } 905 }
893 DPRINTK(PROBE,INFO, "testing %s interrupt\n", 906 DPRINTK(HW, INFO, "testing %s interrupt\n",
894 (shared_int ? "shared" : "unshared")); 907 (shared_int ? "shared" : "unshared"));
895 908
896 /* Disable all the interrupts */ 909 /* Disable all the interrupts */
897 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF); 910 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
898 msec_delay(10); 911 msleep(10);
899 912
900 /* Test each interrupt */ 913 /* Test each interrupt */
901 for (; i < 10; i++) { 914 for (; i < 10; i++) {
@@ -915,7 +928,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
915 adapter->test_icr = 0; 928 adapter->test_icr = 0;
916 E1000_WRITE_REG(&adapter->hw, IMC, mask); 929 E1000_WRITE_REG(&adapter->hw, IMC, mask);
917 E1000_WRITE_REG(&adapter->hw, ICS, mask); 930 E1000_WRITE_REG(&adapter->hw, ICS, mask);
918 msec_delay(10); 931 msleep(10);
919 932
920 if (adapter->test_icr & mask) { 933 if (adapter->test_icr & mask) {
921 *data = 3; 934 *data = 3;
@@ -932,7 +945,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
932 adapter->test_icr = 0; 945 adapter->test_icr = 0;
933 E1000_WRITE_REG(&adapter->hw, IMS, mask); 946 E1000_WRITE_REG(&adapter->hw, IMS, mask);
934 E1000_WRITE_REG(&adapter->hw, ICS, mask); 947 E1000_WRITE_REG(&adapter->hw, ICS, mask);
935 msec_delay(10); 948 msleep(10);
936 949
937 if (!(adapter->test_icr & mask)) { 950 if (!(adapter->test_icr & mask)) {
938 *data = 4; 951 *data = 4;
@@ -949,7 +962,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
949 adapter->test_icr = 0; 962 adapter->test_icr = 0;
950 E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF); 963 E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF);
951 E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF); 964 E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF);
952 msec_delay(10); 965 msleep(10);
953 966
954 if (adapter->test_icr) { 967 if (adapter->test_icr) {
955 *data = 5; 968 *data = 5;
@@ -960,7 +973,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
960 973
961 /* Disable all the interrupts */ 974 /* Disable all the interrupts */
962 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF); 975 E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
963 msec_delay(10); 976 msleep(10);
964 977
965 /* Unhook test interrupt handler */ 978 /* Unhook test interrupt handler */
966 free_irq(irq, netdev); 979 free_irq(irq, netdev);
@@ -1256,11 +1269,10 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1256 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140); 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
1257 /* autoneg off */ 1270 /* autoneg off */
1258 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140); 1271 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
1259 } else if (adapter->hw.phy_type == e1000_phy_gg82563) { 1272 } else if (adapter->hw.phy_type == e1000_phy_gg82563)
1260 e1000_write_phy_reg(&adapter->hw, 1273 e1000_write_phy_reg(&adapter->hw,
1261 GG82563_PHY_KMRN_MODE_CTRL, 1274 GG82563_PHY_KMRN_MODE_CTRL,
1262 0x1CC); 1275 0x1CC);
1263 }
1264 1276
1265 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1277 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1266 1278
@@ -1288,9 +1300,9 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1288 } 1300 }
1289 1301
1290 if (adapter->hw.media_type == e1000_media_type_copper && 1302 if (adapter->hw.media_type == e1000_media_type_copper &&
1291 adapter->hw.phy_type == e1000_phy_m88) { 1303 adapter->hw.phy_type == e1000_phy_m88)
1292 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1304 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1293 } else { 1305 else {
1294 /* Set the ILOS bit on the fiber Nic is half 1306 /* Set the ILOS bit on the fiber Nic is half
1295 * duplex link is detected. */ 1307 * duplex link is detected. */
1296 stat_reg = E1000_READ_REG(&adapter->hw, STATUS); 1308 stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
@@ -1383,7 +1395,7 @@ e1000_setup_loopback_test(struct e1000_adapter *adapter)
1383#define E1000_SERDES_LB_ON 0x410 1395#define E1000_SERDES_LB_ON 0x410
1384 e1000_set_phy_loopback(adapter); 1396 e1000_set_phy_loopback(adapter);
1385 E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_ON); 1397 E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_ON);
1386 msec_delay(10); 1398 msleep(10);
1387 return 0; 1399 return 0;
1388 break; 1400 break;
1389 default: 1401 default:
@@ -1416,7 +1428,7 @@ e1000_loopback_cleanup(struct e1000_adapter *adapter)
1416 hw->media_type == e1000_media_type_internal_serdes) { 1428 hw->media_type == e1000_media_type_internal_serdes) {
1417#define E1000_SERDES_LB_OFF 0x400 1429#define E1000_SERDES_LB_OFF 0x400
1418 E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_OFF); 1430 E1000_WRITE_REG(hw, SCTL, E1000_SERDES_LB_OFF);
1419 msec_delay(10); 1431 msleep(10);
1420 break; 1432 break;
1421 } 1433 }
1422 /* Fall Through */ 1434 /* Fall Through */
@@ -1426,11 +1438,10 @@ e1000_loopback_cleanup(struct e1000_adapter *adapter)
1426 case e1000_82546_rev_3: 1438 case e1000_82546_rev_3:
1427 default: 1439 default:
1428 hw->autoneg = TRUE; 1440 hw->autoneg = TRUE;
1429 if (hw->phy_type == e1000_phy_gg82563) { 1441 if (hw->phy_type == e1000_phy_gg82563)
1430 e1000_write_phy_reg(hw, 1442 e1000_write_phy_reg(hw,
1431 GG82563_PHY_KMRN_MODE_CTRL, 1443 GG82563_PHY_KMRN_MODE_CTRL,
1432 0x180); 1444 0x180);
1433 }
1434 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); 1445 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
1435 if (phy_reg & MII_CR_LOOPBACK) { 1446 if (phy_reg & MII_CR_LOOPBACK) {
1436 phy_reg &= ~MII_CR_LOOPBACK; 1447 phy_reg &= ~MII_CR_LOOPBACK;
@@ -1497,7 +1508,7 @@ e1000_run_loopback_test(struct e1000_adapter *adapter)
1497 if (unlikely(++k == txdr->count)) k = 0; 1508 if (unlikely(++k == txdr->count)) k = 0;
1498 } 1509 }
1499 E1000_WRITE_REG(&adapter->hw, TDT, k); 1510 E1000_WRITE_REG(&adapter->hw, TDT, k);
1500 msec_delay(200); 1511 msleep(200);
1501 time = jiffies; /* set the start time for the receive */ 1512 time = jiffies; /* set the start time for the receive */
1502 good_cnt = 0; 1513 good_cnt = 0;
1503 do { /* receive the sent packets */ 1514 do { /* receive the sent packets */
@@ -1568,14 +1579,14 @@ e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
1568 e1000_check_for_link(&adapter->hw); 1579 e1000_check_for_link(&adapter->hw);
1569 if (adapter->hw.serdes_link_down == FALSE) 1580 if (adapter->hw.serdes_link_down == FALSE)
1570 return *data; 1581 return *data;
1571 msec_delay(20); 1582 msleep(20);
1572 } while (i++ < 3750); 1583 } while (i++ < 3750);
1573 1584
1574 *data = 1; 1585 *data = 1;
1575 } else { 1586 } else {
1576 e1000_check_for_link(&adapter->hw); 1587 e1000_check_for_link(&adapter->hw);
1577 if (adapter->hw.autoneg) /* if auto_neg is set wait for it */ 1588 if (adapter->hw.autoneg) /* if auto_neg is set wait for it */
1578 msec_delay(4000); 1589 msleep(4000);
1579 1590
1580 if (!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { 1591 if (!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
1581 *data = 1; 1592 *data = 1;
@@ -1590,6 +1601,8 @@ e1000_diag_test_count(struct net_device *netdev)
1590 return E1000_TEST_LEN; 1601 return E1000_TEST_LEN;
1591} 1602}
1592 1603
1604extern void e1000_power_up_phy(struct e1000_adapter *);
1605
1593static void 1606static void
1594e1000_diag_test(struct net_device *netdev, 1607e1000_diag_test(struct net_device *netdev,
1595 struct ethtool_test *eth_test, uint64_t *data) 1608 struct ethtool_test *eth_test, uint64_t *data)
@@ -1606,6 +1619,8 @@ e1000_diag_test(struct net_device *netdev,
1606 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex; 1619 uint8_t forced_speed_duplex = adapter->hw.forced_speed_duplex;
1607 uint8_t autoneg = adapter->hw.autoneg; 1620 uint8_t autoneg = adapter->hw.autoneg;
1608 1621
1622 DPRINTK(HW, INFO, "offline testing starting\n");
1623
1609 /* Link test performed before hardware reset so autoneg doesn't 1624 /* Link test performed before hardware reset so autoneg doesn't
1610 * interfere with test result */ 1625 * interfere with test result */
1611 if (e1000_link_test(adapter, &data[4])) 1626 if (e1000_link_test(adapter, &data[4]))
@@ -1629,6 +1644,8 @@ e1000_diag_test(struct net_device *netdev,
1629 eth_test->flags |= ETH_TEST_FL_FAILED; 1644 eth_test->flags |= ETH_TEST_FL_FAILED;
1630 1645
1631 e1000_reset(adapter); 1646 e1000_reset(adapter);
1647 /* make sure the phy is powered up */
1648 e1000_power_up_phy(adapter);
1632 if (e1000_loopback_test(adapter, &data[3])) 1649 if (e1000_loopback_test(adapter, &data[3]))
1633 eth_test->flags |= ETH_TEST_FL_FAILED; 1650 eth_test->flags |= ETH_TEST_FL_FAILED;
1634 1651
@@ -1642,6 +1659,7 @@ e1000_diag_test(struct net_device *netdev,
1642 if (if_running) 1659 if (if_running)
1643 dev_open(netdev); 1660 dev_open(netdev);
1644 } else { 1661 } else {
1662 DPRINTK(HW, INFO, "online testing starting\n");
1645 /* Online tests */ 1663 /* Online tests */
1646 if (e1000_link_test(adapter, &data[4])) 1664 if (e1000_link_test(adapter, &data[4]))
1647 eth_test->flags |= ETH_TEST_FL_FAILED; 1665 eth_test->flags |= ETH_TEST_FL_FAILED;
@@ -1657,14 +1675,12 @@ e1000_diag_test(struct net_device *netdev,
1657 msleep_interruptible(4 * 1000); 1675 msleep_interruptible(4 * 1000);
1658} 1676}
1659 1677
1660static void 1678static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
1661e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1662{ 1679{
1663 struct e1000_adapter *adapter = netdev_priv(netdev);
1664 struct e1000_hw *hw = &adapter->hw; 1680 struct e1000_hw *hw = &adapter->hw;
1681 int retval = 1; /* fail by default */
1665 1682
1666 switch (adapter->hw.device_id) { 1683 switch (hw->device_id) {
1667 case E1000_DEV_ID_82542:
1668 case E1000_DEV_ID_82543GC_FIBER: 1684 case E1000_DEV_ID_82543GC_FIBER:
1669 case E1000_DEV_ID_82543GC_COPPER: 1685 case E1000_DEV_ID_82543GC_COPPER:
1670 case E1000_DEV_ID_82544EI_FIBER: 1686 case E1000_DEV_ID_82544EI_FIBER:
@@ -1672,52 +1688,87 @@ e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1672 case E1000_DEV_ID_82545EM_FIBER: 1688 case E1000_DEV_ID_82545EM_FIBER:
1673 case E1000_DEV_ID_82545EM_COPPER: 1689 case E1000_DEV_ID_82545EM_COPPER:
1674 case E1000_DEV_ID_82546GB_QUAD_COPPER: 1690 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1691 case E1000_DEV_ID_82546GB_PCIE:
1692 /* these don't support WoL at all */
1675 wol->supported = 0; 1693 wol->supported = 0;
1676 wol->wolopts = 0; 1694 break;
1677 return;
1678
1679 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1680 /* device id 10B5 port-A supports wol */
1681 if (!adapter->ksp3_port_a) {
1682 wol->supported = 0;
1683 return;
1684 }
1685 /* KSP3 does not suppport UCAST wake-ups for any interface */
1686 wol->supported = WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
1687
1688 if (adapter->wol & E1000_WUFC_EX)
1689 DPRINTK(DRV, ERR, "Interface does not support "
1690 "directed (unicast) frame wake-up packets\n");
1691 wol->wolopts = 0;
1692 goto do_defaults;
1693
1694 case E1000_DEV_ID_82546EB_FIBER: 1695 case E1000_DEV_ID_82546EB_FIBER:
1695 case E1000_DEV_ID_82546GB_FIBER: 1696 case E1000_DEV_ID_82546GB_FIBER:
1696 case E1000_DEV_ID_82571EB_FIBER: 1697 case E1000_DEV_ID_82571EB_FIBER:
1697 /* Wake events only supported on port A for dual fiber */ 1698 case E1000_DEV_ID_82571EB_SERDES:
1699 case E1000_DEV_ID_82571EB_COPPER:
1700 /* Wake events not supported on port B */
1698 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) { 1701 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
1699 wol->supported = 0; 1702 wol->supported = 0;
1700 wol->wolopts = 0; 1703 break;
1701 return;
1702 } 1704 }
1703 /* Fall Through */ 1705 /* return success for non excluded adapter ports */
1704 1706 retval = 0;
1707 break;
1708 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1709 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1710 /* quad port adapters only support WoL on port A */
1711 if (!adapter->quad_port_a) {
1712 wol->supported = 0;
1713 break;
1714 }
1715 /* return success for non excluded adapter ports */
1716 retval = 0;
1717 break;
1705 default: 1718 default:
1706 wol->supported = WAKE_UCAST | WAKE_MCAST | 1719 /* dual port cards only support WoL on port A from now on
1707 WAKE_BCAST | WAKE_MAGIC; 1720 * unless it was enabled in the eeprom for port B
1708 wol->wolopts = 0; 1721 * so exclude FUNC_1 ports from having WoL enabled */
1722 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1 &&
1723 !adapter->eeprom_wol) {
1724 wol->supported = 0;
1725 break;
1726 }
1709 1727
1710do_defaults: 1728 retval = 0;
1711 if (adapter->wol & E1000_WUFC_EX) 1729 }
1712 wol->wolopts |= WAKE_UCAST; 1730
1713 if (adapter->wol & E1000_WUFC_MC) 1731 return retval;
1714 wol->wolopts |= WAKE_MCAST; 1732}
1715 if (adapter->wol & E1000_WUFC_BC) 1733
1716 wol->wolopts |= WAKE_BCAST; 1734static void
1717 if (adapter->wol & E1000_WUFC_MAG) 1735e1000_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1718 wol->wolopts |= WAKE_MAGIC; 1736{
1737 struct e1000_adapter *adapter = netdev_priv(netdev);
1738
1739 wol->supported = WAKE_UCAST | WAKE_MCAST |
1740 WAKE_BCAST | WAKE_MAGIC;
1741 wol->wolopts = 0;
1742
1743 /* this function will set ->supported = 0 and return 1 if wol is not
1744 * supported by this hardware */
1745 if (e1000_wol_exclusion(adapter, wol))
1719 return; 1746 return;
1747
1748 /* apply any specific unsupported masks here */
1749 switch (adapter->hw.device_id) {
1750 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1751 /* KSP3 does not suppport UCAST wake-ups */
1752 wol->supported &= ~WAKE_UCAST;
1753
1754 if (adapter->wol & E1000_WUFC_EX)
1755 DPRINTK(DRV, ERR, "Interface does not support "
1756 "directed (unicast) frame wake-up packets\n");
1757 break;
1758 default:
1759 break;
1720 } 1760 }
1761
1762 if (adapter->wol & E1000_WUFC_EX)
1763 wol->wolopts |= WAKE_UCAST;
1764 if (adapter->wol & E1000_WUFC_MC)
1765 wol->wolopts |= WAKE_MCAST;
1766 if (adapter->wol & E1000_WUFC_BC)
1767 wol->wolopts |= WAKE_BCAST;
1768 if (adapter->wol & E1000_WUFC_MAG)
1769 wol->wolopts |= WAKE_MAGIC;
1770
1771 return;
1721} 1772}
1722 1773
1723static int 1774static int
@@ -1726,51 +1777,35 @@ e1000_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1726 struct e1000_adapter *adapter = netdev_priv(netdev); 1777 struct e1000_adapter *adapter = netdev_priv(netdev);
1727 struct e1000_hw *hw = &adapter->hw; 1778 struct e1000_hw *hw = &adapter->hw;
1728 1779
1729 switch (adapter->hw.device_id) { 1780 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1730 case E1000_DEV_ID_82542: 1781 return -EOPNOTSUPP;
1731 case E1000_DEV_ID_82543GC_FIBER: 1782
1732 case E1000_DEV_ID_82543GC_COPPER: 1783 if (e1000_wol_exclusion(adapter, wol))
1733 case E1000_DEV_ID_82544EI_FIBER:
1734 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1735 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1736 case E1000_DEV_ID_82545EM_FIBER:
1737 case E1000_DEV_ID_82545EM_COPPER:
1738 return wol->wolopts ? -EOPNOTSUPP : 0; 1784 return wol->wolopts ? -EOPNOTSUPP : 0;
1739 1785
1786 switch (hw->device_id) {
1740 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1787 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1741 /* device id 10B5 port-A supports wol */
1742 if (!adapter->ksp3_port_a)
1743 return wol->wolopts ? -EOPNOTSUPP : 0;
1744
1745 if (wol->wolopts & WAKE_UCAST) { 1788 if (wol->wolopts & WAKE_UCAST) {
1746 DPRINTK(DRV, ERR, "Interface does not support " 1789 DPRINTK(DRV, ERR, "Interface does not support "
1747 "directed (unicast) frame wake-up packets\n"); 1790 "directed (unicast) frame wake-up packets\n");
1748 return -EOPNOTSUPP; 1791 return -EOPNOTSUPP;
1749 } 1792 }
1750 1793 break;
1751 case E1000_DEV_ID_82546EB_FIBER:
1752 case E1000_DEV_ID_82546GB_FIBER:
1753 case E1000_DEV_ID_82571EB_FIBER:
1754 /* Wake events only supported on port A for dual fiber */
1755 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1756 return wol->wolopts ? -EOPNOTSUPP : 0;
1757 /* Fall Through */
1758
1759 default: 1794 default:
1760 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) 1795 break;
1761 return -EOPNOTSUPP; 1796 }
1762 1797
1763 adapter->wol = 0; 1798 /* these settings will always override what we currently have */
1799 adapter->wol = 0;
1764 1800
1765 if (wol->wolopts & WAKE_UCAST) 1801 if (wol->wolopts & WAKE_UCAST)
1766 adapter->wol |= E1000_WUFC_EX; 1802 adapter->wol |= E1000_WUFC_EX;
1767 if (wol->wolopts & WAKE_MCAST) 1803 if (wol->wolopts & WAKE_MCAST)
1768 adapter->wol |= E1000_WUFC_MC; 1804 adapter->wol |= E1000_WUFC_MC;
1769 if (wol->wolopts & WAKE_BCAST) 1805 if (wol->wolopts & WAKE_BCAST)
1770 adapter->wol |= E1000_WUFC_BC; 1806 adapter->wol |= E1000_WUFC_BC;
1771 if (wol->wolopts & WAKE_MAGIC) 1807 if (wol->wolopts & WAKE_MAGIC)
1772 adapter->wol |= E1000_WUFC_MAG; 1808 adapter->wol |= E1000_WUFC_MAG;
1773 }
1774 1809
1775 return 0; 1810 return 0;
1776} 1811}
@@ -1887,7 +1922,7 @@ e1000_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
1887 } 1922 }
1888} 1923}
1889 1924
1890static struct ethtool_ops e1000_ethtool_ops = { 1925static const struct ethtool_ops e1000_ethtool_ops = {
1891 .get_settings = e1000_get_settings, 1926 .get_settings = e1000_get_settings,
1892 .set_settings = e1000_set_settings, 1927 .set_settings = e1000_set_settings,
1893 .get_drvinfo = e1000_get_drvinfo, 1928 .get_drvinfo = e1000_get_drvinfo,
@@ -1895,8 +1930,8 @@ static struct ethtool_ops e1000_ethtool_ops = {
1895 .get_regs = e1000_get_regs, 1930 .get_regs = e1000_get_regs,
1896 .get_wol = e1000_get_wol, 1931 .get_wol = e1000_get_wol,
1897 .set_wol = e1000_set_wol, 1932 .set_wol = e1000_set_wol,
1898 .get_msglevel = e1000_get_msglevel, 1933 .get_msglevel = e1000_get_msglevel,
1899 .set_msglevel = e1000_set_msglevel, 1934 .set_msglevel = e1000_set_msglevel,
1900 .nway_reset = e1000_nway_reset, 1935 .nway_reset = e1000_nway_reset,
1901 .get_link = ethtool_op_get_link, 1936 .get_link = ethtool_op_get_link,
1902 .get_eeprom_len = e1000_get_eeprom_len, 1937 .get_eeprom_len = e1000_get_eeprom_len,
@@ -1904,17 +1939,17 @@ static struct ethtool_ops e1000_ethtool_ops = {
1904 .set_eeprom = e1000_set_eeprom, 1939 .set_eeprom = e1000_set_eeprom,
1905 .get_ringparam = e1000_get_ringparam, 1940 .get_ringparam = e1000_get_ringparam,
1906 .set_ringparam = e1000_set_ringparam, 1941 .set_ringparam = e1000_set_ringparam,
1907 .get_pauseparam = e1000_get_pauseparam, 1942 .get_pauseparam = e1000_get_pauseparam,
1908 .set_pauseparam = e1000_set_pauseparam, 1943 .set_pauseparam = e1000_set_pauseparam,
1909 .get_rx_csum = e1000_get_rx_csum, 1944 .get_rx_csum = e1000_get_rx_csum,
1910 .set_rx_csum = e1000_set_rx_csum, 1945 .set_rx_csum = e1000_set_rx_csum,
1911 .get_tx_csum = e1000_get_tx_csum, 1946 .get_tx_csum = e1000_get_tx_csum,
1912 .set_tx_csum = e1000_set_tx_csum, 1947 .set_tx_csum = e1000_set_tx_csum,
1913 .get_sg = ethtool_op_get_sg, 1948 .get_sg = ethtool_op_get_sg,
1914 .set_sg = ethtool_op_set_sg, 1949 .set_sg = ethtool_op_set_sg,
1915#ifdef NETIF_F_TSO 1950#ifdef NETIF_F_TSO
1916 .get_tso = ethtool_op_get_tso, 1951 .get_tso = ethtool_op_get_tso,
1917 .set_tso = e1000_set_tso, 1952 .set_tso = e1000_set_tso,
1918#endif 1953#endif
1919 .self_test_count = e1000_diag_test_count, 1954 .self_test_count = e1000_diag_test_count,
1920 .self_test = e1000_diag_test, 1955 .self_test = e1000_diag_test,
@@ -1922,7 +1957,7 @@ static struct ethtool_ops e1000_ethtool_ops = {
1922 .phys_id = e1000_phys_id, 1957 .phys_id = e1000_phys_id,
1923 .get_stats_count = e1000_get_stats_count, 1958 .get_stats_count = e1000_get_stats_count,
1924 .get_ethtool_stats = e1000_get_ethtool_stats, 1959 .get_ethtool_stats = e1000_get_ethtool_stats,
1925 .get_perm_addr = ethtool_op_get_perm_addr, 1960 .get_perm_addr = ethtool_op_get_perm_addr,
1926}; 1961};
1927 1962
1928void e1000_set_ethtool_ops(struct net_device *netdev) 1963void e1000_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index b3b919116e0f..10b8c8c25325 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -31,6 +31,7 @@
31 * Shared functions for accessing and configuring the MAC 31 * Shared functions for accessing and configuring the MAC
32 */ 32 */
33 33
34
34#include "e1000_hw.h" 35#include "e1000_hw.h"
35 36
36static int32_t e1000_set_phy_type(struct e1000_hw *hw); 37static int32_t e1000_set_phy_type(struct e1000_hw *hw);
@@ -166,10 +167,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
166{ 167{
167 DEBUGFUNC("e1000_set_phy_type"); 168 DEBUGFUNC("e1000_set_phy_type");
168 169
169 if(hw->mac_type == e1000_undefined) 170 if (hw->mac_type == e1000_undefined)
170 return -E1000_ERR_PHY_TYPE; 171 return -E1000_ERR_PHY_TYPE;
171 172
172 switch(hw->phy_id) { 173 switch (hw->phy_id) {
173 case M88E1000_E_PHY_ID: 174 case M88E1000_E_PHY_ID:
174 case M88E1000_I_PHY_ID: 175 case M88E1000_I_PHY_ID:
175 case M88E1011_I_PHY_ID: 176 case M88E1011_I_PHY_ID:
@@ -177,10 +178,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
177 hw->phy_type = e1000_phy_m88; 178 hw->phy_type = e1000_phy_m88;
178 break; 179 break;
179 case IGP01E1000_I_PHY_ID: 180 case IGP01E1000_I_PHY_ID:
180 if(hw->mac_type == e1000_82541 || 181 if (hw->mac_type == e1000_82541 ||
181 hw->mac_type == e1000_82541_rev_2 || 182 hw->mac_type == e1000_82541_rev_2 ||
182 hw->mac_type == e1000_82547 || 183 hw->mac_type == e1000_82547 ||
183 hw->mac_type == e1000_82547_rev_2) { 184 hw->mac_type == e1000_82547_rev_2) {
184 hw->phy_type = e1000_phy_igp; 185 hw->phy_type = e1000_phy_igp;
185 break; 186 break;
186 } 187 }
@@ -207,6 +208,7 @@ e1000_set_phy_type(struct e1000_hw *hw)
207 return E1000_SUCCESS; 208 return E1000_SUCCESS;
208} 209}
209 210
211
210/****************************************************************************** 212/******************************************************************************
211 * IGP phy init script - initializes the GbE PHY 213 * IGP phy init script - initializes the GbE PHY
212 * 214 *
@@ -220,8 +222,8 @@ e1000_phy_init_script(struct e1000_hw *hw)
220 222
221 DEBUGFUNC("e1000_phy_init_script"); 223 DEBUGFUNC("e1000_phy_init_script");
222 224
223 if(hw->phy_init_script) { 225 if (hw->phy_init_script) {
224 msec_delay(20); 226 msleep(20);
225 227
226 /* Save off the current value of register 0x2F5B to be restored at 228 /* Save off the current value of register 0x2F5B to be restored at
227 * the end of this routine. */ 229 * the end of this routine. */
@@ -230,13 +232,13 @@ e1000_phy_init_script(struct e1000_hw *hw)
230 /* Disabled the PHY transmitter */ 232 /* Disabled the PHY transmitter */
231 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 233 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
232 234
233 msec_delay(20); 235 msleep(20);
234 236
235 e1000_write_phy_reg(hw,0x0000,0x0140); 237 e1000_write_phy_reg(hw,0x0000,0x0140);
236 238
237 msec_delay(5); 239 msleep(5);
238 240
239 switch(hw->mac_type) { 241 switch (hw->mac_type) {
240 case e1000_82541: 242 case e1000_82541:
241 case e1000_82547: 243 case e1000_82547:
242 e1000_write_phy_reg(hw, 0x1F95, 0x0001); 244 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
@@ -268,27 +270,27 @@ e1000_phy_init_script(struct e1000_hw *hw)
268 270
269 e1000_write_phy_reg(hw, 0x0000, 0x3300); 271 e1000_write_phy_reg(hw, 0x0000, 0x3300);
270 272
271 msec_delay(20); 273 msleep(20);
272 274
273 /* Now enable the transmitter */ 275 /* Now enable the transmitter */
274 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 276 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
275 277
276 if(hw->mac_type == e1000_82547) { 278 if (hw->mac_type == e1000_82547) {
277 uint16_t fused, fine, coarse; 279 uint16_t fused, fine, coarse;
278 280
279 /* Move to analog registers page */ 281 /* Move to analog registers page */
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 282 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
281 283
282 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 284 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
283 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); 285 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
284 286
285 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 287 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
286 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 288 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
287 289
288 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 290 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
289 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 291 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
290 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 292 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
291 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 293 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
292 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 294 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
293 295
294 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 296 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
@@ -387,6 +389,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
387 case E1000_DEV_ID_82571EB_COPPER: 389 case E1000_DEV_ID_82571EB_COPPER:
388 case E1000_DEV_ID_82571EB_FIBER: 390 case E1000_DEV_ID_82571EB_FIBER:
389 case E1000_DEV_ID_82571EB_SERDES: 391 case E1000_DEV_ID_82571EB_SERDES:
392 case E1000_DEV_ID_82571EB_QUAD_COPPER:
390 hw->mac_type = e1000_82571; 393 hw->mac_type = e1000_82571;
391 break; 394 break;
392 case E1000_DEV_ID_82572EI_COPPER: 395 case E1000_DEV_ID_82572EI_COPPER:
@@ -418,7 +421,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
418 return -E1000_ERR_MAC_TYPE; 421 return -E1000_ERR_MAC_TYPE;
419 } 422 }
420 423
421 switch(hw->mac_type) { 424 switch (hw->mac_type) {
422 case e1000_ich8lan: 425 case e1000_ich8lan:
423 hw->swfwhw_semaphore_present = TRUE; 426 hw->swfwhw_semaphore_present = TRUE;
424 hw->asf_firmware_present = TRUE; 427 hw->asf_firmware_present = TRUE;
@@ -456,7 +459,7 @@ e1000_set_media_type(struct e1000_hw *hw)
456 459
457 DEBUGFUNC("e1000_set_media_type"); 460 DEBUGFUNC("e1000_set_media_type");
458 461
459 if(hw->mac_type != e1000_82543) { 462 if (hw->mac_type != e1000_82543) {
460 /* tbi_compatibility is only valid on 82543 */ 463 /* tbi_compatibility is only valid on 82543 */
461 hw->tbi_compatibility_en = FALSE; 464 hw->tbi_compatibility_en = FALSE;
462 } 465 }
@@ -516,16 +519,16 @@ e1000_reset_hw(struct e1000_hw *hw)
516 DEBUGFUNC("e1000_reset_hw"); 519 DEBUGFUNC("e1000_reset_hw");
517 520
518 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 521 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
519 if(hw->mac_type == e1000_82542_rev2_0) { 522 if (hw->mac_type == e1000_82542_rev2_0) {
520 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 523 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
521 e1000_pci_clear_mwi(hw); 524 e1000_pci_clear_mwi(hw);
522 } 525 }
523 526
524 if(hw->bus_type == e1000_bus_type_pci_express) { 527 if (hw->bus_type == e1000_bus_type_pci_express) {
525 /* Prevent the PCI-E bus from sticking if there is no TLP connection 528 /* Prevent the PCI-E bus from sticking if there is no TLP connection
526 * on the last TLP read/write transaction when MAC is reset. 529 * on the last TLP read/write transaction when MAC is reset.
527 */ 530 */
528 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { 531 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
529 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 532 DEBUGOUT("PCI-E Master disable polling has failed.\n");
530 } 533 }
531 } 534 }
@@ -548,19 +551,19 @@ e1000_reset_hw(struct e1000_hw *hw)
548 /* Delay to allow any outstanding PCI transactions to complete before 551 /* Delay to allow any outstanding PCI transactions to complete before
549 * resetting the device 552 * resetting the device
550 */ 553 */
551 msec_delay(10); 554 msleep(10);
552 555
553 ctrl = E1000_READ_REG(hw, CTRL); 556 ctrl = E1000_READ_REG(hw, CTRL);
554 557
555 /* Must reset the PHY before resetting the MAC */ 558 /* Must reset the PHY before resetting the MAC */
556 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 559 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
557 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 560 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
558 msec_delay(5); 561 msleep(5);
559 } 562 }
560 563
561 /* Must acquire the MDIO ownership before MAC reset. 564 /* Must acquire the MDIO ownership before MAC reset.
562 * Ownership defaults to firmware after a reset. */ 565 * Ownership defaults to firmware after a reset. */
563 if(hw->mac_type == e1000_82573) { 566 if (hw->mac_type == e1000_82573) {
564 timeout = 10; 567 timeout = 10;
565 568
566 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
@@ -570,14 +573,14 @@ e1000_reset_hw(struct e1000_hw *hw)
570 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 573 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
571 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 574 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
572 575
573 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 576 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
574 break; 577 break;
575 else 578 else
576 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 579 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
577 580
578 msec_delay(2); 581 msleep(2);
579 timeout--; 582 timeout--;
580 } while(timeout); 583 } while (timeout);
581 } 584 }
582 585
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 586 /* Workaround for ICH8 bit corruption issue in FIFO memory */
@@ -595,7 +598,7 @@ e1000_reset_hw(struct e1000_hw *hw)
595 */ 598 */
596 DEBUGOUT("Issuing a global reset to MAC\n"); 599 DEBUGOUT("Issuing a global reset to MAC\n");
597 600
598 switch(hw->mac_type) { 601 switch (hw->mac_type) {
599 case e1000_82544: 602 case e1000_82544:
600 case e1000_82540: 603 case e1000_82540:
601 case e1000_82545: 604 case e1000_82545:
@@ -623,7 +626,7 @@ e1000_reset_hw(struct e1000_hw *hw)
623 626
624 e1000_get_software_flag(hw); 627 e1000_get_software_flag(hw);
625 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 628 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
626 msec_delay(5); 629 msleep(5);
627 break; 630 break;
628 default: 631 default:
629 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 632 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
@@ -634,7 +637,7 @@ e1000_reset_hw(struct e1000_hw *hw)
634 * device. Later controllers reload the EEPROM automatically, so just wait 637 * device. Later controllers reload the EEPROM automatically, so just wait
635 * for reload to complete. 638 * for reload to complete.
636 */ 639 */
637 switch(hw->mac_type) { 640 switch (hw->mac_type) {
638 case e1000_82542_rev2_0: 641 case e1000_82542_rev2_0:
639 case e1000_82542_rev2_1: 642 case e1000_82542_rev2_1:
640 case e1000_82543: 643 case e1000_82543:
@@ -646,14 +649,14 @@ e1000_reset_hw(struct e1000_hw *hw)
646 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 649 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
647 E1000_WRITE_FLUSH(hw); 650 E1000_WRITE_FLUSH(hw);
648 /* Wait for EEPROM reload */ 651 /* Wait for EEPROM reload */
649 msec_delay(2); 652 msleep(2);
650 break; 653 break;
651 case e1000_82541: 654 case e1000_82541:
652 case e1000_82541_rev_2: 655 case e1000_82541_rev_2:
653 case e1000_82547: 656 case e1000_82547:
654 case e1000_82547_rev_2: 657 case e1000_82547_rev_2:
655 /* Wait for EEPROM reload */ 658 /* Wait for EEPROM reload */
656 msec_delay(20); 659 msleep(20);
657 break; 660 break;
658 case e1000_82573: 661 case e1000_82573:
659 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 662 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
@@ -669,24 +672,24 @@ e1000_reset_hw(struct e1000_hw *hw)
669 case e1000_ich8lan: 672 case e1000_ich8lan:
670 case e1000_80003es2lan: 673 case e1000_80003es2lan:
671 ret_val = e1000_get_auto_rd_done(hw); 674 ret_val = e1000_get_auto_rd_done(hw);
672 if(ret_val) 675 if (ret_val)
673 /* We don't want to continue accessing MAC registers. */ 676 /* We don't want to continue accessing MAC registers. */
674 return ret_val; 677 return ret_val;
675 break; 678 break;
676 default: 679 default:
677 /* Wait for EEPROM reload (it happens automatically) */ 680 /* Wait for EEPROM reload (it happens automatically) */
678 msec_delay(5); 681 msleep(5);
679 break; 682 break;
680 } 683 }
681 684
682 /* Disable HW ARPs on ASF enabled adapters */ 685 /* Disable HW ARPs on ASF enabled adapters */
683 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 686 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
684 manc = E1000_READ_REG(hw, MANC); 687 manc = E1000_READ_REG(hw, MANC);
685 manc &= ~(E1000_MANC_ARP_EN); 688 manc &= ~(E1000_MANC_ARP_EN);
686 E1000_WRITE_REG(hw, MANC, manc); 689 E1000_WRITE_REG(hw, MANC, manc);
687 } 690 }
688 691
689 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 692 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
690 e1000_phy_init_script(hw); 693 e1000_phy_init_script(hw);
691 694
692 /* Configure activity LED after PHY reset */ 695 /* Configure activity LED after PHY reset */
@@ -704,8 +707,8 @@ e1000_reset_hw(struct e1000_hw *hw)
704 icr = E1000_READ_REG(hw, ICR); 707 icr = E1000_READ_REG(hw, ICR);
705 708
706 /* If MWI was previously enabled, reenable it. */ 709 /* If MWI was previously enabled, reenable it. */
707 if(hw->mac_type == e1000_82542_rev2_0) { 710 if (hw->mac_type == e1000_82542_rev2_0) {
708 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 711 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
709 e1000_pci_set_mwi(hw); 712 e1000_pci_set_mwi(hw);
710 } 713 }
711 714
@@ -745,9 +748,20 @@ e1000_init_hw(struct e1000_hw *hw)
745 748
746 DEBUGFUNC("e1000_init_hw"); 749 DEBUGFUNC("e1000_init_hw");
747 750
751 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
752 if (hw->mac_type == e1000_ich8lan) {
753 reg_data = E1000_READ_REG(hw, TARC0);
754 reg_data |= 0x30000000;
755 E1000_WRITE_REG(hw, TARC0, reg_data);
756
757 reg_data = E1000_READ_REG(hw, STATUS);
758 reg_data &= ~0x80000000;
759 E1000_WRITE_REG(hw, STATUS, reg_data);
760 }
761
748 /* Initialize Identification LED */ 762 /* Initialize Identification LED */
749 ret_val = e1000_id_led_init(hw); 763 ret_val = e1000_id_led_init(hw);
750 if(ret_val) { 764 if (ret_val) {
751 DEBUGOUT("Error Initializing Identification LED\n"); 765 DEBUGOUT("Error Initializing Identification LED\n");
752 return ret_val; 766 return ret_val;
753 } 767 }
@@ -765,12 +779,12 @@ e1000_init_hw(struct e1000_hw *hw)
765 } 779 }
766 780
767 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 781 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
768 if(hw->mac_type == e1000_82542_rev2_0) { 782 if (hw->mac_type == e1000_82542_rev2_0) {
769 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 783 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
770 e1000_pci_clear_mwi(hw); 784 e1000_pci_clear_mwi(hw);
771 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 785 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
772 E1000_WRITE_FLUSH(hw); 786 E1000_WRITE_FLUSH(hw);
773 msec_delay(5); 787 msleep(5);
774 } 788 }
775 789
776 /* Setup the receive address. This involves initializing all of the Receive 790 /* Setup the receive address. This involves initializing all of the Receive
@@ -779,11 +793,11 @@ e1000_init_hw(struct e1000_hw *hw)
779 e1000_init_rx_addrs(hw); 793 e1000_init_rx_addrs(hw);
780 794
781 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 795 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
782 if(hw->mac_type == e1000_82542_rev2_0) { 796 if (hw->mac_type == e1000_82542_rev2_0) {
783 E1000_WRITE_REG(hw, RCTL, 0); 797 E1000_WRITE_REG(hw, RCTL, 0);
784 E1000_WRITE_FLUSH(hw); 798 E1000_WRITE_FLUSH(hw);
785 msec_delay(1); 799 msleep(1);
786 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 800 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
787 e1000_pci_set_mwi(hw); 801 e1000_pci_set_mwi(hw);
788 } 802 }
789 803
@@ -792,7 +806,7 @@ e1000_init_hw(struct e1000_hw *hw)
792 mta_size = E1000_MC_TBL_SIZE; 806 mta_size = E1000_MC_TBL_SIZE;
793 if (hw->mac_type == e1000_ich8lan) 807 if (hw->mac_type == e1000_ich8lan)
794 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 808 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
795 for(i = 0; i < mta_size; i++) { 809 for (i = 0; i < mta_size; i++) {
796 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 810 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
797 /* use write flush to prevent Memory Write Block (MWB) from 811 /* use write flush to prevent Memory Write Block (MWB) from
798 * occuring when accessing our register space */ 812 * occuring when accessing our register space */
@@ -804,18 +818,18 @@ e1000_init_hw(struct e1000_hw *hw)
804 * gives equal priority to transmits and receives. Valid only on 818 * gives equal priority to transmits and receives. Valid only on
805 * 82542 and 82543 silicon. 819 * 82542 and 82543 silicon.
806 */ 820 */
807 if(hw->dma_fairness && hw->mac_type <= e1000_82543) { 821 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
808 ctrl = E1000_READ_REG(hw, CTRL); 822 ctrl = E1000_READ_REG(hw, CTRL);
809 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
810 } 824 }
811 825
812 switch(hw->mac_type) { 826 switch (hw->mac_type) {
813 case e1000_82545_rev_3: 827 case e1000_82545_rev_3:
814 case e1000_82546_rev_3: 828 case e1000_82546_rev_3:
815 break; 829 break;
816 default: 830 default:
817 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 831 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
818 if(hw->bus_type == e1000_bus_type_pcix) { 832 if (hw->bus_type == e1000_bus_type_pcix) {
819 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); 833 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
820 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 834 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
821 &pcix_stat_hi_word); 835 &pcix_stat_hi_word);
@@ -823,9 +837,9 @@ e1000_init_hw(struct e1000_hw *hw)
823 PCIX_COMMAND_MMRBC_SHIFT; 837 PCIX_COMMAND_MMRBC_SHIFT;
824 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 838 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
825 PCIX_STATUS_HI_MMRBC_SHIFT; 839 PCIX_STATUS_HI_MMRBC_SHIFT;
826 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 840 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
827 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 841 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
828 if(cmd_mmrbc > stat_mmrbc) { 842 if (cmd_mmrbc > stat_mmrbc) {
829 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 843 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
830 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 844 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
831 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 845 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
@@ -837,13 +851,13 @@ e1000_init_hw(struct e1000_hw *hw)
837 851
838 /* More time needed for PHY to initialize */ 852 /* More time needed for PHY to initialize */
839 if (hw->mac_type == e1000_ich8lan) 853 if (hw->mac_type == e1000_ich8lan)
840 msec_delay(15); 854 msleep(15);
841 855
842 /* Call a subroutine to configure the link and setup flow control. */ 856 /* Call a subroutine to configure the link and setup flow control. */
843 ret_val = e1000_setup_link(hw); 857 ret_val = e1000_setup_link(hw);
844 858
845 /* Set the transmit descriptor write-back policy */ 859 /* Set the transmit descriptor write-back policy */
846 if(hw->mac_type > e1000_82544) { 860 if (hw->mac_type > e1000_82544) {
847 ctrl = E1000_READ_REG(hw, TXDCTL); 861 ctrl = E1000_READ_REG(hw, TXDCTL);
848 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 862 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
849 switch (hw->mac_type) { 863 switch (hw->mac_type) {
@@ -894,14 +908,13 @@ e1000_init_hw(struct e1000_hw *hw)
894 case e1000_ich8lan: 908 case e1000_ich8lan:
895 ctrl = E1000_READ_REG(hw, TXDCTL1); 909 ctrl = E1000_READ_REG(hw, TXDCTL1);
896 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 910 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
897 if(hw->mac_type >= e1000_82571) 911 if (hw->mac_type >= e1000_82571)
898 ctrl |= E1000_TXDCTL_COUNT_DESC; 912 ctrl |= E1000_TXDCTL_COUNT_DESC;
899 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 913 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
900 break; 914 break;
901 } 915 }
902 916
903 917
904
905 if (hw->mac_type == e1000_82573) { 918 if (hw->mac_type == e1000_82573) {
906 uint32_t gcr = E1000_READ_REG(hw, GCR); 919 uint32_t gcr = E1000_READ_REG(hw, GCR);
907 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 920 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
@@ -945,10 +958,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
945 958
946 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 959 DEBUGFUNC("e1000_adjust_serdes_amplitude");
947 960
948 if(hw->media_type != e1000_media_type_internal_serdes) 961 if (hw->media_type != e1000_media_type_internal_serdes)
949 return E1000_SUCCESS; 962 return E1000_SUCCESS;
950 963
951 switch(hw->mac_type) { 964 switch (hw->mac_type) {
952 case e1000_82545_rev_3: 965 case e1000_82545_rev_3:
953 case e1000_82546_rev_3: 966 case e1000_82546_rev_3:
954 break; 967 break;
@@ -961,11 +974,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
961 return ret_val; 974 return ret_val;
962 } 975 }
963 976
964 if(eeprom_data != EEPROM_RESERVED_WORD) { 977 if (eeprom_data != EEPROM_RESERVED_WORD) {
965 /* Adjust SERDES output amplitude only. */ 978 /* Adjust SERDES output amplitude only. */
966 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 979 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
967 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 980 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
968 if(ret_val) 981 if (ret_val)
969 return ret_val; 982 return ret_val;
970 } 983 }
971 984
@@ -1033,10 +1046,10 @@ e1000_setup_link(struct e1000_hw *hw)
1033 * in case we get disconnected and then reconnected into a different 1046 * in case we get disconnected and then reconnected into a different
1034 * hub or switch with different Flow Control capabilities. 1047 * hub or switch with different Flow Control capabilities.
1035 */ 1048 */
1036 if(hw->mac_type == e1000_82542_rev2_0) 1049 if (hw->mac_type == e1000_82542_rev2_0)
1037 hw->fc &= (~e1000_fc_tx_pause); 1050 hw->fc &= (~e1000_fc_tx_pause);
1038 1051
1039 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1052 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1040 hw->fc &= (~e1000_fc_rx_pause); 1053 hw->fc &= (~e1000_fc_rx_pause);
1041 1054
1042 hw->original_fc = hw->fc; 1055 hw->original_fc = hw->fc;
@@ -1051,12 +1064,12 @@ e1000_setup_link(struct e1000_hw *hw)
1051 * or e1000_phy_setup() is called. 1064 * or e1000_phy_setup() is called.
1052 */ 1065 */
1053 if (hw->mac_type == e1000_82543) { 1066 if (hw->mac_type == e1000_82543) {
1054 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1067 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1055 1, &eeprom_data); 1068 1, &eeprom_data);
1056 if (ret_val) { 1069 if (ret_val) {
1057 DEBUGOUT("EEPROM Read Error\n"); 1070 DEBUGOUT("EEPROM Read Error\n");
1058 return -E1000_ERR_EEPROM; 1071 return -E1000_ERR_EEPROM;
1059 } 1072 }
1060 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1073 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1061 SWDPIO__EXT_SHIFT); 1074 SWDPIO__EXT_SHIFT);
1062 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1075 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -1089,14 +1102,14 @@ e1000_setup_link(struct e1000_hw *hw)
1089 * ability to transmit pause frames in not enabled, then these 1102 * ability to transmit pause frames in not enabled, then these
1090 * registers will be set to 0. 1103 * registers will be set to 0.
1091 */ 1104 */
1092 if(!(hw->fc & e1000_fc_tx_pause)) { 1105 if (!(hw->fc & e1000_fc_tx_pause)) {
1093 E1000_WRITE_REG(hw, FCRTL, 0); 1106 E1000_WRITE_REG(hw, FCRTL, 0);
1094 E1000_WRITE_REG(hw, FCRTH, 0); 1107 E1000_WRITE_REG(hw, FCRTH, 0);
1095 } else { 1108 } else {
1096 /* We need to set up the Receive Threshold high and low water marks 1109 /* We need to set up the Receive Threshold high and low water marks
1097 * as well as (optionally) enabling the transmission of XON frames. 1110 * as well as (optionally) enabling the transmission of XON frames.
1098 */ 1111 */
1099 if(hw->fc_send_xon) { 1112 if (hw->fc_send_xon) {
1100 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1113 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1101 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1114 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1102 } else { 1115 } else {
@@ -1143,11 +1156,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1143 * the EEPROM. 1156 * the EEPROM.
1144 */ 1157 */
1145 ctrl = E1000_READ_REG(hw, CTRL); 1158 ctrl = E1000_READ_REG(hw, CTRL);
1146 if(hw->media_type == e1000_media_type_fiber) 1159 if (hw->media_type == e1000_media_type_fiber)
1147 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1160 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1148 1161
1149 ret_val = e1000_adjust_serdes_amplitude(hw); 1162 ret_val = e1000_adjust_serdes_amplitude(hw);
1150 if(ret_val) 1163 if (ret_val)
1151 return ret_val; 1164 return ret_val;
1152 1165
1153 /* Take the link out of reset */ 1166 /* Take the link out of reset */
@@ -1155,7 +1168,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1155 1168
1156 /* Adjust VCO speed to improve BER performance */ 1169 /* Adjust VCO speed to improve BER performance */
1157 ret_val = e1000_set_vco_speed(hw); 1170 ret_val = e1000_set_vco_speed(hw);
1158 if(ret_val) 1171 if (ret_val)
1159 return ret_val; 1172 return ret_val;
1160 1173
1161 e1000_config_collision_dist(hw); 1174 e1000_config_collision_dist(hw);
@@ -1218,7 +1231,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1218 E1000_WRITE_FLUSH(hw); 1231 E1000_WRITE_FLUSH(hw);
1219 1232
1220 hw->txcw = txcw; 1233 hw->txcw = txcw;
1221 msec_delay(1); 1234 msleep(1);
1222 1235
1223 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1236 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1224 * indication in the Device Status Register. Time-out if a link isn't 1237 * indication in the Device Status Register. Time-out if a link isn't
@@ -1226,15 +1239,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1226 * less than 500 milliseconds even if the other end is doing it in SW). 1239 * less than 500 milliseconds even if the other end is doing it in SW).
1227 * For internal serdes, we just assume a signal is present, then poll. 1240 * For internal serdes, we just assume a signal is present, then poll.
1228 */ 1241 */
1229 if(hw->media_type == e1000_media_type_internal_serdes || 1242 if (hw->media_type == e1000_media_type_internal_serdes ||
1230 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1243 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1231 DEBUGOUT("Looking for Link\n"); 1244 DEBUGOUT("Looking for Link\n");
1232 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1245 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1233 msec_delay(10); 1246 msleep(10);
1234 status = E1000_READ_REG(hw, STATUS); 1247 status = E1000_READ_REG(hw, STATUS);
1235 if(status & E1000_STATUS_LU) break; 1248 if (status & E1000_STATUS_LU) break;
1236 } 1249 }
1237 if(i == (LINK_UP_TIMEOUT / 10)) { 1250 if (i == (LINK_UP_TIMEOUT / 10)) {
1238 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1251 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1239 hw->autoneg_failed = 1; 1252 hw->autoneg_failed = 1;
1240 /* AutoNeg failed to achieve a link, so we'll call 1253 /* AutoNeg failed to achieve a link, so we'll call
@@ -1243,7 +1256,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1243 * non-autonegotiating link partners. 1256 * non-autonegotiating link partners.
1244 */ 1257 */
1245 ret_val = e1000_check_for_link(hw); 1258 ret_val = e1000_check_for_link(hw);
1246 if(ret_val) { 1259 if (ret_val) {
1247 DEBUGOUT("Error while checking for link\n"); 1260 DEBUGOUT("Error while checking for link\n");
1248 return ret_val; 1261 return ret_val;
1249 } 1262 }
@@ -1277,7 +1290,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1277 * the PHY speed and duplex configuration is. In addition, we need to 1290 * the PHY speed and duplex configuration is. In addition, we need to
1278 * perform a hardware reset on the PHY to take it out of reset. 1291 * perform a hardware reset on the PHY to take it out of reset.
1279 */ 1292 */
1280 if(hw->mac_type > e1000_82543) { 1293 if (hw->mac_type > e1000_82543) {
1281 ctrl |= E1000_CTRL_SLU; 1294 ctrl |= E1000_CTRL_SLU;
1282 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1295 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1283 E1000_WRITE_REG(hw, CTRL, ctrl); 1296 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -1285,13 +1298,13 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1285 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1286 E1000_WRITE_REG(hw, CTRL, ctrl); 1299 E1000_WRITE_REG(hw, CTRL, ctrl);
1287 ret_val = e1000_phy_hw_reset(hw); 1300 ret_val = e1000_phy_hw_reset(hw);
1288 if(ret_val) 1301 if (ret_val)
1289 return ret_val; 1302 return ret_val;
1290 } 1303 }
1291 1304
1292 /* Make sure we have a valid PHY */ 1305 /* Make sure we have a valid PHY */
1293 ret_val = e1000_detect_gig_phy(hw); 1306 ret_val = e1000_detect_gig_phy(hw);
1294 if(ret_val) { 1307 if (ret_val) {
1295 DEBUGOUT("Error, did not detect valid phy.\n"); 1308 DEBUGOUT("Error, did not detect valid phy.\n");
1296 return ret_val; 1309 return ret_val;
1297 } 1310 }
@@ -1299,19 +1312,19 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
1299 1312
1300 /* Set PHY to class A mode (if necessary) */ 1313 /* Set PHY to class A mode (if necessary) */
1301 ret_val = e1000_set_phy_mode(hw); 1314 ret_val = e1000_set_phy_mode(hw);
1302 if(ret_val) 1315 if (ret_val)
1303 return ret_val; 1316 return ret_val;
1304 1317
1305 if((hw->mac_type == e1000_82545_rev_3) || 1318 if ((hw->mac_type == e1000_82545_rev_3) ||
1306 (hw->mac_type == e1000_82546_rev_3)) { 1319 (hw->mac_type == e1000_82546_rev_3)) {
1307 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1320 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1308 phy_data |= 0x00000008; 1321 phy_data |= 0x00000008;
1309 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1322 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1310 } 1323 }
1311 1324
1312 if(hw->mac_type <= e1000_82543 || 1325 if (hw->mac_type <= e1000_82543 ||
1313 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || 1326 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1314 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1327 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1315 hw->phy_reset_disable = FALSE; 1328 hw->phy_reset_disable = FALSE;
1316 1329
1317 return E1000_SUCCESS; 1330 return E1000_SUCCESS;
@@ -1341,8 +1354,8 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1341 return ret_val; 1354 return ret_val;
1342 } 1355 }
1343 1356
1344 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1357 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1345 msec_delay(15); 1358 msleep(15);
1346 if (hw->mac_type != e1000_ich8lan) { 1359 if (hw->mac_type != e1000_ich8lan) {
1347 /* Configure activity LED after PHY reset */ 1360 /* Configure activity LED after PHY reset */
1348 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1361 led_ctrl = E1000_READ_REG(hw, LEDCTL);
@@ -1351,11 +1364,14 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1364 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1352 } 1365 }
1353 1366
1354 /* disable lplu d3 during driver init */ 1367 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1355 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1368 if (hw->phy_type == e1000_phy_igp) {
1356 if (ret_val) { 1369 /* disable lplu d3 during driver init */
1357 DEBUGOUT("Error Disabling LPLU D3\n"); 1370 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1358 return ret_val; 1371 if (ret_val) {
1372 DEBUGOUT("Error Disabling LPLU D3\n");
1373 return ret_val;
1374 }
1359 } 1375 }
1360 1376
1361 /* disable lplu d0 during driver init */ 1377 /* disable lplu d0 during driver init */
@@ -1393,45 +1409,45 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1393 } 1409 }
1394 } 1410 }
1395 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1411 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1396 if(ret_val) 1412 if (ret_val)
1397 return ret_val; 1413 return ret_val;
1398 1414
1399 /* set auto-master slave resolution settings */ 1415 /* set auto-master slave resolution settings */
1400 if(hw->autoneg) { 1416 if (hw->autoneg) {
1401 e1000_ms_type phy_ms_setting = hw->master_slave; 1417 e1000_ms_type phy_ms_setting = hw->master_slave;
1402 1418
1403 if(hw->ffe_config_state == e1000_ffe_config_active) 1419 if (hw->ffe_config_state == e1000_ffe_config_active)
1404 hw->ffe_config_state = e1000_ffe_config_enabled; 1420 hw->ffe_config_state = e1000_ffe_config_enabled;
1405 1421
1406 if(hw->dsp_config_state == e1000_dsp_config_activated) 1422 if (hw->dsp_config_state == e1000_dsp_config_activated)
1407 hw->dsp_config_state = e1000_dsp_config_enabled; 1423 hw->dsp_config_state = e1000_dsp_config_enabled;
1408 1424
1409 /* when autonegotiation advertisment is only 1000Mbps then we 1425 /* when autonegotiation advertisment is only 1000Mbps then we
1410 * should disable SmartSpeed and enable Auto MasterSlave 1426 * should disable SmartSpeed and enable Auto MasterSlave
1411 * resolution as hardware default. */ 1427 * resolution as hardware default. */
1412 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1428 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1413 /* Disable SmartSpeed */ 1429 /* Disable SmartSpeed */
1414 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 1430 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1415 if(ret_val) 1431 &phy_data);
1432 if (ret_val)
1416 return ret_val; 1433 return ret_val;
1417 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1434 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1418 ret_val = e1000_write_phy_reg(hw, 1435 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1419 IGP01E1000_PHY_PORT_CONFIG, 1436 phy_data);
1420 phy_data); 1437 if (ret_val)
1421 if(ret_val)
1422 return ret_val; 1438 return ret_val;
1423 /* Set auto Master/Slave resolution process */ 1439 /* Set auto Master/Slave resolution process */
1424 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1440 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1425 if(ret_val) 1441 if (ret_val)
1426 return ret_val; 1442 return ret_val;
1427 phy_data &= ~CR_1000T_MS_ENABLE; 1443 phy_data &= ~CR_1000T_MS_ENABLE;
1428 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1444 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1429 if(ret_val) 1445 if (ret_val)
1430 return ret_val; 1446 return ret_val;
1431 } 1447 }
1432 1448
1433 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1449 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1434 if(ret_val) 1450 if (ret_val)
1435 return ret_val; 1451 return ret_val;
1436 1452
1437 /* load defaults for future use */ 1453 /* load defaults for future use */
@@ -1455,7 +1471,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1455 break; 1471 break;
1456 } 1472 }
1457 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1473 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1458 if(ret_val) 1474 if (ret_val)
1459 return ret_val; 1475 return ret_val;
1460 } 1476 }
1461 1477
@@ -1476,12 +1492,12 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1476 1492
1477 DEBUGFUNC("e1000_copper_link_ggp_setup"); 1493 DEBUGFUNC("e1000_copper_link_ggp_setup");
1478 1494
1479 if(!hw->phy_reset_disable) { 1495 if (!hw->phy_reset_disable) {
1480 1496
1481 /* Enable CRS on TX for half-duplex operation. */ 1497 /* Enable CRS on TX for half-duplex operation. */
1482 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1498 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1483 &phy_data); 1499 &phy_data);
1484 if(ret_val) 1500 if (ret_val)
1485 return ret_val; 1501 return ret_val;
1486 1502
1487 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1503 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -1490,7 +1506,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1490 1506
1491 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 1507 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1492 phy_data); 1508 phy_data);
1493 if(ret_val) 1509 if (ret_val)
1494 return ret_val; 1510 return ret_val;
1495 1511
1496 /* Options: 1512 /* Options:
@@ -1501,7 +1517,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1501 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1517 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1502 */ 1518 */
1503 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); 1519 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1504 if(ret_val) 1520 if (ret_val)
1505 return ret_val; 1521 return ret_val;
1506 1522
1507 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1523 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
@@ -1526,11 +1542,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1526 * 1 - Enabled 1542 * 1 - Enabled
1527 */ 1543 */
1528 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1544 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1529 if(hw->disable_polarity_correction == 1) 1545 if (hw->disable_polarity_correction == 1)
1530 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1546 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1531 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 1547 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1532 1548
1533 if(ret_val) 1549 if (ret_val)
1534 return ret_val; 1550 return ret_val;
1535 1551
1536 /* SW Reset the PHY so all changes take effect */ 1552 /* SW Reset the PHY so all changes take effect */
@@ -1586,9 +1602,9 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1586 return ret_val; 1602 return ret_val;
1587 1603
1588 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1604 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1589
1590 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1605 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1591 phy_data); 1606 phy_data);
1607
1592 if (ret_val) 1608 if (ret_val)
1593 return ret_val; 1609 return ret_val;
1594 } 1610 }
@@ -1623,12 +1639,12 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1623 1639
1624 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1640 DEBUGFUNC("e1000_copper_link_mgp_setup");
1625 1641
1626 if(hw->phy_reset_disable) 1642 if (hw->phy_reset_disable)
1627 return E1000_SUCCESS; 1643 return E1000_SUCCESS;
1628 1644
1629 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1645 /* Enable CRS on TX. This must be set for half-duplex operation. */
1630 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1646 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1631 if(ret_val) 1647 if (ret_val)
1632 return ret_val; 1648 return ret_val;
1633 1649
1634 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1650 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1665,7 +1681,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1665 * 1 - Enabled 1681 * 1 - Enabled
1666 */ 1682 */
1667 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1683 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1668 if(hw->disable_polarity_correction == 1) 1684 if (hw->disable_polarity_correction == 1)
1669 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1685 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1686 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1671 if (ret_val) 1687 if (ret_val)
@@ -1705,7 +1721,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1705 1721
1706 /* SW Reset the PHY so all changes take effect */ 1722 /* SW Reset the PHY so all changes take effect */
1707 ret_val = e1000_phy_reset(hw); 1723 ret_val = e1000_phy_reset(hw);
1708 if(ret_val) { 1724 if (ret_val) {
1709 DEBUGOUT("Error Resetting the PHY\n"); 1725 DEBUGOUT("Error Resetting the PHY\n");
1710 return ret_val; 1726 return ret_val;
1711 } 1727 }
@@ -1735,7 +1751,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1735 /* If autoneg_advertised is zero, we assume it was not defaulted 1751 /* If autoneg_advertised is zero, we assume it was not defaulted
1736 * by the calling code so we set to advertise full capability. 1752 * by the calling code so we set to advertise full capability.
1737 */ 1753 */
1738 if(hw->autoneg_advertised == 0) 1754 if (hw->autoneg_advertised == 0)
1739 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1755 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1740 1756
1741 /* IFE phy only supports 10/100 */ 1757 /* IFE phy only supports 10/100 */
@@ -1744,7 +1760,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1744 1760
1745 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1761 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1746 ret_val = e1000_phy_setup_autoneg(hw); 1762 ret_val = e1000_phy_setup_autoneg(hw);
1747 if(ret_val) { 1763 if (ret_val) {
1748 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1764 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1749 return ret_val; 1765 return ret_val;
1750 } 1766 }
@@ -1754,20 +1770,20 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1754 * the Auto Neg Restart bit in the PHY control register. 1770 * the Auto Neg Restart bit in the PHY control register.
1755 */ 1771 */
1756 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1772 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1757 if(ret_val) 1773 if (ret_val)
1758 return ret_val; 1774 return ret_val;
1759 1775
1760 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1776 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1761 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1777 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1762 if(ret_val) 1778 if (ret_val)
1763 return ret_val; 1779 return ret_val;
1764 1780
1765 /* Does the user want to wait for Auto-Neg to complete here, or 1781 /* Does the user want to wait for Auto-Neg to complete here, or
1766 * check at a later time (for example, callback routine). 1782 * check at a later time (for example, callback routine).
1767 */ 1783 */
1768 if(hw->wait_autoneg_complete) { 1784 if (hw->wait_autoneg_complete) {
1769 ret_val = e1000_wait_autoneg(hw); 1785 ret_val = e1000_wait_autoneg(hw);
1770 if(ret_val) { 1786 if (ret_val) {
1771 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1787 DEBUGOUT("Error while waiting for autoneg to complete\n");
1772 return ret_val; 1788 return ret_val;
1773 } 1789 }
@@ -1778,7 +1794,6 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1778 return E1000_SUCCESS; 1794 return E1000_SUCCESS;
1779} 1795}
1780 1796
1781
1782/****************************************************************************** 1797/******************************************************************************
1783* Config the MAC and the PHY after link is up. 1798* Config the MAC and the PHY after link is up.
1784* 1) Set up the MAC to the current PHY speed/duplex 1799* 1) Set up the MAC to the current PHY speed/duplex
@@ -1797,25 +1812,25 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
1797 int32_t ret_val; 1812 int32_t ret_val;
1798 DEBUGFUNC("e1000_copper_link_postconfig"); 1813 DEBUGFUNC("e1000_copper_link_postconfig");
1799 1814
1800 if(hw->mac_type >= e1000_82544) { 1815 if (hw->mac_type >= e1000_82544) {
1801 e1000_config_collision_dist(hw); 1816 e1000_config_collision_dist(hw);
1802 } else { 1817 } else {
1803 ret_val = e1000_config_mac_to_phy(hw); 1818 ret_val = e1000_config_mac_to_phy(hw);
1804 if(ret_val) { 1819 if (ret_val) {
1805 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1820 DEBUGOUT("Error configuring MAC to PHY settings\n");
1806 return ret_val; 1821 return ret_val;
1807 } 1822 }
1808 } 1823 }
1809 ret_val = e1000_config_fc_after_link_up(hw); 1824 ret_val = e1000_config_fc_after_link_up(hw);
1810 if(ret_val) { 1825 if (ret_val) {
1811 DEBUGOUT("Error Configuring Flow Control\n"); 1826 DEBUGOUT("Error Configuring Flow Control\n");
1812 return ret_val; 1827 return ret_val;
1813 } 1828 }
1814 1829
1815 /* Config DSP to improve Giga link quality */ 1830 /* Config DSP to improve Giga link quality */
1816 if(hw->phy_type == e1000_phy_igp) { 1831 if (hw->phy_type == e1000_phy_igp) {
1817 ret_val = e1000_config_dsp_after_link_change(hw, TRUE); 1832 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1818 if(ret_val) { 1833 if (ret_val) {
1819 DEBUGOUT("Error Configuring DSP after link up\n"); 1834 DEBUGOUT("Error Configuring DSP after link up\n");
1820 return ret_val; 1835 return ret_val;
1821 } 1836 }
@@ -1861,7 +1876,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1861 1876
1862 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1877 /* Check if it is a valid PHY and set PHY mode if necessary. */
1863 ret_val = e1000_copper_link_preconfig(hw); 1878 ret_val = e1000_copper_link_preconfig(hw);
1864 if(ret_val) 1879 if (ret_val)
1865 return ret_val; 1880 return ret_val;
1866 1881
1867 switch (hw->mac_type) { 1882 switch (hw->mac_type) {
@@ -1882,30 +1897,30 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1882 hw->phy_type == e1000_phy_igp_3 || 1897 hw->phy_type == e1000_phy_igp_3 ||
1883 hw->phy_type == e1000_phy_igp_2) { 1898 hw->phy_type == e1000_phy_igp_2) {
1884 ret_val = e1000_copper_link_igp_setup(hw); 1899 ret_val = e1000_copper_link_igp_setup(hw);
1885 if(ret_val) 1900 if (ret_val)
1886 return ret_val; 1901 return ret_val;
1887 } else if (hw->phy_type == e1000_phy_m88) { 1902 } else if (hw->phy_type == e1000_phy_m88) {
1888 ret_val = e1000_copper_link_mgp_setup(hw); 1903 ret_val = e1000_copper_link_mgp_setup(hw);
1889 if(ret_val) 1904 if (ret_val)
1890 return ret_val; 1905 return ret_val;
1891 } else if (hw->phy_type == e1000_phy_gg82563) { 1906 } else if (hw->phy_type == e1000_phy_gg82563) {
1892 ret_val = e1000_copper_link_ggp_setup(hw); 1907 ret_val = e1000_copper_link_ggp_setup(hw);
1893 if(ret_val) 1908 if (ret_val)
1894 return ret_val; 1909 return ret_val;
1895 } 1910 }
1896 1911
1897 if(hw->autoneg) { 1912 if (hw->autoneg) {
1898 /* Setup autoneg and flow control advertisement 1913 /* Setup autoneg and flow control advertisement
1899 * and perform autonegotiation */ 1914 * and perform autonegotiation */
1900 ret_val = e1000_copper_link_autoneg(hw); 1915 ret_val = e1000_copper_link_autoneg(hw);
1901 if(ret_val) 1916 if (ret_val)
1902 return ret_val; 1917 return ret_val;
1903 } else { 1918 } else {
1904 /* PHY will be set to 10H, 10F, 100H,or 100F 1919 /* PHY will be set to 10H, 10F, 100H,or 100F
1905 * depending on value from forced_speed_duplex. */ 1920 * depending on value from forced_speed_duplex. */
1906 DEBUGOUT("Forcing speed and duplex\n"); 1921 DEBUGOUT("Forcing speed and duplex\n");
1907 ret_val = e1000_phy_force_speed_duplex(hw); 1922 ret_val = e1000_phy_force_speed_duplex(hw);
1908 if(ret_val) { 1923 if (ret_val) {
1909 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1924 DEBUGOUT("Error Forcing Speed and Duplex\n");
1910 return ret_val; 1925 return ret_val;
1911 } 1926 }
@@ -1914,18 +1929,18 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1914 /* Check link status. Wait up to 100 microseconds for link to become 1929 /* Check link status. Wait up to 100 microseconds for link to become
1915 * valid. 1930 * valid.
1916 */ 1931 */
1917 for(i = 0; i < 10; i++) { 1932 for (i = 0; i < 10; i++) {
1918 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1933 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1919 if(ret_val) 1934 if (ret_val)
1920 return ret_val; 1935 return ret_val;
1921 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1936 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1922 if(ret_val) 1937 if (ret_val)
1923 return ret_val; 1938 return ret_val;
1924 1939
1925 if(phy_data & MII_SR_LINK_STATUS) { 1940 if (phy_data & MII_SR_LINK_STATUS) {
1926 /* Config the MAC and PHY after link is up */ 1941 /* Config the MAC and PHY after link is up */
1927 ret_val = e1000_copper_link_postconfig(hw); 1942 ret_val = e1000_copper_link_postconfig(hw);
1928 if(ret_val) 1943 if (ret_val)
1929 return ret_val; 1944 return ret_val;
1930 1945
1931 DEBUGOUT("Valid link established!!!\n"); 1946 DEBUGOUT("Valid link established!!!\n");
@@ -2027,7 +2042,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2027 2042
2028 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2043 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2029 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2044 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2030 if(ret_val) 2045 if (ret_val)
2031 return ret_val; 2046 return ret_val;
2032 2047
2033 if (hw->phy_type != e1000_phy_ife) { 2048 if (hw->phy_type != e1000_phy_ife) {
@@ -2055,36 +2070,36 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2055 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2070 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2056 2071
2057 /* Do we want to advertise 10 Mb Half Duplex? */ 2072 /* Do we want to advertise 10 Mb Half Duplex? */
2058 if(hw->autoneg_advertised & ADVERTISE_10_HALF) { 2073 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2059 DEBUGOUT("Advertise 10mb Half duplex\n"); 2074 DEBUGOUT("Advertise 10mb Half duplex\n");
2060 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2075 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2061 } 2076 }
2062 2077
2063 /* Do we want to advertise 10 Mb Full Duplex? */ 2078 /* Do we want to advertise 10 Mb Full Duplex? */
2064 if(hw->autoneg_advertised & ADVERTISE_10_FULL) { 2079 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2065 DEBUGOUT("Advertise 10mb Full duplex\n"); 2080 DEBUGOUT("Advertise 10mb Full duplex\n");
2066 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2081 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2067 } 2082 }
2068 2083
2069 /* Do we want to advertise 100 Mb Half Duplex? */ 2084 /* Do we want to advertise 100 Mb Half Duplex? */
2070 if(hw->autoneg_advertised & ADVERTISE_100_HALF) { 2085 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2071 DEBUGOUT("Advertise 100mb Half duplex\n"); 2086 DEBUGOUT("Advertise 100mb Half duplex\n");
2072 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2087 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2073 } 2088 }
2074 2089
2075 /* Do we want to advertise 100 Mb Full Duplex? */ 2090 /* Do we want to advertise 100 Mb Full Duplex? */
2076 if(hw->autoneg_advertised & ADVERTISE_100_FULL) { 2091 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2077 DEBUGOUT("Advertise 100mb Full duplex\n"); 2092 DEBUGOUT("Advertise 100mb Full duplex\n");
2078 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2093 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2079 } 2094 }
2080 2095
2081 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2096 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2082 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2097 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2083 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 2098 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2084 } 2099 }
2085 2100
2086 /* Do we want to advertise 1000 Mb Full Duplex? */ 2101 /* Do we want to advertise 1000 Mb Full Duplex? */
2087 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2102 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2088 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2103 DEBUGOUT("Advertise 1000mb Full duplex\n");
2089 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2104 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2090 if (hw->phy_type == e1000_phy_ife) { 2105 if (hw->phy_type == e1000_phy_ife) {
@@ -2146,7 +2161,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2146 } 2161 }
2147 2162
2148 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2163 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2149 if(ret_val) 2164 if (ret_val)
2150 return ret_val; 2165 return ret_val;
2151 2166
2152 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2167 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
@@ -2194,7 +2209,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2194 2209
2195 /* Read the MII Control Register. */ 2210 /* Read the MII Control Register. */
2196 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2211 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2197 if(ret_val) 2212 if (ret_val)
2198 return ret_val; 2213 return ret_val;
2199 2214
2200 /* We need to disable autoneg in order to force link and duplex. */ 2215 /* We need to disable autoneg in order to force link and duplex. */
@@ -2202,8 +2217,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2202 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2217 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2203 2218
2204 /* Are we forcing Full or Half Duplex? */ 2219 /* Are we forcing Full or Half Duplex? */
2205 if(hw->forced_speed_duplex == e1000_100_full || 2220 if (hw->forced_speed_duplex == e1000_100_full ||
2206 hw->forced_speed_duplex == e1000_10_full) { 2221 hw->forced_speed_duplex == e1000_10_full) {
2207 /* We want to force full duplex so we SET the full duplex bits in the 2222 /* We want to force full duplex so we SET the full duplex bits in the
2208 * Device and MII Control Registers. 2223 * Device and MII Control Registers.
2209 */ 2224 */
@@ -2220,7 +2235,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2220 } 2235 }
2221 2236
2222 /* Are we forcing 100Mbps??? */ 2237 /* Are we forcing 100Mbps??? */
2223 if(hw->forced_speed_duplex == e1000_100_full || 2238 if (hw->forced_speed_duplex == e1000_100_full ||
2224 hw->forced_speed_duplex == e1000_100_half) { 2239 hw->forced_speed_duplex == e1000_100_half) {
2225 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 2240 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2226 ctrl |= E1000_CTRL_SPD_100; 2241 ctrl |= E1000_CTRL_SPD_100;
@@ -2243,7 +2258,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2243 if ((hw->phy_type == e1000_phy_m88) || 2258 if ((hw->phy_type == e1000_phy_m88) ||
2244 (hw->phy_type == e1000_phy_gg82563)) { 2259 (hw->phy_type == e1000_phy_gg82563)) {
2245 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2260 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2246 if(ret_val) 2261 if (ret_val)
2247 return ret_val; 2262 return ret_val;
2248 2263
2249 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 2264 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
@@ -2251,7 +2266,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2251 */ 2266 */
2252 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2267 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2253 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2268 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2254 if(ret_val) 2269 if (ret_val)
2255 return ret_val; 2270 return ret_val;
2256 2271
2257 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 2272 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
@@ -2275,20 +2290,20 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2275 * forced whenever speed or duplex are forced. 2290 * forced whenever speed or duplex are forced.
2276 */ 2291 */
2277 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2292 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2278 if(ret_val) 2293 if (ret_val)
2279 return ret_val; 2294 return ret_val;
2280 2295
2281 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2296 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2282 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2297 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2283 2298
2284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2285 if(ret_val) 2300 if (ret_val)
2286 return ret_val; 2301 return ret_val;
2287 } 2302 }
2288 2303
2289 /* Write back the modified PHY MII control register. */ 2304 /* Write back the modified PHY MII control register. */
2290 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 2305 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2291 if(ret_val) 2306 if (ret_val)
2292 return ret_val; 2307 return ret_val;
2293 2308
2294 udelay(1); 2309 udelay(1);
@@ -2300,50 +2315,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2300 * only if the user has set wait_autoneg_complete to 1, which is 2315 * only if the user has set wait_autoneg_complete to 1, which is
2301 * the default. 2316 * the default.
2302 */ 2317 */
2303 if(hw->wait_autoneg_complete) { 2318 if (hw->wait_autoneg_complete) {
2304 /* We will wait for autoneg to complete. */ 2319 /* We will wait for autoneg to complete. */
2305 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 2320 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2306 mii_status_reg = 0; 2321 mii_status_reg = 0;
2307 2322
2308 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2323 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2309 for(i = PHY_FORCE_TIME; i > 0; i--) { 2324 for (i = PHY_FORCE_TIME; i > 0; i--) {
2310 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2325 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2311 * to be set. 2326 * to be set.
2312 */ 2327 */
2313 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2328 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2314 if(ret_val) 2329 if (ret_val)
2315 return ret_val; 2330 return ret_val;
2316 2331
2317 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2332 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2318 if(ret_val) 2333 if (ret_val)
2319 return ret_val; 2334 return ret_val;
2320 2335
2321 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2336 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2322 msec_delay(100); 2337 msleep(100);
2323 } 2338 }
2324 if((i == 0) && 2339 if ((i == 0) &&
2325 ((hw->phy_type == e1000_phy_m88) || 2340 ((hw->phy_type == e1000_phy_m88) ||
2326 (hw->phy_type == e1000_phy_gg82563))) { 2341 (hw->phy_type == e1000_phy_gg82563))) {
2327 /* We didn't get link. Reset the DSP and wait again for link. */ 2342 /* We didn't get link. Reset the DSP and wait again for link. */
2328 ret_val = e1000_phy_reset_dsp(hw); 2343 ret_val = e1000_phy_reset_dsp(hw);
2329 if(ret_val) { 2344 if (ret_val) {
2330 DEBUGOUT("Error Resetting PHY DSP\n"); 2345 DEBUGOUT("Error Resetting PHY DSP\n");
2331 return ret_val; 2346 return ret_val;
2332 } 2347 }
2333 } 2348 }
2334 /* This loop will early-out if the link condition has been met. */ 2349 /* This loop will early-out if the link condition has been met. */
2335 for(i = PHY_FORCE_TIME; i > 0; i--) { 2350 for (i = PHY_FORCE_TIME; i > 0; i--) {
2336 if(mii_status_reg & MII_SR_LINK_STATUS) break; 2351 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2337 msec_delay(100); 2352 msleep(100);
2338 /* Read the MII Status Register and wait for Auto-Neg Complete bit 2353 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2339 * to be set. 2354 * to be set.
2340 */ 2355 */
2341 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2356 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2342 if(ret_val) 2357 if (ret_val)
2343 return ret_val; 2358 return ret_val;
2344 2359
2345 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2360 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2346 if(ret_val) 2361 if (ret_val)
2347 return ret_val; 2362 return ret_val;
2348 } 2363 }
2349 } 2364 }
@@ -2354,32 +2369,31 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2354 * defaults back to a 2.5MHz clock when the PHY is reset. 2369 * defaults back to a 2.5MHz clock when the PHY is reset.
2355 */ 2370 */
2356 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 2371 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2357 if(ret_val) 2372 if (ret_val)
2358 return ret_val; 2373 return ret_val;
2359 2374
2360 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2361 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2376 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2362 if(ret_val) 2377 if (ret_val)
2363 return ret_val; 2378 return ret_val;
2364 2379
2365 /* In addition, because of the s/w reset above, we need to enable CRS on 2380 /* In addition, because of the s/w reset above, we need to enable CRS on
2366 * TX. This must be set for both full and half duplex operation. 2381 * TX. This must be set for both full and half duplex operation.
2367 */ 2382 */
2368 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2383 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2369 if(ret_val) 2384 if (ret_val)
2370 return ret_val; 2385 return ret_val;
2371 2386
2372 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2373 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2388 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2374 if(ret_val) 2389 if (ret_val)
2375 return ret_val; 2390 return ret_val;
2376 2391
2377 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2392 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2378 (!hw->autoneg) && 2393 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2379 (hw->forced_speed_duplex == e1000_10_full || 2394 hw->forced_speed_duplex == e1000_10_half)) {
2380 hw->forced_speed_duplex == e1000_10_half)) {
2381 ret_val = e1000_polarity_reversal_workaround(hw); 2395 ret_val = e1000_polarity_reversal_workaround(hw);
2382 if(ret_val) 2396 if (ret_val)
2383 return ret_val; 2397 return ret_val;
2384 } 2398 }
2385 } else if (hw->phy_type == e1000_phy_gg82563) { 2399 } else if (hw->phy_type == e1000_phy_gg82563) {
@@ -2470,10 +2484,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2470 * registers depending on negotiated values. 2484 * registers depending on negotiated values.
2471 */ 2485 */
2472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2473 if(ret_val) 2487 if (ret_val)
2474 return ret_val; 2488 return ret_val;
2475 2489
2476 if(phy_data & M88E1000_PSSR_DPLX) 2490 if (phy_data & M88E1000_PSSR_DPLX)
2477 ctrl |= E1000_CTRL_FD; 2491 ctrl |= E1000_CTRL_FD;
2478 else 2492 else
2479 ctrl &= ~E1000_CTRL_FD; 2493 ctrl &= ~E1000_CTRL_FD;
@@ -2483,9 +2497,9 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
2483 /* Set up speed in the Device Control register depending on 2497 /* Set up speed in the Device Control register depending on
2484 * negotiated values. 2498 * negotiated values.
2485 */ 2499 */
2486 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 2500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2487 ctrl |= E1000_CTRL_SPD_1000; 2501 ctrl |= E1000_CTRL_SPD_1000;
2488 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 2502 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2489 ctrl |= E1000_CTRL_SPD_100; 2503 ctrl |= E1000_CTRL_SPD_100;
2490 2504
2491 /* Write the configured values back to the Device Control Reg. */ 2505 /* Write the configured values back to the Device Control Reg. */
@@ -2553,7 +2567,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2553 } 2567 }
2554 2568
2555 /* Disable TX Flow Control for 82542 (rev 2.0) */ 2569 /* Disable TX Flow Control for 82542 (rev 2.0) */
2556 if(hw->mac_type == e1000_82542_rev2_0) 2570 if (hw->mac_type == e1000_82542_rev2_0)
2557 ctrl &= (~E1000_CTRL_TFCE); 2571 ctrl &= (~E1000_CTRL_TFCE);
2558 2572
2559 E1000_WRITE_REG(hw, CTRL, ctrl); 2573 E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -2587,11 +2601,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2587 * so we had to force link. In this case, we need to force the 2601 * so we had to force link. In this case, we need to force the
2588 * configuration of the MAC to match the "fc" parameter. 2602 * configuration of the MAC to match the "fc" parameter.
2589 */ 2603 */
2590 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 2604 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2591 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || 2605 ((hw->media_type == e1000_media_type_internal_serdes) &&
2592 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 2606 (hw->autoneg_failed)) ||
2607 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2593 ret_val = e1000_force_mac_fc(hw); 2608 ret_val = e1000_force_mac_fc(hw);
2594 if(ret_val) { 2609 if (ret_val) {
2595 DEBUGOUT("Error forcing flow control settings\n"); 2610 DEBUGOUT("Error forcing flow control settings\n");
2596 return ret_val; 2611 return ret_val;
2597 } 2612 }
@@ -2602,19 +2617,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2602 * has completed, and if so, how the PHY and link partner has 2617 * has completed, and if so, how the PHY and link partner has
2603 * flow control configured. 2618 * flow control configured.
2604 */ 2619 */
2605 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2620 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2606 /* Read the MII Status Register and check to see if AutoNeg 2621 /* Read the MII Status Register and check to see if AutoNeg
2607 * has completed. We read this twice because this reg has 2622 * has completed. We read this twice because this reg has
2608 * some "sticky" (latched) bits. 2623 * some "sticky" (latched) bits.
2609 */ 2624 */
2610 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2625 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2611 if(ret_val) 2626 if (ret_val)
2612 return ret_val; 2627 return ret_val;
2613 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2628 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2614 if(ret_val) 2629 if (ret_val)
2615 return ret_val; 2630 return ret_val;
2616 2631
2617 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2632 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2618 /* The AutoNeg process has completed, so we now need to 2633 /* The AutoNeg process has completed, so we now need to
2619 * read both the Auto Negotiation Advertisement Register 2634 * read both the Auto Negotiation Advertisement Register
2620 * (Address 4) and the Auto_Negotiation Base Page Ability 2635 * (Address 4) and the Auto_Negotiation Base Page Ability
@@ -2623,11 +2638,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2623 */ 2638 */
2624 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2639 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2625 &mii_nway_adv_reg); 2640 &mii_nway_adv_reg);
2626 if(ret_val) 2641 if (ret_val)
2627 return ret_val; 2642 return ret_val;
2628 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2643 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2629 &mii_nway_lp_ability_reg); 2644 &mii_nway_lp_ability_reg);
2630 if(ret_val) 2645 if (ret_val)
2631 return ret_val; 2646 return ret_val;
2632 2647
2633 /* Two bits in the Auto Negotiation Advertisement Register 2648 /* Two bits in the Auto Negotiation Advertisement Register
@@ -2664,15 +2679,15 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2664 * 1 | DC | 1 | DC | e1000_fc_full 2679 * 1 | DC | 1 | DC | e1000_fc_full
2665 * 2680 *
2666 */ 2681 */
2667 if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2682 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2668 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2683 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2669 /* Now we need to check if the user selected RX ONLY 2684 /* Now we need to check if the user selected RX ONLY
2670 * of pause frames. In this case, we had to advertise 2685 * of pause frames. In this case, we had to advertise
2671 * FULL flow control because we could not advertise RX 2686 * FULL flow control because we could not advertise RX
2672 * ONLY. Hence, we must now check to see if we need to 2687 * ONLY. Hence, we must now check to see if we need to
2673 * turn OFF the TRANSMISSION of PAUSE frames. 2688 * turn OFF the TRANSMISSION of PAUSE frames.
2674 */ 2689 */
2675 if(hw->original_fc == e1000_fc_full) { 2690 if (hw->original_fc == e1000_fc_full) {
2676 hw->fc = e1000_fc_full; 2691 hw->fc = e1000_fc_full;
2677 DEBUGOUT("Flow Control = FULL.\n"); 2692 DEBUGOUT("Flow Control = FULL.\n");
2678 } else { 2693 } else {
@@ -2688,10 +2703,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2688 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2703 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2689 * 2704 *
2690 */ 2705 */
2691 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2706 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2692 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2693 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2708 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2694 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2695 hw->fc = e1000_fc_tx_pause; 2710 hw->fc = e1000_fc_tx_pause;
2696 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2711 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2697 } 2712 }
@@ -2703,10 +2718,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2703 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2718 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2704 * 2719 *
2705 */ 2720 */
2706 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2721 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2722 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2708 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2723 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2724 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2710 hw->fc = e1000_fc_rx_pause; 2725 hw->fc = e1000_fc_rx_pause;
2711 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2726 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2712 } 2727 }
@@ -2730,9 +2745,9 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2730 * be asked to delay transmission of packets than asking 2745 * be asked to delay transmission of packets than asking
2731 * our link partner to pause transmission of frames. 2746 * our link partner to pause transmission of frames.
2732 */ 2747 */
2733 else if((hw->original_fc == e1000_fc_none || 2748 else if ((hw->original_fc == e1000_fc_none ||
2734 hw->original_fc == e1000_fc_tx_pause) || 2749 hw->original_fc == e1000_fc_tx_pause) ||
2735 hw->fc_strict_ieee) { 2750 hw->fc_strict_ieee) {
2736 hw->fc = e1000_fc_none; 2751 hw->fc = e1000_fc_none;
2737 DEBUGOUT("Flow Control = NONE.\n"); 2752 DEBUGOUT("Flow Control = NONE.\n");
2738 } else { 2753 } else {
@@ -2745,19 +2760,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2745 * enabled per IEEE 802.3 spec. 2760 * enabled per IEEE 802.3 spec.
2746 */ 2761 */
2747 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2762 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2748 if(ret_val) { 2763 if (ret_val) {
2749 DEBUGOUT("Error getting link speed and duplex\n"); 2764 DEBUGOUT("Error getting link speed and duplex\n");
2750 return ret_val; 2765 return ret_val;
2751 } 2766 }
2752 2767
2753 if(duplex == HALF_DUPLEX) 2768 if (duplex == HALF_DUPLEX)
2754 hw->fc = e1000_fc_none; 2769 hw->fc = e1000_fc_none;
2755 2770
2756 /* Now we call a subroutine to actually force the MAC 2771 /* Now we call a subroutine to actually force the MAC
2757 * controller to use the correct flow control settings. 2772 * controller to use the correct flow control settings.
2758 */ 2773 */
2759 ret_val = e1000_force_mac_fc(hw); 2774 ret_val = e1000_force_mac_fc(hw);
2760 if(ret_val) { 2775 if (ret_val) {
2761 DEBUGOUT("Error forcing flow control settings\n"); 2776 DEBUGOUT("Error forcing flow control settings\n");
2762 return ret_val; 2777 return ret_val;
2763 } 2778 }
@@ -2796,13 +2811,13 @@ e1000_check_for_link(struct e1000_hw *hw)
2796 * set when the optics detect a signal. On older adapters, it will be 2811 * set when the optics detect a signal. On older adapters, it will be
2797 * cleared when there is a signal. This applies to fiber media only. 2812 * cleared when there is a signal. This applies to fiber media only.
2798 */ 2813 */
2799 if((hw->media_type == e1000_media_type_fiber) || 2814 if ((hw->media_type == e1000_media_type_fiber) ||
2800 (hw->media_type == e1000_media_type_internal_serdes)) { 2815 (hw->media_type == e1000_media_type_internal_serdes)) {
2801 rxcw = E1000_READ_REG(hw, RXCW); 2816 rxcw = E1000_READ_REG(hw, RXCW);
2802 2817
2803 if(hw->media_type == e1000_media_type_fiber) { 2818 if (hw->media_type == e1000_media_type_fiber) {
2804 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2819 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2805 if(status & E1000_STATUS_LU) 2820 if (status & E1000_STATUS_LU)
2806 hw->get_link_status = FALSE; 2821 hw->get_link_status = FALSE;
2807 } 2822 }
2808 } 2823 }
@@ -2813,20 +2828,20 @@ e1000_check_for_link(struct e1000_hw *hw)
2813 * receive a Link Status Change interrupt or we have Rx Sequence 2828 * receive a Link Status Change interrupt or we have Rx Sequence
2814 * Errors. 2829 * Errors.
2815 */ 2830 */
2816 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2831 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2817 /* First we want to see if the MII Status Register reports 2832 /* First we want to see if the MII Status Register reports
2818 * link. If so, then we want to get the current speed/duplex 2833 * link. If so, then we want to get the current speed/duplex
2819 * of the PHY. 2834 * of the PHY.
2820 * Read the register twice since the link bit is sticky. 2835 * Read the register twice since the link bit is sticky.
2821 */ 2836 */
2822 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2837 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2823 if(ret_val) 2838 if (ret_val)
2824 return ret_val; 2839 return ret_val;
2825 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2826 if(ret_val) 2841 if (ret_val)
2827 return ret_val; 2842 return ret_val;
2828 2843
2829 if(phy_data & MII_SR_LINK_STATUS) { 2844 if (phy_data & MII_SR_LINK_STATUS) {
2830 hw->get_link_status = FALSE; 2845 hw->get_link_status = FALSE;
2831 /* Check if there was DownShift, must be checked immediately after 2846 /* Check if there was DownShift, must be checked immediately after
2832 * link-up */ 2847 * link-up */
@@ -2840,10 +2855,10 @@ e1000_check_for_link(struct e1000_hw *hw)
2840 * happen due to the execution of this workaround. 2855 * happen due to the execution of this workaround.
2841 */ 2856 */
2842 2857
2843 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2858 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2844 (!hw->autoneg) && 2859 (!hw->autoneg) &&
2845 (hw->forced_speed_duplex == e1000_10_full || 2860 (hw->forced_speed_duplex == e1000_10_full ||
2846 hw->forced_speed_duplex == e1000_10_half)) { 2861 hw->forced_speed_duplex == e1000_10_half)) {
2847 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2862 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2848 ret_val = e1000_polarity_reversal_workaround(hw); 2863 ret_val = e1000_polarity_reversal_workaround(hw);
2849 icr = E1000_READ_REG(hw, ICR); 2864 icr = E1000_READ_REG(hw, ICR);
@@ -2860,7 +2875,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2860 /* If we are forcing speed/duplex, then we simply return since 2875 /* If we are forcing speed/duplex, then we simply return since
2861 * we have already determined whether we have link or not. 2876 * we have already determined whether we have link or not.
2862 */ 2877 */
2863 if(!hw->autoneg) return -E1000_ERR_CONFIG; 2878 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2864 2879
2865 /* optimize the dsp settings for the igp phy */ 2880 /* optimize the dsp settings for the igp phy */
2866 e1000_config_dsp_after_link_change(hw, TRUE); 2881 e1000_config_dsp_after_link_change(hw, TRUE);
@@ -2873,11 +2888,11 @@ e1000_check_for_link(struct e1000_hw *hw)
2873 * speed/duplex on the MAC to the current PHY speed/duplex 2888 * speed/duplex on the MAC to the current PHY speed/duplex
2874 * settings. 2889 * settings.
2875 */ 2890 */
2876 if(hw->mac_type >= e1000_82544) 2891 if (hw->mac_type >= e1000_82544)
2877 e1000_config_collision_dist(hw); 2892 e1000_config_collision_dist(hw);
2878 else { 2893 else {
2879 ret_val = e1000_config_mac_to_phy(hw); 2894 ret_val = e1000_config_mac_to_phy(hw);
2880 if(ret_val) { 2895 if (ret_val) {
2881 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2896 DEBUGOUT("Error configuring MAC to PHY settings\n");
2882 return ret_val; 2897 return ret_val;
2883 } 2898 }
@@ -2888,7 +2903,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2888 * have had to re-autoneg with a different link partner. 2903 * have had to re-autoneg with a different link partner.
2889 */ 2904 */
2890 ret_val = e1000_config_fc_after_link_up(hw); 2905 ret_val = e1000_config_fc_after_link_up(hw);
2891 if(ret_val) { 2906 if (ret_val) {
2892 DEBUGOUT("Error configuring flow control\n"); 2907 DEBUGOUT("Error configuring flow control\n");
2893 return ret_val; 2908 return ret_val;
2894 } 2909 }
@@ -2900,7 +2915,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2900 * at gigabit speed, then TBI compatibility is not needed. If we are 2915 * at gigabit speed, then TBI compatibility is not needed. If we are
2901 * at gigabit speed, we turn on TBI compatibility. 2916 * at gigabit speed, we turn on TBI compatibility.
2902 */ 2917 */
2903 if(hw->tbi_compatibility_en) { 2918 if (hw->tbi_compatibility_en) {
2904 uint16_t speed, duplex; 2919 uint16_t speed, duplex;
2905 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2920 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2906 if (ret_val) { 2921 if (ret_val) {
@@ -2911,7 +2926,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2911 /* If link speed is not set to gigabit speed, we do not need 2926 /* If link speed is not set to gigabit speed, we do not need
2912 * to enable TBI compatibility. 2927 * to enable TBI compatibility.
2913 */ 2928 */
2914 if(hw->tbi_compatibility_on) { 2929 if (hw->tbi_compatibility_on) {
2915 /* If we previously were in the mode, turn it off. */ 2930 /* If we previously were in the mode, turn it off. */
2916 rctl = E1000_READ_REG(hw, RCTL); 2931 rctl = E1000_READ_REG(hw, RCTL);
2917 rctl &= ~E1000_RCTL_SBP; 2932 rctl &= ~E1000_RCTL_SBP;
@@ -2924,7 +2939,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2924 * packets. Some frames have an additional byte on the end and 2939 * packets. Some frames have an additional byte on the end and
2925 * will look like CRC errors to to the hardware. 2940 * will look like CRC errors to to the hardware.
2926 */ 2941 */
2927 if(!hw->tbi_compatibility_on) { 2942 if (!hw->tbi_compatibility_on) {
2928 hw->tbi_compatibility_on = TRUE; 2943 hw->tbi_compatibility_on = TRUE;
2929 rctl = E1000_READ_REG(hw, RCTL); 2944 rctl = E1000_READ_REG(hw, RCTL);
2930 rctl |= E1000_RCTL_SBP; 2945 rctl |= E1000_RCTL_SBP;
@@ -2940,12 +2955,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2940 * auto-negotiation time to complete, in case the cable was just plugged 2955 * auto-negotiation time to complete, in case the cable was just plugged
2941 * in. The autoneg_failed flag does this. 2956 * in. The autoneg_failed flag does this.
2942 */ 2957 */
2943 else if((((hw->media_type == e1000_media_type_fiber) && 2958 else if ((((hw->media_type == e1000_media_type_fiber) &&
2944 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 2959 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2945 (hw->media_type == e1000_media_type_internal_serdes)) && 2960 (hw->media_type == e1000_media_type_internal_serdes)) &&
2946 (!(status & E1000_STATUS_LU)) && 2961 (!(status & E1000_STATUS_LU)) &&
2947 (!(rxcw & E1000_RXCW_C))) { 2962 (!(rxcw & E1000_RXCW_C))) {
2948 if(hw->autoneg_failed == 0) { 2963 if (hw->autoneg_failed == 0) {
2949 hw->autoneg_failed = 1; 2964 hw->autoneg_failed = 1;
2950 return 0; 2965 return 0;
2951 } 2966 }
@@ -2961,7 +2976,7 @@ e1000_check_for_link(struct e1000_hw *hw)
2961 2976
2962 /* Configure Flow Control after forcing link up. */ 2977 /* Configure Flow Control after forcing link up. */
2963 ret_val = e1000_config_fc_after_link_up(hw); 2978 ret_val = e1000_config_fc_after_link_up(hw);
2964 if(ret_val) { 2979 if (ret_val) {
2965 DEBUGOUT("Error configuring flow control\n"); 2980 DEBUGOUT("Error configuring flow control\n");
2966 return ret_val; 2981 return ret_val;
2967 } 2982 }
@@ -2971,9 +2986,9 @@ e1000_check_for_link(struct e1000_hw *hw)
2971 * Device Control register in an attempt to auto-negotiate with our link 2986 * Device Control register in an attempt to auto-negotiate with our link
2972 * partner. 2987 * partner.
2973 */ 2988 */
2974 else if(((hw->media_type == e1000_media_type_fiber) || 2989 else if (((hw->media_type == e1000_media_type_fiber) ||
2975 (hw->media_type == e1000_media_type_internal_serdes)) && 2990 (hw->media_type == e1000_media_type_internal_serdes)) &&
2976 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 2991 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2977 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 2992 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2978 E1000_WRITE_REG(hw, TXCW, hw->txcw); 2993 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2979 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 2994 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2983,12 +2998,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2983 /* If we force link for non-auto-negotiation switch, check link status 2998 /* If we force link for non-auto-negotiation switch, check link status
2984 * based on MAC synchronization for internal serdes media type. 2999 * based on MAC synchronization for internal serdes media type.
2985 */ 3000 */
2986 else if((hw->media_type == e1000_media_type_internal_serdes) && 3001 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
2987 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3002 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2988 /* SYNCH bit and IV bit are sticky. */ 3003 /* SYNCH bit and IV bit are sticky. */
2989 udelay(10); 3004 udelay(10);
2990 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3005 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2991 if(!(rxcw & E1000_RXCW_IV)) { 3006 if (!(rxcw & E1000_RXCW_IV)) {
2992 hw->serdes_link_down = FALSE; 3007 hw->serdes_link_down = FALSE;
2993 DEBUGOUT("SERDES: Link is up.\n"); 3008 DEBUGOUT("SERDES: Link is up.\n");
2994 } 3009 }
@@ -2997,8 +3012,8 @@ e1000_check_for_link(struct e1000_hw *hw)
2997 DEBUGOUT("SERDES: Link is down.\n"); 3012 DEBUGOUT("SERDES: Link is down.\n");
2998 } 3013 }
2999 } 3014 }
3000 if((hw->media_type == e1000_media_type_internal_serdes) && 3015 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3001 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3016 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3002 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3017 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3003 } 3018 }
3004 return E1000_SUCCESS; 3019 return E1000_SUCCESS;
@@ -3022,12 +3037,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3022 3037
3023 DEBUGFUNC("e1000_get_speed_and_duplex"); 3038 DEBUGFUNC("e1000_get_speed_and_duplex");
3024 3039
3025 if(hw->mac_type >= e1000_82543) { 3040 if (hw->mac_type >= e1000_82543) {
3026 status = E1000_READ_REG(hw, STATUS); 3041 status = E1000_READ_REG(hw, STATUS);
3027 if(status & E1000_STATUS_SPEED_1000) { 3042 if (status & E1000_STATUS_SPEED_1000) {
3028 *speed = SPEED_1000; 3043 *speed = SPEED_1000;
3029 DEBUGOUT("1000 Mbs, "); 3044 DEBUGOUT("1000 Mbs, ");
3030 } else if(status & E1000_STATUS_SPEED_100) { 3045 } else if (status & E1000_STATUS_SPEED_100) {
3031 *speed = SPEED_100; 3046 *speed = SPEED_100;
3032 DEBUGOUT("100 Mbs, "); 3047 DEBUGOUT("100 Mbs, ");
3033 } else { 3048 } else {
@@ -3035,7 +3050,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3035 DEBUGOUT("10 Mbs, "); 3050 DEBUGOUT("10 Mbs, ");
3036 } 3051 }
3037 3052
3038 if(status & E1000_STATUS_FD) { 3053 if (status & E1000_STATUS_FD) {
3039 *duplex = FULL_DUPLEX; 3054 *duplex = FULL_DUPLEX;
3040 DEBUGOUT("Full Duplex\n"); 3055 DEBUGOUT("Full Duplex\n");
3041 } else { 3056 } else {
@@ -3052,18 +3067,18 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
3052 * if it is operating at half duplex. Here we set the duplex settings to 3067 * if it is operating at half duplex. Here we set the duplex settings to
3053 * match the duplex in the link partner's capabilities. 3068 * match the duplex in the link partner's capabilities.
3054 */ 3069 */
3055 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 3070 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3056 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 3071 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3057 if(ret_val) 3072 if (ret_val)
3058 return ret_val; 3073 return ret_val;
3059 3074
3060 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 3075 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3061 *duplex = HALF_DUPLEX; 3076 *duplex = HALF_DUPLEX;
3062 else { 3077 else {
3063 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 3078 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3064 if(ret_val) 3079 if (ret_val)
3065 return ret_val; 3080 return ret_val;
3066 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 3081 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3067 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 3082 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3068 *duplex = HALF_DUPLEX; 3083 *duplex = HALF_DUPLEX;
3069 } 3084 }
@@ -3104,20 +3119,20 @@ e1000_wait_autoneg(struct e1000_hw *hw)
3104 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 3119 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3105 3120
3106 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 3121 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3107 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { 3122 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3108 /* Read the MII Status Register and wait for Auto-Neg 3123 /* Read the MII Status Register and wait for Auto-Neg
3109 * Complete bit to be set. 3124 * Complete bit to be set.
3110 */ 3125 */
3111 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3112 if(ret_val) 3127 if (ret_val)
3113 return ret_val; 3128 return ret_val;
3114 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3115 if(ret_val) 3130 if (ret_val)
3116 return ret_val; 3131 return ret_val;
3117 if(phy_data & MII_SR_AUTONEG_COMPLETE) { 3132 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3118 return E1000_SUCCESS; 3133 return E1000_SUCCESS;
3119 } 3134 }
3120 msec_delay(100); 3135 msleep(100);
3121 } 3136 }
3122 return E1000_SUCCESS; 3137 return E1000_SUCCESS;
3123} 3138}
@@ -3187,14 +3202,16 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3187 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3202 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3188 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3203 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3189 3204
3190 while(mask) { 3205 while (mask) {
3191 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 3206 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3192 * then raising and lowering the Management Data Clock. A "0" is 3207 * then raising and lowering the Management Data Clock. A "0" is
3193 * shifted out to the PHY by setting the MDIO bit to "0" and then 3208 * shifted out to the PHY by setting the MDIO bit to "0" and then
3194 * raising and lowering the clock. 3209 * raising and lowering the clock.
3195 */ 3210 */
3196 if(data & mask) ctrl |= E1000_CTRL_MDIO; 3211 if (data & mask)
3197 else ctrl &= ~E1000_CTRL_MDIO; 3212 ctrl |= E1000_CTRL_MDIO;
3213 else
3214 ctrl &= ~E1000_CTRL_MDIO;
3198 3215
3199 E1000_WRITE_REG(hw, CTRL, ctrl); 3216 E1000_WRITE_REG(hw, CTRL, ctrl);
3200 E1000_WRITE_FLUSH(hw); 3217 E1000_WRITE_FLUSH(hw);
@@ -3245,12 +3262,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3245 e1000_raise_mdi_clk(hw, &ctrl); 3262 e1000_raise_mdi_clk(hw, &ctrl);
3246 e1000_lower_mdi_clk(hw, &ctrl); 3263 e1000_lower_mdi_clk(hw, &ctrl);
3247 3264
3248 for(data = 0, i = 0; i < 16; i++) { 3265 for (data = 0, i = 0; i < 16; i++) {
3249 data = data << 1; 3266 data = data << 1;
3250 e1000_raise_mdi_clk(hw, &ctrl); 3267 e1000_raise_mdi_clk(hw, &ctrl);
3251 ctrl = E1000_READ_REG(hw, CTRL); 3268 ctrl = E1000_READ_REG(hw, CTRL);
3252 /* Check to see if we shifted in a "1". */ 3269 /* Check to see if we shifted in a "1". */
3253 if(ctrl & E1000_CTRL_MDIO) data |= 1; 3270 if (ctrl & E1000_CTRL_MDIO)
3271 data |= 1;
3254 e1000_lower_mdi_clk(hw, &ctrl); 3272 e1000_lower_mdi_clk(hw, &ctrl);
3255 } 3273 }
3256 3274
@@ -3276,7 +3294,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3276 if (!hw->swfw_sync_present) 3294 if (!hw->swfw_sync_present)
3277 return e1000_get_hw_eeprom_semaphore(hw); 3295 return e1000_get_hw_eeprom_semaphore(hw);
3278 3296
3279 while(timeout) { 3297 while (timeout) {
3280 if (e1000_get_hw_eeprom_semaphore(hw)) 3298 if (e1000_get_hw_eeprom_semaphore(hw))
3281 return -E1000_ERR_SWFW_SYNC; 3299 return -E1000_ERR_SWFW_SYNC;
3282 3300
@@ -3288,7 +3306,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3288 /* firmware currently using resource (fwmask) */ 3306 /* firmware currently using resource (fwmask) */
3289 /* or other software thread currently using resource (swmask) */ 3307 /* or other software thread currently using resource (swmask) */
3290 e1000_put_hw_eeprom_semaphore(hw); 3308 e1000_put_hw_eeprom_semaphore(hw);
3291 msec_delay_irq(5); 3309 mdelay(5);
3292 timeout--; 3310 timeout--;
3293 } 3311 }
3294 3312
@@ -3365,7 +3383,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3365 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3383 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3366 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3384 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3367 (uint16_t)reg_addr); 3385 (uint16_t)reg_addr);
3368 if(ret_val) { 3386 if (ret_val) {
3369 e1000_swfw_sync_release(hw, swfw); 3387 e1000_swfw_sync_release(hw, swfw);
3370 return ret_val; 3388 return ret_val;
3371 } 3389 }
@@ -3410,12 +3428,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3410 3428
3411 DEBUGFUNC("e1000_read_phy_reg_ex"); 3429 DEBUGFUNC("e1000_read_phy_reg_ex");
3412 3430
3413 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3431 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3414 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3432 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3415 return -E1000_ERR_PARAM; 3433 return -E1000_ERR_PARAM;
3416 } 3434 }
3417 3435
3418 if(hw->mac_type > e1000_82543) { 3436 if (hw->mac_type > e1000_82543) {
3419 /* Set up Op-code, Phy Address, and register address in the MDI 3437 /* Set up Op-code, Phy Address, and register address in the MDI
3420 * Control register. The MAC will take care of interfacing with the 3438 * Control register. The MAC will take care of interfacing with the
3421 * PHY to retrieve the desired data. 3439 * PHY to retrieve the desired data.
@@ -3427,16 +3445,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3427 E1000_WRITE_REG(hw, MDIC, mdic); 3445 E1000_WRITE_REG(hw, MDIC, mdic);
3428 3446
3429 /* Poll the ready bit to see if the MDI read completed */ 3447 /* Poll the ready bit to see if the MDI read completed */
3430 for(i = 0; i < 64; i++) { 3448 for (i = 0; i < 64; i++) {
3431 udelay(50); 3449 udelay(50);
3432 mdic = E1000_READ_REG(hw, MDIC); 3450 mdic = E1000_READ_REG(hw, MDIC);
3433 if(mdic & E1000_MDIC_READY) break; 3451 if (mdic & E1000_MDIC_READY) break;
3434 } 3452 }
3435 if(!(mdic & E1000_MDIC_READY)) { 3453 if (!(mdic & E1000_MDIC_READY)) {
3436 DEBUGOUT("MDI Read did not complete\n"); 3454 DEBUGOUT("MDI Read did not complete\n");
3437 return -E1000_ERR_PHY; 3455 return -E1000_ERR_PHY;
3438 } 3456 }
3439 if(mdic & E1000_MDIC_ERROR) { 3457 if (mdic & E1000_MDIC_ERROR) {
3440 DEBUGOUT("MDI Error\n"); 3458 DEBUGOUT("MDI Error\n");
3441 return -E1000_ERR_PHY; 3459 return -E1000_ERR_PHY;
3442 } 3460 }
@@ -3505,7 +3523,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3505 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3523 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3506 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3524 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3507 (uint16_t)reg_addr); 3525 (uint16_t)reg_addr);
3508 if(ret_val) { 3526 if (ret_val) {
3509 e1000_swfw_sync_release(hw, swfw); 3527 e1000_swfw_sync_release(hw, swfw);
3510 return ret_val; 3528 return ret_val;
3511 } 3529 }
@@ -3550,12 +3568,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3550 3568
3551 DEBUGFUNC("e1000_write_phy_reg_ex"); 3569 DEBUGFUNC("e1000_write_phy_reg_ex");
3552 3570
3553 if(reg_addr > MAX_PHY_REG_ADDRESS) { 3571 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3554 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 3572 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3555 return -E1000_ERR_PARAM; 3573 return -E1000_ERR_PARAM;
3556 } 3574 }
3557 3575
3558 if(hw->mac_type > e1000_82543) { 3576 if (hw->mac_type > e1000_82543) {
3559 /* Set up Op-code, Phy Address, register address, and data intended 3577 /* Set up Op-code, Phy Address, register address, and data intended
3560 * for the PHY register in the MDI Control register. The MAC will take 3578 * for the PHY register in the MDI Control register. The MAC will take
3561 * care of interfacing with the PHY to send the desired data. 3579 * care of interfacing with the PHY to send the desired data.
@@ -3568,12 +3586,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3568 E1000_WRITE_REG(hw, MDIC, mdic); 3586 E1000_WRITE_REG(hw, MDIC, mdic);
3569 3587
3570 /* Poll the ready bit to see if the MDI read completed */ 3588 /* Poll the ready bit to see if the MDI read completed */
3571 for(i = 0; i < 640; i++) { 3589 for (i = 0; i < 641; i++) {
3572 udelay(5); 3590 udelay(5);
3573 mdic = E1000_READ_REG(hw, MDIC); 3591 mdic = E1000_READ_REG(hw, MDIC);
3574 if(mdic & E1000_MDIC_READY) break; 3592 if (mdic & E1000_MDIC_READY) break;
3575 } 3593 }
3576 if(!(mdic & E1000_MDIC_READY)) { 3594 if (!(mdic & E1000_MDIC_READY)) {
3577 DEBUGOUT("MDI Write did not complete\n"); 3595 DEBUGOUT("MDI Write did not complete\n");
3578 return -E1000_ERR_PHY; 3596 return -E1000_ERR_PHY;
3579 } 3597 }
@@ -3685,7 +3703,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3685 3703
3686 DEBUGOUT("Resetting Phy...\n"); 3704 DEBUGOUT("Resetting Phy...\n");
3687 3705
3688 if(hw->mac_type > e1000_82543) { 3706 if (hw->mac_type > e1000_82543) {
3689 if ((hw->mac_type == e1000_80003es2lan) && 3707 if ((hw->mac_type == e1000_80003es2lan) &&
3690 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3708 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3691 swfw = E1000_SWFW_PHY1_SM; 3709 swfw = E1000_SWFW_PHY1_SM;
@@ -3707,7 +3725,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3707 E1000_WRITE_FLUSH(hw); 3725 E1000_WRITE_FLUSH(hw);
3708 3726
3709 if (hw->mac_type < e1000_82571) 3727 if (hw->mac_type < e1000_82571)
3710 msec_delay(10); 3728 msleep(10);
3711 else 3729 else
3712 udelay(100); 3730 udelay(100);
3713 3731
@@ -3715,7 +3733,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3715 E1000_WRITE_FLUSH(hw); 3733 E1000_WRITE_FLUSH(hw);
3716 3734
3717 if (hw->mac_type >= e1000_82571) 3735 if (hw->mac_type >= e1000_82571)
3718 msec_delay_irq(10); 3736 mdelay(10);
3719 e1000_swfw_sync_release(hw, swfw); 3737 e1000_swfw_sync_release(hw, swfw);
3720 } else { 3738 } else {
3721 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3739 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3726,14 +3744,14 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3726 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3744 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3727 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3745 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3728 E1000_WRITE_FLUSH(hw); 3746 E1000_WRITE_FLUSH(hw);
3729 msec_delay(10); 3747 msleep(10);
3730 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3748 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3731 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3749 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3732 E1000_WRITE_FLUSH(hw); 3750 E1000_WRITE_FLUSH(hw);
3733 } 3751 }
3734 udelay(150); 3752 udelay(150);
3735 3753
3736 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3754 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3737 /* Configure activity LED after PHY reset */ 3755 /* Configure activity LED after PHY reset */
3738 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3756 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3739 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3757 led_ctrl &= IGP_ACTIVITY_LED_MASK;
@@ -3743,14 +3761,13 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3743 3761
3744 /* Wait for FW to finish PHY configuration. */ 3762 /* Wait for FW to finish PHY configuration. */
3745 ret_val = e1000_get_phy_cfg_done(hw); 3763 ret_val = e1000_get_phy_cfg_done(hw);
3764 if (ret_val != E1000_SUCCESS)
3765 return ret_val;
3746 e1000_release_software_semaphore(hw); 3766 e1000_release_software_semaphore(hw);
3747 3767
3748 if ((hw->mac_type == e1000_ich8lan) && 3768 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3749 (hw->phy_type == e1000_phy_igp_3)) { 3769 ret_val = e1000_init_lcd_from_nvm(hw);
3750 ret_val = e1000_init_lcd_from_nvm(hw); 3770
3751 if (ret_val)
3752 return ret_val;
3753 }
3754 return ret_val; 3771 return ret_val;
3755} 3772}
3756 3773
@@ -3781,25 +3798,25 @@ e1000_phy_reset(struct e1000_hw *hw)
3781 case e1000_82572: 3798 case e1000_82572:
3782 case e1000_ich8lan: 3799 case e1000_ich8lan:
3783 ret_val = e1000_phy_hw_reset(hw); 3800 ret_val = e1000_phy_hw_reset(hw);
3784 if(ret_val) 3801 if (ret_val)
3785 return ret_val; 3802 return ret_val;
3786 3803
3787 break; 3804 break;
3788 default: 3805 default:
3789 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3806 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3790 if(ret_val) 3807 if (ret_val)
3791 return ret_val; 3808 return ret_val;
3792 3809
3793 phy_data |= MII_CR_RESET; 3810 phy_data |= MII_CR_RESET;
3794 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 3811 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3795 if(ret_val) 3812 if (ret_val)
3796 return ret_val; 3813 return ret_val;
3797 3814
3798 udelay(1); 3815 udelay(1);
3799 break; 3816 break;
3800 } 3817 }
3801 3818
3802 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) 3819 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3803 e1000_phy_init_script(hw); 3820 e1000_phy_init_script(hw);
3804 3821
3805 return E1000_SUCCESS; 3822 return E1000_SUCCESS;
@@ -3877,8 +3894,8 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3877 if (hw->kmrn_lock_loss_workaround_disabled) 3894 if (hw->kmrn_lock_loss_workaround_disabled)
3878 return E1000_SUCCESS; 3895 return E1000_SUCCESS;
3879 3896
3880 /* Make sure link is up before proceeding. If not just return. 3897 /* Make sure link is up before proceeding. If not just return.
3881 * Attempting this while link is negotiating fouls up link 3898 * Attempting this while link is negotiating fouled up link
3882 * stability */ 3899 * stability */
3883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3884 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3901 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
@@ -3900,7 +3917,7 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3900 3917
3901 /* Issue PHY reset */ 3918 /* Issue PHY reset */
3902 e1000_phy_hw_reset(hw); 3919 e1000_phy_hw_reset(hw);
3903 msec_delay_irq(5); 3920 mdelay(5);
3904 } 3921 }
3905 /* Disable GigE link negotiation */ 3922 /* Disable GigE link negotiation */
3906 reg = E1000_READ_REG(hw, PHY_CTRL); 3923 reg = E1000_READ_REG(hw, PHY_CTRL);
@@ -3955,34 +3972,34 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3955 hw->phy_id = (uint32_t) (phy_id_high << 16); 3972 hw->phy_id = (uint32_t) (phy_id_high << 16);
3956 udelay(20); 3973 udelay(20);
3957 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3974 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3958 if(ret_val) 3975 if (ret_val)
3959 return ret_val; 3976 return ret_val;
3960 3977
3961 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 3978 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3962 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 3979 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3963 3980
3964 switch(hw->mac_type) { 3981 switch (hw->mac_type) {
3965 case e1000_82543: 3982 case e1000_82543:
3966 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; 3983 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3967 break; 3984 break;
3968 case e1000_82544: 3985 case e1000_82544:
3969 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; 3986 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3970 break; 3987 break;
3971 case e1000_82540: 3988 case e1000_82540:
3972 case e1000_82545: 3989 case e1000_82545:
3973 case e1000_82545_rev_3: 3990 case e1000_82545_rev_3:
3974 case e1000_82546: 3991 case e1000_82546:
3975 case e1000_82546_rev_3: 3992 case e1000_82546_rev_3:
3976 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; 3993 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3977 break; 3994 break;
3978 case e1000_82541: 3995 case e1000_82541:
3979 case e1000_82541_rev_2: 3996 case e1000_82541_rev_2:
3980 case e1000_82547: 3997 case e1000_82547:
3981 case e1000_82547_rev_2: 3998 case e1000_82547_rev_2:
3982 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3999 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3983 break; 4000 break;
3984 case e1000_82573: 4001 case e1000_82573:
3985 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; 4002 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3986 break; 4003 break;
3987 case e1000_80003es2lan: 4004 case e1000_80003es2lan:
3988 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 4005 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
@@ -4021,14 +4038,14 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
4021 do { 4038 do {
4022 if (hw->phy_type != e1000_phy_gg82563) { 4039 if (hw->phy_type != e1000_phy_gg82563) {
4023 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 4040 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4024 if(ret_val) break; 4041 if (ret_val) break;
4025 } 4042 }
4026 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 4043 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4027 if(ret_val) break; 4044 if (ret_val) break;
4028 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 4045 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4029 if(ret_val) break; 4046 if (ret_val) break;
4030 ret_val = E1000_SUCCESS; 4047 ret_val = E1000_SUCCESS;
4031 } while(0); 4048 } while (0);
4032 4049
4033 return ret_val; 4050 return ret_val;
4034} 4051}
@@ -4060,23 +4077,23 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4060 4077
4061 /* Check polarity status */ 4078 /* Check polarity status */
4062 ret_val = e1000_check_polarity(hw, &polarity); 4079 ret_val = e1000_check_polarity(hw, &polarity);
4063 if(ret_val) 4080 if (ret_val)
4064 return ret_val; 4081 return ret_val;
4065 4082
4066 phy_info->cable_polarity = polarity; 4083 phy_info->cable_polarity = polarity;
4067 4084
4068 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 4085 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4069 if(ret_val) 4086 if (ret_val)
4070 return ret_val; 4087 return ret_val;
4071 4088
4072 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> 4089 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4073 IGP01E1000_PSSR_MDIX_SHIFT; 4090 IGP01E1000_PSSR_MDIX_SHIFT;
4074 4091
4075 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4092 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4076 IGP01E1000_PSSR_SPEED_1000MBPS) { 4093 IGP01E1000_PSSR_SPEED_1000MBPS) {
4077 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 4094 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4078 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4095 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4079 if(ret_val) 4096 if (ret_val)
4080 return ret_val; 4097 return ret_val;
4081 4098
4082 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4099 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4086,19 +4103,19 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4086 4103
4087 /* Get cable length */ 4104 /* Get cable length */
4088 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 4105 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4089 if(ret_val) 4106 if (ret_val)
4090 return ret_val; 4107 return ret_val;
4091 4108
4092 /* Translate to old method */ 4109 /* Translate to old method */
4093 average = (max_length + min_length) / 2; 4110 average = (max_length + min_length) / 2;
4094 4111
4095 if(average <= e1000_igp_cable_length_50) 4112 if (average <= e1000_igp_cable_length_50)
4096 phy_info->cable_length = e1000_cable_length_50; 4113 phy_info->cable_length = e1000_cable_length_50;
4097 else if(average <= e1000_igp_cable_length_80) 4114 else if (average <= e1000_igp_cable_length_80)
4098 phy_info->cable_length = e1000_cable_length_50_80; 4115 phy_info->cable_length = e1000_cable_length_50_80;
4099 else if(average <= e1000_igp_cable_length_110) 4116 else if (average <= e1000_igp_cable_length_110)
4100 phy_info->cable_length = e1000_cable_length_80_110; 4117 phy_info->cable_length = e1000_cable_length_80_110;
4101 else if(average <= e1000_igp_cable_length_140) 4118 else if (average <= e1000_igp_cable_length_140)
4102 phy_info->cable_length = e1000_cable_length_110_140; 4119 phy_info->cable_length = e1000_cable_length_110_140;
4103 else 4120 else
4104 phy_info->cable_length = e1000_cable_length_140; 4121 phy_info->cable_length = e1000_cable_length_140;
@@ -4174,7 +4191,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4174 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 4191 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4175 4192
4176 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4177 if(ret_val) 4194 if (ret_val)
4178 return ret_val; 4195 return ret_val;
4179 4196
4180 phy_info->extended_10bt_distance = 4197 phy_info->extended_10bt_distance =
@@ -4186,12 +4203,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4186 4203
4187 /* Check polarity status */ 4204 /* Check polarity status */
4188 ret_val = e1000_check_polarity(hw, &polarity); 4205 ret_val = e1000_check_polarity(hw, &polarity);
4189 if(ret_val) 4206 if (ret_val)
4190 return ret_val; 4207 return ret_val;
4191 phy_info->cable_polarity = polarity; 4208 phy_info->cable_polarity = polarity;
4192 4209
4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 4210 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4194 if(ret_val) 4211 if (ret_val)
4195 return ret_val; 4212 return ret_val;
4196 4213
4197 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> 4214 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -4214,7 +4231,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4214 } 4231 }
4215 4232
4216 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4233 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4217 if(ret_val) 4234 if (ret_val)
4218 return ret_val; 4235 return ret_val;
4219 4236
4220 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4237 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4251,20 +4268,20 @@ e1000_phy_get_info(struct e1000_hw *hw,
4251 phy_info->local_rx = e1000_1000t_rx_status_undefined; 4268 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4252 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 4269 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4253 4270
4254 if(hw->media_type != e1000_media_type_copper) { 4271 if (hw->media_type != e1000_media_type_copper) {
4255 DEBUGOUT("PHY info is only valid for copper media\n"); 4272 DEBUGOUT("PHY info is only valid for copper media\n");
4256 return -E1000_ERR_CONFIG; 4273 return -E1000_ERR_CONFIG;
4257 } 4274 }
4258 4275
4259 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4276 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4260 if(ret_val) 4277 if (ret_val)
4261 return ret_val; 4278 return ret_val;
4262 4279
4263 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 4280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4264 if(ret_val) 4281 if (ret_val)
4265 return ret_val; 4282 return ret_val;
4266 4283
4267 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 4284 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4268 DEBUGOUT("PHY info is only valid if link is up\n"); 4285 DEBUGOUT("PHY info is only valid if link is up\n");
4269 return -E1000_ERR_CONFIG; 4286 return -E1000_ERR_CONFIG;
4270 } 4287 }
@@ -4284,7 +4301,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
4284{ 4301{
4285 DEBUGFUNC("e1000_validate_mdi_settings"); 4302 DEBUGFUNC("e1000_validate_mdi_settings");
4286 4303
4287 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { 4304 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4288 DEBUGOUT("Invalid MDI setting detected\n"); 4305 DEBUGOUT("Invalid MDI setting detected\n");
4289 hw->mdix = 1; 4306 hw->mdix = 1;
4290 return -E1000_ERR_CONFIG; 4307 return -E1000_ERR_CONFIG;
@@ -4331,7 +4348,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4331 eeprom->type = e1000_eeprom_microwire; 4348 eeprom->type = e1000_eeprom_microwire;
4332 eeprom->opcode_bits = 3; 4349 eeprom->opcode_bits = 3;
4333 eeprom->delay_usec = 50; 4350 eeprom->delay_usec = 50;
4334 if(eecd & E1000_EECD_SIZE) { 4351 if (eecd & E1000_EECD_SIZE) {
4335 eeprom->word_size = 256; 4352 eeprom->word_size = 256;
4336 eeprom->address_bits = 8; 4353 eeprom->address_bits = 8;
4337 } else { 4354 } else {
@@ -4399,7 +4416,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4399 } 4416 }
4400 eeprom->use_eerd = TRUE; 4417 eeprom->use_eerd = TRUE;
4401 eeprom->use_eewr = TRUE; 4418 eeprom->use_eewr = TRUE;
4402 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { 4419 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4403 eeprom->type = e1000_eeprom_flash; 4420 eeprom->type = e1000_eeprom_flash;
4404 eeprom->word_size = 2048; 4421 eeprom->word_size = 2048;
4405 4422
@@ -4460,17 +4477,17 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4460 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 4477 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4461 * 32KB (incremented by powers of 2). 4478 * 32KB (incremented by powers of 2).
4462 */ 4479 */
4463 if(hw->mac_type <= e1000_82547_rev_2) { 4480 if (hw->mac_type <= e1000_82547_rev_2) {
4464 /* Set to default value for initial eeprom read. */ 4481 /* Set to default value for initial eeprom read. */
4465 eeprom->word_size = 64; 4482 eeprom->word_size = 64;
4466 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 4483 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4467 if(ret_val) 4484 if (ret_val)
4468 return ret_val; 4485 return ret_val;
4469 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 4486 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4470 /* 256B eeprom size was not supported in earlier hardware, so we 4487 /* 256B eeprom size was not supported in earlier hardware, so we
4471 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 4488 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4472 * is never the result used in the shifting logic below. */ 4489 * is never the result used in the shifting logic below. */
4473 if(eeprom_size) 4490 if (eeprom_size)
4474 eeprom_size++; 4491 eeprom_size++;
4475 } else { 4492 } else {
4476 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> 4493 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
@@ -4555,7 +4572,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4555 */ 4572 */
4556 eecd &= ~E1000_EECD_DI; 4573 eecd &= ~E1000_EECD_DI;
4557 4574
4558 if(data & mask) 4575 if (data & mask)
4559 eecd |= E1000_EECD_DI; 4576 eecd |= E1000_EECD_DI;
4560 4577
4561 E1000_WRITE_REG(hw, EECD, eecd); 4578 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4568,7 +4585,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
4568 4585
4569 mask = mask >> 1; 4586 mask = mask >> 1;
4570 4587
4571 } while(mask); 4588 } while (mask);
4572 4589
4573 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4590 /* We leave the "DI" bit set to "0" when we leave this routine. */
4574 eecd &= ~E1000_EECD_DI; 4591 eecd &= ~E1000_EECD_DI;
@@ -4600,14 +4617,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
4600 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4617 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4601 data = 0; 4618 data = 0;
4602 4619
4603 for(i = 0; i < count; i++) { 4620 for (i = 0; i < count; i++) {
4604 data = data << 1; 4621 data = data << 1;
4605 e1000_raise_ee_clk(hw, &eecd); 4622 e1000_raise_ee_clk(hw, &eecd);
4606 4623
4607 eecd = E1000_READ_REG(hw, EECD); 4624 eecd = E1000_READ_REG(hw, EECD);
4608 4625
4609 eecd &= ~(E1000_EECD_DI); 4626 eecd &= ~(E1000_EECD_DI);
4610 if(eecd & E1000_EECD_DO) 4627 if (eecd & E1000_EECD_DO)
4611 data |= 1; 4628 data |= 1;
4612 4629
4613 e1000_lower_ee_clk(hw, &eecd); 4630 e1000_lower_ee_clk(hw, &eecd);
@@ -4638,17 +4655,17 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
4638 4655
4639 if (hw->mac_type != e1000_82573) { 4656 if (hw->mac_type != e1000_82573) {
4640 /* Request EEPROM Access */ 4657 /* Request EEPROM Access */
4641 if(hw->mac_type > e1000_82544) { 4658 if (hw->mac_type > e1000_82544) {
4642 eecd |= E1000_EECD_REQ; 4659 eecd |= E1000_EECD_REQ;
4643 E1000_WRITE_REG(hw, EECD, eecd); 4660 E1000_WRITE_REG(hw, EECD, eecd);
4644 eecd = E1000_READ_REG(hw, EECD); 4661 eecd = E1000_READ_REG(hw, EECD);
4645 while((!(eecd & E1000_EECD_GNT)) && 4662 while ((!(eecd & E1000_EECD_GNT)) &&
4646 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4663 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4647 i++; 4664 i++;
4648 udelay(5); 4665 udelay(5);
4649 eecd = E1000_READ_REG(hw, EECD); 4666 eecd = E1000_READ_REG(hw, EECD);
4650 } 4667 }
4651 if(!(eecd & E1000_EECD_GNT)) { 4668 if (!(eecd & E1000_EECD_GNT)) {
4652 eecd &= ~E1000_EECD_REQ; 4669 eecd &= ~E1000_EECD_REQ;
4653 E1000_WRITE_REG(hw, EECD, eecd); 4670 E1000_WRITE_REG(hw, EECD, eecd);
4654 DEBUGOUT("Could not acquire EEPROM grant\n"); 4671 DEBUGOUT("Could not acquire EEPROM grant\n");
@@ -4691,7 +4708,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4691 4708
4692 eecd = E1000_READ_REG(hw, EECD); 4709 eecd = E1000_READ_REG(hw, EECD);
4693 4710
4694 if(eeprom->type == e1000_eeprom_microwire) { 4711 if (eeprom->type == e1000_eeprom_microwire) {
4695 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4712 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4696 E1000_WRITE_REG(hw, EECD, eecd); 4713 E1000_WRITE_REG(hw, EECD, eecd);
4697 E1000_WRITE_FLUSH(hw); 4714 E1000_WRITE_FLUSH(hw);
@@ -4714,7 +4731,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
4714 E1000_WRITE_REG(hw, EECD, eecd); 4731 E1000_WRITE_REG(hw, EECD, eecd);
4715 E1000_WRITE_FLUSH(hw); 4732 E1000_WRITE_FLUSH(hw);
4716 udelay(eeprom->delay_usec); 4733 udelay(eeprom->delay_usec);
4717 } else if(eeprom->type == e1000_eeprom_spi) { 4734 } else if (eeprom->type == e1000_eeprom_spi) {
4718 /* Toggle CS to flush commands */ 4735 /* Toggle CS to flush commands */
4719 eecd |= E1000_EECD_CS; 4736 eecd |= E1000_EECD_CS;
4720 E1000_WRITE_REG(hw, EECD, eecd); 4737 E1000_WRITE_REG(hw, EECD, eecd);
@@ -4748,7 +4765,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4748 E1000_WRITE_REG(hw, EECD, eecd); 4765 E1000_WRITE_REG(hw, EECD, eecd);
4749 4766
4750 udelay(hw->eeprom.delay_usec); 4767 udelay(hw->eeprom.delay_usec);
4751 } else if(hw->eeprom.type == e1000_eeprom_microwire) { 4768 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4752 /* cleanup eeprom */ 4769 /* cleanup eeprom */
4753 4770
4754 /* CS on Microwire is active-high */ 4771 /* CS on Microwire is active-high */
@@ -4770,7 +4787,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4770 } 4787 }
4771 4788
4772 /* Stop requesting EEPROM access */ 4789 /* Stop requesting EEPROM access */
4773 if(hw->mac_type > e1000_82544) { 4790 if (hw->mac_type > e1000_82544) {
4774 eecd &= ~E1000_EECD_REQ; 4791 eecd &= ~E1000_EECD_REQ;
4775 E1000_WRITE_REG(hw, EECD, eecd); 4792 E1000_WRITE_REG(hw, EECD, eecd);
4776 } 4793 }
@@ -4808,12 +4825,12 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
4808 retry_count += 5; 4825 retry_count += 5;
4809 4826
4810 e1000_standby_eeprom(hw); 4827 e1000_standby_eeprom(hw);
4811 } while(retry_count < EEPROM_MAX_RETRY_SPI); 4828 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4812 4829
4813 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 4830 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4814 * only 0-5mSec on 5V devices) 4831 * only 0-5mSec on 5V devices)
4815 */ 4832 */
4816 if(retry_count >= EEPROM_MAX_RETRY_SPI) { 4833 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4817 DEBUGOUT("SPI EEPROM Status error\n"); 4834 DEBUGOUT("SPI EEPROM Status error\n");
4818 return -E1000_ERR_EEPROM; 4835 return -E1000_ERR_EEPROM;
4819 } 4836 }
@@ -4844,7 +4861,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4844 /* A check for invalid values: offset too large, too many words, and not 4861 /* A check for invalid values: offset too large, too many words, and not
4845 * enough words. 4862 * enough words.
4846 */ 4863 */
4847 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4864 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4848 (words == 0)) { 4865 (words == 0)) {
4849 DEBUGOUT("\"words\" parameter out of bounds\n"); 4866 DEBUGOUT("\"words\" parameter out of bounds\n");
4850 return -E1000_ERR_EEPROM; 4867 return -E1000_ERR_EEPROM;
@@ -4852,7 +4869,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4852 4869
4853 /* FLASH reads without acquiring the semaphore are safe */ 4870 /* FLASH reads without acquiring the semaphore are safe */
4854 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4871 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4855 hw->eeprom.use_eerd == FALSE) { 4872 hw->eeprom.use_eerd == FALSE) {
4856 switch (hw->mac_type) { 4873 switch (hw->mac_type) {
4857 case e1000_80003es2lan: 4874 case e1000_80003es2lan:
4858 break; 4875 break;
@@ -4879,7 +4896,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4879 uint16_t word_in; 4896 uint16_t word_in;
4880 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4897 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4881 4898
4882 if(e1000_spi_eeprom_ready(hw)) { 4899 if (e1000_spi_eeprom_ready(hw)) {
4883 e1000_release_eeprom(hw); 4900 e1000_release_eeprom(hw);
4884 return -E1000_ERR_EEPROM; 4901 return -E1000_ERR_EEPROM;
4885 } 4902 }
@@ -4887,7 +4904,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4887 e1000_standby_eeprom(hw); 4904 e1000_standby_eeprom(hw);
4888 4905
4889 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4906 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4890 if((eeprom->address_bits == 8) && (offset >= 128)) 4907 if ((eeprom->address_bits == 8) && (offset >= 128))
4891 read_opcode |= EEPROM_A8_OPCODE_SPI; 4908 read_opcode |= EEPROM_A8_OPCODE_SPI;
4892 4909
4893 /* Send the READ command (opcode + addr) */ 4910 /* Send the READ command (opcode + addr) */
@@ -4903,7 +4920,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
4903 word_in = e1000_shift_in_ee_bits(hw, 16); 4920 word_in = e1000_shift_in_ee_bits(hw, 16);
4904 data[i] = (word_in >> 8) | (word_in << 8); 4921 data[i] = (word_in >> 8) | (word_in << 8);
4905 } 4922 }
4906 } else if(eeprom->type == e1000_eeprom_microwire) { 4923 } else if (eeprom->type == e1000_eeprom_microwire) {
4907 for (i = 0; i < words; i++) { 4924 for (i = 0; i < words; i++) {
4908 /* Send the READ command (opcode + addr) */ 4925 /* Send the READ command (opcode + addr) */
4909 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 4926 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
@@ -4948,7 +4965,7 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
4948 E1000_WRITE_REG(hw, EERD, eerd); 4965 E1000_WRITE_REG(hw, EERD, eerd);
4949 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 4966 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4950 4967
4951 if(error) { 4968 if (error) {
4952 break; 4969 break;
4953 } 4970 }
4954 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 4971 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
@@ -4985,7 +5002,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
4985 E1000_EEPROM_RW_REG_START; 5002 E1000_EEPROM_RW_REG_START;
4986 5003
4987 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5004 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4988 if(error) { 5005 if (error) {
4989 break; 5006 break;
4990 } 5007 }
4991 5008
@@ -4993,7 +5010,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
4993 5010
4994 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5011 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4995 5012
4996 if(error) { 5013 if (error) {
4997 break; 5014 break;
4998 } 5015 }
4999 } 5016 }
@@ -5014,13 +5031,13 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5014 uint32_t i, reg = 0; 5031 uint32_t i, reg = 0;
5015 int32_t done = E1000_ERR_EEPROM; 5032 int32_t done = E1000_ERR_EEPROM;
5016 5033
5017 for(i = 0; i < attempts; i++) { 5034 for (i = 0; i < attempts; i++) {
5018 if(eerd == E1000_EEPROM_POLL_READ) 5035 if (eerd == E1000_EEPROM_POLL_READ)
5019 reg = E1000_READ_REG(hw, EERD); 5036 reg = E1000_READ_REG(hw, EERD);
5020 else 5037 else
5021 reg = E1000_READ_REG(hw, EEWR); 5038 reg = E1000_READ_REG(hw, EEWR);
5022 5039
5023 if(reg & E1000_EEPROM_RW_REG_DONE) { 5040 if (reg & E1000_EEPROM_RW_REG_DONE) {
5024 done = E1000_SUCCESS; 5041 done = E1000_SUCCESS;
5025 break; 5042 break;
5026 } 5043 }
@@ -5052,7 +5069,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5052 eecd = ((eecd >> 15) & 0x03); 5069 eecd = ((eecd >> 15) & 0x03);
5053 5070
5054 /* If both bits are set, device is Flash type */ 5071 /* If both bits are set, device is Flash type */
5055 if(eecd == 0x03) { 5072 if (eecd == 0x03) {
5056 return FALSE; 5073 return FALSE;
5057 } 5074 }
5058 } 5075 }
@@ -5117,7 +5134,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5117 checksum += eeprom_data; 5134 checksum += eeprom_data;
5118 } 5135 }
5119 5136
5120 if(checksum == (uint16_t) EEPROM_SUM) 5137 if (checksum == (uint16_t) EEPROM_SUM)
5121 return E1000_SUCCESS; 5138 return E1000_SUCCESS;
5122 else { 5139 else {
5123 DEBUGOUT("EEPROM Checksum Invalid\n"); 5140 DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5142,15 +5159,15 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5142 5159
5143 DEBUGFUNC("e1000_update_eeprom_checksum"); 5160 DEBUGFUNC("e1000_update_eeprom_checksum");
5144 5161
5145 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { 5162 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5146 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5163 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5147 DEBUGOUT("EEPROM Read Error\n"); 5164 DEBUGOUT("EEPROM Read Error\n");
5148 return -E1000_ERR_EEPROM; 5165 return -E1000_ERR_EEPROM;
5149 } 5166 }
5150 checksum += eeprom_data; 5167 checksum += eeprom_data;
5151 } 5168 }
5152 checksum = (uint16_t) EEPROM_SUM - checksum; 5169 checksum = (uint16_t) EEPROM_SUM - checksum;
5153 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 5170 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5154 DEBUGOUT("EEPROM Write Error\n"); 5171 DEBUGOUT("EEPROM Write Error\n");
5155 return -E1000_ERR_EEPROM; 5172 return -E1000_ERR_EEPROM;
5156 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5173 } else if (hw->eeprom.type == e1000_eeprom_flash) {
@@ -5162,7 +5179,7 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
5162 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5179 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5163 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 5180 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5164 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5181 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5165 msec_delay(10); 5182 msleep(10);
5166 } 5183 }
5167 return E1000_SUCCESS; 5184 return E1000_SUCCESS;
5168} 5185}
@@ -5192,14 +5209,14 @@ e1000_write_eeprom(struct e1000_hw *hw,
5192 /* A check for invalid values: offset too large, too many words, and not 5209 /* A check for invalid values: offset too large, too many words, and not
5193 * enough words. 5210 * enough words.
5194 */ 5211 */
5195 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 5212 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5196 (words == 0)) { 5213 (words == 0)) {
5197 DEBUGOUT("\"words\" parameter out of bounds\n"); 5214 DEBUGOUT("\"words\" parameter out of bounds\n");
5198 return -E1000_ERR_EEPROM; 5215 return -E1000_ERR_EEPROM;
5199 } 5216 }
5200 5217
5201 /* 82573 writes only through eewr */ 5218 /* 82573 writes only through eewr */
5202 if(eeprom->use_eewr == TRUE) 5219 if (eeprom->use_eewr == TRUE)
5203 return e1000_write_eeprom_eewr(hw, offset, words, data); 5220 return e1000_write_eeprom_eewr(hw, offset, words, data);
5204 5221
5205 if (eeprom->type == e1000_eeprom_ich8) 5222 if (eeprom->type == e1000_eeprom_ich8)
@@ -5209,11 +5226,11 @@ e1000_write_eeprom(struct e1000_hw *hw,
5209 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5226 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5210 return -E1000_ERR_EEPROM; 5227 return -E1000_ERR_EEPROM;
5211 5228
5212 if(eeprom->type == e1000_eeprom_microwire) { 5229 if (eeprom->type == e1000_eeprom_microwire) {
5213 status = e1000_write_eeprom_microwire(hw, offset, words, data); 5230 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5214 } else { 5231 } else {
5215 status = e1000_write_eeprom_spi(hw, offset, words, data); 5232 status = e1000_write_eeprom_spi(hw, offset, words, data);
5216 msec_delay(10); 5233 msleep(10);
5217 } 5234 }
5218 5235
5219 /* Done with writing */ 5236 /* Done with writing */
@@ -5245,7 +5262,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5245 while (widx < words) { 5262 while (widx < words) {
5246 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 5263 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5247 5264
5248 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 5265 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5249 5266
5250 e1000_standby_eeprom(hw); 5267 e1000_standby_eeprom(hw);
5251 5268
@@ -5256,7 +5273,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5256 e1000_standby_eeprom(hw); 5273 e1000_standby_eeprom(hw);
5257 5274
5258 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 5275 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5259 if((eeprom->address_bits == 8) && (offset >= 128)) 5276 if ((eeprom->address_bits == 8) && (offset >= 128))
5260 write_opcode |= EEPROM_A8_OPCODE_SPI; 5277 write_opcode |= EEPROM_A8_OPCODE_SPI;
5261 5278
5262 /* Send the Write command (8-bit opcode + addr) */ 5279 /* Send the Write command (8-bit opcode + addr) */
@@ -5278,7 +5295,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5278 * operation, while the smaller eeproms are capable of an 8-byte 5295 * operation, while the smaller eeproms are capable of an 8-byte
5279 * PAGE WRITE operation. Break the inner loop to pass new address 5296 * PAGE WRITE operation. Break the inner loop to pass new address
5280 */ 5297 */
5281 if((((offset + widx)*2) % eeprom->page_size) == 0) { 5298 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5282 e1000_standby_eeprom(hw); 5299 e1000_standby_eeprom(hw);
5283 break; 5300 break;
5284 } 5301 }
@@ -5344,12 +5361,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
5344 * signal that the command has been completed by raising the DO signal. 5361 * signal that the command has been completed by raising the DO signal.
5345 * If DO does not go high in 10 milliseconds, then error out. 5362 * If DO does not go high in 10 milliseconds, then error out.
5346 */ 5363 */
5347 for(i = 0; i < 200; i++) { 5364 for (i = 0; i < 200; i++) {
5348 eecd = E1000_READ_REG(hw, EECD); 5365 eecd = E1000_READ_REG(hw, EECD);
5349 if(eecd & E1000_EECD_DO) break; 5366 if (eecd & E1000_EECD_DO) break;
5350 udelay(50); 5367 udelay(50);
5351 } 5368 }
5352 if(i == 200) { 5369 if (i == 200) {
5353 DEBUGOUT("EEPROM Write did not complete\n"); 5370 DEBUGOUT("EEPROM Write did not complete\n");
5354 return -E1000_ERR_EEPROM; 5371 return -E1000_ERR_EEPROM;
5355 } 5372 }
@@ -5540,40 +5557,6 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5540} 5557}
5541 5558
5542/****************************************************************************** 5559/******************************************************************************
5543 * Reads the adapter's part number from the EEPROM
5544 *
5545 * hw - Struct containing variables accessed by shared code
5546 * part_num - Adapter's part number
5547 *****************************************************************************/
5548int32_t
5549e1000_read_part_num(struct e1000_hw *hw,
5550 uint32_t *part_num)
5551{
5552 uint16_t offset = EEPROM_PBA_BYTE_1;
5553 uint16_t eeprom_data;
5554
5555 DEBUGFUNC("e1000_read_part_num");
5556
5557 /* Get word 0 from EEPROM */
5558 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5559 DEBUGOUT("EEPROM Read Error\n");
5560 return -E1000_ERR_EEPROM;
5561 }
5562 /* Save word 0 in upper half of part_num */
5563 *part_num = (uint32_t) (eeprom_data << 16);
5564
5565 /* Get word 1 from EEPROM */
5566 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5567 DEBUGOUT("EEPROM Read Error\n");
5568 return -E1000_ERR_EEPROM;
5569 }
5570 /* Save word 1 in lower half of part_num */
5571 *part_num |= eeprom_data;
5572
5573 return E1000_SUCCESS;
5574}
5575
5576/******************************************************************************
5577 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 5560 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5578 * second function of dual function devices 5561 * second function of dual function devices
5579 * 5562 *
@@ -5587,9 +5570,9 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5587 5570
5588 DEBUGFUNC("e1000_read_mac_addr"); 5571 DEBUGFUNC("e1000_read_mac_addr");
5589 5572
5590 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 5573 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5591 offset = i >> 1; 5574 offset = i >> 1;
5592 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 5575 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5593 DEBUGOUT("EEPROM Read Error\n"); 5576 DEBUGOUT("EEPROM Read Error\n");
5594 return -E1000_ERR_EEPROM; 5577 return -E1000_ERR_EEPROM;
5595 } 5578 }
@@ -5604,12 +5587,12 @@ e1000_read_mac_addr(struct e1000_hw * hw)
5604 case e1000_82546_rev_3: 5587 case e1000_82546_rev_3:
5605 case e1000_82571: 5588 case e1000_82571:
5606 case e1000_80003es2lan: 5589 case e1000_80003es2lan:
5607 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5590 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5608 hw->perm_mac_addr[5] ^= 0x01; 5591 hw->perm_mac_addr[5] ^= 0x01;
5609 break; 5592 break;
5610 } 5593 }
5611 5594
5612 for(i = 0; i < NODE_ADDRESS_SIZE; i++) 5595 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5613 hw->mac_addr[i] = hw->perm_mac_addr[i]; 5596 hw->mac_addr[i] = hw->perm_mac_addr[i];
5614 return E1000_SUCCESS; 5597 return E1000_SUCCESS;
5615} 5598}
@@ -5648,7 +5631,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5648 5631
5649 /* Zero out the other 15 receive addresses. */ 5632 /* Zero out the other 15 receive addresses. */
5650 DEBUGOUT("Clearing RAR[1-15]\n"); 5633 DEBUGOUT("Clearing RAR[1-15]\n");
5651 for(i = 1; i < rar_num; i++) { 5634 for (i = 1; i < rar_num; i++) {
5652 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5635 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5653 E1000_WRITE_FLUSH(hw); 5636 E1000_WRITE_FLUSH(hw);
5654 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5637 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5699,7 +5682,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5699 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5682 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5700 num_rar_entry -= 1; 5683 num_rar_entry -= 1;
5701 5684
5702 for(i = rar_used_count; i < num_rar_entry; i++) { 5685 for (i = rar_used_count; i < num_rar_entry; i++) {
5703 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5686 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5704 E1000_WRITE_FLUSH(hw); 5687 E1000_WRITE_FLUSH(hw);
5705 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5688 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5711,13 +5694,13 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5711 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5694 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5712 if (hw->mac_type == e1000_ich8lan) 5695 if (hw->mac_type == e1000_ich8lan)
5713 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 5696 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5714 for(i = 0; i < num_mta_entry; i++) { 5697 for (i = 0; i < num_mta_entry; i++) {
5715 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5698 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5716 E1000_WRITE_FLUSH(hw); 5699 E1000_WRITE_FLUSH(hw);
5717 } 5700 }
5718 5701
5719 /* Add the new addresses */ 5702 /* Add the new addresses */
5720 for(i = 0; i < mc_addr_count; i++) { 5703 for (i = 0; i < mc_addr_count; i++) {
5721 DEBUGOUT(" Adding the multicast addresses:\n"); 5704 DEBUGOUT(" Adding the multicast addresses:\n");
5722 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 5705 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5723 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
@@ -5849,7 +5832,7 @@ e1000_mta_set(struct e1000_hw *hw,
5849 * in the MTA, save off the previous entry before writing and 5832 * in the MTA, save off the previous entry before writing and
5850 * restore the old value after writing. 5833 * restore the old value after writing.
5851 */ 5834 */
5852 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5835 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5836 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5837 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5855 E1000_WRITE_FLUSH(hw); 5838 E1000_WRITE_FLUSH(hw);
@@ -5999,7 +5982,7 @@ e1000_id_led_init(struct e1000_hw * hw)
5999 5982
6000 DEBUGFUNC("e1000_id_led_init"); 5983 DEBUGFUNC("e1000_id_led_init");
6001 5984
6002 if(hw->mac_type < e1000_82540) { 5985 if (hw->mac_type < e1000_82540) {
6003 /* Nothing to do */ 5986 /* Nothing to do */
6004 return E1000_SUCCESS; 5987 return E1000_SUCCESS;
6005 } 5988 }
@@ -6009,7 +5992,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6009 hw->ledctl_mode1 = hw->ledctl_default; 5992 hw->ledctl_mode1 = hw->ledctl_default;
6010 hw->ledctl_mode2 = hw->ledctl_default; 5993 hw->ledctl_mode2 = hw->ledctl_default;
6011 5994
6012 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 5995 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6013 DEBUGOUT("EEPROM Read Error\n"); 5996 DEBUGOUT("EEPROM Read Error\n");
6014 return -E1000_ERR_EEPROM; 5997 return -E1000_ERR_EEPROM;
6015 } 5998 }
@@ -6026,7 +6009,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6026 } 6009 }
6027 for (i = 0; i < 4; i++) { 6010 for (i = 0; i < 4; i++) {
6028 temp = (eeprom_data >> (i << 2)) & led_mask; 6011 temp = (eeprom_data >> (i << 2)) & led_mask;
6029 switch(temp) { 6012 switch (temp) {
6030 case ID_LED_ON1_DEF2: 6013 case ID_LED_ON1_DEF2:
6031 case ID_LED_ON1_ON2: 6014 case ID_LED_ON1_ON2:
6032 case ID_LED_ON1_OFF2: 6015 case ID_LED_ON1_OFF2:
@@ -6043,7 +6026,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6043 /* Do nothing */ 6026 /* Do nothing */
6044 break; 6027 break;
6045 } 6028 }
6046 switch(temp) { 6029 switch (temp) {
6047 case ID_LED_DEF1_ON2: 6030 case ID_LED_DEF1_ON2:
6048 case ID_LED_ON1_ON2: 6031 case ID_LED_ON1_ON2:
6049 case ID_LED_OFF1_ON2: 6032 case ID_LED_OFF1_ON2:
@@ -6077,7 +6060,7 @@ e1000_setup_led(struct e1000_hw *hw)
6077 6060
6078 DEBUGFUNC("e1000_setup_led"); 6061 DEBUGFUNC("e1000_setup_led");
6079 6062
6080 switch(hw->mac_type) { 6063 switch (hw->mac_type) {
6081 case e1000_82542_rev2_0: 6064 case e1000_82542_rev2_0:
6082 case e1000_82542_rev2_1: 6065 case e1000_82542_rev2_1:
6083 case e1000_82543: 6066 case e1000_82543:
@@ -6091,16 +6074,16 @@ e1000_setup_led(struct e1000_hw *hw)
6091 /* Turn off PHY Smart Power Down (if enabled) */ 6074 /* Turn off PHY Smart Power Down (if enabled) */
6092 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 6075 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6093 &hw->phy_spd_default); 6076 &hw->phy_spd_default);
6094 if(ret_val) 6077 if (ret_val)
6095 return ret_val; 6078 return ret_val;
6096 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6079 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6097 (uint16_t)(hw->phy_spd_default & 6080 (uint16_t)(hw->phy_spd_default &
6098 ~IGP01E1000_GMII_SPD)); 6081 ~IGP01E1000_GMII_SPD));
6099 if(ret_val) 6082 if (ret_val)
6100 return ret_val; 6083 return ret_val;
6101 /* Fall Through */ 6084 /* Fall Through */
6102 default: 6085 default:
6103 if(hw->media_type == e1000_media_type_fiber) { 6086 if (hw->media_type == e1000_media_type_fiber) {
6104 ledctl = E1000_READ_REG(hw, LEDCTL); 6087 ledctl = E1000_READ_REG(hw, LEDCTL);
6105 /* Save current LEDCTL settings */ 6088 /* Save current LEDCTL settings */
6106 hw->ledctl_default = ledctl; 6089 hw->ledctl_default = ledctl;
@@ -6111,7 +6094,7 @@ e1000_setup_led(struct e1000_hw *hw)
6111 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6094 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6112 E1000_LEDCTL_LED0_MODE_SHIFT); 6095 E1000_LEDCTL_LED0_MODE_SHIFT);
6113 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6096 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6114 } else if(hw->media_type == e1000_media_type_copper) 6097 } else if (hw->media_type == e1000_media_type_copper)
6115 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6098 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6116 break; 6099 break;
6117 } 6100 }
@@ -6119,6 +6102,7 @@ e1000_setup_led(struct e1000_hw *hw)
6119 return E1000_SUCCESS; 6102 return E1000_SUCCESS;
6120} 6103}
6121 6104
6105
6122/****************************************************************************** 6106/******************************************************************************
6123 * Used on 82571 and later Si that has LED blink bits. 6107 * Used on 82571 and later Si that has LED blink bits.
6124 * Callers must use their own timer and should have already called 6108 * Callers must use their own timer and should have already called
@@ -6169,7 +6153,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6169 6153
6170 DEBUGFUNC("e1000_cleanup_led"); 6154 DEBUGFUNC("e1000_cleanup_led");
6171 6155
6172 switch(hw->mac_type) { 6156 switch (hw->mac_type) {
6173 case e1000_82542_rev2_0: 6157 case e1000_82542_rev2_0:
6174 case e1000_82542_rev2_1: 6158 case e1000_82542_rev2_1:
6175 case e1000_82543: 6159 case e1000_82543:
@@ -6183,7 +6167,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
6183 /* Turn on PHY Smart Power Down (if previously enabled) */ 6167 /* Turn on PHY Smart Power Down (if previously enabled) */
6184 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 6168 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6185 hw->phy_spd_default); 6169 hw->phy_spd_default);
6186 if(ret_val) 6170 if (ret_val)
6187 return ret_val; 6171 return ret_val;
6188 /* Fall Through */ 6172 /* Fall Through */
6189 default: 6173 default:
@@ -6211,7 +6195,7 @@ e1000_led_on(struct e1000_hw *hw)
6211 6195
6212 DEBUGFUNC("e1000_led_on"); 6196 DEBUGFUNC("e1000_led_on");
6213 6197
6214 switch(hw->mac_type) { 6198 switch (hw->mac_type) {
6215 case e1000_82542_rev2_0: 6199 case e1000_82542_rev2_0:
6216 case e1000_82542_rev2_1: 6200 case e1000_82542_rev2_1:
6217 case e1000_82543: 6201 case e1000_82543:
@@ -6220,7 +6204,7 @@ e1000_led_on(struct e1000_hw *hw)
6220 ctrl |= E1000_CTRL_SWDPIO0; 6204 ctrl |= E1000_CTRL_SWDPIO0;
6221 break; 6205 break;
6222 case e1000_82544: 6206 case e1000_82544:
6223 if(hw->media_type == e1000_media_type_fiber) { 6207 if (hw->media_type == e1000_media_type_fiber) {
6224 /* Set SW Defineable Pin 0 to turn on the LED */ 6208 /* Set SW Defineable Pin 0 to turn on the LED */
6225 ctrl |= E1000_CTRL_SWDPIN0; 6209 ctrl |= E1000_CTRL_SWDPIN0;
6226 ctrl |= E1000_CTRL_SWDPIO0; 6210 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6231,7 +6215,7 @@ e1000_led_on(struct e1000_hw *hw)
6231 } 6215 }
6232 break; 6216 break;
6233 default: 6217 default:
6234 if(hw->media_type == e1000_media_type_fiber) { 6218 if (hw->media_type == e1000_media_type_fiber) {
6235 /* Clear SW Defineable Pin 0 to turn on the LED */ 6219 /* Clear SW Defineable Pin 0 to turn on the LED */
6236 ctrl &= ~E1000_CTRL_SWDPIN0; 6220 ctrl &= ~E1000_CTRL_SWDPIN0;
6237 ctrl |= E1000_CTRL_SWDPIO0; 6221 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6262,7 +6246,7 @@ e1000_led_off(struct e1000_hw *hw)
6262 6246
6263 DEBUGFUNC("e1000_led_off"); 6247 DEBUGFUNC("e1000_led_off");
6264 6248
6265 switch(hw->mac_type) { 6249 switch (hw->mac_type) {
6266 case e1000_82542_rev2_0: 6250 case e1000_82542_rev2_0:
6267 case e1000_82542_rev2_1: 6251 case e1000_82542_rev2_1:
6268 case e1000_82543: 6252 case e1000_82543:
@@ -6271,7 +6255,7 @@ e1000_led_off(struct e1000_hw *hw)
6271 ctrl |= E1000_CTRL_SWDPIO0; 6255 ctrl |= E1000_CTRL_SWDPIO0;
6272 break; 6256 break;
6273 case e1000_82544: 6257 case e1000_82544:
6274 if(hw->media_type == e1000_media_type_fiber) { 6258 if (hw->media_type == e1000_media_type_fiber) {
6275 /* Clear SW Defineable Pin 0 to turn off the LED */ 6259 /* Clear SW Defineable Pin 0 to turn off the LED */
6276 ctrl &= ~E1000_CTRL_SWDPIN0; 6260 ctrl &= ~E1000_CTRL_SWDPIN0;
6277 ctrl |= E1000_CTRL_SWDPIO0; 6261 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6282,7 +6266,7 @@ e1000_led_off(struct e1000_hw *hw)
6282 } 6266 }
6283 break; 6267 break;
6284 default: 6268 default:
6285 if(hw->media_type == e1000_media_type_fiber) { 6269 if (hw->media_type == e1000_media_type_fiber) {
6286 /* Set SW Defineable Pin 0 to turn off the LED */ 6270 /* Set SW Defineable Pin 0 to turn off the LED */
6287 ctrl |= E1000_CTRL_SWDPIN0; 6271 ctrl |= E1000_CTRL_SWDPIN0;
6288 ctrl |= E1000_CTRL_SWDPIO0; 6272 ctrl |= E1000_CTRL_SWDPIO0;
@@ -6306,7 +6290,7 @@ e1000_led_off(struct e1000_hw *hw)
6306 * 6290 *
6307 * hw - Struct containing variables accessed by shared code 6291 * hw - Struct containing variables accessed by shared code
6308 *****************************************************************************/ 6292 *****************************************************************************/
6309static void 6293void
6310e1000_clear_hw_cntrs(struct e1000_hw *hw) 6294e1000_clear_hw_cntrs(struct e1000_hw *hw)
6311{ 6295{
6312 volatile uint32_t temp; 6296 volatile uint32_t temp;
@@ -6369,7 +6353,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6369 temp = E1000_READ_REG(hw, MPTC); 6353 temp = E1000_READ_REG(hw, MPTC);
6370 temp = E1000_READ_REG(hw, BPTC); 6354 temp = E1000_READ_REG(hw, BPTC);
6371 6355
6372 if(hw->mac_type < e1000_82543) return; 6356 if (hw->mac_type < e1000_82543) return;
6373 6357
6374 temp = E1000_READ_REG(hw, ALGNERRC); 6358 temp = E1000_READ_REG(hw, ALGNERRC);
6375 temp = E1000_READ_REG(hw, RXERRC); 6359 temp = E1000_READ_REG(hw, RXERRC);
@@ -6378,13 +6362,13 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
6378 temp = E1000_READ_REG(hw, TSCTC); 6362 temp = E1000_READ_REG(hw, TSCTC);
6379 temp = E1000_READ_REG(hw, TSCTFC); 6363 temp = E1000_READ_REG(hw, TSCTFC);
6380 6364
6381 if(hw->mac_type <= e1000_82544) return; 6365 if (hw->mac_type <= e1000_82544) return;
6382 6366
6383 temp = E1000_READ_REG(hw, MGTPRC); 6367 temp = E1000_READ_REG(hw, MGTPRC);
6384 temp = E1000_READ_REG(hw, MGTPDC); 6368 temp = E1000_READ_REG(hw, MGTPDC);
6385 temp = E1000_READ_REG(hw, MGTPTC); 6369 temp = E1000_READ_REG(hw, MGTPTC);
6386 6370
6387 if(hw->mac_type <= e1000_82547_rev_2) return; 6371 if (hw->mac_type <= e1000_82547_rev_2) return;
6388 6372
6389 temp = E1000_READ_REG(hw, IAC); 6373 temp = E1000_READ_REG(hw, IAC);
6390 temp = E1000_READ_REG(hw, ICRXOC); 6374 temp = E1000_READ_REG(hw, ICRXOC);
@@ -6415,8 +6399,8 @@ e1000_reset_adaptive(struct e1000_hw *hw)
6415{ 6399{
6416 DEBUGFUNC("e1000_reset_adaptive"); 6400 DEBUGFUNC("e1000_reset_adaptive");
6417 6401
6418 if(hw->adaptive_ifs) { 6402 if (hw->adaptive_ifs) {
6419 if(!hw->ifs_params_forced) { 6403 if (!hw->ifs_params_forced) {
6420 hw->current_ifs_val = 0; 6404 hw->current_ifs_val = 0;
6421 hw->ifs_min_val = IFS_MIN; 6405 hw->ifs_min_val = IFS_MIN;
6422 hw->ifs_max_val = IFS_MAX; 6406 hw->ifs_max_val = IFS_MAX;
@@ -6443,12 +6427,12 @@ e1000_update_adaptive(struct e1000_hw *hw)
6443{ 6427{
6444 DEBUGFUNC("e1000_update_adaptive"); 6428 DEBUGFUNC("e1000_update_adaptive");
6445 6429
6446 if(hw->adaptive_ifs) { 6430 if (hw->adaptive_ifs) {
6447 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 6431 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6448 if(hw->tx_packet_delta > MIN_NUM_XMITS) { 6432 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6449 hw->in_ifs_mode = TRUE; 6433 hw->in_ifs_mode = TRUE;
6450 if(hw->current_ifs_val < hw->ifs_max_val) { 6434 if (hw->current_ifs_val < hw->ifs_max_val) {
6451 if(hw->current_ifs_val == 0) 6435 if (hw->current_ifs_val == 0)
6452 hw->current_ifs_val = hw->ifs_min_val; 6436 hw->current_ifs_val = hw->ifs_min_val;
6453 else 6437 else
6454 hw->current_ifs_val += hw->ifs_step_size; 6438 hw->current_ifs_val += hw->ifs_step_size;
@@ -6456,7 +6440,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
6456 } 6440 }
6457 } 6441 }
6458 } else { 6442 } else {
6459 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6443 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6460 hw->current_ifs_val = 0; 6444 hw->current_ifs_val = 0;
6461 hw->in_ifs_mode = FALSE; 6445 hw->in_ifs_mode = FALSE;
6462 E1000_WRITE_REG(hw, AIT, 0); 6446 E1000_WRITE_REG(hw, AIT, 0);
@@ -6503,46 +6487,46 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6503 * This could be simplified if all environments supported 6487 * This could be simplified if all environments supported
6504 * 64-bit integers. 6488 * 64-bit integers.
6505 */ 6489 */
6506 if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) 6490 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6507 stats->gorch++; 6491 stats->gorch++;
6508 /* Is this a broadcast or multicast? Check broadcast first, 6492 /* Is this a broadcast or multicast? Check broadcast first,
6509 * since the test for a multicast frame will test positive on 6493 * since the test for a multicast frame will test positive on
6510 * a broadcast frame. 6494 * a broadcast frame.
6511 */ 6495 */
6512 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 6496 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6513 /* Broadcast packet */ 6497 /* Broadcast packet */
6514 stats->bprc++; 6498 stats->bprc++;
6515 else if(*mac_addr & 0x01) 6499 else if (*mac_addr & 0x01)
6516 /* Multicast packet */ 6500 /* Multicast packet */
6517 stats->mprc++; 6501 stats->mprc++;
6518 6502
6519 if(frame_len == hw->max_frame_size) { 6503 if (frame_len == hw->max_frame_size) {
6520 /* In this case, the hardware has overcounted the number of 6504 /* In this case, the hardware has overcounted the number of
6521 * oversize frames. 6505 * oversize frames.
6522 */ 6506 */
6523 if(stats->roc > 0) 6507 if (stats->roc > 0)
6524 stats->roc--; 6508 stats->roc--;
6525 } 6509 }
6526 6510
6527 /* Adjust the bin counters when the extra byte put the frame in the 6511 /* Adjust the bin counters when the extra byte put the frame in the
6528 * wrong bin. Remember that the frame_len was adjusted above. 6512 * wrong bin. Remember that the frame_len was adjusted above.
6529 */ 6513 */
6530 if(frame_len == 64) { 6514 if (frame_len == 64) {
6531 stats->prc64++; 6515 stats->prc64++;
6532 stats->prc127--; 6516 stats->prc127--;
6533 } else if(frame_len == 127) { 6517 } else if (frame_len == 127) {
6534 stats->prc127++; 6518 stats->prc127++;
6535 stats->prc255--; 6519 stats->prc255--;
6536 } else if(frame_len == 255) { 6520 } else if (frame_len == 255) {
6537 stats->prc255++; 6521 stats->prc255++;
6538 stats->prc511--; 6522 stats->prc511--;
6539 } else if(frame_len == 511) { 6523 } else if (frame_len == 511) {
6540 stats->prc511++; 6524 stats->prc511++;
6541 stats->prc1023--; 6525 stats->prc1023--;
6542 } else if(frame_len == 1023) { 6526 } else if (frame_len == 1023) {
6543 stats->prc1023++; 6527 stats->prc1023++;
6544 stats->prc1522--; 6528 stats->prc1522--;
6545 } else if(frame_len == 1522) { 6529 } else if (frame_len == 1522) {
6546 stats->prc1522++; 6530 stats->prc1522++;
6547 } 6531 }
6548} 6532}
@@ -6582,10 +6566,10 @@ e1000_get_bus_info(struct e1000_hw *hw)
6582 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6566 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6583 e1000_bus_type_pcix : e1000_bus_type_pci; 6567 e1000_bus_type_pcix : e1000_bus_type_pci;
6584 6568
6585 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 6569 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6586 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 6570 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6587 e1000_bus_speed_66 : e1000_bus_speed_120; 6571 e1000_bus_speed_66 : e1000_bus_speed_120;
6588 } else if(hw->bus_type == e1000_bus_type_pci) { 6572 } else if (hw->bus_type == e1000_bus_type_pci) {
6589 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 6573 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6590 e1000_bus_speed_66 : e1000_bus_speed_33; 6574 e1000_bus_speed_66 : e1000_bus_speed_33;
6591 } else { 6575 } else {
@@ -6680,11 +6664,11 @@ e1000_get_cable_length(struct e1000_hw *hw,
6680 *min_length = *max_length = 0; 6664 *min_length = *max_length = 0;
6681 6665
6682 /* Use old method for Phy older than IGP */ 6666 /* Use old method for Phy older than IGP */
6683 if(hw->phy_type == e1000_phy_m88) { 6667 if (hw->phy_type == e1000_phy_m88) {
6684 6668
6685 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6669 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6686 &phy_data); 6670 &phy_data);
6687 if(ret_val) 6671 if (ret_val)
6688 return ret_val; 6672 return ret_val;
6689 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 6673 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6690 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 6674 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
@@ -6743,7 +6727,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6743 return -E1000_ERR_PHY; 6727 return -E1000_ERR_PHY;
6744 break; 6728 break;
6745 } 6729 }
6746 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6730 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6747 uint16_t cur_agc_value; 6731 uint16_t cur_agc_value;
6748 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 6732 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6749 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6733 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
@@ -6752,10 +6736,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6752 IGP01E1000_PHY_AGC_C, 6736 IGP01E1000_PHY_AGC_C,
6753 IGP01E1000_PHY_AGC_D}; 6737 IGP01E1000_PHY_AGC_D};
6754 /* Read the AGC registers for all channels */ 6738 /* Read the AGC registers for all channels */
6755 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6739 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6756 6740
6757 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 6741 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6758 if(ret_val) 6742 if (ret_val)
6759 return ret_val; 6743 return ret_val;
6760 6744
6761 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6745 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -6805,7 +6789,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6805 if (ret_val) 6789 if (ret_val)
6806 return ret_val; 6790 return ret_val;
6807 6791
6808 /* Getting bits 15:9, which represent the combination of course and 6792 /* Getting bits 15:9, which represent the combination of course and
6809 * fine gain values. The result is a number that can be put into 6793 * fine gain values. The result is a number that can be put into
6810 * the lookup table to obtain the approximate cable length. */ 6794 * the lookup table to obtain the approximate cable length. */
6811 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6795 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
@@ -6870,7 +6854,7 @@ e1000_check_polarity(struct e1000_hw *hw,
6870 /* return the Polarity bit in the Status register. */ 6854 /* return the Polarity bit in the Status register. */
6871 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6855 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6872 &phy_data); 6856 &phy_data);
6873 if(ret_val) 6857 if (ret_val)
6874 return ret_val; 6858 return ret_val;
6875 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6859 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6876 M88E1000_PSSR_REV_POLARITY_SHIFT; 6860 M88E1000_PSSR_REV_POLARITY_SHIFT;
@@ -6880,18 +6864,18 @@ e1000_check_polarity(struct e1000_hw *hw,
6880 /* Read the Status register to check the speed */ 6864 /* Read the Status register to check the speed */
6881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6865 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6882 &phy_data); 6866 &phy_data);
6883 if(ret_val) 6867 if (ret_val)
6884 return ret_val; 6868 return ret_val;
6885 6869
6886 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 6870 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6887 * find the polarity status */ 6871 * find the polarity status */
6888 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 6872 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6889 IGP01E1000_PSSR_SPEED_1000MBPS) { 6873 IGP01E1000_PSSR_SPEED_1000MBPS) {
6890 6874
6891 /* Read the GIG initialization PCS register (0x00B4) */ 6875 /* Read the GIG initialization PCS register (0x00B4) */
6892 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 6876 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6893 &phy_data); 6877 &phy_data);
6894 if(ret_val) 6878 if (ret_val)
6895 return ret_val; 6879 return ret_val;
6896 6880
6897 /* Check the polarity bits */ 6881 /* Check the polarity bits */
@@ -6940,7 +6924,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6940 hw->phy_type == e1000_phy_igp_2) { 6924 hw->phy_type == e1000_phy_igp_2) {
6941 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6925 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6942 &phy_data); 6926 &phy_data);
6943 if(ret_val) 6927 if (ret_val)
6944 return ret_val; 6928 return ret_val;
6945 6929
6946 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 6930 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
@@ -6948,7 +6932,7 @@ e1000_check_downshift(struct e1000_hw *hw)
6948 (hw->phy_type == e1000_phy_gg82563)) { 6932 (hw->phy_type == e1000_phy_gg82563)) {
6949 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 6933 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6950 &phy_data); 6934 &phy_data);
6951 if(ret_val) 6935 if (ret_val)
6952 return ret_val; 6936 return ret_val;
6953 6937
6954 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6938 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -6988,42 +6972,42 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6988 6972
6989 DEBUGFUNC("e1000_config_dsp_after_link_change"); 6973 DEBUGFUNC("e1000_config_dsp_after_link_change");
6990 6974
6991 if(hw->phy_type != e1000_phy_igp) 6975 if (hw->phy_type != e1000_phy_igp)
6992 return E1000_SUCCESS; 6976 return E1000_SUCCESS;
6993 6977
6994 if(link_up) { 6978 if (link_up) {
6995 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 6979 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6996 if(ret_val) { 6980 if (ret_val) {
6997 DEBUGOUT("Error getting link speed and duplex\n"); 6981 DEBUGOUT("Error getting link speed and duplex\n");
6998 return ret_val; 6982 return ret_val;
6999 } 6983 }
7000 6984
7001 if(speed == SPEED_1000) { 6985 if (speed == SPEED_1000) {
7002 6986
7003 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 6987 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7004 if (ret_val) 6988 if (ret_val)
7005 return ret_val; 6989 return ret_val;
7006 6990
7007 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6991 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7008 min_length >= e1000_igp_cable_length_50) { 6992 min_length >= e1000_igp_cable_length_50) {
7009 6993
7010 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 6994 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7011 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 6995 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7012 &phy_data); 6996 &phy_data);
7013 if(ret_val) 6997 if (ret_val)
7014 return ret_val; 6998 return ret_val;
7015 6999
7016 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7000 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7017 7001
7018 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 7002 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7019 phy_data); 7003 phy_data);
7020 if(ret_val) 7004 if (ret_val)
7021 return ret_val; 7005 return ret_val;
7022 } 7006 }
7023 hw->dsp_config_state = e1000_dsp_config_activated; 7007 hw->dsp_config_state = e1000_dsp_config_activated;
7024 } 7008 }
7025 7009
7026 if((hw->ffe_config_state == e1000_ffe_config_enabled) && 7010 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7027 (min_length < e1000_igp_cable_length_50)) { 7011 (min_length < e1000_igp_cable_length_50)) {
7028 7012
7029 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7013 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
@@ -7032,119 +7016,119 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7032 /* clear previous idle error counts */ 7016 /* clear previous idle error counts */
7033 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7017 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7034 &phy_data); 7018 &phy_data);
7035 if(ret_val) 7019 if (ret_val)
7036 return ret_val; 7020 return ret_val;
7037 7021
7038 for(i = 0; i < ffe_idle_err_timeout; i++) { 7022 for (i = 0; i < ffe_idle_err_timeout; i++) {
7039 udelay(1000); 7023 udelay(1000);
7040 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 7024 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7041 &phy_data); 7025 &phy_data);
7042 if(ret_val) 7026 if (ret_val)
7043 return ret_val; 7027 return ret_val;
7044 7028
7045 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 7029 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7046 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7030 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7047 hw->ffe_config_state = e1000_ffe_config_active; 7031 hw->ffe_config_state = e1000_ffe_config_active;
7048 7032
7049 ret_val = e1000_write_phy_reg(hw, 7033 ret_val = e1000_write_phy_reg(hw,
7050 IGP01E1000_PHY_DSP_FFE, 7034 IGP01E1000_PHY_DSP_FFE,
7051 IGP01E1000_PHY_DSP_FFE_CM_CP); 7035 IGP01E1000_PHY_DSP_FFE_CM_CP);
7052 if(ret_val) 7036 if (ret_val)
7053 return ret_val; 7037 return ret_val;
7054 break; 7038 break;
7055 } 7039 }
7056 7040
7057 if(idle_errs) 7041 if (idle_errs)
7058 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7042 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7059 } 7043 }
7060 } 7044 }
7061 } 7045 }
7062 } else { 7046 } else {
7063 if(hw->dsp_config_state == e1000_dsp_config_activated) { 7047 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7064 /* Save off the current value of register 0x2F5B to be restored at 7048 /* Save off the current value of register 0x2F5B to be restored at
7065 * the end of the routines. */ 7049 * the end of the routines. */
7066 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7050 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7067 7051
7068 if(ret_val) 7052 if (ret_val)
7069 return ret_val; 7053 return ret_val;
7070 7054
7071 /* Disable the PHY transmitter */ 7055 /* Disable the PHY transmitter */
7072 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7056 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7073 7057
7074 if(ret_val) 7058 if (ret_val)
7075 return ret_val; 7059 return ret_val;
7076 7060
7077 msec_delay_irq(20); 7061 mdelay(20);
7078 7062
7079 ret_val = e1000_write_phy_reg(hw, 0x0000, 7063 ret_val = e1000_write_phy_reg(hw, 0x0000,
7080 IGP01E1000_IEEE_FORCE_GIGA); 7064 IGP01E1000_IEEE_FORCE_GIGA);
7081 if(ret_val) 7065 if (ret_val)
7082 return ret_val; 7066 return ret_val;
7083 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7067 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7084 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 7068 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7085 if(ret_val) 7069 if (ret_val)
7086 return ret_val; 7070 return ret_val;
7087 7071
7088 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7072 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7089 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7073 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7090 7074
7091 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); 7075 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7092 if(ret_val) 7076 if (ret_val)
7093 return ret_val; 7077 return ret_val;
7094 } 7078 }
7095 7079
7096 ret_val = e1000_write_phy_reg(hw, 0x0000, 7080 ret_val = e1000_write_phy_reg(hw, 0x0000,
7097 IGP01E1000_IEEE_RESTART_AUTONEG); 7081 IGP01E1000_IEEE_RESTART_AUTONEG);
7098 if(ret_val) 7082 if (ret_val)
7099 return ret_val; 7083 return ret_val;
7100 7084
7101 msec_delay_irq(20); 7085 mdelay(20);
7102 7086
7103 /* Now enable the transmitter */ 7087 /* Now enable the transmitter */
7104 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7088 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7105 7089
7106 if(ret_val) 7090 if (ret_val)
7107 return ret_val; 7091 return ret_val;
7108 7092
7109 hw->dsp_config_state = e1000_dsp_config_enabled; 7093 hw->dsp_config_state = e1000_dsp_config_enabled;
7110 } 7094 }
7111 7095
7112 if(hw->ffe_config_state == e1000_ffe_config_active) { 7096 if (hw->ffe_config_state == e1000_ffe_config_active) {
7113 /* Save off the current value of register 0x2F5B to be restored at 7097 /* Save off the current value of register 0x2F5B to be restored at
7114 * the end of the routines. */ 7098 * the end of the routines. */
7115 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7099 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7116 7100
7117 if(ret_val) 7101 if (ret_val)
7118 return ret_val; 7102 return ret_val;
7119 7103
7120 /* Disable the PHY transmitter */ 7104 /* Disable the PHY transmitter */
7121 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 7105 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7122 7106
7123 if(ret_val) 7107 if (ret_val)
7124 return ret_val; 7108 return ret_val;
7125 7109
7126 msec_delay_irq(20); 7110 mdelay(20);
7127 7111
7128 ret_val = e1000_write_phy_reg(hw, 0x0000, 7112 ret_val = e1000_write_phy_reg(hw, 0x0000,
7129 IGP01E1000_IEEE_FORCE_GIGA); 7113 IGP01E1000_IEEE_FORCE_GIGA);
7130 if(ret_val) 7114 if (ret_val)
7131 return ret_val; 7115 return ret_val;
7132 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 7116 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7133 IGP01E1000_PHY_DSP_FFE_DEFAULT); 7117 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7134 if(ret_val) 7118 if (ret_val)
7135 return ret_val; 7119 return ret_val;
7136 7120
7137 ret_val = e1000_write_phy_reg(hw, 0x0000, 7121 ret_val = e1000_write_phy_reg(hw, 0x0000,
7138 IGP01E1000_IEEE_RESTART_AUTONEG); 7122 IGP01E1000_IEEE_RESTART_AUTONEG);
7139 if(ret_val) 7123 if (ret_val)
7140 return ret_val; 7124 return ret_val;
7141 7125
7142 msec_delay_irq(20); 7126 mdelay(20);
7143 7127
7144 /* Now enable the transmitter */ 7128 /* Now enable the transmitter */
7145 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7129 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7146 7130
7147 if(ret_val) 7131 if (ret_val)
7148 return ret_val; 7132 return ret_val;
7149 7133
7150 hw->ffe_config_state = e1000_ffe_config_enabled; 7134 hw->ffe_config_state = e1000_ffe_config_enabled;
@@ -7169,20 +7153,20 @@ e1000_set_phy_mode(struct e1000_hw *hw)
7169 7153
7170 DEBUGFUNC("e1000_set_phy_mode"); 7154 DEBUGFUNC("e1000_set_phy_mode");
7171 7155
7172 if((hw->mac_type == e1000_82545_rev_3) && 7156 if ((hw->mac_type == e1000_82545_rev_3) &&
7173 (hw->media_type == e1000_media_type_copper)) { 7157 (hw->media_type == e1000_media_type_copper)) {
7174 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 7158 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7175 if(ret_val) { 7159 if (ret_val) {
7176 return ret_val; 7160 return ret_val;
7177 } 7161 }
7178 7162
7179 if((eeprom_data != EEPROM_RESERVED_WORD) && 7163 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7180 (eeprom_data & EEPROM_PHY_CLASS_A)) { 7164 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7181 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 7165 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7182 if(ret_val) 7166 if (ret_val)
7183 return ret_val; 7167 return ret_val;
7184 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 7168 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7185 if(ret_val) 7169 if (ret_val)
7186 return ret_val; 7170 return ret_val;
7187 7171
7188 hw->phy_reset_disable = FALSE; 7172 hw->phy_reset_disable = FALSE;
@@ -7233,16 +7217,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7233 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7217 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7234 } else { 7218 } else {
7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7219 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7236 if(ret_val) 7220 if (ret_val)
7237 return ret_val; 7221 return ret_val;
7238 } 7222 }
7239 7223
7240 if(!active) { 7224 if (!active) {
7241 if(hw->mac_type == e1000_82541_rev_2 || 7225 if (hw->mac_type == e1000_82541_rev_2 ||
7242 hw->mac_type == e1000_82547_rev_2) { 7226 hw->mac_type == e1000_82547_rev_2) {
7243 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 7227 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7244 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7228 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7245 if(ret_val) 7229 if (ret_val)
7246 return ret_val; 7230 return ret_val;
7247 } else { 7231 } else {
7248 if (hw->mac_type == e1000_ich8lan) { 7232 if (hw->mac_type == e1000_ich8lan) {
@@ -7264,13 +7248,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7264 if (hw->smart_speed == e1000_smart_speed_on) { 7248 if (hw->smart_speed == e1000_smart_speed_on) {
7265 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7249 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7266 &phy_data); 7250 &phy_data);
7267 if(ret_val) 7251 if (ret_val)
7268 return ret_val; 7252 return ret_val;
7269 7253
7270 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7254 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7271 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7255 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7272 phy_data); 7256 phy_data);
7273 if(ret_val) 7257 if (ret_val)
7274 return ret_val; 7258 return ret_val;
7275 } else if (hw->smart_speed == e1000_smart_speed_off) { 7259 } else if (hw->smart_speed == e1000_smart_speed_off) {
7276 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7281,19 +7265,19 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7281 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7265 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7282 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7266 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7283 phy_data); 7267 phy_data);
7284 if(ret_val) 7268 if (ret_val)
7285 return ret_val; 7269 return ret_val;
7286 } 7270 }
7287 7271
7288 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 7272 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7289 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 7273 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7274 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7291 7275
7292 if(hw->mac_type == e1000_82541_rev_2 || 7276 if (hw->mac_type == e1000_82541_rev_2 ||
7293 hw->mac_type == e1000_82547_rev_2) { 7277 hw->mac_type == e1000_82547_rev_2) {
7294 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7278 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7279 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7296 if(ret_val) 7280 if (ret_val)
7297 return ret_val; 7281 return ret_val;
7298 } else { 7282 } else {
7299 if (hw->mac_type == e1000_ich8lan) { 7283 if (hw->mac_type == e1000_ich8lan) {
@@ -7310,12 +7294,12 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7310 7294
7311 /* When LPLU is enabled we should disable SmartSpeed */ 7295 /* When LPLU is enabled we should disable SmartSpeed */
7312 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7296 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7313 if(ret_val) 7297 if (ret_val)
7314 return ret_val; 7298 return ret_val;
7315 7299
7316 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7300 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7317 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7301 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7318 if(ret_val) 7302 if (ret_val)
7319 return ret_val; 7303 return ret_val;
7320 7304
7321 } 7305 }
@@ -7345,14 +7329,14 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7345 uint16_t phy_data; 7329 uint16_t phy_data;
7346 DEBUGFUNC("e1000_set_d0_lplu_state"); 7330 DEBUGFUNC("e1000_set_d0_lplu_state");
7347 7331
7348 if(hw->mac_type <= e1000_82547_rev_2) 7332 if (hw->mac_type <= e1000_82547_rev_2)
7349 return E1000_SUCCESS; 7333 return E1000_SUCCESS;
7350 7334
7351 if (hw->mac_type == e1000_ich8lan) { 7335 if (hw->mac_type == e1000_ich8lan) {
7352 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7336 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7353 } else { 7337 } else {
7354 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7338 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7355 if(ret_val) 7339 if (ret_val)
7356 return ret_val; 7340 return ret_val;
7357 } 7341 }
7358 7342
@@ -7374,13 +7358,13 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7374 if (hw->smart_speed == e1000_smart_speed_on) { 7358 if (hw->smart_speed == e1000_smart_speed_on) {
7375 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7359 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7376 &phy_data); 7360 &phy_data);
7377 if(ret_val) 7361 if (ret_val)
7378 return ret_val; 7362 return ret_val;
7379 7363
7380 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 7364 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7381 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7365 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7382 phy_data); 7366 phy_data);
7383 if(ret_val) 7367 if (ret_val)
7384 return ret_val; 7368 return ret_val;
7385 } else if (hw->smart_speed == e1000_smart_speed_off) { 7369 } else if (hw->smart_speed == e1000_smart_speed_off) {
7386 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7370 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7391,7 +7375,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7391 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7375 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7392 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7376 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7393 phy_data); 7377 phy_data);
7394 if(ret_val) 7378 if (ret_val)
7395 return ret_val; 7379 return ret_val;
7396 } 7380 }
7397 7381
@@ -7410,12 +7394,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7410 7394
7411 /* When LPLU is enabled we should disable SmartSpeed */ 7395 /* When LPLU is enabled we should disable SmartSpeed */
7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7396 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7413 if(ret_val) 7397 if (ret_val)
7414 return ret_val; 7398 return ret_val;
7415 7399
7416 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7400 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7417 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 7401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7418 if(ret_val) 7402 if (ret_val)
7419 return ret_val; 7403 return ret_val;
7420 7404
7421 } 7405 }
@@ -7436,7 +7420,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7436 7420
7437 DEBUGFUNC("e1000_set_vco_speed"); 7421 DEBUGFUNC("e1000_set_vco_speed");
7438 7422
7439 switch(hw->mac_type) { 7423 switch (hw->mac_type) {
7440 case e1000_82545_rev_3: 7424 case e1000_82545_rev_3:
7441 case e1000_82546_rev_3: 7425 case e1000_82546_rev_3:
7442 break; 7426 break;
@@ -7447,39 +7431,39 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7447 /* Set PHY register 30, page 5, bit 8 to 0 */ 7431 /* Set PHY register 30, page 5, bit 8 to 0 */
7448 7432
7449 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 7433 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7450 if(ret_val) 7434 if (ret_val)
7451 return ret_val; 7435 return ret_val;
7452 7436
7453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 7437 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7454 if(ret_val) 7438 if (ret_val)
7455 return ret_val; 7439 return ret_val;
7456 7440
7457 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7441 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7458 if(ret_val) 7442 if (ret_val)
7459 return ret_val; 7443 return ret_val;
7460 7444
7461 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 7445 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7462 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7446 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7463 if(ret_val) 7447 if (ret_val)
7464 return ret_val; 7448 return ret_val;
7465 7449
7466 /* Set PHY register 30, page 4, bit 11 to 1 */ 7450 /* Set PHY register 30, page 4, bit 11 to 1 */
7467 7451
7468 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 7452 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7469 if(ret_val) 7453 if (ret_val)
7470 return ret_val; 7454 return ret_val;
7471 7455
7472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 7456 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7473 if(ret_val) 7457 if (ret_val)
7474 return ret_val; 7458 return ret_val;
7475 7459
7476 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 7460 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7477 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 7461 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7478 if(ret_val) 7462 if (ret_val)
7479 return ret_val; 7463 return ret_val;
7480 7464
7481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7482 if(ret_val) 7466 if (ret_val)
7483 return ret_val; 7467 return ret_val;
7484 7468
7485 return E1000_SUCCESS; 7469 return E1000_SUCCESS;
@@ -7535,7 +7519,7 @@ e1000_mng_enable_host_if(struct e1000_hw * hw)
7535 hicr = E1000_READ_REG(hw, HICR); 7519 hicr = E1000_READ_REG(hw, HICR);
7536 if (!(hicr & E1000_HICR_C)) 7520 if (!(hicr & E1000_HICR_C))
7537 break; 7521 break;
7538 msec_delay_irq(1); 7522 mdelay(1);
7539 } 7523 }
7540 7524
7541 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 7525 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
@@ -7558,7 +7542,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7558{ 7542{
7559 uint8_t *tmp; 7543 uint8_t *tmp;
7560 uint8_t *bufptr = buffer; 7544 uint8_t *bufptr = buffer;
7561 uint32_t data; 7545 uint32_t data = 0;
7562 uint16_t remaining, i, j, prev_bytes; 7546 uint16_t remaining, i, j, prev_bytes;
7563 7547
7564 /* sum = only sum of the data and it is not checksum */ 7548 /* sum = only sum of the data and it is not checksum */
@@ -7638,7 +7622,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7638 7622
7639 buffer = (uint8_t *) hdr; 7623 buffer = (uint8_t *) hdr;
7640 i = length; 7624 i = length;
7641 while(i--) 7625 while (i--)
7642 sum += buffer[i]; 7626 sum += buffer[i];
7643 7627
7644 hdr->checksum = 0 - sum; 7628 hdr->checksum = 0 - sum;
@@ -7661,8 +7645,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
7661 * returns - E1000_SUCCESS for success. 7645 * returns - E1000_SUCCESS for success.
7662 ****************************************************************************/ 7646 ****************************************************************************/
7663static int32_t 7647static int32_t
7664e1000_mng_write_commit( 7648e1000_mng_write_commit(struct e1000_hw * hw)
7665 struct e1000_hw * hw)
7666{ 7649{
7667 uint32_t hicr; 7650 uint32_t hicr;
7668 7651
@@ -7834,75 +7817,75 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7834 /* Disable the transmitter on the PHY */ 7817 /* Disable the transmitter on the PHY */
7835 7818
7836 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7819 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7837 if(ret_val) 7820 if (ret_val)
7838 return ret_val; 7821 return ret_val;
7839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 7822 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7840 if(ret_val) 7823 if (ret_val)
7841 return ret_val; 7824 return ret_val;
7842 7825
7843 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7826 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7844 if(ret_val) 7827 if (ret_val)
7845 return ret_val; 7828 return ret_val;
7846 7829
7847 /* This loop will early-out if the NO link condition has been met. */ 7830 /* This loop will early-out if the NO link condition has been met. */
7848 for(i = PHY_FORCE_TIME; i > 0; i--) { 7831 for (i = PHY_FORCE_TIME; i > 0; i--) {
7849 /* Read the MII Status Register and wait for Link Status bit 7832 /* Read the MII Status Register and wait for Link Status bit
7850 * to be clear. 7833 * to be clear.
7851 */ 7834 */
7852 7835
7853 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7854 if(ret_val) 7837 if (ret_val)
7855 return ret_val; 7838 return ret_val;
7856 7839
7857 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7858 if(ret_val) 7841 if (ret_val)
7859 return ret_val; 7842 return ret_val;
7860 7843
7861 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 7844 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7862 msec_delay_irq(100); 7845 mdelay(100);
7863 } 7846 }
7864 7847
7865 /* Recommended delay time after link has been lost */ 7848 /* Recommended delay time after link has been lost */
7866 msec_delay_irq(1000); 7849 mdelay(1000);
7867 7850
7868 /* Now we will re-enable th transmitter on the PHY */ 7851 /* Now we will re-enable th transmitter on the PHY */
7869 7852
7870 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7871 if(ret_val) 7854 if (ret_val)
7872 return ret_val; 7855 return ret_val;
7873 msec_delay_irq(50); 7856 mdelay(50);
7874 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 7857 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7875 if(ret_val) 7858 if (ret_val)
7876 return ret_val; 7859 return ret_val;
7877 msec_delay_irq(50); 7860 mdelay(50);
7878 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 7861 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7879 if(ret_val) 7862 if (ret_val)
7880 return ret_val; 7863 return ret_val;
7881 msec_delay_irq(50); 7864 mdelay(50);
7882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 7865 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7883 if(ret_val) 7866 if (ret_val)
7884 return ret_val; 7867 return ret_val;
7885 7868
7886 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 7869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7887 if(ret_val) 7870 if (ret_val)
7888 return ret_val; 7871 return ret_val;
7889 7872
7890 /* This loop will early-out if the link condition has been met. */ 7873 /* This loop will early-out if the link condition has been met. */
7891 for(i = PHY_FORCE_TIME; i > 0; i--) { 7874 for (i = PHY_FORCE_TIME; i > 0; i--) {
7892 /* Read the MII Status Register and wait for Link Status bit 7875 /* Read the MII Status Register and wait for Link Status bit
7893 * to be set. 7876 * to be set.
7894 */ 7877 */
7895 7878
7896 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7879 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7897 if(ret_val) 7880 if (ret_val)
7898 return ret_val; 7881 return ret_val;
7899 7882
7900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 7883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7901 if(ret_val) 7884 if (ret_val)
7902 return ret_val; 7885 return ret_val;
7903 7886
7904 if(mii_status_reg & MII_SR_LINK_STATUS) break; 7887 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7905 msec_delay_irq(100); 7888 mdelay(100);
7906 } 7889 }
7907 return E1000_SUCCESS; 7890 return E1000_SUCCESS;
7908} 7891}
@@ -7980,15 +7963,15 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
7980 7963
7981 e1000_set_pci_express_master_disable(hw); 7964 e1000_set_pci_express_master_disable(hw);
7982 7965
7983 while(timeout) { 7966 while (timeout) {
7984 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7967 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7985 break; 7968 break;
7986 else 7969 else
7987 udelay(100); 7970 udelay(100);
7988 timeout--; 7971 timeout--;
7989 } 7972 }
7990 7973
7991 if(!timeout) { 7974 if (!timeout) {
7992 DEBUGOUT("Master requests are pending.\n"); 7975 DEBUGOUT("Master requests are pending.\n");
7993 return -E1000_ERR_MASTER_REQUESTS_PENDING; 7976 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7994 } 7977 }
@@ -8015,7 +7998,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8015 7998
8016 switch (hw->mac_type) { 7999 switch (hw->mac_type) {
8017 default: 8000 default:
8018 msec_delay(5); 8001 msleep(5);
8019 break; 8002 break;
8020 case e1000_82571: 8003 case e1000_82571:
8021 case e1000_82572: 8004 case e1000_82572:
@@ -8025,11 +8008,11 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8025 while (timeout) { 8008 while (timeout) {
8026 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 8009 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8027 break; 8010 break;
8028 else msec_delay(1); 8011 else msleep(1);
8029 timeout--; 8012 timeout--;
8030 } 8013 }
8031 8014
8032 if(!timeout) { 8015 if (!timeout) {
8033 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); 8016 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8034 return -E1000_ERR_RESET; 8017 return -E1000_ERR_RESET;
8035 } 8018 }
@@ -8040,7 +8023,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
8040 * Need to wait for PHY configuration completion before accessing NVM 8023 * Need to wait for PHY configuration completion before accessing NVM
8041 * and PHY. */ 8024 * and PHY. */
8042 if (hw->mac_type == e1000_82573) 8025 if (hw->mac_type == e1000_82573)
8043 msec_delay(25); 8026 msleep(25);
8044 8027
8045 return E1000_SUCCESS; 8028 return E1000_SUCCESS;
8046} 8029}
@@ -8064,7 +8047,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8064 8047
8065 switch (hw->mac_type) { 8048 switch (hw->mac_type) {
8066 default: 8049 default:
8067 msec_delay_irq(10); 8050 mdelay(10);
8068 break; 8051 break;
8069 case e1000_80003es2lan: 8052 case e1000_80003es2lan:
8070 /* Separate *_CFG_DONE_* bit for each port */ 8053 /* Separate *_CFG_DONE_* bit for each port */
@@ -8077,7 +8060,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8077 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8060 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8078 break; 8061 break;
8079 else 8062 else
8080 msec_delay(1); 8063 msleep(1);
8081 timeout--; 8064 timeout--;
8082 } 8065 }
8083 8066
@@ -8110,7 +8093,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8110 8093
8111 DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); 8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8112 8095
8113 if(!hw->eeprom_semaphore_present) 8096 if (!hw->eeprom_semaphore_present)
8114 return E1000_SUCCESS; 8097 return E1000_SUCCESS;
8115 8098
8116 if (hw->mac_type == e1000_80003es2lan) { 8099 if (hw->mac_type == e1000_80003es2lan) {
@@ -8121,20 +8104,20 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8121 8104
8122 /* Get the FW semaphore. */ 8105 /* Get the FW semaphore. */
8123 timeout = hw->eeprom.word_size + 1; 8106 timeout = hw->eeprom.word_size + 1;
8124 while(timeout) { 8107 while (timeout) {
8125 swsm = E1000_READ_REG(hw, SWSM); 8108 swsm = E1000_READ_REG(hw, SWSM);
8126 swsm |= E1000_SWSM_SWESMBI; 8109 swsm |= E1000_SWSM_SWESMBI;
8127 E1000_WRITE_REG(hw, SWSM, swsm); 8110 E1000_WRITE_REG(hw, SWSM, swsm);
8128 /* if we managed to set the bit we got the semaphore. */ 8111 /* if we managed to set the bit we got the semaphore. */
8129 swsm = E1000_READ_REG(hw, SWSM); 8112 swsm = E1000_READ_REG(hw, SWSM);
8130 if(swsm & E1000_SWSM_SWESMBI) 8113 if (swsm & E1000_SWSM_SWESMBI)
8131 break; 8114 break;
8132 8115
8133 udelay(50); 8116 udelay(50);
8134 timeout--; 8117 timeout--;
8135 } 8118 }
8136 8119
8137 if(!timeout) { 8120 if (!timeout) {
8138 /* Release semaphores */ 8121 /* Release semaphores */
8139 e1000_put_hw_eeprom_semaphore(hw); 8122 e1000_put_hw_eeprom_semaphore(hw);
8140 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); 8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
@@ -8159,7 +8142,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8159 8142
8160 DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); 8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8161 8144
8162 if(!hw->eeprom_semaphore_present) 8145 if (!hw->eeprom_semaphore_present)
8163 return; 8146 return;
8164 8147
8165 swsm = E1000_READ_REG(hw, SWSM); 8148 swsm = E1000_READ_REG(hw, SWSM);
@@ -8192,16 +8175,16 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8192 if (hw->mac_type != e1000_80003es2lan) 8175 if (hw->mac_type != e1000_80003es2lan)
8193 return E1000_SUCCESS; 8176 return E1000_SUCCESS;
8194 8177
8195 while(timeout) { 8178 while (timeout) {
8196 swsm = E1000_READ_REG(hw, SWSM); 8179 swsm = E1000_READ_REG(hw, SWSM);
8197 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8180 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8198 if(!(swsm & E1000_SWSM_SMBI)) 8181 if (!(swsm & E1000_SWSM_SMBI))
8199 break; 8182 break;
8200 msec_delay_irq(1); 8183 mdelay(1);
8201 timeout--; 8184 timeout--;
8202 } 8185 }
8203 8186
8204 if(!timeout) { 8187 if (!timeout) {
8205 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8188 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8206 return -E1000_ERR_RESET; 8189 return -E1000_ERR_RESET;
8207 } 8190 }
@@ -8277,7 +8260,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
8277 case e1000_82573: 8260 case e1000_82573:
8278 case e1000_80003es2lan: 8261 case e1000_80003es2lan:
8279 fwsm = E1000_READ_REG(hw, FWSM); 8262 fwsm = E1000_READ_REG(hw, FWSM);
8280 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8263 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8281 return TRUE; 8264 return TRUE;
8282 break; 8265 break;
8283 case e1000_ich8lan: 8266 case e1000_ich8lan:
@@ -8356,7 +8339,7 @@ e1000_get_software_flag(struct e1000_hw *hw)
8356 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8339 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8357 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8340 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8358 break; 8341 break;
8359 msec_delay_irq(1); 8342 mdelay(1);
8360 timeout--; 8343 timeout--;
8361 } 8344 }
8362 8345
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 375b95518c31..a170e96251f6 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -336,9 +336,9 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 336#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
337 337
338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 338#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
341#define E1000_MNG_IAMT_MODE 0x3 341#define E1000_MNG_IAMT_MODE 0x3
342#define E1000_MNG_ICH_IAMT_MODE 0x2 342#define E1000_MNG_ICH_IAMT_MODE 0x2
343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
344 344
@@ -385,7 +385,7 @@ struct e1000_host_mng_dhcp_cookie{
385#endif 385#endif
386 386
387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, 387int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
388 uint16_t length); 388 uint16_t length);
389boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 389boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 390boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
391 391
@@ -470,6 +470,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
470#define E1000_DEV_ID_82571EB_COPPER 0x105E 470#define E1000_DEV_ID_82571EB_COPPER 0x105E
471#define E1000_DEV_ID_82571EB_FIBER 0x105F 471#define E1000_DEV_ID_82571EB_FIBER 0x105F
472#define E1000_DEV_ID_82571EB_SERDES 0x1060 472#define E1000_DEV_ID_82571EB_SERDES 0x1060
473#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
473#define E1000_DEV_ID_82572EI_COPPER 0x107D 474#define E1000_DEV_ID_82572EI_COPPER 0x107D
474#define E1000_DEV_ID_82572EI_FIBER 0x107E 475#define E1000_DEV_ID_82572EI_FIBER 0x107E
475#define E1000_DEV_ID_82572EI_SERDES 0x107F 476#define E1000_DEV_ID_82572EI_SERDES 0x107F
@@ -523,7 +524,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
523 524
524 525
525/* 802.1q VLAN Packet Sizes */ 526/* 802.1q VLAN Packet Sizes */
526#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 527#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
527 528
528/* Ethertype field values */ 529/* Ethertype field values */
529#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 530#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
@@ -697,6 +698,7 @@ union e1000_rx_desc_packet_split {
697 E1000_RXDEXT_STATERR_CXE | \ 698 E1000_RXDEXT_STATERR_CXE | \
698 E1000_RXDEXT_STATERR_RXE) 699 E1000_RXDEXT_STATERR_RXE)
699 700
701
700/* Transmit Descriptor */ 702/* Transmit Descriptor */
701struct e1000_tx_desc { 703struct e1000_tx_desc {
702 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 704 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@@ -2086,7 +2088,7 @@ struct e1000_hw {
2086#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2088#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2087 * filtering */ 2089 * filtering */
2088#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2090#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2089#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2091#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2090#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2092#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2091#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2093#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2092#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2094#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -2172,7 +2174,7 @@ struct e1000_host_command_info {
2172 2174
2173#define E1000_MDALIGN 4096 2175#define E1000_MDALIGN 4096
2174 2176
2175/* PCI-Ex registers */ 2177/* PCI-Ex registers*/
2176 2178
2177/* PCI-Ex Control Register */ 2179/* PCI-Ex Control Register */
2178#define E1000_GCR_RXD_NO_SNOOP 0x00000001 2180#define E1000_GCR_RXD_NO_SNOOP 0x00000001
@@ -2224,7 +2226,7 @@ struct e1000_host_command_info {
2224#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2226#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2225 2227
2226/* EEPROM Commands - SPI */ 2228/* EEPROM Commands - SPI */
2227#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2229#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2228#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2230#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2229#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2231#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2230#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2232#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
@@ -3082,10 +3084,10 @@ struct e1000_host_command_info {
3082 3084
3083/* DSP Distance Register (Page 5, Register 26) */ 3085/* DSP Distance Register (Page 5, Register 26) */
3084#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 3086#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3085 1 = 50-80M; 3087 1 = 50-80M;
3086 2 = 80-110M; 3088 2 = 80-110M;
3087 3 = 110-140M; 3089 3 = 110-140M;
3088 4 = >140M */ 3090 4 = >140M */
3089 3091
3090/* Kumeran Mode Control Register (Page 193, Register 16) */ 3092/* Kumeran Mode Control Register (Page 193, Register 16) */
3091#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ 3093#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 2ab9f96f5dab..3f6a752700a1 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -36,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "7.1.9-k4"DRIVERNAPI 39#define DRV_VERSION "7.2.7-k2"DRIVERNAPI
40char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -99,6 +99,7 @@ static struct pci_device_id e1000_pci_tbl[] = {
99 INTEL_E1000_ETHERNET_DEVICE(0x1098), 99 INTEL_E1000_ETHERNET_DEVICE(0x1098),
100 INTEL_E1000_ETHERNET_DEVICE(0x1099), 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
101 INTEL_E1000_ETHERNET_DEVICE(0x109A), 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
102 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
102 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 103 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
103 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 104 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA), 105 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
@@ -245,7 +246,7 @@ e1000_init_module(void)
245 246
246 printk(KERN_INFO "%s\n", e1000_copyright); 247 printk(KERN_INFO "%s\n", e1000_copyright);
247 248
248 ret = pci_module_init(&e1000_driver); 249 ret = pci_register_driver(&e1000_driver);
249 250
250 return ret; 251 return ret;
251} 252}
@@ -485,7 +486,7 @@ e1000_up(struct e1000_adapter *adapter)
485 * 486 *
486 **/ 487 **/
487 488
488static void e1000_power_up_phy(struct e1000_adapter *adapter) 489void e1000_power_up_phy(struct e1000_adapter *adapter)
489{ 490{
490 uint16_t mii_reg = 0; 491 uint16_t mii_reg = 0;
491 492
@@ -682,9 +683,9 @@ e1000_probe(struct pci_dev *pdev,
682 unsigned long flash_start, flash_len; 683 unsigned long flash_start, flash_len;
683 684
684 static int cards_found = 0; 685 static int cards_found = 0;
685 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 686 static int global_quad_port_a = 0; /* global ksp3 port a indication */
686 int i, err, pci_using_dac; 687 int i, err, pci_using_dac;
687 uint16_t eeprom_data; 688 uint16_t eeprom_data = 0;
688 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 689 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
689 if ((err = pci_enable_device(pdev))) 690 if ((err = pci_enable_device(pdev)))
690 return err; 691 return err;
@@ -696,21 +697,20 @@ e1000_probe(struct pci_dev *pdev,
696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) && 697 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) { 698 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
698 E1000_ERR("No usable DMA configuration, aborting\n"); 699 E1000_ERR("No usable DMA configuration, aborting\n");
699 return err; 700 goto err_dma;
700 } 701 }
701 pci_using_dac = 0; 702 pci_using_dac = 0;
702 } 703 }
703 704
704 if ((err = pci_request_regions(pdev, e1000_driver_name))) 705 if ((err = pci_request_regions(pdev, e1000_driver_name)))
705 return err; 706 goto err_pci_reg;
706 707
707 pci_set_master(pdev); 708 pci_set_master(pdev);
708 709
710 err = -ENOMEM;
709 netdev = alloc_etherdev(sizeof(struct e1000_adapter)); 711 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
710 if (!netdev) { 712 if (!netdev)
711 err = -ENOMEM;
712 goto err_alloc_etherdev; 713 goto err_alloc_etherdev;
713 }
714 714
715 SET_MODULE_OWNER(netdev); 715 SET_MODULE_OWNER(netdev);
716 SET_NETDEV_DEV(netdev, &pdev->dev); 716 SET_NETDEV_DEV(netdev, &pdev->dev);
@@ -725,11 +725,10 @@ e1000_probe(struct pci_dev *pdev,
725 mmio_start = pci_resource_start(pdev, BAR_0); 725 mmio_start = pci_resource_start(pdev, BAR_0);
726 mmio_len = pci_resource_len(pdev, BAR_0); 726 mmio_len = pci_resource_len(pdev, BAR_0);
727 727
728 err = -EIO;
728 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); 729 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
729 if (!adapter->hw.hw_addr) { 730 if (!adapter->hw.hw_addr)
730 err = -EIO;
731 goto err_ioremap; 731 goto err_ioremap;
732 }
733 732
734 for (i = BAR_1; i <= BAR_5; i++) { 733 for (i = BAR_1; i <= BAR_5; i++) {
735 if (pci_resource_len(pdev, i) == 0) 734 if (pci_resource_len(pdev, i) == 0)
@@ -774,6 +773,7 @@ e1000_probe(struct pci_dev *pdev,
774 if ((err = e1000_sw_init(adapter))) 773 if ((err = e1000_sw_init(adapter)))
775 goto err_sw_init; 774 goto err_sw_init;
776 775
776 err = -EIO;
777 /* Flash BAR mapping must happen after e1000_sw_init 777 /* Flash BAR mapping must happen after e1000_sw_init
778 * because it depends on mac_type */ 778 * because it depends on mac_type */
779 if ((adapter->hw.mac_type == e1000_ich8lan) && 779 if ((adapter->hw.mac_type == e1000_ich8lan) &&
@@ -781,24 +781,13 @@ e1000_probe(struct pci_dev *pdev,
781 flash_start = pci_resource_start(pdev, 1); 781 flash_start = pci_resource_start(pdev, 1);
782 flash_len = pci_resource_len(pdev, 1); 782 flash_len = pci_resource_len(pdev, 1);
783 adapter->hw.flash_address = ioremap(flash_start, flash_len); 783 adapter->hw.flash_address = ioremap(flash_start, flash_len);
784 if (!adapter->hw.flash_address) { 784 if (!adapter->hw.flash_address)
785 err = -EIO;
786 goto err_flashmap; 785 goto err_flashmap;
787 }
788 } 786 }
789 787
790 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 788 if (e1000_check_phy_reset_block(&adapter->hw))
791 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 789 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
792 790
793 /* if ksp3, indicate if it's port a being setup */
794 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
795 e1000_ksp3_port_a == 0)
796 adapter->ksp3_port_a = 1;
797 e1000_ksp3_port_a++;
798 /* Reset for multiple KP3 adapters */
799 if (e1000_ksp3_port_a == 4)
800 e1000_ksp3_port_a = 0;
801
802 if (adapter->hw.mac_type >= e1000_82543) { 791 if (adapter->hw.mac_type >= e1000_82543) {
803 netdev->features = NETIF_F_SG | 792 netdev->features = NETIF_F_SG |
804 NETIF_F_HW_CSUM | 793 NETIF_F_HW_CSUM |
@@ -830,7 +819,7 @@ e1000_probe(struct pci_dev *pdev,
830 819
831 if (e1000_init_eeprom_params(&adapter->hw)) { 820 if (e1000_init_eeprom_params(&adapter->hw)) {
832 E1000_ERR("EEPROM initialization failed\n"); 821 E1000_ERR("EEPROM initialization failed\n");
833 return -EIO; 822 goto err_eeprom;
834 } 823 }
835 824
836 /* before reading the EEPROM, reset the controller to 825 /* before reading the EEPROM, reset the controller to
@@ -842,7 +831,6 @@ e1000_probe(struct pci_dev *pdev,
842 831
843 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) { 832 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
844 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n"); 833 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
845 err = -EIO;
846 goto err_eeprom; 834 goto err_eeprom;
847 } 835 }
848 836
@@ -855,12 +843,9 @@ e1000_probe(struct pci_dev *pdev,
855 843
856 if (!is_valid_ether_addr(netdev->perm_addr)) { 844 if (!is_valid_ether_addr(netdev->perm_addr)) {
857 DPRINTK(PROBE, ERR, "Invalid MAC Address\n"); 845 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
858 err = -EIO;
859 goto err_eeprom; 846 goto err_eeprom;
860 } 847 }
861 848
862 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
863
864 e1000_get_bus_info(&adapter->hw); 849 e1000_get_bus_info(&adapter->hw);
865 850
866 init_timer(&adapter->tx_fifo_stall_timer); 851 init_timer(&adapter->tx_fifo_stall_timer);
@@ -921,7 +906,38 @@ e1000_probe(struct pci_dev *pdev,
921 break; 906 break;
922 } 907 }
923 if (eeprom_data & eeprom_apme_mask) 908 if (eeprom_data & eeprom_apme_mask)
924 adapter->wol |= E1000_WUFC_MAG; 909 adapter->eeprom_wol |= E1000_WUFC_MAG;
910
911 /* now that we have the eeprom settings, apply the special cases
912 * where the eeprom may be wrong or the board simply won't support
913 * wake on lan on a particular port */
914 switch (pdev->device) {
915 case E1000_DEV_ID_82546GB_PCIE:
916 adapter->eeprom_wol = 0;
917 break;
918 case E1000_DEV_ID_82546EB_FIBER:
919 case E1000_DEV_ID_82546GB_FIBER:
920 case E1000_DEV_ID_82571EB_FIBER:
921 /* Wake events only supported on port A for dual fiber
922 * regardless of eeprom setting */
923 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
924 adapter->eeprom_wol = 0;
925 break;
926 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
927 case E1000_DEV_ID_82571EB_QUAD_COPPER:
928 /* if quad port adapter, disable WoL on all but port A */
929 if (global_quad_port_a != 0)
930 adapter->eeprom_wol = 0;
931 else
932 adapter->quad_port_a = 1;
933 /* Reset for multiple quad port adapters */
934 if (++global_quad_port_a == 4)
935 global_quad_port_a = 0;
936 break;
937 }
938
939 /* initialize the wol settings based on the eeprom settings */
940 adapter->wol = adapter->eeprom_wol;
925 941
926 /* print bus type/speed/width info */ 942 /* print bus type/speed/width info */
927 { 943 {
@@ -964,16 +980,33 @@ e1000_probe(struct pci_dev *pdev,
964 return 0; 980 return 0;
965 981
966err_register: 982err_register:
983 e1000_release_hw_control(adapter);
984err_eeprom:
985 if (!e1000_check_phy_reset_block(&adapter->hw))
986 e1000_phy_hw_reset(&adapter->hw);
987
967 if (adapter->hw.flash_address) 988 if (adapter->hw.flash_address)
968 iounmap(adapter->hw.flash_address); 989 iounmap(adapter->hw.flash_address);
969err_flashmap: 990err_flashmap:
991#ifdef CONFIG_E1000_NAPI
992 for (i = 0; i < adapter->num_rx_queues; i++)
993 dev_put(&adapter->polling_netdev[i]);
994#endif
995
996 kfree(adapter->tx_ring);
997 kfree(adapter->rx_ring);
998#ifdef CONFIG_E1000_NAPI
999 kfree(adapter->polling_netdev);
1000#endif
970err_sw_init: 1001err_sw_init:
971err_eeprom:
972 iounmap(adapter->hw.hw_addr); 1002 iounmap(adapter->hw.hw_addr);
973err_ioremap: 1003err_ioremap:
974 free_netdev(netdev); 1004 free_netdev(netdev);
975err_alloc_etherdev: 1005err_alloc_etherdev:
976 pci_release_regions(pdev); 1006 pci_release_regions(pdev);
1007err_pci_reg:
1008err_dma:
1009 pci_disable_device(pdev);
977 return err; 1010 return err;
978} 1011}
979 1012
@@ -1208,7 +1241,7 @@ e1000_open(struct net_device *netdev)
1208 1241
1209 err = e1000_request_irq(adapter); 1242 err = e1000_request_irq(adapter);
1210 if (err) 1243 if (err)
1211 goto err_up; 1244 goto err_req_irq;
1212 1245
1213 e1000_power_up_phy(adapter); 1246 e1000_power_up_phy(adapter);
1214 1247
@@ -1229,6 +1262,9 @@ e1000_open(struct net_device *netdev)
1229 return E1000_SUCCESS; 1262 return E1000_SUCCESS;
1230 1263
1231err_up: 1264err_up:
1265 e1000_power_down_phy(adapter);
1266 e1000_free_irq(adapter);
1267err_req_irq:
1232 e1000_free_all_rx_resources(adapter); 1268 e1000_free_all_rx_resources(adapter);
1233err_setup_rx: 1269err_setup_rx:
1234 e1000_free_all_tx_resources(adapter); 1270 e1000_free_all_tx_resources(adapter);
@@ -1381,10 +1417,6 @@ setup_tx_desc_die:
1381 * (Descriptors) for all queues 1417 * (Descriptors) for all queues
1382 * @adapter: board private structure 1418 * @adapter: board private structure
1383 * 1419 *
1384 * If this function returns with an error, then it's possible one or
1385 * more of the rings is populated (while the rest are not). It is the
1386 * callers duty to clean those orphaned rings.
1387 *
1388 * Return 0 on success, negative on failure 1420 * Return 0 on success, negative on failure
1389 **/ 1421 **/
1390 1422
@@ -1398,6 +1430,9 @@ e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1398 if (err) { 1430 if (err) {
1399 DPRINTK(PROBE, ERR, 1431 DPRINTK(PROBE, ERR,
1400 "Allocation for Tx Queue %u failed\n", i); 1432 "Allocation for Tx Queue %u failed\n", i);
1433 for (i-- ; i >= 0; i--)
1434 e1000_free_tx_resources(adapter,
1435 &adapter->tx_ring[i]);
1401 break; 1436 break;
1402 } 1437 }
1403 } 1438 }
@@ -1499,8 +1534,6 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1499 } else if (hw->mac_type == e1000_80003es2lan) { 1534 } else if (hw->mac_type == e1000_80003es2lan) {
1500 tarc = E1000_READ_REG(hw, TARC0); 1535 tarc = E1000_READ_REG(hw, TARC0);
1501 tarc |= 1; 1536 tarc |= 1;
1502 if (hw->media_type == e1000_media_type_internal_serdes)
1503 tarc |= (1 << 20);
1504 E1000_WRITE_REG(hw, TARC0, tarc); 1537 E1000_WRITE_REG(hw, TARC0, tarc);
1505 tarc = E1000_READ_REG(hw, TARC1); 1538 tarc = E1000_READ_REG(hw, TARC1);
1506 tarc |= 1; 1539 tarc |= 1;
@@ -1639,10 +1672,6 @@ setup_rx_desc_die:
1639 * (Descriptors) for all queues 1672 * (Descriptors) for all queues
1640 * @adapter: board private structure 1673 * @adapter: board private structure
1641 * 1674 *
1642 * If this function returns with an error, then it's possible one or
1643 * more of the rings is populated (while the rest are not). It is the
1644 * callers duty to clean those orphaned rings.
1645 *
1646 * Return 0 on success, negative on failure 1675 * Return 0 on success, negative on failure
1647 **/ 1676 **/
1648 1677
@@ -1656,6 +1685,9 @@ e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1656 if (err) { 1685 if (err) {
1657 DPRINTK(PROBE, ERR, 1686 DPRINTK(PROBE, ERR,
1658 "Allocation for Rx Queue %u failed\n", i); 1687 "Allocation for Rx Queue %u failed\n", i);
1688 for (i-- ; i >= 0; i--)
1689 e1000_free_rx_resources(adapter,
1690 &adapter->rx_ring[i]);
1659 break; 1691 break;
1660 } 1692 }
1661 } 1693 }
@@ -2442,10 +2474,9 @@ e1000_watchdog(unsigned long data)
2442 * disable receives in the ISR and 2474 * disable receives in the ISR and
2443 * reset device here in the watchdog 2475 * reset device here in the watchdog
2444 */ 2476 */
2445 if (adapter->hw.mac_type == e1000_80003es2lan) { 2477 if (adapter->hw.mac_type == e1000_80003es2lan)
2446 /* reset device */ 2478 /* reset device */
2447 schedule_work(&adapter->reset_task); 2479 schedule_work(&adapter->reset_task);
2448 }
2449 } 2480 }
2450 2481
2451 e1000_smartspeed(adapter); 2482 e1000_smartspeed(adapter);
@@ -2545,7 +2576,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2545 cmd_length = E1000_TXD_CMD_IP; 2576 cmd_length = E1000_TXD_CMD_IP;
2546 ipcse = skb->h.raw - skb->data - 1; 2577 ipcse = skb->h.raw - skb->data - 1;
2547#ifdef NETIF_F_TSO_IPV6 2578#ifdef NETIF_F_TSO_IPV6
2548 } else if (skb->protocol == ntohs(ETH_P_IPV6)) { 2579 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2549 skb->nh.ipv6h->payload_len = 0; 2580 skb->nh.ipv6h->payload_len = 0;
2550 skb->h.th->check = 2581 skb->h.th->check =
2551 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr, 2582 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
@@ -3680,7 +3711,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3680 E1000_DBG("%s: Receive packet consumed multiple" 3711 E1000_DBG("%s: Receive packet consumed multiple"
3681 " buffers\n", netdev->name); 3712 " buffers\n", netdev->name);
3682 /* recycle */ 3713 /* recycle */
3683 buffer_info-> skb = skb; 3714 buffer_info->skb = skb;
3684 goto next_desc; 3715 goto next_desc;
3685 } 3716 }
3686 3717
@@ -3711,7 +3742,6 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3711 netdev_alloc_skb(netdev, length + NET_IP_ALIGN); 3742 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
3712 if (new_skb) { 3743 if (new_skb) {
3713 skb_reserve(new_skb, NET_IP_ALIGN); 3744 skb_reserve(new_skb, NET_IP_ALIGN);
3714 new_skb->dev = netdev;
3715 memcpy(new_skb->data - NET_IP_ALIGN, 3745 memcpy(new_skb->data - NET_IP_ALIGN,
3716 skb->data - NET_IP_ALIGN, 3746 skb->data - NET_IP_ALIGN,
3717 length + NET_IP_ALIGN); 3747 length + NET_IP_ALIGN);
@@ -3978,13 +4008,13 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3978 buffer_info = &rx_ring->buffer_info[i]; 4008 buffer_info = &rx_ring->buffer_info[i];
3979 4009
3980 while (cleaned_count--) { 4010 while (cleaned_count--) {
3981 if (!(skb = buffer_info->skb)) 4011 skb = buffer_info->skb;
3982 skb = netdev_alloc_skb(netdev, bufsz); 4012 if (skb) {
3983 else {
3984 skb_trim(skb, 0); 4013 skb_trim(skb, 0);
3985 goto map_skb; 4014 goto map_skb;
3986 } 4015 }
3987 4016
4017 skb = netdev_alloc_skb(netdev, bufsz);
3988 if (unlikely(!skb)) { 4018 if (unlikely(!skb)) {
3989 /* Better luck next round */ 4019 /* Better luck next round */
3990 adapter->alloc_rx_buff_failed++; 4020 adapter->alloc_rx_buff_failed++;
@@ -4009,10 +4039,10 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4009 dev_kfree_skb(skb); 4039 dev_kfree_skb(skb);
4010 dev_kfree_skb(oldskb); 4040 dev_kfree_skb(oldskb);
4011 break; /* while !buffer_info->skb */ 4041 break; /* while !buffer_info->skb */
4012 } else {
4013 /* Use new allocation */
4014 dev_kfree_skb(oldskb);
4015 } 4042 }
4043
4044 /* Use new allocation */
4045 dev_kfree_skb(oldskb);
4016 } 4046 }
4017 /* Make buffer alignment 2 beyond a 16 byte boundary 4047 /* Make buffer alignment 2 beyond a 16 byte boundary
4018 * this will result in a 16 byte aligned IP header after 4048 * this will result in a 16 byte aligned IP header after
@@ -4020,8 +4050,6 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
4020 */ 4050 */
4021 skb_reserve(skb, NET_IP_ALIGN); 4051 skb_reserve(skb, NET_IP_ALIGN);
4022 4052
4023 skb->dev = netdev;
4024
4025 buffer_info->skb = skb; 4053 buffer_info->skb = skb;
4026 buffer_info->length = adapter->rx_buffer_len; 4054 buffer_info->length = adapter->rx_buffer_len;
4027map_skb: 4055map_skb:
@@ -4135,8 +4163,6 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
4135 */ 4163 */
4136 skb_reserve(skb, NET_IP_ALIGN); 4164 skb_reserve(skb, NET_IP_ALIGN);
4137 4165
4138 skb->dev = netdev;
4139
4140 buffer_info->skb = skb; 4166 buffer_info->skb = skb;
4141 buffer_info->length = adapter->rx_ps_bsize0; 4167 buffer_info->length = adapter->rx_ps_bsize0;
4142 buffer_info->dma = pci_map_single(pdev, skb->data, 4168 buffer_info->dma = pci_map_single(pdev, skb->data,
@@ -4628,7 +4654,7 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4628 e1000_set_multi(netdev); 4654 e1000_set_multi(netdev);
4629 4655
4630 /* turn on all-multi mode if wake on multicast is enabled */ 4656 /* turn on all-multi mode if wake on multicast is enabled */
4631 if (adapter->wol & E1000_WUFC_MC) { 4657 if (wufc & E1000_WUFC_MC) {
4632 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4658 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4633 rctl |= E1000_RCTL_MPE; 4659 rctl |= E1000_RCTL_MPE;
4634 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4660 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
@@ -4700,11 +4726,14 @@ e1000_resume(struct pci_dev *pdev)
4700{ 4726{
4701 struct net_device *netdev = pci_get_drvdata(pdev); 4727 struct net_device *netdev = pci_get_drvdata(pdev);
4702 struct e1000_adapter *adapter = netdev_priv(netdev); 4728 struct e1000_adapter *adapter = netdev_priv(netdev);
4703 uint32_t manc, ret_val; 4729 uint32_t manc, err;
4704 4730
4705 pci_set_power_state(pdev, PCI_D0); 4731 pci_set_power_state(pdev, PCI_D0);
4706 e1000_pci_restore_state(adapter); 4732 e1000_pci_restore_state(adapter);
4707 ret_val = pci_enable_device(pdev); 4733 if ((err = pci_enable_device(pdev))) {
4734 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
4735 return err;
4736 }
4708 pci_set_master(pdev); 4737 pci_set_master(pdev);
4709 4738
4710 pci_enable_wake(pdev, PCI_D3hot, 0); 4739 pci_enable_wake(pdev, PCI_D3hot, 0);
@@ -4782,6 +4811,7 @@ static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channe
4782 4811
4783 if (netif_running(netdev)) 4812 if (netif_running(netdev))
4784 e1000_down(adapter); 4813 e1000_down(adapter);
4814 pci_disable_device(pdev);
4785 4815
4786 /* Request a slot slot reset. */ 4816 /* Request a slot slot reset. */
4787 return PCI_ERS_RESULT_NEED_RESET; 4817 return PCI_ERS_RESULT_NEED_RESET;
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 2d3e8b06cab0..46bc49df15e7 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -42,25 +42,6 @@
42#include <linux/interrupt.h> 42#include <linux/interrupt.h>
43#include <linux/sched.h> 43#include <linux/sched.h>
44 44
45#ifndef msec_delay
46#define msec_delay(x) do { if(in_interrupt()) { \
47 /* Don't mdelay in interrupt context! */ \
48 BUG(); \
49 } else { \
50 msleep(x); \
51 } } while (0)
52
53/* Some workarounds require millisecond delays and are run during interrupt
54 * context. Most notably, when establishing link, the phy may need tweaking
55 * but cannot process phy register reads/writes faster than millisecond
56 * intervals...and we establish link due to a "link status change" interrupt.
57 */
58#define msec_delay_irq(x) mdelay(x)
59#endif
60
61#define PCI_COMMAND_REGISTER PCI_COMMAND
62#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
63
64typedef enum { 45typedef enum {
65#undef FALSE 46#undef FALSE
66 FALSE = 0, 47 FALSE = 0,
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 0ef413172c68..212842738972 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -324,7 +324,6 @@ e1000_check_options(struct e1000_adapter *adapter)
324 DPRINTK(PROBE, NOTICE, 324 DPRINTK(PROBE, NOTICE,
325 "Warning: no configuration for board #%i\n", bd); 325 "Warning: no configuration for board #%i\n", bd);
326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); 326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
327 bd = E1000_MAX_NIC;
328 } 327 }
329 328
330 { /* Transmit Descriptor Count */ 329 { /* Transmit Descriptor Count */
@@ -342,9 +341,14 @@ e1000_check_options(struct e1000_adapter *adapter)
342 opt.arg.r.max = mac_type < e1000_82544 ? 341 opt.arg.r.max = mac_type < e1000_82544 ?
343 E1000_MAX_TXD : E1000_MAX_82544_TXD; 342 E1000_MAX_TXD : E1000_MAX_82544_TXD;
344 343
345 tx_ring->count = TxDescriptors[bd]; 344 if (num_TxDescriptors > bd) {
346 e1000_validate_option(&tx_ring->count, &opt, adapter); 345 tx_ring->count = TxDescriptors[bd];
347 E1000_ROUNDUP(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE); 346 e1000_validate_option(&tx_ring->count, &opt, adapter);
347 E1000_ROUNDUP(tx_ring->count,
348 REQ_TX_DESCRIPTOR_MULTIPLE);
349 } else {
350 tx_ring->count = opt.def;
351 }
348 for (i = 0; i < adapter->num_tx_queues; i++) 352 for (i = 0; i < adapter->num_tx_queues; i++)
349 tx_ring[i].count = tx_ring->count; 353 tx_ring[i].count = tx_ring->count;
350 } 354 }
@@ -363,9 +367,14 @@ e1000_check_options(struct e1000_adapter *adapter)
363 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : 367 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
364 E1000_MAX_82544_RXD; 368 E1000_MAX_82544_RXD;
365 369
366 rx_ring->count = RxDescriptors[bd]; 370 if (num_RxDescriptors > bd) {
367 e1000_validate_option(&rx_ring->count, &opt, adapter); 371 rx_ring->count = RxDescriptors[bd];
368 E1000_ROUNDUP(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE); 372 e1000_validate_option(&rx_ring->count, &opt, adapter);
373 E1000_ROUNDUP(rx_ring->count,
374 REQ_RX_DESCRIPTOR_MULTIPLE);
375 } else {
376 rx_ring->count = opt.def;
377 }
369 for (i = 0; i < adapter->num_rx_queues; i++) 378 for (i = 0; i < adapter->num_rx_queues; i++)
370 rx_ring[i].count = rx_ring->count; 379 rx_ring[i].count = rx_ring->count;
371 } 380 }
@@ -377,9 +386,13 @@ e1000_check_options(struct e1000_adapter *adapter)
377 .def = OPTION_ENABLED 386 .def = OPTION_ENABLED
378 }; 387 };
379 388
380 int rx_csum = XsumRX[bd]; 389 if (num_XsumRX > bd) {
381 e1000_validate_option(&rx_csum, &opt, adapter); 390 int rx_csum = XsumRX[bd];
382 adapter->rx_csum = rx_csum; 391 e1000_validate_option(&rx_csum, &opt, adapter);
392 adapter->rx_csum = rx_csum;
393 } else {
394 adapter->rx_csum = opt.def;
395 }
383 } 396 }
384 { /* Flow Control */ 397 { /* Flow Control */
385 398
@@ -399,9 +412,13 @@ e1000_check_options(struct e1000_adapter *adapter)
399 .p = fc_list }} 412 .p = fc_list }}
400 }; 413 };
401 414
402 int fc = FlowControl[bd]; 415 if (num_FlowControl > bd) {
403 e1000_validate_option(&fc, &opt, adapter); 416 int fc = FlowControl[bd];
404 adapter->hw.fc = adapter->hw.original_fc = fc; 417 e1000_validate_option(&fc, &opt, adapter);
418 adapter->hw.fc = adapter->hw.original_fc = fc;
419 } else {
420 adapter->hw.fc = adapter->hw.original_fc = opt.def;
421 }
405 } 422 }
406 { /* Transmit Interrupt Delay */ 423 { /* Transmit Interrupt Delay */
407 struct e1000_option opt = { 424 struct e1000_option opt = {
@@ -413,8 +430,13 @@ e1000_check_options(struct e1000_adapter *adapter)
413 .max = MAX_TXDELAY }} 430 .max = MAX_TXDELAY }}
414 }; 431 };
415 432
416 adapter->tx_int_delay = TxIntDelay[bd]; 433 if (num_TxIntDelay > bd) {
417 e1000_validate_option(&adapter->tx_int_delay, &opt, adapter); 434 adapter->tx_int_delay = TxIntDelay[bd];
435 e1000_validate_option(&adapter->tx_int_delay, &opt,
436 adapter);
437 } else {
438 adapter->tx_int_delay = opt.def;
439 }
418 } 440 }
419 { /* Transmit Absolute Interrupt Delay */ 441 { /* Transmit Absolute Interrupt Delay */
420 struct e1000_option opt = { 442 struct e1000_option opt = {
@@ -426,9 +448,13 @@ e1000_check_options(struct e1000_adapter *adapter)
426 .max = MAX_TXABSDELAY }} 448 .max = MAX_TXABSDELAY }}
427 }; 449 };
428 450
429 adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 451 if (num_TxAbsIntDelay > bd) {
430 e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 452 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
431 adapter); 453 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
454 adapter);
455 } else {
456 adapter->tx_abs_int_delay = opt.def;
457 }
432 } 458 }
433 { /* Receive Interrupt Delay */ 459 { /* Receive Interrupt Delay */
434 struct e1000_option opt = { 460 struct e1000_option opt = {
@@ -440,8 +466,13 @@ e1000_check_options(struct e1000_adapter *adapter)
440 .max = MAX_RXDELAY }} 466 .max = MAX_RXDELAY }}
441 }; 467 };
442 468
443 adapter->rx_int_delay = RxIntDelay[bd]; 469 if (num_RxIntDelay > bd) {
444 e1000_validate_option(&adapter->rx_int_delay, &opt, adapter); 470 adapter->rx_int_delay = RxIntDelay[bd];
471 e1000_validate_option(&adapter->rx_int_delay, &opt,
472 adapter);
473 } else {
474 adapter->rx_int_delay = opt.def;
475 }
445 } 476 }
446 { /* Receive Absolute Interrupt Delay */ 477 { /* Receive Absolute Interrupt Delay */
447 struct e1000_option opt = { 478 struct e1000_option opt = {
@@ -453,9 +484,13 @@ e1000_check_options(struct e1000_adapter *adapter)
453 .max = MAX_RXABSDELAY }} 484 .max = MAX_RXABSDELAY }}
454 }; 485 };
455 486
456 adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 487 if (num_RxAbsIntDelay > bd) {
457 e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 488 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
458 adapter); 489 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
490 adapter);
491 } else {
492 adapter->rx_abs_int_delay = opt.def;
493 }
459 } 494 }
460 { /* Interrupt Throttling Rate */ 495 { /* Interrupt Throttling Rate */
461 struct e1000_option opt = { 496 struct e1000_option opt = {
@@ -467,18 +502,24 @@ e1000_check_options(struct e1000_adapter *adapter)
467 .max = MAX_ITR }} 502 .max = MAX_ITR }}
468 }; 503 };
469 504
470 adapter->itr = InterruptThrottleRate[bd]; 505 if (num_InterruptThrottleRate > bd) {
471 switch (adapter->itr) { 506 adapter->itr = InterruptThrottleRate[bd];
472 case 0: 507 switch (adapter->itr) {
473 DPRINTK(PROBE, INFO, "%s turned off\n", opt.name); 508 case 0:
474 break; 509 DPRINTK(PROBE, INFO, "%s turned off\n",
475 case 1: 510 opt.name);
476 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 511 break;
477 opt.name); 512 case 1:
478 break; 513 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
479 default: 514 opt.name);
480 e1000_validate_option(&adapter->itr, &opt, adapter); 515 break;
481 break; 516 default:
517 e1000_validate_option(&adapter->itr, &opt,
518 adapter);
519 break;
520 }
521 } else {
522 adapter->itr = opt.def;
482 } 523 }
483 } 524 }
484 { /* Smart Power Down */ 525 { /* Smart Power Down */
@@ -489,9 +530,13 @@ e1000_check_options(struct e1000_adapter *adapter)
489 .def = OPTION_DISABLED 530 .def = OPTION_DISABLED
490 }; 531 };
491 532
492 int spd = SmartPowerDownEnable[bd]; 533 if (num_SmartPowerDownEnable > bd) {
493 e1000_validate_option(&spd, &opt, adapter); 534 int spd = SmartPowerDownEnable[bd];
494 adapter->smart_power_down = spd; 535 e1000_validate_option(&spd, &opt, adapter);
536 adapter->smart_power_down = spd;
537 } else {
538 adapter->smart_power_down = opt.def;
539 }
495 } 540 }
496 { /* Kumeran Lock Loss Workaround */ 541 { /* Kumeran Lock Loss Workaround */
497 struct e1000_option opt = { 542 struct e1000_option opt = {
@@ -501,9 +546,13 @@ e1000_check_options(struct e1000_adapter *adapter)
501 .def = OPTION_ENABLED 546 .def = OPTION_ENABLED
502 }; 547 };
503 548
549 if (num_KumeranLockLoss > bd) {
504 int kmrn_lock_loss = KumeranLockLoss[bd]; 550 int kmrn_lock_loss = KumeranLockLoss[bd];
505 e1000_validate_option(&kmrn_lock_loss, &opt, adapter); 551 e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
506 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss; 552 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
553 } else {
554 adapter->hw.kmrn_lock_loss_workaround_disabled = !opt.def;
555 }
507 } 556 }
508 557
509 switch (adapter->hw.media_type) { 558 switch (adapter->hw.media_type) {
@@ -530,18 +579,17 @@ static void __devinit
530e1000_check_fiber_options(struct e1000_adapter *adapter) 579e1000_check_fiber_options(struct e1000_adapter *adapter)
531{ 580{
532 int bd = adapter->bd_number; 581 int bd = adapter->bd_number;
533 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd; 582 if (num_Speed > bd) {
534 if ((Speed[bd] != OPTION_UNSET)) {
535 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " 583 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
536 "parameter ignored\n"); 584 "parameter ignored\n");
537 } 585 }
538 586
539 if ((Duplex[bd] != OPTION_UNSET)) { 587 if (num_Duplex > bd) {
540 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " 588 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
541 "parameter ignored\n"); 589 "parameter ignored\n");
542 } 590 }
543 591
544 if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) { 592 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) {
545 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " 593 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
546 "not valid for fiber adapters, " 594 "not valid for fiber adapters, "
547 "parameter ignored\n"); 595 "parameter ignored\n");
@@ -560,7 +608,6 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
560{ 608{
561 int speed, dplx, an; 609 int speed, dplx, an;
562 int bd = adapter->bd_number; 610 int bd = adapter->bd_number;
563 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
564 611
565 { /* Speed */ 612 { /* Speed */
566 struct e1000_opt_list speed_list[] = {{ 0, "" }, 613 struct e1000_opt_list speed_list[] = {{ 0, "" },
@@ -577,8 +624,12 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
577 .p = speed_list }} 624 .p = speed_list }}
578 }; 625 };
579 626
580 speed = Speed[bd]; 627 if (num_Speed > bd) {
581 e1000_validate_option(&speed, &opt, adapter); 628 speed = Speed[bd];
629 e1000_validate_option(&speed, &opt, adapter);
630 } else {
631 speed = opt.def;
632 }
582 } 633 }
583 { /* Duplex */ 634 { /* Duplex */
584 struct e1000_opt_list dplx_list[] = {{ 0, "" }, 635 struct e1000_opt_list dplx_list[] = {{ 0, "" },
@@ -600,11 +651,15 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
600 "Speed/Duplex/AutoNeg parameter ignored.\n"); 651 "Speed/Duplex/AutoNeg parameter ignored.\n");
601 return; 652 return;
602 } 653 }
603 dplx = Duplex[bd]; 654 if (num_Duplex > bd) {
604 e1000_validate_option(&dplx, &opt, adapter); 655 dplx = Duplex[bd];
656 e1000_validate_option(&dplx, &opt, adapter);
657 } else {
658 dplx = opt.def;
659 }
605 } 660 }
606 661
607 if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) { 662 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) {
608 DPRINTK(PROBE, INFO, 663 DPRINTK(PROBE, INFO,
609 "AutoNeg specified along with Speed or Duplex, " 664 "AutoNeg specified along with Speed or Duplex, "
610 "parameter ignored\n"); 665 "parameter ignored\n");
@@ -653,15 +708,19 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
653 .p = an_list }} 708 .p = an_list }}
654 }; 709 };
655 710
656 an = AutoNeg[bd]; 711 if (num_AutoNeg > bd) {
657 e1000_validate_option(&an, &opt, adapter); 712 an = AutoNeg[bd];
713 e1000_validate_option(&an, &opt, adapter);
714 } else {
715 an = opt.def;
716 }
658 adapter->hw.autoneg_advertised = an; 717 adapter->hw.autoneg_advertised = an;
659 } 718 }
660 719
661 switch (speed + dplx) { 720 switch (speed + dplx) {
662 case 0: 721 case 0:
663 adapter->hw.autoneg = adapter->fc_autoneg = 1; 722 adapter->hw.autoneg = adapter->fc_autoneg = 1;
664 if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET) 723 if ((num_Speed > bd) && (speed != 0 || dplx != 0))
665 DPRINTK(PROBE, INFO, 724 DPRINTK(PROBE, INFO,
666 "Speed and duplex autonegotiation enabled\n"); 725 "Speed and duplex autonegotiation enabled\n");
667 break; 726 break;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 05:47:04 -0500