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authorDavid Woodhouse <dwmw2@infradead.org>2006-08-30 18:30:38 -0400
committerDavid Woodhouse <dwmw2@infradead.org>2006-08-30 18:30:38 -0400
commit0a7d5f8ce960e74fa22986bda4af488539796e49 (patch)
treee29ad17808a5c3410518e22dae8dfe94801b59f3 /drivers/net/e1000
parent0165508c80a2b5d5268d9c5dfa9b30c534a33693 (diff)
parentdc709bd190c130b299ac19d596594256265c042a (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/e1000.h13
-rw-r--r--drivers/net/e1000/e1000_ethtool.c141
-rw-r--r--drivers/net/e1000/e1000_hw.c1819
-rw-r--r--drivers/net/e1000/e1000_hw.h386
-rw-r--r--drivers/net/e1000/e1000_main.c448
-rw-r--r--drivers/net/e1000/e1000_osdep.h13
-rw-r--r--drivers/net/e1000/e1000_param.c199
7 files changed, 2581 insertions, 438 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 3042d33e2d4d..d304297c496c 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -68,7 +68,6 @@
68#ifdef NETIF_F_TSO 68#ifdef NETIF_F_TSO
69#include <net/checksum.h> 69#include <net/checksum.h>
70#endif 70#endif
71#include <linux/workqueue.h>
72#include <linux/mii.h> 71#include <linux/mii.h>
73#include <linux/ethtool.h> 72#include <linux/ethtool.h>
74#include <linux/if_vlan.h> 73#include <linux/if_vlan.h>
@@ -111,6 +110,9 @@ struct e1000_adapter;
111#define E1000_MIN_RXD 80 110#define E1000_MIN_RXD 80
112#define E1000_MAX_82544_RXD 4096 111#define E1000_MAX_82544_RXD 4096
113 112
113/* this is the size past which hardware will drop packets when setting LPE=0 */
114#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
115
114/* Supported Rx Buffer Sizes */ 116/* Supported Rx Buffer Sizes */
115#define E1000_RXBUFFER_128 128 /* Used for packet split */ 117#define E1000_RXBUFFER_128 128 /* Used for packet split */
116#define E1000_RXBUFFER_256 256 /* Used for packet split */ 118#define E1000_RXBUFFER_256 256 /* Used for packet split */
@@ -143,6 +145,7 @@ struct e1000_adapter;
143 145
144#define AUTO_ALL_MODES 0 146#define AUTO_ALL_MODES 0
145#define E1000_EEPROM_82544_APM 0x0004 147#define E1000_EEPROM_82544_APM 0x0004
148#define E1000_EEPROM_ICH8_APME 0x0004
146#define E1000_EEPROM_APME 0x0400 149#define E1000_EEPROM_APME 0x0400
147 150
148#ifndef E1000_MASTER_SLAVE 151#ifndef E1000_MASTER_SLAVE
@@ -254,7 +257,6 @@ struct e1000_adapter {
254 spinlock_t tx_queue_lock; 257 spinlock_t tx_queue_lock;
255#endif 258#endif
256 atomic_t irq_sem; 259 atomic_t irq_sem;
257 struct work_struct watchdog_task;
258 struct work_struct reset_task; 260 struct work_struct reset_task;
259 uint8_t fc_autoneg; 261 uint8_t fc_autoneg;
260 262
@@ -339,8 +341,14 @@ struct e1000_adapter {
339#ifdef NETIF_F_TSO 341#ifdef NETIF_F_TSO
340 boolean_t tso_force; 342 boolean_t tso_force;
341#endif 343#endif
344 boolean_t smart_power_down; /* phy smart power down */
345 unsigned long flags;
342}; 346};
343 347
348enum e1000_state_t {
349 __E1000_DRIVER_TESTING,
350 __E1000_RESETTING,
351};
344 352
345/* e1000_main.c */ 353/* e1000_main.c */
346extern char e1000_driver_name[]; 354extern char e1000_driver_name[];
@@ -348,6 +356,7 @@ extern char e1000_driver_version[];
348int e1000_up(struct e1000_adapter *adapter); 356int e1000_up(struct e1000_adapter *adapter);
349void e1000_down(struct e1000_adapter *adapter); 357void e1000_down(struct e1000_adapter *adapter);
350void e1000_reset(struct e1000_adapter *adapter); 358void e1000_reset(struct e1000_adapter *adapter);
359void e1000_reinit_locked(struct e1000_adapter *adapter);
351int e1000_setup_all_tx_resources(struct e1000_adapter *adapter); 360int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
352void e1000_free_all_tx_resources(struct e1000_adapter *adapter); 361void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
353int e1000_setup_all_rx_resources(struct e1000_adapter *adapter); 362int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index d19664891768..88a82ba88f57 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -109,7 +109,8 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
109 SUPPORTED_1000baseT_Full| 109 SUPPORTED_1000baseT_Full|
110 SUPPORTED_Autoneg | 110 SUPPORTED_Autoneg |
111 SUPPORTED_TP); 111 SUPPORTED_TP);
112 112 if (hw->phy_type == e1000_phy_ife)
113 ecmd->supported &= ~SUPPORTED_1000baseT_Full;
113 ecmd->advertising = ADVERTISED_TP; 114 ecmd->advertising = ADVERTISED_TP;
114 115
115 if (hw->autoneg == 1) { 116 if (hw->autoneg == 1) {
@@ -203,11 +204,9 @@ e1000_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
203 204
204 /* reset the link */ 205 /* reset the link */
205 206
206 if (netif_running(adapter->netdev)) { 207 if (netif_running(adapter->netdev))
207 e1000_down(adapter); 208 e1000_reinit_locked(adapter);
208 e1000_reset(adapter); 209 else
209 e1000_up(adapter);
210 } else
211 e1000_reset(adapter); 210 e1000_reset(adapter);
212 211
213 return 0; 212 return 0;
@@ -254,10 +253,9 @@ e1000_set_pauseparam(struct net_device *netdev,
254 hw->original_fc = hw->fc; 253 hw->original_fc = hw->fc;
255 254
256 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 255 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
257 if (netif_running(adapter->netdev)) { 256 if (netif_running(adapter->netdev))
258 e1000_down(adapter); 257 e1000_reinit_locked(adapter);
259 e1000_up(adapter); 258 else
260 } else
261 e1000_reset(adapter); 259 e1000_reset(adapter);
262 } else 260 } else
263 return ((hw->media_type == e1000_media_type_fiber) ? 261 return ((hw->media_type == e1000_media_type_fiber) ?
@@ -279,10 +277,9 @@ e1000_set_rx_csum(struct net_device *netdev, uint32_t data)
279 struct e1000_adapter *adapter = netdev_priv(netdev); 277 struct e1000_adapter *adapter = netdev_priv(netdev);
280 adapter->rx_csum = data; 278 adapter->rx_csum = data;
281 279
282 if (netif_running(netdev)) { 280 if (netif_running(netdev))
283 e1000_down(adapter); 281 e1000_reinit_locked(adapter);
284 e1000_up(adapter); 282 else
285 } else
286 e1000_reset(adapter); 283 e1000_reset(adapter);
287 return 0; 284 return 0;
288} 285}
@@ -577,6 +574,7 @@ e1000_get_drvinfo(struct net_device *netdev,
577 case e1000_82572: 574 case e1000_82572:
578 case e1000_82573: 575 case e1000_82573:
579 case e1000_80003es2lan: 576 case e1000_80003es2lan:
577 case e1000_ich8lan:
580 sprintf(firmware_version, "%d.%d-%d", 578 sprintf(firmware_version, "%d.%d-%d",
581 (eeprom_data & 0xF000) >> 12, 579 (eeprom_data & 0xF000) >> 12,
582 (eeprom_data & 0x0FF0) >> 4, 580 (eeprom_data & 0x0FF0) >> 4,
@@ -631,6 +629,9 @@ e1000_set_ringparam(struct net_device *netdev,
631 tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues; 629 tx_ring_size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
632 rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues; 630 rx_ring_size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
633 631
632 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
633 msleep(1);
634
634 if (netif_running(adapter->netdev)) 635 if (netif_running(adapter->netdev))
635 e1000_down(adapter); 636 e1000_down(adapter);
636 637
@@ -691,9 +692,11 @@ e1000_set_ringparam(struct net_device *netdev,
691 adapter->rx_ring = rx_new; 692 adapter->rx_ring = rx_new;
692 adapter->tx_ring = tx_new; 693 adapter->tx_ring = tx_new;
693 if ((err = e1000_up(adapter))) 694 if ((err = e1000_up(adapter)))
694 return err; 695 goto err_setup;
695 } 696 }
696 697
698 clear_bit(__E1000_RESETTING, &adapter->flags);
699
697 return 0; 700 return 0;
698err_setup_tx: 701err_setup_tx:
699 e1000_free_all_rx_resources(adapter); 702 e1000_free_all_rx_resources(adapter);
@@ -701,6 +704,8 @@ err_setup_rx:
701 adapter->rx_ring = rx_old; 704 adapter->rx_ring = rx_old;
702 adapter->tx_ring = tx_old; 705 adapter->tx_ring = tx_old;
703 e1000_up(adapter); 706 e1000_up(adapter);
707err_setup:
708 clear_bit(__E1000_RESETTING, &adapter->flags);
704 return err; 709 return err;
705} 710}
706 711
@@ -754,6 +759,7 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
754 toggle = 0x7FFFF3FF; 759 toggle = 0x7FFFF3FF;
755 break; 760 break;
756 case e1000_82573: 761 case e1000_82573:
762 case e1000_ich8lan:
757 toggle = 0x7FFFF033; 763 toggle = 0x7FFFF033;
758 break; 764 break;
759 default: 765 default:
@@ -773,11 +779,12 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
773 } 779 }
774 /* restore previous status */ 780 /* restore previous status */
775 E1000_WRITE_REG(&adapter->hw, STATUS, before); 781 E1000_WRITE_REG(&adapter->hw, STATUS, before);
776 782 if (adapter->hw.mac_type != e1000_ich8lan) {
777 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 783 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
778 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 784 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
779 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); 785 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
780 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); 786 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
787 }
781 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); 788 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
782 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); 789 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
783 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); 790 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -790,20 +797,22 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
790 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); 797 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
791 798
792 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); 799 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
793 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB); 800 before = (adapter->hw.mac_type == e1000_ich8lan ?
801 0x06C3B33E : 0x06DFB3FE);
802 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
794 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); 803 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
795 804
796 if (adapter->hw.mac_type >= e1000_82543) { 805 if (adapter->hw.mac_type >= e1000_82543) {
797 806
798 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF); 807 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
799 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 808 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
800 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); 809 if (adapter->hw.mac_type != e1000_ich8lan)
810 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
801 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 811 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
802 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); 812 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
803 813 value = (adapter->hw.mac_type == e1000_ich8lan ?
804 for (i = 0; i < E1000_RAR_ENTRIES; i++) { 814 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
805 REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF, 815 for (i = 0; i < value; i++) {
806 0xFFFFFFFF);
807 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, 816 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
808 0xFFFFFFFF); 817 0xFFFFFFFF);
809 } 818 }
@@ -817,7 +826,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
817 826
818 } 827 }
819 828
820 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 829 value = (adapter->hw.mac_type == e1000_ich8lan ?
830 E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
831 for (i = 0; i < value; i++)
821 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); 832 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
822 833
823 *data = 0; 834 *data = 0;
@@ -889,6 +900,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
889 /* Test each interrupt */ 900 /* Test each interrupt */
890 for (; i < 10; i++) { 901 for (; i < 10; i++) {
891 902
903 if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
904 continue;
892 /* Interrupt to test */ 905 /* Interrupt to test */
893 mask = 1 << i; 906 mask = 1 << i;
894 907
@@ -1246,18 +1259,33 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1246 } else if (adapter->hw.phy_type == e1000_phy_gg82563) { 1259 } else if (adapter->hw.phy_type == e1000_phy_gg82563) {
1247 e1000_write_phy_reg(&adapter->hw, 1260 e1000_write_phy_reg(&adapter->hw,
1248 GG82563_PHY_KMRN_MODE_CTRL, 1261 GG82563_PHY_KMRN_MODE_CTRL,
1249 0x1CE); 1262 0x1CC);
1250 } 1263 }
1251 /* force 1000, set loopback */
1252 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1253 1264
1254 /* Now set up the MAC to the same speed/duplex as the PHY. */
1255 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1265 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1256 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1266
1257 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1267 if (adapter->hw.phy_type == e1000_phy_ife) {
1258 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1268 /* force 100, set loopback */
1259 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x6100);
1260 E1000_CTRL_FD); /* Force Duplex to FULL */ 1270
1271 /* Now set up the MAC to the same speed/duplex as the PHY. */
1272 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1273 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1274 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1275 E1000_CTRL_SPD_100 |/* Force Speed to 100 */
1276 E1000_CTRL_FD); /* Force Duplex to FULL */
1277 } else {
1278 /* force 1000, set loopback */
1279 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1280
1281 /* Now set up the MAC to the same speed/duplex as the PHY. */
1282 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1283 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1284 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1285 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1286 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1287 E1000_CTRL_FD); /* Force Duplex to FULL */
1288 }
1261 1289
1262 if (adapter->hw.media_type == e1000_media_type_copper && 1290 if (adapter->hw.media_type == e1000_media_type_copper &&
1263 adapter->hw.phy_type == e1000_phy_m88) { 1291 adapter->hw.phy_type == e1000_phy_m88) {
@@ -1317,6 +1345,7 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1317 case e1000_82572: 1345 case e1000_82572:
1318 case e1000_82573: 1346 case e1000_82573:
1319 case e1000_80003es2lan: 1347 case e1000_80003es2lan:
1348 case e1000_ich8lan:
1320 return e1000_integrated_phy_loopback(adapter); 1349 return e1000_integrated_phy_loopback(adapter);
1321 break; 1350 break;
1322 1351
@@ -1568,6 +1597,7 @@ e1000_diag_test(struct net_device *netdev,
1568 struct e1000_adapter *adapter = netdev_priv(netdev); 1597 struct e1000_adapter *adapter = netdev_priv(netdev);
1569 boolean_t if_running = netif_running(netdev); 1598 boolean_t if_running = netif_running(netdev);
1570 1599
1600 set_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1571 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1601 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1572 /* Offline tests */ 1602 /* Offline tests */
1573 1603
@@ -1582,7 +1612,8 @@ e1000_diag_test(struct net_device *netdev,
1582 eth_test->flags |= ETH_TEST_FL_FAILED; 1612 eth_test->flags |= ETH_TEST_FL_FAILED;
1583 1613
1584 if (if_running) 1614 if (if_running)
1585 e1000_down(adapter); 1615 /* indicate we're in test mode */
1616 dev_close(netdev);
1586 else 1617 else
1587 e1000_reset(adapter); 1618 e1000_reset(adapter);
1588 1619
@@ -1607,8 +1638,9 @@ e1000_diag_test(struct net_device *netdev,
1607 adapter->hw.autoneg = autoneg; 1638 adapter->hw.autoneg = autoneg;
1608 1639
1609 e1000_reset(adapter); 1640 e1000_reset(adapter);
1641 clear_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1610 if (if_running) 1642 if (if_running)
1611 e1000_up(adapter); 1643 dev_open(netdev);
1612 } else { 1644 } else {
1613 /* Online tests */ 1645 /* Online tests */
1614 if (e1000_link_test(adapter, &data[4])) 1646 if (e1000_link_test(adapter, &data[4]))
@@ -1619,6 +1651,8 @@ e1000_diag_test(struct net_device *netdev,
1619 data[1] = 0; 1651 data[1] = 0;
1620 data[2] = 0; 1652 data[2] = 0;
1621 data[3] = 0; 1653 data[3] = 0;
1654
1655 clear_bit(__E1000_DRIVER_TESTING, &adapter->flags);
1622 } 1656 }
1623 msleep_interruptible(4 * 1000); 1657 msleep_interruptible(4 * 1000);
1624} 1658}
@@ -1778,21 +1812,18 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
1778 mod_timer(&adapter->blink_timer, jiffies); 1812 mod_timer(&adapter->blink_timer, jiffies);
1779 msleep_interruptible(data * 1000); 1813 msleep_interruptible(data * 1000);
1780 del_timer_sync(&adapter->blink_timer); 1814 del_timer_sync(&adapter->blink_timer);
1781 } else if (adapter->hw.mac_type < e1000_82573) { 1815 } else if (adapter->hw.phy_type == e1000_phy_ife) {
1782 E1000_WRITE_REG(&adapter->hw, LEDCTL, 1816 if (!adapter->blink_timer.function) {
1783 (E1000_LEDCTL_LED2_BLINK_RATE | 1817 init_timer(&adapter->blink_timer);
1784 E1000_LEDCTL_LED0_BLINK | E1000_LEDCTL_LED2_BLINK | 1818 adapter->blink_timer.function = e1000_led_blink_callback;
1785 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED2_MODE_SHIFT) | 1819 adapter->blink_timer.data = (unsigned long) adapter;
1786 (E1000_LEDCTL_MODE_LINK_ACTIVITY << E1000_LEDCTL_LED0_MODE_SHIFT) | 1820 }
1787 (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED1_MODE_SHIFT))); 1821 mod_timer(&adapter->blink_timer, jiffies);
1788 msleep_interruptible(data * 1000); 1822 msleep_interruptible(data * 1000);
1823 del_timer_sync(&adapter->blink_timer);
1824 e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
1789 } else { 1825 } else {
1790 E1000_WRITE_REG(&adapter->hw, LEDCTL, 1826 e1000_blink_led_start(&adapter->hw);
1791 (E1000_LEDCTL_LED2_BLINK_RATE |
1792 E1000_LEDCTL_LED1_BLINK | E1000_LEDCTL_LED2_BLINK |
1793 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED2_MODE_SHIFT) |
1794 (E1000_LEDCTL_MODE_LINK_ACTIVITY << E1000_LEDCTL_LED1_MODE_SHIFT) |
1795 (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT)));
1796 msleep_interruptible(data * 1000); 1827 msleep_interruptible(data * 1000);
1797 } 1828 }
1798 1829
@@ -1807,10 +1838,8 @@ static int
1807e1000_nway_reset(struct net_device *netdev) 1838e1000_nway_reset(struct net_device *netdev)
1808{ 1839{
1809 struct e1000_adapter *adapter = netdev_priv(netdev); 1840 struct e1000_adapter *adapter = netdev_priv(netdev);
1810 if (netif_running(netdev)) { 1841 if (netif_running(netdev))
1811 e1000_down(adapter); 1842 e1000_reinit_locked(adapter);
1812 e1000_up(adapter);
1813 }
1814 return 0; 1843 return 0;
1815} 1844}
1816 1845
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 3959039b16ec..b3b919116e0f 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -101,9 +101,37 @@ static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 101
102#define E1000_WRITE_REG_IO(a, reg, val) \ 102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val) 103 e1000_write_reg_io((a), E1000_##reg, val)
104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
105static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
106 107
108static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
109 uint32_t segment);
110static int32_t e1000_get_software_flag(struct e1000_hw *hw);
111static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
112static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
113static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
114static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
115 uint16_t words, uint16_t *data);
116static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
117 uint8_t* data);
118static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
119 uint16_t *data);
120static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
121 uint16_t *data);
122static void e1000_release_software_flag(struct e1000_hw *hw);
123static void e1000_release_software_semaphore(struct e1000_hw *hw);
124static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
125 uint32_t no_snoop);
126static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
127 uint32_t index, uint8_t byte);
128static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
129 uint16_t words, uint16_t *data);
130static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
131 uint8_t data);
132static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
133 uint16_t data);
134
107/* IGP cable length table */ 135/* IGP cable length table */
108static const 136static const
109uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 137uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
@@ -156,6 +184,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
156 hw->phy_type = e1000_phy_igp; 184 hw->phy_type = e1000_phy_igp;
157 break; 185 break;
158 } 186 }
187 case IGP03E1000_E_PHY_ID:
188 hw->phy_type = e1000_phy_igp_3;
189 break;
190 case IFE_E_PHY_ID:
191 case IFE_PLUS_E_PHY_ID:
192 case IFE_C_E_PHY_ID:
193 hw->phy_type = e1000_phy_ife;
194 break;
159 case GG82563_E_PHY_ID: 195 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) { 196 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563; 197 hw->phy_type = e1000_phy_gg82563;
@@ -332,6 +368,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
332 break; 368 break;
333 case E1000_DEV_ID_82541EI: 369 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE: 370 case E1000_DEV_ID_82541EI_MOBILE:
371 case E1000_DEV_ID_82541ER_LOM:
335 hw->mac_type = e1000_82541; 372 hw->mac_type = e1000_82541;
336 break; 373 break;
337 case E1000_DEV_ID_82541ER: 374 case E1000_DEV_ID_82541ER:
@@ -341,6 +378,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
341 hw->mac_type = e1000_82541_rev_2; 378 hw->mac_type = e1000_82541_rev_2;
342 break; 379 break;
343 case E1000_DEV_ID_82547EI: 380 case E1000_DEV_ID_82547EI:
381 case E1000_DEV_ID_82547EI_MOBILE:
344 hw->mac_type = e1000_82547; 382 hw->mac_type = e1000_82547;
345 break; 383 break;
346 case E1000_DEV_ID_82547GI: 384 case E1000_DEV_ID_82547GI:
@@ -354,6 +392,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
354 case E1000_DEV_ID_82572EI_COPPER: 392 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER: 393 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES: 394 case E1000_DEV_ID_82572EI_SERDES:
395 case E1000_DEV_ID_82572EI:
357 hw->mac_type = e1000_82572; 396 hw->mac_type = e1000_82572;
358 break; 397 break;
359 case E1000_DEV_ID_82573E: 398 case E1000_DEV_ID_82573E:
@@ -361,16 +400,29 @@ e1000_set_mac_type(struct e1000_hw *hw)
361 case E1000_DEV_ID_82573L: 400 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573; 401 hw->mac_type = e1000_82573;
363 break; 402 break;
403 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
404 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 405 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 406 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan; 407 hw->mac_type = e1000_80003es2lan;
367 break; 408 break;
409 case E1000_DEV_ID_ICH8_IGP_M_AMT:
410 case E1000_DEV_ID_ICH8_IGP_AMT:
411 case E1000_DEV_ID_ICH8_IGP_C:
412 case E1000_DEV_ID_ICH8_IFE:
413 case E1000_DEV_ID_ICH8_IGP_M:
414 hw->mac_type = e1000_ich8lan;
415 break;
368 default: 416 default:
369 /* Should never have loaded on this device */ 417 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE; 418 return -E1000_ERR_MAC_TYPE;
371 } 419 }
372 420
373 switch(hw->mac_type) { 421 switch(hw->mac_type) {
422 case e1000_ich8lan:
423 hw->swfwhw_semaphore_present = TRUE;
424 hw->asf_firmware_present = TRUE;
425 break;
374 case e1000_80003es2lan: 426 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE; 427 hw->swfw_sync_present = TRUE;
376 /* fall through */ 428 /* fall through */
@@ -423,6 +475,7 @@ e1000_set_media_type(struct e1000_hw *hw)
423 case e1000_82542_rev2_1: 475 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber; 476 hw->media_type = e1000_media_type_fiber;
425 break; 477 break;
478 case e1000_ich8lan:
426 case e1000_82573: 479 case e1000_82573:
427 /* The STATUS_TBIMODE bit is reserved or reused for the this 480 /* The STATUS_TBIMODE bit is reserved or reused for the this
428 * device. 481 * device.
@@ -527,6 +580,14 @@ e1000_reset_hw(struct e1000_hw *hw)
527 } while(timeout); 580 } while(timeout);
528 } 581 }
529 582
583 /* Workaround for ICH8 bit corruption issue in FIFO memory */
584 if (hw->mac_type == e1000_ich8lan) {
585 /* Set Tx and Rx buffer allocation to 8k apiece. */
586 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
587 /* Set Packet Buffer Size to 16k. */
588 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
589 }
590
530 /* Issue a global reset to the MAC. This will reset the chip's 591 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect 592 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self- 593 * the current PCI configuration. The global reset bit is self-
@@ -550,6 +611,20 @@ e1000_reset_hw(struct e1000_hw *hw)
550 /* Reset is performed on a shadow of the control register */ 611 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 612 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
552 break; 613 break;
614 case e1000_ich8lan:
615 if (!hw->phy_reset_disable &&
616 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
617 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
618 * at the same time to make sure the interface between
619 * MAC and the external PHY is reset.
620 */
621 ctrl |= E1000_CTRL_PHY_RST;
622 }
623
624 e1000_get_software_flag(hw);
625 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
626 msec_delay(5);
627 break;
553 default: 628 default:
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 629 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
555 break; 630 break;
@@ -591,6 +666,7 @@ e1000_reset_hw(struct e1000_hw *hw)
591 /* fall through */ 666 /* fall through */
592 case e1000_82571: 667 case e1000_82571:
593 case e1000_82572: 668 case e1000_82572:
669 case e1000_ich8lan:
594 case e1000_80003es2lan: 670 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw); 671 ret_val = e1000_get_auto_rd_done(hw);
596 if(ret_val) 672 if(ret_val)
@@ -633,6 +709,12 @@ e1000_reset_hw(struct e1000_hw *hw)
633 e1000_pci_set_mwi(hw); 709 e1000_pci_set_mwi(hw);
634 } 710 }
635 711
712 if (hw->mac_type == e1000_ich8lan) {
713 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
714 kab |= E1000_KABGTXD_BGSQLBIAS;
715 E1000_WRITE_REG(hw, KABGTXD, kab);
716 }
717
636 return E1000_SUCCESS; 718 return E1000_SUCCESS;
637} 719}
638 720
@@ -675,9 +757,12 @@ e1000_init_hw(struct e1000_hw *hw)
675 757
676 /* Disabling VLAN filtering. */ 758 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n"); 759 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3) 760 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
679 E1000_WRITE_REG(hw, VET, 0); 761 if (hw->mac_type != e1000_ich8lan) {
680 e1000_clear_vfta(hw); 762 if (hw->mac_type < e1000_82545_rev_3)
763 E1000_WRITE_REG(hw, VET, 0);
764 e1000_clear_vfta(hw);
765 }
681 766
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 767 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) { 768 if(hw->mac_type == e1000_82542_rev2_0) {
@@ -705,8 +790,14 @@ e1000_init_hw(struct e1000_hw *hw)
705 /* Zero out the Multicast HASH table */ 790 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n"); 791 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE; 792 mta_size = E1000_MC_TBL_SIZE;
708 for(i = 0; i < mta_size; i++) 793 if (hw->mac_type == e1000_ich8lan)
794 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
795 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 796 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
797 /* use write flush to prevent Memory Write Block (MWB) from
798 * occuring when accessing our register space */
799 E1000_WRITE_FLUSH(hw);
800 }
710 801
711 /* Set the PCI priority bit correctly in the CTRL register. This 802 /* Set the PCI priority bit correctly in the CTRL register. This
712 * determines if the adapter gives priority to receives, or if it 803 * determines if the adapter gives priority to receives, or if it
@@ -744,6 +835,10 @@ e1000_init_hw(struct e1000_hw *hw)
744 break; 835 break;
745 } 836 }
746 837
838 /* More time needed for PHY to initialize */
839 if (hw->mac_type == e1000_ich8lan)
840 msec_delay(15);
841
747 /* Call a subroutine to configure the link and setup flow control. */ 842 /* Call a subroutine to configure the link and setup flow control. */
748 ret_val = e1000_setup_link(hw); 843 ret_val = e1000_setup_link(hw);
749 844
@@ -757,6 +852,7 @@ e1000_init_hw(struct e1000_hw *hw)
757 case e1000_82571: 852 case e1000_82571:
758 case e1000_82572: 853 case e1000_82572:
759 case e1000_82573: 854 case e1000_82573:
855 case e1000_ich8lan:
760 case e1000_80003es2lan: 856 case e1000_80003es2lan:
761 ctrl |= E1000_TXDCTL_COUNT_DESC; 857 ctrl |= E1000_TXDCTL_COUNT_DESC;
762 break; 858 break;
@@ -795,6 +891,7 @@ e1000_init_hw(struct e1000_hw *hw)
795 /* Fall through */ 891 /* Fall through */
796 case e1000_82571: 892 case e1000_82571:
797 case e1000_82572: 893 case e1000_82572:
894 case e1000_ich8lan:
798 ctrl = E1000_READ_REG(hw, TXDCTL1); 895 ctrl = E1000_READ_REG(hw, TXDCTL1);
799 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 896 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
800 if(hw->mac_type >= e1000_82571) 897 if(hw->mac_type >= e1000_82571)
@@ -818,6 +915,11 @@ e1000_init_hw(struct e1000_hw *hw)
818 */ 915 */
819 e1000_clear_hw_cntrs(hw); 916 e1000_clear_hw_cntrs(hw);
820 917
918 /* ICH8 No-snoop bits are opposite polarity.
919 * Set to snoop by default after reset. */
920 if (hw->mac_type == e1000_ich8lan)
921 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
922
821 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 923 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
822 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 924 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
823 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 925 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -905,6 +1007,7 @@ e1000_setup_link(struct e1000_hw *hw)
905 */ 1007 */
906 if (hw->fc == e1000_fc_default) { 1008 if (hw->fc == e1000_fc_default) {
907 switch (hw->mac_type) { 1009 switch (hw->mac_type) {
1010 case e1000_ich8lan:
908 case e1000_82573: 1011 case e1000_82573:
909 hw->fc = e1000_fc_full; 1012 hw->fc = e1000_fc_full;
910 break; 1013 break;
@@ -971,9 +1074,12 @@ e1000_setup_link(struct e1000_hw *hw)
971 */ 1074 */
972 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1075 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
973 1076
974 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1077 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
975 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1078 if (hw->mac_type != e1000_ich8lan) {
976 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1079 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1080 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1081 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1082 }
977 1083
978 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1084 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
979 1085
@@ -1237,12 +1343,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1237 1343
1238 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1344 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1239 msec_delay(15); 1345 msec_delay(15);
1240 1346 if (hw->mac_type != e1000_ich8lan) {
1241 /* Configure activity LED after PHY reset */ 1347 /* Configure activity LED after PHY reset */
1242 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1348 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1243 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1349 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1244 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1350 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1245 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1351 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1352 }
1246 1353
1247 /* disable lplu d3 during driver init */ 1354 /* disable lplu d3 during driver init */
1248 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1355 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
@@ -1478,8 +1585,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1478 if (ret_val) 1585 if (ret_val)
1479 return ret_val; 1586 return ret_val;
1480 1587
1481 /* Enable Pass False Carrier on the PHY */ 1588 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1482 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1483 1589
1484 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1590 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1485 phy_data); 1591 phy_data);
@@ -1561,28 +1667,40 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1561 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1667 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1562 if(hw->disable_polarity_correction == 1) 1668 if(hw->disable_polarity_correction == 1)
1563 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1669 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1564 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1670 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1565 if(ret_val) 1671 if (ret_val)
1566 return ret_val;
1567
1568 /* Force TX_CLK in the Extended PHY Specific Control Register
1569 * to 25MHz clock.
1570 */
1571 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1572 if(ret_val)
1573 return ret_val; 1672 return ret_val;
1574 1673
1575 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1576
1577 if (hw->phy_revision < M88E1011_I_REV_4) { 1674 if (hw->phy_revision < M88E1011_I_REV_4) {
1578 /* Configure Master and Slave downshift values */ 1675 /* Force TX_CLK in the Extended PHY Specific Control Register
1579 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1676 * to 25MHz clock.
1677 */
1678 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1679 if (ret_val)
1680 return ret_val;
1681
1682 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1683
1684 if ((hw->phy_revision == E1000_REVISION_2) &&
1685 (hw->phy_id == M88E1111_I_PHY_ID)) {
1686 /* Vidalia Phy, set the downshift counter to 5x */
1687 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1688 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1689 ret_val = e1000_write_phy_reg(hw,
1690 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1691 if (ret_val)
1692 return ret_val;
1693 } else {
1694 /* Configure Master and Slave downshift values */
1695 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1580 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1696 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1581 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1697 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1582 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1698 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1583 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1699 ret_val = e1000_write_phy_reg(hw,
1584 if(ret_val) 1700 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1585 return ret_val; 1701 if (ret_val)
1702 return ret_val;
1703 }
1586 } 1704 }
1587 1705
1588 /* SW Reset the PHY so all changes take effect */ 1706 /* SW Reset the PHY so all changes take effect */
@@ -1620,6 +1738,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1620 if(hw->autoneg_advertised == 0) 1738 if(hw->autoneg_advertised == 0)
1621 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1739 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1622 1740
1741 /* IFE phy only supports 10/100 */
1742 if (hw->phy_type == e1000_phy_ife)
1743 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1744
1623 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1745 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1624 ret_val = e1000_phy_setup_autoneg(hw); 1746 ret_val = e1000_phy_setup_autoneg(hw);
1625 if(ret_val) { 1747 if(ret_val) {
@@ -1717,6 +1839,26 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1717 1839
1718 DEBUGFUNC("e1000_setup_copper_link"); 1840 DEBUGFUNC("e1000_setup_copper_link");
1719 1841
1842 switch (hw->mac_type) {
1843 case e1000_80003es2lan:
1844 case e1000_ich8lan:
1845 /* Set the mac to wait the maximum time between each
1846 * iteration and increase the max iterations when
1847 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1848 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1849 if (ret_val)
1850 return ret_val;
1851 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1852 if (ret_val)
1853 return ret_val;
1854 reg_data |= 0x3F;
1855 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1856 if (ret_val)
1857 return ret_val;
1858 default:
1859 break;
1860 }
1861
1720 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1862 /* Check if it is a valid PHY and set PHY mode if necessary. */
1721 ret_val = e1000_copper_link_preconfig(hw); 1863 ret_val = e1000_copper_link_preconfig(hw);
1722 if(ret_val) 1864 if(ret_val)
@@ -1724,10 +1866,8 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1724 1866
1725 switch (hw->mac_type) { 1867 switch (hw->mac_type) {
1726 case e1000_80003es2lan: 1868 case e1000_80003es2lan:
1727 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1869 /* Kumeran registers are written-only */
1728 &reg_data); 1870 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1729 if (ret_val)
1730 return ret_val;
1731 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1871 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1732 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1872 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1733 reg_data); 1873 reg_data);
@@ -1739,6 +1879,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1739 } 1879 }
1740 1880
1741 if (hw->phy_type == e1000_phy_igp || 1881 if (hw->phy_type == e1000_phy_igp ||
1882 hw->phy_type == e1000_phy_igp_3 ||
1742 hw->phy_type == e1000_phy_igp_2) { 1883 hw->phy_type == e1000_phy_igp_2) {
1743 ret_val = e1000_copper_link_igp_setup(hw); 1884 ret_val = e1000_copper_link_igp_setup(hw);
1744 if(ret_val) 1885 if(ret_val)
@@ -1803,7 +1944,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1803* hw - Struct containing variables accessed by shared code 1944* hw - Struct containing variables accessed by shared code
1804******************************************************************************/ 1945******************************************************************************/
1805static int32_t 1946static int32_t
1806e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) 1947e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1807{ 1948{
1808 int32_t ret_val = E1000_SUCCESS; 1949 int32_t ret_val = E1000_SUCCESS;
1809 uint32_t tipg; 1950 uint32_t tipg;
@@ -1823,6 +1964,18 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1823 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1964 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1824 E1000_WRITE_REG(hw, TIPG, tipg); 1965 E1000_WRITE_REG(hw, TIPG, tipg);
1825 1966
1967 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1968
1969 if (ret_val)
1970 return ret_val;
1971
1972 if (duplex == HALF_DUPLEX)
1973 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1974 else
1975 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1976
1977 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1978
1826 return ret_val; 1979 return ret_val;
1827} 1980}
1828 1981
@@ -1847,6 +2000,14 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1847 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2000 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1848 E1000_WRITE_REG(hw, TIPG, tipg); 2001 E1000_WRITE_REG(hw, TIPG, tipg);
1849 2002
2003 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2004
2005 if (ret_val)
2006 return ret_val;
2007
2008 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2009 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2010
1850 return ret_val; 2011 return ret_val;
1851} 2012}
1852 2013
@@ -1869,10 +2030,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1869 if(ret_val) 2030 if(ret_val)
1870 return ret_val; 2031 return ret_val;
1871 2032
1872 /* Read the MII 1000Base-T Control Register (Address 9). */ 2033 if (hw->phy_type != e1000_phy_ife) {
1873 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2034 /* Read the MII 1000Base-T Control Register (Address 9). */
1874 if(ret_val) 2035 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1875 return ret_val; 2036 if (ret_val)
2037 return ret_val;
2038 } else
2039 mii_1000t_ctrl_reg=0;
1876 2040
1877 /* Need to parse both autoneg_advertised and fc and set up 2041 /* Need to parse both autoneg_advertised and fc and set up
1878 * the appropriate PHY registers. First we will parse for 2042 * the appropriate PHY registers. First we will parse for
@@ -1923,6 +2087,9 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1923 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2087 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1924 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2088 DEBUGOUT("Advertise 1000mb Full duplex\n");
1925 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2089 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2090 if (hw->phy_type == e1000_phy_ife) {
2091 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2092 }
1926 } 2093 }
1927 2094
1928 /* Check for a software override of the flow control settings, and 2095 /* Check for a software override of the flow control settings, and
@@ -1984,9 +2151,11 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1984 2151
1985 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2152 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1986 2153
1987 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2154 if (hw->phy_type != e1000_phy_ife) {
1988 if(ret_val) 2155 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1989 return ret_val; 2156 if (ret_val)
2157 return ret_val;
2158 }
1990 2159
1991 return E1000_SUCCESS; 2160 return E1000_SUCCESS;
1992} 2161}
@@ -2089,6 +2258,18 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2089 2258
2090 /* Need to reset the PHY or these changes will be ignored */ 2259 /* Need to reset the PHY or these changes will be ignored */
2091 mii_ctrl_reg |= MII_CR_RESET; 2260 mii_ctrl_reg |= MII_CR_RESET;
2261 /* Disable MDI-X support for 10/100 */
2262 } else if (hw->phy_type == e1000_phy_ife) {
2263 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2264 if (ret_val)
2265 return ret_val;
2266
2267 phy_data &= ~IFE_PMC_AUTO_MDIX;
2268 phy_data &= ~IFE_PMC_FORCE_MDIX;
2269
2270 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2271 if (ret_val)
2272 return ret_val;
2092 } else { 2273 } else {
2093 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2274 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2094 * forced whenever speed or duplex are forced. 2275 * forced whenever speed or duplex are forced.
@@ -2721,8 +2902,12 @@ e1000_check_for_link(struct e1000_hw *hw)
2721 */ 2902 */
2722 if(hw->tbi_compatibility_en) { 2903 if(hw->tbi_compatibility_en) {
2723 uint16_t speed, duplex; 2904 uint16_t speed, duplex;
2724 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2905 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2725 if(speed != SPEED_1000) { 2906 if (ret_val) {
2907 DEBUGOUT("Error getting link speed and duplex\n");
2908 return ret_val;
2909 }
2910 if (speed != SPEED_1000) {
2726 /* If link speed is not set to gigabit speed, we do not need 2911 /* If link speed is not set to gigabit speed, we do not need
2727 * to enable TBI compatibility. 2912 * to enable TBI compatibility.
2728 */ 2913 */
@@ -2889,7 +3074,13 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2889 if (*speed == SPEED_1000) 3074 if (*speed == SPEED_1000)
2890 ret_val = e1000_configure_kmrn_for_1000(hw); 3075 ret_val = e1000_configure_kmrn_for_1000(hw);
2891 else 3076 else
2892 ret_val = e1000_configure_kmrn_for_10_100(hw); 3077 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3078 if (ret_val)
3079 return ret_val;
3080 }
3081
3082 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3083 ret_val = e1000_kumeran_lock_loss_workaround(hw);
2893 if (ret_val) 3084 if (ret_val)
2894 return ret_val; 3085 return ret_val;
2895 } 3086 }
@@ -3069,7 +3260,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3069 return data; 3260 return data;
3070} 3261}
3071 3262
3072int32_t 3263static int32_t
3073e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) 3264e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3074{ 3265{
3075 uint32_t swfw_sync = 0; 3266 uint32_t swfw_sync = 0;
@@ -3079,6 +3270,9 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3079 3270
3080 DEBUGFUNC("e1000_swfw_sync_acquire"); 3271 DEBUGFUNC("e1000_swfw_sync_acquire");
3081 3272
3273 if (hw->swfwhw_semaphore_present)
3274 return e1000_get_software_flag(hw);
3275
3082 if (!hw->swfw_sync_present) 3276 if (!hw->swfw_sync_present)
3083 return e1000_get_hw_eeprom_semaphore(hw); 3277 return e1000_get_hw_eeprom_semaphore(hw);
3084 3278
@@ -3110,7 +3304,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3110 return E1000_SUCCESS; 3304 return E1000_SUCCESS;
3111} 3305}
3112 3306
3113void 3307static void
3114e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) 3308e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3115{ 3309{
3116 uint32_t swfw_sync; 3310 uint32_t swfw_sync;
@@ -3118,6 +3312,11 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3118 3312
3119 DEBUGFUNC("e1000_swfw_sync_release"); 3313 DEBUGFUNC("e1000_swfw_sync_release");
3120 3314
3315 if (hw->swfwhw_semaphore_present) {
3316 e1000_release_software_flag(hw);
3317 return;
3318 }
3319
3121 if (!hw->swfw_sync_present) { 3320 if (!hw->swfw_sync_present) {
3122 e1000_put_hw_eeprom_semaphore(hw); 3321 e1000_put_hw_eeprom_semaphore(hw);
3123 return; 3322 return;
@@ -3160,7 +3359,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3160 if (e1000_swfw_sync_acquire(hw, swfw)) 3359 if (e1000_swfw_sync_acquire(hw, swfw))
3161 return -E1000_ERR_SWFW_SYNC; 3360 return -E1000_ERR_SWFW_SYNC;
3162 3361
3163 if((hw->phy_type == e1000_phy_igp || 3362 if ((hw->phy_type == e1000_phy_igp ||
3363 hw->phy_type == e1000_phy_igp_3 ||
3164 hw->phy_type == e1000_phy_igp_2) && 3364 hw->phy_type == e1000_phy_igp_2) &&
3165 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3365 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3166 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3366 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3299,7 +3499,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3299 if (e1000_swfw_sync_acquire(hw, swfw)) 3499 if (e1000_swfw_sync_acquire(hw, swfw))
3300 return -E1000_ERR_SWFW_SYNC; 3500 return -E1000_ERR_SWFW_SYNC;
3301 3501
3302 if((hw->phy_type == e1000_phy_igp || 3502 if ((hw->phy_type == e1000_phy_igp ||
3503 hw->phy_type == e1000_phy_igp_3 ||
3303 hw->phy_type == e1000_phy_igp_2) && 3504 hw->phy_type == e1000_phy_igp_2) &&
3304 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3505 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3305 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3506 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3401,7 +3602,7 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
3401 return E1000_SUCCESS; 3602 return E1000_SUCCESS;
3402} 3603}
3403 3604
3404int32_t 3605static int32_t
3405e1000_read_kmrn_reg(struct e1000_hw *hw, 3606e1000_read_kmrn_reg(struct e1000_hw *hw,
3406 uint32_t reg_addr, 3607 uint32_t reg_addr,
3407 uint16_t *data) 3608 uint16_t *data)
@@ -3434,7 +3635,7 @@ e1000_read_kmrn_reg(struct e1000_hw *hw,
3434 return E1000_SUCCESS; 3635 return E1000_SUCCESS;
3435} 3636}
3436 3637
3437int32_t 3638static int32_t
3438e1000_write_kmrn_reg(struct e1000_hw *hw, 3639e1000_write_kmrn_reg(struct e1000_hw *hw,
3439 uint32_t reg_addr, 3640 uint32_t reg_addr,
3440 uint16_t data) 3641 uint16_t data)
@@ -3514,7 +3715,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3514 E1000_WRITE_FLUSH(hw); 3715 E1000_WRITE_FLUSH(hw);
3515 3716
3516 if (hw->mac_type >= e1000_82571) 3717 if (hw->mac_type >= e1000_82571)
3517 msec_delay(10); 3718 msec_delay_irq(10);
3518 e1000_swfw_sync_release(hw, swfw); 3719 e1000_swfw_sync_release(hw, swfw);
3519 } else { 3720 } else {
3520 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3721 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3544,6 +3745,12 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3544 ret_val = e1000_get_phy_cfg_done(hw); 3745 ret_val = e1000_get_phy_cfg_done(hw);
3545 e1000_release_software_semaphore(hw); 3746 e1000_release_software_semaphore(hw);
3546 3747
3748 if ((hw->mac_type == e1000_ich8lan) &&
3749 (hw->phy_type == e1000_phy_igp_3)) {
3750 ret_val = e1000_init_lcd_from_nvm(hw);
3751 if (ret_val)
3752 return ret_val;
3753 }
3547 return ret_val; 3754 return ret_val;
3548} 3755}
3549 3756
@@ -3572,9 +3779,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3572 case e1000_82541_rev_2: 3779 case e1000_82541_rev_2:
3573 case e1000_82571: 3780 case e1000_82571:
3574 case e1000_82572: 3781 case e1000_82572:
3782 case e1000_ich8lan:
3575 ret_val = e1000_phy_hw_reset(hw); 3783 ret_val = e1000_phy_hw_reset(hw);
3576 if(ret_val) 3784 if(ret_val)
3577 return ret_val; 3785 return ret_val;
3786
3578 break; 3787 break;
3579 default: 3788 default:
3580 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3789 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3597,11 +3806,120 @@ e1000_phy_reset(struct e1000_hw *hw)
3597} 3806}
3598 3807
3599/****************************************************************************** 3808/******************************************************************************
3809* Work-around for 82566 power-down: on D3 entry-
3810* 1) disable gigabit link
3811* 2) write VR power-down enable
3812* 3) read it back
3813* if successful continue, else issue LCD reset and repeat
3814*
3815* hw - struct containing variables accessed by shared code
3816******************************************************************************/
3817void
3818e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3819{
3820 int32_t reg;
3821 uint16_t phy_data;
3822 int32_t retry = 0;
3823
3824 DEBUGFUNC("e1000_phy_powerdown_workaround");
3825
3826 if (hw->phy_type != e1000_phy_igp_3)
3827 return;
3828
3829 do {
3830 /* Disable link */
3831 reg = E1000_READ_REG(hw, PHY_CTRL);
3832 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3833 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3834
3835 /* Write VR power-down enable */
3836 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3837 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3838 IGP3_VR_CTRL_MODE_SHUT);
3839
3840 /* Read it back and test */
3841 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3842 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3843 break;
3844
3845 /* Issue PHY reset and repeat at most one more time */
3846 reg = E1000_READ_REG(hw, CTRL);
3847 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3848 retry++;
3849 } while (retry);
3850
3851 return;
3852
3853}
3854
3855/******************************************************************************
3856* Work-around for 82566 Kumeran PCS lock loss:
3857* On link status change (i.e. PCI reset, speed change) and link is up and
3858* speed is gigabit-
3859* 0) if workaround is optionally disabled do nothing
3860* 1) wait 1ms for Kumeran link to come up
3861* 2) check Kumeran Diagnostic register PCS lock loss bit
3862* 3) if not set the link is locked (all is good), otherwise...
3863* 4) reset the PHY
3864* 5) repeat up to 10 times
3865* Note: this is only called for IGP3 copper when speed is 1gb.
3866*
3867* hw - struct containing variables accessed by shared code
3868******************************************************************************/
3869static int32_t
3870e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3871{
3872 int32_t ret_val;
3873 int32_t reg;
3874 int32_t cnt;
3875 uint16_t phy_data;
3876
3877 if (hw->kmrn_lock_loss_workaround_disabled)
3878 return E1000_SUCCESS;
3879
3880 /* Make sure link is up before proceeding. If not just return.
3881 * Attempting this while link is negotiating fouls up link
3882 * stability */
3883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3884 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3885
3886 if (phy_data & MII_SR_LINK_STATUS) {
3887 for (cnt = 0; cnt < 10; cnt++) {
3888 /* read once to clear */
3889 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3890 if (ret_val)
3891 return ret_val;
3892 /* and again to get new status */
3893 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3894 if (ret_val)
3895 return ret_val;
3896
3897 /* check for PCS lock */
3898 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3899 return E1000_SUCCESS;
3900
3901 /* Issue PHY reset */
3902 e1000_phy_hw_reset(hw);
3903 msec_delay_irq(5);
3904 }
3905 /* Disable GigE link negotiation */
3906 reg = E1000_READ_REG(hw, PHY_CTRL);
3907 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3908 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3909
3910 /* unable to acquire PCS lock */
3911 return E1000_ERR_PHY;
3912 }
3913
3914 return E1000_SUCCESS;
3915}
3916
3917/******************************************************************************
3600* Probes the expected PHY address for known PHY IDs 3918* Probes the expected PHY address for known PHY IDs
3601* 3919*
3602* hw - Struct containing variables accessed by shared code 3920* hw - Struct containing variables accessed by shared code
3603******************************************************************************/ 3921******************************************************************************/
3604static int32_t 3922int32_t
3605e1000_detect_gig_phy(struct e1000_hw *hw) 3923e1000_detect_gig_phy(struct e1000_hw *hw)
3606{ 3924{
3607 int32_t phy_init_status, ret_val; 3925 int32_t phy_init_status, ret_val;
@@ -3613,8 +3931,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3613 /* The 82571 firmware may still be configuring the PHY. In this 3931 /* The 82571 firmware may still be configuring the PHY. In this
3614 * case, we cannot access the PHY until the configuration is done. So 3932 * case, we cannot access the PHY until the configuration is done. So
3615 * we explicitly set the PHY values. */ 3933 * we explicitly set the PHY values. */
3616 if(hw->mac_type == e1000_82571 || 3934 if (hw->mac_type == e1000_82571 ||
3617 hw->mac_type == e1000_82572) { 3935 hw->mac_type == e1000_82572) {
3618 hw->phy_id = IGP01E1000_I_PHY_ID; 3936 hw->phy_id = IGP01E1000_I_PHY_ID;
3619 hw->phy_type = e1000_phy_igp_2; 3937 hw->phy_type = e1000_phy_igp_2;
3620 return E1000_SUCCESS; 3938 return E1000_SUCCESS;
@@ -3631,7 +3949,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3631 3949
3632 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3950 /* Read the PHY ID Registers to identify which PHY is onboard. */
3633 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3951 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3634 if(ret_val) 3952 if (ret_val)
3635 return ret_val; 3953 return ret_val;
3636 3954
3637 hw->phy_id = (uint32_t) (phy_id_high << 16); 3955 hw->phy_id = (uint32_t) (phy_id_high << 16);
@@ -3669,6 +3987,12 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3669 case e1000_80003es2lan: 3987 case e1000_80003es2lan:
3670 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 3988 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3671 break; 3989 break;
3990 case e1000_ich8lan:
3991 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3992 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3993 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3994 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3995 break;
3672 default: 3996 default:
3673 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3997 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3674 return -E1000_ERR_CONFIG; 3998 return -E1000_ERR_CONFIG;
@@ -3784,6 +4108,53 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
3784} 4108}
3785 4109
3786/****************************************************************************** 4110/******************************************************************************
4111* Get PHY information from various PHY registers for ife PHY only.
4112*
4113* hw - Struct containing variables accessed by shared code
4114* phy_info - PHY information structure
4115******************************************************************************/
4116static int32_t
4117e1000_phy_ife_get_info(struct e1000_hw *hw,
4118 struct e1000_phy_info *phy_info)
4119{
4120 int32_t ret_val;
4121 uint16_t phy_data, polarity;
4122
4123 DEBUGFUNC("e1000_phy_ife_get_info");
4124
4125 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4126 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4127
4128 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4129 if (ret_val)
4130 return ret_val;
4131 phy_info->polarity_correction =
4132 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4133 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4134
4135 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4136 ret_val = e1000_check_polarity(hw, &polarity);
4137 if (ret_val)
4138 return ret_val;
4139 } else {
4140 /* Polarity is forced. */
4141 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4142 IFE_PSC_FORCE_POLARITY_SHIFT;
4143 }
4144 phy_info->cable_polarity = polarity;
4145
4146 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4147 if (ret_val)
4148 return ret_val;
4149
4150 phy_info->mdix_mode =
4151 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4152 IFE_PMC_MDIX_MODE_SHIFT;
4153
4154 return E1000_SUCCESS;
4155}
4156
4157/******************************************************************************
3787* Get PHY information from various PHY registers fot m88 PHY only. 4158* Get PHY information from various PHY registers fot m88 PHY only.
3788* 4159*
3789* hw - Struct containing variables accessed by shared code 4160* hw - Struct containing variables accessed by shared code
@@ -3898,9 +4269,12 @@ e1000_phy_get_info(struct e1000_hw *hw,
3898 return -E1000_ERR_CONFIG; 4269 return -E1000_ERR_CONFIG;
3899 } 4270 }
3900 4271
3901 if(hw->phy_type == e1000_phy_igp || 4272 if (hw->phy_type == e1000_phy_igp ||
4273 hw->phy_type == e1000_phy_igp_3 ||
3902 hw->phy_type == e1000_phy_igp_2) 4274 hw->phy_type == e1000_phy_igp_2)
3903 return e1000_phy_igp_get_info(hw, phy_info); 4275 return e1000_phy_igp_get_info(hw, phy_info);
4276 else if (hw->phy_type == e1000_phy_ife)
4277 return e1000_phy_ife_get_info(hw, phy_info);
3904 else 4278 else
3905 return e1000_phy_m88_get_info(hw, phy_info); 4279 return e1000_phy_m88_get_info(hw, phy_info);
3906} 4280}
@@ -4049,6 +4423,35 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4049 eeprom->use_eerd = TRUE; 4423 eeprom->use_eerd = TRUE;
4050 eeprom->use_eewr = FALSE; 4424 eeprom->use_eewr = FALSE;
4051 break; 4425 break;
4426 case e1000_ich8lan:
4427 {
4428 int32_t i = 0;
4429 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4430
4431 eeprom->type = e1000_eeprom_ich8;
4432 eeprom->use_eerd = FALSE;
4433 eeprom->use_eewr = FALSE;
4434 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4435
4436 /* Zero the shadow RAM structure. But don't load it from NVM
4437 * so as to save time for driver init */
4438 if (hw->eeprom_shadow_ram != NULL) {
4439 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4440 hw->eeprom_shadow_ram[i].modified = FALSE;
4441 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4442 }
4443 }
4444
4445 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4446 ICH8_FLASH_SECTOR_SIZE;
4447
4448 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4449 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4450 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4451 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4452
4453 break;
4454 }
4052 default: 4455 default:
4053 break; 4456 break;
4054 } 4457 }
@@ -4469,7 +4872,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
4469 return ret_val; 4872 return ret_val;
4470 } 4873 }
4471 4874
4472 if(eeprom->type == e1000_eeprom_spi) { 4875 if (eeprom->type == e1000_eeprom_ich8)
4876 return e1000_read_eeprom_ich8(hw, offset, words, data);
4877
4878 if (eeprom->type == e1000_eeprom_spi) {
4473 uint16_t word_in; 4879 uint16_t word_in;
4474 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4880 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4475 4881
@@ -4636,7 +5042,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4636 5042
4637 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5043 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4638 5044
4639 if(hw->mac_type == e1000_82573) { 5045 if (hw->mac_type == e1000_ich8lan)
5046 return FALSE;
5047
5048 if (hw->mac_type == e1000_82573) {
4640 eecd = E1000_READ_REG(hw, EECD); 5049 eecd = E1000_READ_REG(hw, EECD);
4641 5050
4642 /* Isolate bits 15 & 16 */ 5051 /* Isolate bits 15 & 16 */
@@ -4686,8 +5095,22 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4686 } 5095 }
4687 } 5096 }
4688 5097
4689 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5098 if (hw->mac_type == e1000_ich8lan) {
4690 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5099 /* Drivers must allocate the shadow ram structure for the
5100 * EEPROM checksum to be updated. Otherwise, this bit as well
5101 * as the checksum must both be set correctly for this
5102 * validation to pass.
5103 */
5104 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5105 if ((eeprom_data & 0x40) == 0) {
5106 eeprom_data |= 0x40;
5107 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5108 e1000_update_eeprom_checksum(hw);
5109 }
5110 }
5111
5112 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5113 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4691 DEBUGOUT("EEPROM Read Error\n"); 5114 DEBUGOUT("EEPROM Read Error\n");
4692 return -E1000_ERR_EEPROM; 5115 return -E1000_ERR_EEPROM;
4693 } 5116 }
@@ -4713,6 +5136,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4713int32_t 5136int32_t
4714e1000_update_eeprom_checksum(struct e1000_hw *hw) 5137e1000_update_eeprom_checksum(struct e1000_hw *hw)
4715{ 5138{
5139 uint32_t ctrl_ext;
4716 uint16_t checksum = 0; 5140 uint16_t checksum = 0;
4717 uint16_t i, eeprom_data; 5141 uint16_t i, eeprom_data;
4718 5142
@@ -4731,6 +5155,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
4731 return -E1000_ERR_EEPROM; 5155 return -E1000_ERR_EEPROM;
4732 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5156 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4733 e1000_commit_shadow_ram(hw); 5157 e1000_commit_shadow_ram(hw);
5158 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5159 e1000_commit_shadow_ram(hw);
5160 /* Reload the EEPROM, or else modifications will not appear
5161 * until after next adapter reset. */
5162 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5163 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5164 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5165 msec_delay(10);
4734 } 5166 }
4735 return E1000_SUCCESS; 5167 return E1000_SUCCESS;
4736} 5168}
@@ -4770,6 +5202,9 @@ e1000_write_eeprom(struct e1000_hw *hw,
4770 if(eeprom->use_eewr == TRUE) 5202 if(eeprom->use_eewr == TRUE)
4771 return e1000_write_eeprom_eewr(hw, offset, words, data); 5203 return e1000_write_eeprom_eewr(hw, offset, words, data);
4772 5204
5205 if (eeprom->type == e1000_eeprom_ich8)
5206 return e1000_write_eeprom_ich8(hw, offset, words, data);
5207
4773 /* Prepare the EEPROM for writing */ 5208 /* Prepare the EEPROM for writing */
4774 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5209 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4775 return -E1000_ERR_EEPROM; 5210 return -E1000_ERR_EEPROM;
@@ -4957,11 +5392,17 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4957 uint32_t flop = 0; 5392 uint32_t flop = 0;
4958 uint32_t i = 0; 5393 uint32_t i = 0;
4959 int32_t error = E1000_SUCCESS; 5394 int32_t error = E1000_SUCCESS;
4960 5395 uint32_t old_bank_offset = 0;
4961 /* The flop register will be used to determine if flash type is STM */ 5396 uint32_t new_bank_offset = 0;
4962 flop = E1000_READ_REG(hw, FLOP); 5397 uint32_t sector_retries = 0;
5398 uint8_t low_byte = 0;
5399 uint8_t high_byte = 0;
5400 uint8_t temp_byte = 0;
5401 boolean_t sector_write_failed = FALSE;
4963 5402
4964 if (hw->mac_type == e1000_82573) { 5403 if (hw->mac_type == e1000_82573) {
5404 /* The flop register will be used to determine if flash type is STM */
5405 flop = E1000_READ_REG(hw, FLOP);
4965 for (i=0; i < attempts; i++) { 5406 for (i=0; i < attempts; i++) {
4966 eecd = E1000_READ_REG(hw, EECD); 5407 eecd = E1000_READ_REG(hw, EECD);
4967 if ((eecd & E1000_EECD_FLUPD) == 0) { 5408 if ((eecd & E1000_EECD_FLUPD) == 0) {
@@ -4995,6 +5436,106 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
4995 } 5436 }
4996 } 5437 }
4997 5438
5439 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5440 /* We're writing to the opposite bank so if we're on bank 1,
5441 * write to bank 0 etc. We also need to erase the segment that
5442 * is going to be written */
5443 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5444 new_bank_offset = hw->flash_bank_size * 2;
5445 old_bank_offset = 0;
5446 e1000_erase_ich8_4k_segment(hw, 1);
5447 } else {
5448 old_bank_offset = hw->flash_bank_size * 2;
5449 new_bank_offset = 0;
5450 e1000_erase_ich8_4k_segment(hw, 0);
5451 }
5452
5453 do {
5454 sector_write_failed = FALSE;
5455 /* Loop for every byte in the shadow RAM,
5456 * which is in units of words. */
5457 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5458 /* Determine whether to write the value stored
5459 * in the other NVM bank or a modified value stored
5460 * in the shadow RAM */
5461 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5462 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5463 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5464 &temp_byte);
5465 udelay(100);
5466 error = e1000_verify_write_ich8_byte(hw,
5467 (i << 1) + new_bank_offset,
5468 low_byte);
5469 if (error != E1000_SUCCESS)
5470 sector_write_failed = TRUE;
5471 high_byte =
5472 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5473 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5474 &temp_byte);
5475 udelay(100);
5476 } else {
5477 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5478 &low_byte);
5479 udelay(100);
5480 error = e1000_verify_write_ich8_byte(hw,
5481 (i << 1) + new_bank_offset, low_byte);
5482 if (error != E1000_SUCCESS)
5483 sector_write_failed = TRUE;
5484 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5485 &high_byte);
5486 }
5487
5488 /* If the word is 0x13, then make sure the signature bits
5489 * (15:14) are 11b until the commit has completed.
5490 * This will allow us to write 10b which indicates the
5491 * signature is valid. We want to do this after the write
5492 * has completed so that we don't mark the segment valid
5493 * while the write is still in progress */
5494 if (i == E1000_ICH8_NVM_SIG_WORD)
5495 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5496
5497 error = e1000_verify_write_ich8_byte(hw,
5498 (i << 1) + new_bank_offset + 1, high_byte);
5499 if (error != E1000_SUCCESS)
5500 sector_write_failed = TRUE;
5501
5502 if (sector_write_failed == FALSE) {
5503 /* Clear the now not used entry in the cache */
5504 hw->eeprom_shadow_ram[i].modified = FALSE;
5505 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5506 }
5507 }
5508
5509 /* Don't bother writing the segment valid bits if sector
5510 * programming failed. */
5511 if (sector_write_failed == FALSE) {
5512 /* Finally validate the new segment by setting bit 15:14
5513 * to 10b in word 0x13 , this can be done without an
5514 * erase as well since these bits are 11 to start with
5515 * and we need to change bit 14 to 0b */
5516 e1000_read_ich8_byte(hw,
5517 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5518 &high_byte);
5519 high_byte &= 0xBF;
5520 error = e1000_verify_write_ich8_byte(hw,
5521 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5522 high_byte);
5523 if (error != E1000_SUCCESS)
5524 sector_write_failed = TRUE;
5525
5526 /* And invalidate the previously valid segment by setting
5527 * its signature word (0x13) high_byte to 0b. This can be
5528 * done without an erase because flash erase sets all bits
5529 * to 1's. We can write 1's to 0's without an erase */
5530 error = e1000_verify_write_ich8_byte(hw,
5531 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5532 0);
5533 if (error != E1000_SUCCESS)
5534 sector_write_failed = TRUE;
5535 }
5536 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5537 }
5538
4998 return error; 5539 return error;
4999} 5540}
5000 5541
@@ -5102,15 +5643,19 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5102 * the other port. */ 5643 * the other port. */
5103 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5644 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5104 rar_num -= 1; 5645 rar_num -= 1;
5646 if (hw->mac_type == e1000_ich8lan)
5647 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5648
5105 /* Zero out the other 15 receive addresses. */ 5649 /* Zero out the other 15 receive addresses. */
5106 DEBUGOUT("Clearing RAR[1-15]\n"); 5650 DEBUGOUT("Clearing RAR[1-15]\n");
5107 for(i = 1; i < rar_num; i++) { 5651 for(i = 1; i < rar_num; i++) {
5108 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5652 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5653 E1000_WRITE_FLUSH(hw);
5109 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5654 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5655 E1000_WRITE_FLUSH(hw);
5110 } 5656 }
5111} 5657}
5112 5658
5113#if 0
5114/****************************************************************************** 5659/******************************************************************************
5115 * Updates the MAC's list of multicast addresses. 5660 * Updates the MAC's list of multicast addresses.
5116 * 5661 *
@@ -5125,6 +5670,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5125 * for the first 15 multicast addresses, and hashes the rest into the 5670 * for the first 15 multicast addresses, and hashes the rest into the
5126 * multicast table. 5671 * multicast table.
5127 *****************************************************************************/ 5672 *****************************************************************************/
5673#if 0
5128void 5674void
5129e1000_mc_addr_list_update(struct e1000_hw *hw, 5675e1000_mc_addr_list_update(struct e1000_hw *hw,
5130 uint8_t *mc_addr_list, 5676 uint8_t *mc_addr_list,
@@ -5145,6 +5691,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5145 /* Clear RAR[1-15] */ 5691 /* Clear RAR[1-15] */
5146 DEBUGOUT(" Clearing RAR[1-15]\n"); 5692 DEBUGOUT(" Clearing RAR[1-15]\n");
5147 num_rar_entry = E1000_RAR_ENTRIES; 5693 num_rar_entry = E1000_RAR_ENTRIES;
5694 if (hw->mac_type == e1000_ich8lan)
5695 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5148 /* Reserve a spot for the Locally Administered Address to work around 5696 /* Reserve a spot for the Locally Administered Address to work around
5149 * an 82571 issue in which a reset on one port will reload the MAC on 5697 * an 82571 issue in which a reset on one port will reload the MAC on
5150 * the other port. */ 5698 * the other port. */
@@ -5153,14 +5701,19 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5153 5701
5154 for(i = rar_used_count; i < num_rar_entry; i++) { 5702 for(i = rar_used_count; i < num_rar_entry; i++) {
5155 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5703 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5704 E1000_WRITE_FLUSH(hw);
5156 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5705 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5706 E1000_WRITE_FLUSH(hw);
5157 } 5707 }
5158 5708
5159 /* Clear the MTA */ 5709 /* Clear the MTA */
5160 DEBUGOUT(" Clearing MTA\n"); 5710 DEBUGOUT(" Clearing MTA\n");
5161 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5711 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5712 if (hw->mac_type == e1000_ich8lan)
5713 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5162 for(i = 0; i < num_mta_entry; i++) { 5714 for(i = 0; i < num_mta_entry; i++) {
5163 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5715 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5716 E1000_WRITE_FLUSH(hw);
5164 } 5717 }
5165 5718
5166 /* Add the new addresses */ 5719 /* Add the new addresses */
@@ -5217,24 +5770,46 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5217 * LSB MSB 5770 * LSB MSB
5218 */ 5771 */
5219 case 0: 5772 case 0:
5220 /* [47:36] i.e. 0x563 for above example address */ 5773 if (hw->mac_type == e1000_ich8lan) {
5221 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5774 /* [47:38] i.e. 0x158 for above example address */
5775 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5776 } else {
5777 /* [47:36] i.e. 0x563 for above example address */
5778 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5779 }
5222 break; 5780 break;
5223 case 1: 5781 case 1:
5224 /* [46:35] i.e. 0xAC6 for above example address */ 5782 if (hw->mac_type == e1000_ich8lan) {
5225 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5783 /* [46:37] i.e. 0x2B1 for above example address */
5784 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5785 } else {
5786 /* [46:35] i.e. 0xAC6 for above example address */
5787 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5788 }
5226 break; 5789 break;
5227 case 2: 5790 case 2:
5228 /* [45:34] i.e. 0x5D8 for above example address */ 5791 if (hw->mac_type == e1000_ich8lan) {
5229 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5792 /*[45:36] i.e. 0x163 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5794 } else {
5795 /* [45:34] i.e. 0x5D8 for above example address */
5796 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5797 }
5230 break; 5798 break;
5231 case 3: 5799 case 3:
5232 /* [43:32] i.e. 0x634 for above example address */ 5800 if (hw->mac_type == e1000_ich8lan) {
5233 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5801 /* [43:34] i.e. 0x18D for above example address */
5802 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5803 } else {
5804 /* [43:32] i.e. 0x634 for above example address */
5805 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5806 }
5234 break; 5807 break;
5235 } 5808 }
5236 5809
5237 hash_value &= 0xFFF; 5810 hash_value &= 0xFFF;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_value &= 0x3FF;
5238 5813
5239 return hash_value; 5814 return hash_value;
5240} 5815}
@@ -5262,6 +5837,8 @@ e1000_mta_set(struct e1000_hw *hw,
5262 * register are determined by the lower 5 bits of the value. 5837 * register are determined by the lower 5 bits of the value.
5263 */ 5838 */
5264 hash_reg = (hash_value >> 5) & 0x7F; 5839 hash_reg = (hash_value >> 5) & 0x7F;
5840 if (hw->mac_type == e1000_ich8lan)
5841 hash_reg &= 0x1F;
5265 hash_bit = hash_value & 0x1F; 5842 hash_bit = hash_value & 0x1F;
5266 5843
5267 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5844 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -5275,9 +5852,12 @@ e1000_mta_set(struct e1000_hw *hw,
5275 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5852 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5276 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5277 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5855 E1000_WRITE_FLUSH(hw);
5278 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5856 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5857 E1000_WRITE_FLUSH(hw);
5279 } else { 5858 } else {
5280 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5859 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5860 E1000_WRITE_FLUSH(hw);
5281 } 5861 }
5282} 5862}
5283 5863
@@ -5334,7 +5914,9 @@ e1000_rar_set(struct e1000_hw *hw,
5334 } 5914 }
5335 5915
5336 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5916 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5917 E1000_WRITE_FLUSH(hw);
5337 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5918 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5919 E1000_WRITE_FLUSH(hw);
5338} 5920}
5339 5921
5340/****************************************************************************** 5922/******************************************************************************
@@ -5351,12 +5933,18 @@ e1000_write_vfta(struct e1000_hw *hw,
5351{ 5933{
5352 uint32_t temp; 5934 uint32_t temp;
5353 5935
5354 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5936 if (hw->mac_type == e1000_ich8lan)
5937 return;
5938
5939 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5355 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5940 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5356 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5941 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5942 E1000_WRITE_FLUSH(hw);
5357 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5943 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5944 E1000_WRITE_FLUSH(hw);
5358 } else { 5945 } else {
5359 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5946 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5947 E1000_WRITE_FLUSH(hw);
5360 } 5948 }
5361} 5949}
5362 5950
@@ -5373,6 +5961,9 @@ e1000_clear_vfta(struct e1000_hw *hw)
5373 uint32_t vfta_offset = 0; 5961 uint32_t vfta_offset = 0;
5374 uint32_t vfta_bit_in_reg = 0; 5962 uint32_t vfta_bit_in_reg = 0;
5375 5963
5964 if (hw->mac_type == e1000_ich8lan)
5965 return;
5966
5376 if (hw->mac_type == e1000_82573) { 5967 if (hw->mac_type == e1000_82573) {
5377 if (hw->mng_cookie.vlan_id != 0) { 5968 if (hw->mng_cookie.vlan_id != 0) {
5378 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5969 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
@@ -5392,6 +5983,7 @@ e1000_clear_vfta(struct e1000_hw *hw)
5392 * manageability unit */ 5983 * manageability unit */
5393 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5984 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5394 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5985 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5986 E1000_WRITE_FLUSH(hw);
5395 } 5987 }
5396} 5988}
5397 5989
@@ -5421,9 +6013,18 @@ e1000_id_led_init(struct e1000_hw * hw)
5421 DEBUGOUT("EEPROM Read Error\n"); 6013 DEBUGOUT("EEPROM Read Error\n");
5422 return -E1000_ERR_EEPROM; 6014 return -E1000_ERR_EEPROM;
5423 } 6015 }
5424 if((eeprom_data== ID_LED_RESERVED_0000) || 6016
5425 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 6017 if ((hw->mac_type == e1000_82573) &&
5426 for(i = 0; i < 4; i++) { 6018 (eeprom_data == ID_LED_RESERVED_82573))
6019 eeprom_data = ID_LED_DEFAULT_82573;
6020 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6021 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6022 if (hw->mac_type == e1000_ich8lan)
6023 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6024 else
6025 eeprom_data = ID_LED_DEFAULT;
6026 }
6027 for (i = 0; i < 4; i++) {
5427 temp = (eeprom_data >> (i << 2)) & led_mask; 6028 temp = (eeprom_data >> (i << 2)) & led_mask;
5428 switch(temp) { 6029 switch(temp) {
5429 case ID_LED_ON1_DEF2: 6030 case ID_LED_ON1_DEF2:
@@ -5519,6 +6120,44 @@ e1000_setup_led(struct e1000_hw *hw)
5519} 6120}
5520 6121
5521/****************************************************************************** 6122/******************************************************************************
6123 * Used on 82571 and later Si that has LED blink bits.
6124 * Callers must use their own timer and should have already called
6125 * e1000_id_led_init()
6126 * Call e1000_cleanup led() to stop blinking
6127 *
6128 * hw - Struct containing variables accessed by shared code
6129 *****************************************************************************/
6130int32_t
6131e1000_blink_led_start(struct e1000_hw *hw)
6132{
6133 int16_t i;
6134 uint32_t ledctl_blink = 0;
6135
6136 DEBUGFUNC("e1000_id_led_blink_on");
6137
6138 if (hw->mac_type < e1000_82571) {
6139 /* Nothing to do */
6140 return E1000_SUCCESS;
6141 }
6142 if (hw->media_type == e1000_media_type_fiber) {
6143 /* always blink LED0 for PCI-E fiber */
6144 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6145 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6146 } else {
6147 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6148 ledctl_blink = hw->ledctl_mode2;
6149 for (i=0; i < 4; i++)
6150 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6151 E1000_LEDCTL_MODE_LED_ON)
6152 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6153 }
6154
6155 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6156
6157 return E1000_SUCCESS;
6158}
6159
6160/******************************************************************************
5522 * Restores the saved state of the SW controlable LED. 6161 * Restores the saved state of the SW controlable LED.
5523 * 6162 *
5524 * hw - Struct containing variables accessed by shared code 6163 * hw - Struct containing variables accessed by shared code
@@ -5548,6 +6187,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
5548 return ret_val; 6187 return ret_val;
5549 /* Fall Through */ 6188 /* Fall Through */
5550 default: 6189 default:
6190 if (hw->phy_type == e1000_phy_ife) {
6191 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6192 break;
6193 }
5551 /* Restore LEDCTL settings */ 6194 /* Restore LEDCTL settings */
5552 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6195 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5553 break; 6196 break;
@@ -5592,7 +6235,10 @@ e1000_led_on(struct e1000_hw *hw)
5592 /* Clear SW Defineable Pin 0 to turn on the LED */ 6235 /* Clear SW Defineable Pin 0 to turn on the LED */
5593 ctrl &= ~E1000_CTRL_SWDPIN0; 6236 ctrl &= ~E1000_CTRL_SWDPIN0;
5594 ctrl |= E1000_CTRL_SWDPIO0; 6237 ctrl |= E1000_CTRL_SWDPIO0;
5595 } else if(hw->media_type == e1000_media_type_copper) { 6238 } else if (hw->phy_type == e1000_phy_ife) {
6239 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6240 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6241 } else if (hw->media_type == e1000_media_type_copper) {
5596 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6242 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5597 return E1000_SUCCESS; 6243 return E1000_SUCCESS;
5598 } 6244 }
@@ -5640,7 +6286,10 @@ e1000_led_off(struct e1000_hw *hw)
5640 /* Set SW Defineable Pin 0 to turn off the LED */ 6286 /* Set SW Defineable Pin 0 to turn off the LED */
5641 ctrl |= E1000_CTRL_SWDPIN0; 6287 ctrl |= E1000_CTRL_SWDPIN0;
5642 ctrl |= E1000_CTRL_SWDPIO0; 6288 ctrl |= E1000_CTRL_SWDPIO0;
5643 } else if(hw->media_type == e1000_media_type_copper) { 6289 } else if (hw->phy_type == e1000_phy_ife) {
6290 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6291 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6292 } else if (hw->media_type == e1000_media_type_copper) {
5644 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6293 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5645 return E1000_SUCCESS; 6294 return E1000_SUCCESS;
5646 } 6295 }
@@ -5678,12 +6327,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5678 temp = E1000_READ_REG(hw, XOFFRXC); 6327 temp = E1000_READ_REG(hw, XOFFRXC);
5679 temp = E1000_READ_REG(hw, XOFFTXC); 6328 temp = E1000_READ_REG(hw, XOFFTXC);
5680 temp = E1000_READ_REG(hw, FCRUC); 6329 temp = E1000_READ_REG(hw, FCRUC);
6330
6331 if (hw->mac_type != e1000_ich8lan) {
5681 temp = E1000_READ_REG(hw, PRC64); 6332 temp = E1000_READ_REG(hw, PRC64);
5682 temp = E1000_READ_REG(hw, PRC127); 6333 temp = E1000_READ_REG(hw, PRC127);
5683 temp = E1000_READ_REG(hw, PRC255); 6334 temp = E1000_READ_REG(hw, PRC255);
5684 temp = E1000_READ_REG(hw, PRC511); 6335 temp = E1000_READ_REG(hw, PRC511);
5685 temp = E1000_READ_REG(hw, PRC1023); 6336 temp = E1000_READ_REG(hw, PRC1023);
5686 temp = E1000_READ_REG(hw, PRC1522); 6337 temp = E1000_READ_REG(hw, PRC1522);
6338 }
6339
5687 temp = E1000_READ_REG(hw, GPRC); 6340 temp = E1000_READ_REG(hw, GPRC);
5688 temp = E1000_READ_REG(hw, BPRC); 6341 temp = E1000_READ_REG(hw, BPRC);
5689 temp = E1000_READ_REG(hw, MPRC); 6342 temp = E1000_READ_REG(hw, MPRC);
@@ -5703,12 +6356,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5703 temp = E1000_READ_REG(hw, TOTH); 6356 temp = E1000_READ_REG(hw, TOTH);
5704 temp = E1000_READ_REG(hw, TPR); 6357 temp = E1000_READ_REG(hw, TPR);
5705 temp = E1000_READ_REG(hw, TPT); 6358 temp = E1000_READ_REG(hw, TPT);
6359
6360 if (hw->mac_type != e1000_ich8lan) {
5706 temp = E1000_READ_REG(hw, PTC64); 6361 temp = E1000_READ_REG(hw, PTC64);
5707 temp = E1000_READ_REG(hw, PTC127); 6362 temp = E1000_READ_REG(hw, PTC127);
5708 temp = E1000_READ_REG(hw, PTC255); 6363 temp = E1000_READ_REG(hw, PTC255);
5709 temp = E1000_READ_REG(hw, PTC511); 6364 temp = E1000_READ_REG(hw, PTC511);
5710 temp = E1000_READ_REG(hw, PTC1023); 6365 temp = E1000_READ_REG(hw, PTC1023);
5711 temp = E1000_READ_REG(hw, PTC1522); 6366 temp = E1000_READ_REG(hw, PTC1522);
6367 }
6368
5712 temp = E1000_READ_REG(hw, MPTC); 6369 temp = E1000_READ_REG(hw, MPTC);
5713 temp = E1000_READ_REG(hw, BPTC); 6370 temp = E1000_READ_REG(hw, BPTC);
5714 6371
@@ -5731,6 +6388,9 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5731 6388
5732 temp = E1000_READ_REG(hw, IAC); 6389 temp = E1000_READ_REG(hw, IAC);
5733 temp = E1000_READ_REG(hw, ICRXOC); 6390 temp = E1000_READ_REG(hw, ICRXOC);
6391
6392 if (hw->mac_type == e1000_ich8lan) return;
6393
5734 temp = E1000_READ_REG(hw, ICRXPTC); 6394 temp = E1000_READ_REG(hw, ICRXPTC);
5735 temp = E1000_READ_REG(hw, ICRXATC); 6395 temp = E1000_READ_REG(hw, ICRXATC);
5736 temp = E1000_READ_REG(hw, ICTXPTC); 6396 temp = E1000_READ_REG(hw, ICTXPTC);
@@ -5911,6 +6571,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5911 hw->bus_width = e1000_bus_width_pciex_1; 6571 hw->bus_width = e1000_bus_width_pciex_1;
5912 break; 6572 break;
5913 case e1000_82571: 6573 case e1000_82571:
6574 case e1000_ich8lan:
5914 case e1000_80003es2lan: 6575 case e1000_80003es2lan:
5915 hw->bus_type = e1000_bus_type_pci_express; 6576 hw->bus_type = e1000_bus_type_pci_express;
5916 hw->bus_speed = e1000_bus_speed_2500; 6577 hw->bus_speed = e1000_bus_speed_2500;
@@ -5948,8 +6609,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
5948 break; 6609 break;
5949 } 6610 }
5950} 6611}
5951
5952#if 0
5953/****************************************************************************** 6612/******************************************************************************
5954 * Reads a value from one of the devices registers using port I/O (as opposed 6613 * Reads a value from one of the devices registers using port I/O (as opposed
5955 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6614 * memory mapped I/O). Only 82544 and newer devices support port I/O.
@@ -5957,6 +6616,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
5957 * hw - Struct containing variables accessed by shared code 6616 * hw - Struct containing variables accessed by shared code
5958 * offset - offset to read from 6617 * offset - offset to read from
5959 *****************************************************************************/ 6618 *****************************************************************************/
6619#if 0
5960uint32_t 6620uint32_t
5961e1000_read_reg_io(struct e1000_hw *hw, 6621e1000_read_reg_io(struct e1000_hw *hw,
5962 uint32_t offset) 6622 uint32_t offset)
@@ -6012,8 +6672,6 @@ e1000_get_cable_length(struct e1000_hw *hw,
6012{ 6672{
6013 int32_t ret_val; 6673 int32_t ret_val;
6014 uint16_t agc_value = 0; 6674 uint16_t agc_value = 0;
6015 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6016 uint16_t max_agc = 0;
6017 uint16_t i, phy_data; 6675 uint16_t i, phy_data;
6018 uint16_t cable_length; 6676 uint16_t cable_length;
6019 6677
@@ -6086,6 +6744,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6086 break; 6744 break;
6087 } 6745 }
6088 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6746 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6747 uint16_t cur_agc_value;
6748 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6089 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6749 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6090 {IGP01E1000_PHY_AGC_A, 6750 {IGP01E1000_PHY_AGC_A,
6091 IGP01E1000_PHY_AGC_B, 6751 IGP01E1000_PHY_AGC_B,
@@ -6098,23 +6758,23 @@ e1000_get_cable_length(struct e1000_hw *hw,
6098 if(ret_val) 6758 if(ret_val)
6099 return ret_val; 6759 return ret_val;
6100 6760
6101 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6761 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6102 6762
6103 /* Array bound check. */ 6763 /* Value bound check. */
6104 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6764 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6105 (cur_agc == 0)) 6765 (cur_agc_value == 0))
6106 return -E1000_ERR_PHY; 6766 return -E1000_ERR_PHY;
6107 6767
6108 agc_value += cur_agc; 6768 agc_value += cur_agc_value;
6109 6769
6110 /* Update minimal AGC value. */ 6770 /* Update minimal AGC value. */
6111 if(min_agc > cur_agc) 6771 if (min_agc_value > cur_agc_value)
6112 min_agc = cur_agc; 6772 min_agc_value = cur_agc_value;
6113 } 6773 }
6114 6774
6115 /* Remove the minimal AGC result for length < 50m */ 6775 /* Remove the minimal AGC result for length < 50m */
6116 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6776 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6117 agc_value -= min_agc; 6777 agc_value -= min_agc_value;
6118 6778
6119 /* Get the average length of the remaining 3 channels */ 6779 /* Get the average length of the remaining 3 channels */
6120 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6780 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
@@ -6130,7 +6790,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6130 IGP01E1000_AGC_RANGE) : 0; 6790 IGP01E1000_AGC_RANGE) : 0;
6131 *max_length = e1000_igp_cable_length_table[agc_value] + 6791 *max_length = e1000_igp_cable_length_table[agc_value] +
6132 IGP01E1000_AGC_RANGE; 6792 IGP01E1000_AGC_RANGE;
6133 } else if (hw->phy_type == e1000_phy_igp_2) { 6793 } else if (hw->phy_type == e1000_phy_igp_2 ||
6794 hw->phy_type == e1000_phy_igp_3) {
6795 uint16_t cur_agc_index, max_agc_index = 0;
6796 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6134 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6797 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6135 {IGP02E1000_PHY_AGC_A, 6798 {IGP02E1000_PHY_AGC_A,
6136 IGP02E1000_PHY_AGC_B, 6799 IGP02E1000_PHY_AGC_B,
@@ -6145,19 +6808,27 @@ e1000_get_cable_length(struct e1000_hw *hw,
6145 /* Getting bits 15:9, which represent the combination of course and 6808 /* Getting bits 15:9, which represent the combination of course and
6146 * fine gain values. The result is a number that can be put into 6809 * fine gain values. The result is a number that can be put into
6147 * the lookup table to obtain the approximate cable length. */ 6810 * the lookup table to obtain the approximate cable length. */
6148 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6811 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6149 IGP02E1000_AGC_LENGTH_MASK; 6812 IGP02E1000_AGC_LENGTH_MASK;
6150 6813
6151 /* Remove min & max AGC values from calculation. */ 6814 /* Array index bound check. */
6152 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) 6815 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6153 min_agc = cur_agc; 6816 (cur_agc_index == 0))
6154 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) 6817 return -E1000_ERR_PHY;
6155 max_agc = cur_agc;
6156 6818
6157 agc_value += e1000_igp_2_cable_length_table[cur_agc]; 6819 /* Remove min & max AGC values from calculation. */
6820 if (e1000_igp_2_cable_length_table[min_agc_index] >
6821 e1000_igp_2_cable_length_table[cur_agc_index])
6822 min_agc_index = cur_agc_index;
6823 if (e1000_igp_2_cable_length_table[max_agc_index] <
6824 e1000_igp_2_cable_length_table[cur_agc_index])
6825 max_agc_index = cur_agc_index;
6826
6827 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6158 } 6828 }
6159 6829
6160 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); 6830 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6831 e1000_igp_2_cable_length_table[max_agc_index]);
6161 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6832 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6162 6833
6163 /* Calculate cable length with the error range of +/- 10 meters. */ 6834 /* Calculate cable length with the error range of +/- 10 meters. */
@@ -6203,7 +6874,8 @@ e1000_check_polarity(struct e1000_hw *hw,
6203 return ret_val; 6874 return ret_val;
6204 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6875 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6205 M88E1000_PSSR_REV_POLARITY_SHIFT; 6876 M88E1000_PSSR_REV_POLARITY_SHIFT;
6206 } else if(hw->phy_type == e1000_phy_igp || 6877 } else if (hw->phy_type == e1000_phy_igp ||
6878 hw->phy_type == e1000_phy_igp_3 ||
6207 hw->phy_type == e1000_phy_igp_2) { 6879 hw->phy_type == e1000_phy_igp_2) {
6208 /* Read the Status register to check the speed */ 6880 /* Read the Status register to check the speed */
6209 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
@@ -6229,6 +6901,13 @@ e1000_check_polarity(struct e1000_hw *hw,
6229 * 100 Mbps this bit is always 0) */ 6901 * 100 Mbps this bit is always 0) */
6230 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6902 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6231 } 6903 }
6904 } else if (hw->phy_type == e1000_phy_ife) {
6905 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6906 &phy_data);
6907 if (ret_val)
6908 return ret_val;
6909 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6910 IFE_PESC_POLARITY_REVERSED_SHIFT;
6232 } 6911 }
6233 return E1000_SUCCESS; 6912 return E1000_SUCCESS;
6234} 6913}
@@ -6256,7 +6935,8 @@ e1000_check_downshift(struct e1000_hw *hw)
6256 6935
6257 DEBUGFUNC("e1000_check_downshift"); 6936 DEBUGFUNC("e1000_check_downshift");
6258 6937
6259 if(hw->phy_type == e1000_phy_igp || 6938 if (hw->phy_type == e1000_phy_igp ||
6939 hw->phy_type == e1000_phy_igp_3 ||
6260 hw->phy_type == e1000_phy_igp_2) { 6940 hw->phy_type == e1000_phy_igp_2) {
6261 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6941 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6262 &phy_data); 6942 &phy_data);
@@ -6273,6 +6953,9 @@ e1000_check_downshift(struct e1000_hw *hw)
6273 6953
6274 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6954 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6275 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6955 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6956 } else if (hw->phy_type == e1000_phy_ife) {
6957 /* e1000_phy_ife supports 10/100 speed only */
6958 hw->speed_downgraded = FALSE;
6276 } 6959 }
6277 6960
6278 return E1000_SUCCESS; 6961 return E1000_SUCCESS;
@@ -6317,7 +7000,9 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6317 7000
6318 if(speed == SPEED_1000) { 7001 if(speed == SPEED_1000) {
6319 7002
6320 e1000_get_cable_length(hw, &min_length, &max_length); 7003 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7004 if (ret_val)
7005 return ret_val;
6321 7006
6322 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 7007 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6323 min_length >= e1000_igp_cable_length_50) { 7008 min_length >= e1000_igp_cable_length_50) {
@@ -6525,20 +7210,27 @@ static int32_t
6525e1000_set_d3_lplu_state(struct e1000_hw *hw, 7210e1000_set_d3_lplu_state(struct e1000_hw *hw,
6526 boolean_t active) 7211 boolean_t active)
6527{ 7212{
7213 uint32_t phy_ctrl = 0;
6528 int32_t ret_val; 7214 int32_t ret_val;
6529 uint16_t phy_data; 7215 uint16_t phy_data;
6530 DEBUGFUNC("e1000_set_d3_lplu_state"); 7216 DEBUGFUNC("e1000_set_d3_lplu_state");
6531 7217
6532 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) 7218 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7219 && hw->phy_type != e1000_phy_igp_3)
6533 return E1000_SUCCESS; 7220 return E1000_SUCCESS;
6534 7221
6535 /* During driver activity LPLU should not be used or it will attain link 7222 /* During driver activity LPLU should not be used or it will attain link
6536 * from the lowest speeds starting from 10Mbps. The capability is used for 7223 * from the lowest speeds starting from 10Mbps. The capability is used for
6537 * Dx transitions and states */ 7224 * Dx transitions and states */
6538 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7225 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6539 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7226 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6540 if(ret_val) 7227 if (ret_val)
6541 return ret_val; 7228 return ret_val;
7229 } else if (hw->mac_type == e1000_ich8lan) {
7230 /* MAC writes into PHY register based on the state transition
7231 * and start auto-negotiation. SW driver can overwrite the settings
7232 * in CSR PHY power control E1000_PHY_CTRL register. */
7233 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
6542 } else { 7234 } else {
6543 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7235 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6544 if(ret_val) 7236 if(ret_val)
@@ -6553,11 +7245,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6553 if(ret_val) 7245 if(ret_val)
6554 return ret_val; 7246 return ret_val;
6555 } else { 7247 } else {
7248 if (hw->mac_type == e1000_ich8lan) {
7249 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7250 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7251 } else {
6556 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7252 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6557 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7253 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6558 phy_data); 7254 phy_data);
6559 if (ret_val) 7255 if (ret_val)
6560 return ret_val; 7256 return ret_val;
7257 }
6561 } 7258 }
6562 7259
6563 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7260 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -6593,17 +7290,22 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6593 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7290 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6594 7291
6595 if(hw->mac_type == e1000_82541_rev_2 || 7292 if(hw->mac_type == e1000_82541_rev_2 ||
6596 hw->mac_type == e1000_82547_rev_2) { 7293 hw->mac_type == e1000_82547_rev_2) {
6597 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7294 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6598 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6599 if(ret_val) 7296 if(ret_val)
6600 return ret_val; 7297 return ret_val;
6601 } else { 7298 } else {
7299 if (hw->mac_type == e1000_ich8lan) {
7300 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7301 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7302 } else {
6602 phy_data |= IGP02E1000_PM_D3_LPLU; 7303 phy_data |= IGP02E1000_PM_D3_LPLU;
6603 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7304 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6604 phy_data); 7305 phy_data);
6605 if (ret_val) 7306 if (ret_val)
6606 return ret_val; 7307 return ret_val;
7308 }
6607 } 7309 }
6608 7310
6609 /* When LPLU is enabled we should disable SmartSpeed */ 7311 /* When LPLU is enabled we should disable SmartSpeed */
@@ -6638,6 +7340,7 @@ static int32_t
6638e1000_set_d0_lplu_state(struct e1000_hw *hw, 7340e1000_set_d0_lplu_state(struct e1000_hw *hw,
6639 boolean_t active) 7341 boolean_t active)
6640{ 7342{
7343 uint32_t phy_ctrl = 0;
6641 int32_t ret_val; 7344 int32_t ret_val;
6642 uint16_t phy_data; 7345 uint16_t phy_data;
6643 DEBUGFUNC("e1000_set_d0_lplu_state"); 7346 DEBUGFUNC("e1000_set_d0_lplu_state");
@@ -6645,15 +7348,24 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6645 if(hw->mac_type <= e1000_82547_rev_2) 7348 if(hw->mac_type <= e1000_82547_rev_2)
6646 return E1000_SUCCESS; 7349 return E1000_SUCCESS;
6647 7350
7351 if (hw->mac_type == e1000_ich8lan) {
7352 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7353 } else {
6648 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7354 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6649 if(ret_val) 7355 if(ret_val)
6650 return ret_val; 7356 return ret_val;
7357 }
6651 7358
6652 if (!active) { 7359 if (!active) {
7360 if (hw->mac_type == e1000_ich8lan) {
7361 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7362 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7363 } else {
6653 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7364 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6654 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7365 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6655 if (ret_val) 7366 if (ret_val)
6656 return ret_val; 7367 return ret_val;
7368 }
6657 7369
6658 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7370 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6659 * Dx states where the power conservation is most important. During 7371 * Dx states where the power conservation is most important. During
@@ -6686,10 +7398,15 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6686 7398
6687 } else { 7399 } else {
6688 7400
7401 if (hw->mac_type == e1000_ich8lan) {
7402 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7403 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7404 } else {
6689 phy_data |= IGP02E1000_PM_D0_LPLU; 7405 phy_data |= IGP02E1000_PM_D0_LPLU;
6690 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7406 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6691 if (ret_val) 7407 if (ret_val)
6692 return ret_val; 7408 return ret_val;
7409 }
6693 7410
6694 /* When LPLU is enabled we should disable SmartSpeed */ 7411 /* When LPLU is enabled we should disable SmartSpeed */
6695 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
@@ -6928,8 +7645,10 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
6928 7645
6929 length >>= 2; 7646 length >>= 2;
6930 /* The device driver writes the relevant command block into the ram area. */ 7647 /* The device driver writes the relevant command block into the ram area. */
6931 for (i = 0; i < length; i++) 7648 for (i = 0; i < length; i++) {
6932 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); 7649 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7650 E1000_WRITE_FLUSH(hw);
7651 }
6933 7652
6934 return E1000_SUCCESS; 7653 return E1000_SUCCESS;
6935} 7654}
@@ -6961,15 +7680,18 @@ e1000_mng_write_commit(
6961 * returns - TRUE when the mode is IAMT or FALSE. 7680 * returns - TRUE when the mode is IAMT or FALSE.
6962 ****************************************************************************/ 7681 ****************************************************************************/
6963boolean_t 7682boolean_t
6964e1000_check_mng_mode( 7683e1000_check_mng_mode(struct e1000_hw *hw)
6965 struct e1000_hw *hw)
6966{ 7684{
6967 uint32_t fwsm; 7685 uint32_t fwsm;
6968 7686
6969 fwsm = E1000_READ_REG(hw, FWSM); 7687 fwsm = E1000_READ_REG(hw, FWSM);
6970 7688
6971 if((fwsm & E1000_FWSM_MODE_MASK) == 7689 if (hw->mac_type == e1000_ich8lan) {
6972 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7690 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7691 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7692 return TRUE;
7693 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7694 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6973 return TRUE; 7695 return TRUE;
6974 7696
6975 return FALSE; 7697 return FALSE;
@@ -7209,7 +7931,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7209 E1000_WRITE_REG(hw, CTRL, ctrl); 7931 E1000_WRITE_REG(hw, CTRL, ctrl);
7210} 7932}
7211 7933
7212#if 0
7213/*************************************************************************** 7934/***************************************************************************
7214 * 7935 *
7215 * Enables PCI-Express master access. 7936 * Enables PCI-Express master access.
@@ -7219,6 +7940,7 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7219 * returns: - none. 7940 * returns: - none.
7220 * 7941 *
7221 ***************************************************************************/ 7942 ***************************************************************************/
7943#if 0
7222void 7944void
7223e1000_enable_pciex_master(struct e1000_hw *hw) 7945e1000_enable_pciex_master(struct e1000_hw *hw)
7224{ 7946{
@@ -7299,8 +8021,10 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
7299 case e1000_82572: 8021 case e1000_82572:
7300 case e1000_82573: 8022 case e1000_82573:
7301 case e1000_80003es2lan: 8023 case e1000_80003es2lan:
7302 while(timeout) { 8024 case e1000_ich8lan:
7303 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 8025 while (timeout) {
8026 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8027 break;
7304 else msec_delay(1); 8028 else msec_delay(1);
7305 timeout--; 8029 timeout--;
7306 } 8030 }
@@ -7340,7 +8064,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
7340 8064
7341 switch (hw->mac_type) { 8065 switch (hw->mac_type) {
7342 default: 8066 default:
7343 msec_delay(10); 8067 msec_delay_irq(10);
7344 break; 8068 break;
7345 case e1000_80003es2lan: 8069 case e1000_80003es2lan:
7346 /* Separate *_CFG_DONE_* bit for each port */ 8070 /* Separate *_CFG_DONE_* bit for each port */
@@ -7457,7 +8181,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7457 * E1000_SUCCESS at any other case. 8181 * E1000_SUCCESS at any other case.
7458 * 8182 *
7459 ***************************************************************************/ 8183 ***************************************************************************/
7460int32_t 8184static int32_t
7461e1000_get_software_semaphore(struct e1000_hw *hw) 8185e1000_get_software_semaphore(struct e1000_hw *hw)
7462{ 8186{
7463 int32_t timeout = hw->eeprom.word_size + 1; 8187 int32_t timeout = hw->eeprom.word_size + 1;
@@ -7492,7 +8216,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
7492 * hw: Struct containing variables accessed by shared code 8216 * hw: Struct containing variables accessed by shared code
7493 * 8217 *
7494 ***************************************************************************/ 8218 ***************************************************************************/
7495void 8219static void
7496e1000_release_software_semaphore(struct e1000_hw *hw) 8220e1000_release_software_semaphore(struct e1000_hw *hw)
7497{ 8221{
7498 uint32_t swsm; 8222 uint32_t swsm;
@@ -7523,6 +8247,13 @@ int32_t
7523e1000_check_phy_reset_block(struct e1000_hw *hw) 8247e1000_check_phy_reset_block(struct e1000_hw *hw)
7524{ 8248{
7525 uint32_t manc = 0; 8249 uint32_t manc = 0;
8250 uint32_t fwsm = 0;
8251
8252 if (hw->mac_type == e1000_ich8lan) {
8253 fwsm = E1000_READ_REG(hw, FWSM);
8254 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8255 : E1000_BLK_PHY_RESET;
8256 }
7526 8257
7527 if (hw->mac_type > e1000_82547_rev_2) 8258 if (hw->mac_type > e1000_82547_rev_2)
7528 manc = E1000_READ_REG(hw, MANC); 8259 manc = E1000_READ_REG(hw, MANC);
@@ -7549,6 +8280,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7549 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8280 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7550 return TRUE; 8281 return TRUE;
7551 break; 8282 break;
8283 case e1000_ich8lan:
8284 return TRUE;
7552 default: 8285 default:
7553 break; 8286 break;
7554 } 8287 }
@@ -7556,4 +8289,854 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7556} 8289}
7557 8290
7558 8291
8292/******************************************************************************
8293 * Configure PCI-Ex no-snoop
8294 *
8295 * hw - Struct containing variables accessed by shared code.
8296 * no_snoop - Bitmap of no-snoop events.
8297 *
8298 * returns: E1000_SUCCESS
8299 *
8300 *****************************************************************************/
8301static int32_t
8302e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8303{
8304 uint32_t gcr_reg = 0;
8305
8306 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8307
8308 if (hw->bus_type == e1000_bus_type_unknown)
8309 e1000_get_bus_info(hw);
8310
8311 if (hw->bus_type != e1000_bus_type_pci_express)
8312 return E1000_SUCCESS;
8313
8314 if (no_snoop) {
8315 gcr_reg = E1000_READ_REG(hw, GCR);
8316 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8317 gcr_reg |= no_snoop;
8318 E1000_WRITE_REG(hw, GCR, gcr_reg);
8319 }
8320 if (hw->mac_type == e1000_ich8lan) {
8321 uint32_t ctrl_ext;
8322
8323 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8324
8325 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8326 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8327 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8328 }
8329
8330 return E1000_SUCCESS;
8331}
8332
8333/***************************************************************************
8334 *
8335 * Get software semaphore FLAG bit (SWFLAG).
8336 * SWFLAG is used to synchronize the access to all shared resource between
8337 * SW, FW and HW.
8338 *
8339 * hw: Struct containing variables accessed by shared code
8340 *
8341 ***************************************************************************/
8342static int32_t
8343e1000_get_software_flag(struct e1000_hw *hw)
8344{
8345 int32_t timeout = PHY_CFG_TIMEOUT;
8346 uint32_t extcnf_ctrl;
8347
8348 DEBUGFUNC("e1000_get_software_flag");
8349
8350 if (hw->mac_type == e1000_ich8lan) {
8351 while (timeout) {
8352 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8353 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8354 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8355
8356 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8357 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8358 break;
8359 msec_delay_irq(1);
8360 timeout--;
8361 }
8362
8363 if (!timeout) {
8364 DEBUGOUT("FW or HW locks the resource too long.\n");
8365 return -E1000_ERR_CONFIG;
8366 }
8367 }
8368
8369 return E1000_SUCCESS;
8370}
8371
8372/***************************************************************************
8373 *
8374 * Release software semaphore FLAG bit (SWFLAG).
8375 * SWFLAG is used to synchronize the access to all shared resource between
8376 * SW, FW and HW.
8377 *
8378 * hw: Struct containing variables accessed by shared code
8379 *
8380 ***************************************************************************/
8381static void
8382e1000_release_software_flag(struct e1000_hw *hw)
8383{
8384 uint32_t extcnf_ctrl;
8385
8386 DEBUGFUNC("e1000_release_software_flag");
8387
8388 if (hw->mac_type == e1000_ich8lan) {
8389 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8390 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8391 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8392 }
8393
8394 return;
8395}
8396
8397/***************************************************************************
8398 *
8399 * Disable dynamic power down mode in ife PHY.
8400 * It can be used to workaround band-gap problem.
8401 *
8402 * hw: Struct containing variables accessed by shared code
8403 *
8404 ***************************************************************************/
8405#if 0
8406int32_t
8407e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8408{
8409 uint16_t phy_data;
8410 int32_t ret_val = E1000_SUCCESS;
8411
8412 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8413
8414 if (hw->phy_type == e1000_phy_ife) {
8415 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8416 if (ret_val)
8417 return ret_val;
8418
8419 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8420 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8421 }
8422
8423 return ret_val;
8424}
8425#endif /* 0 */
8426
8427/***************************************************************************
8428 *
8429 * Enable dynamic power down mode in ife PHY.
8430 * It can be used to workaround band-gap problem.
8431 *
8432 * hw: Struct containing variables accessed by shared code
8433 *
8434 ***************************************************************************/
8435#if 0
8436int32_t
8437e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8438{
8439 uint16_t phy_data;
8440 int32_t ret_val = E1000_SUCCESS;
8441
8442 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8443
8444 if (hw->phy_type == e1000_phy_ife) {
8445 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8446 if (ret_val)
8447 return ret_val;
8448
8449 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8450 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8451 }
8452
8453 return ret_val;
8454}
8455#endif /* 0 */
8456
8457/******************************************************************************
8458 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8459 * register.
8460 *
8461 * hw - Struct containing variables accessed by shared code
8462 * offset - offset of word in the EEPROM to read
8463 * data - word read from the EEPROM
8464 * words - number of words to read
8465 *****************************************************************************/
8466static int32_t
8467e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8468 uint16_t *data)
8469{
8470 int32_t error = E1000_SUCCESS;
8471 uint32_t flash_bank = 0;
8472 uint32_t act_offset = 0;
8473 uint32_t bank_offset = 0;
8474 uint16_t word = 0;
8475 uint16_t i = 0;
8476
8477 /* We need to know which is the valid flash bank. In the event
8478 * that we didn't allocate eeprom_shadow_ram, we may not be
8479 * managing flash_bank. So it cannot be trusted and needs
8480 * to be updated with each read.
8481 */
8482 /* Value of bit 22 corresponds to the flash bank we're on. */
8483 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8484
8485 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8486 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8487
8488 error = e1000_get_software_flag(hw);
8489 if (error != E1000_SUCCESS)
8490 return error;
8491
8492 for (i = 0; i < words; i++) {
8493 if (hw->eeprom_shadow_ram != NULL &&
8494 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8495 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8496 } else {
8497 /* The NVM part needs a byte offset, hence * 2 */
8498 act_offset = bank_offset + ((offset + i) * 2);
8499 error = e1000_read_ich8_word(hw, act_offset, &word);
8500 if (error != E1000_SUCCESS)
8501 break;
8502 data[i] = word;
8503 }
8504 }
8505
8506 e1000_release_software_flag(hw);
8507
8508 return error;
8509}
8510
8511/******************************************************************************
8512 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8513 * register. Actually, writes are written to the shadow ram cache in the hw
8514 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8515 * the NVM, which occurs when the NVM checksum is updated.
8516 *
8517 * hw - Struct containing variables accessed by shared code
8518 * offset - offset of word in the EEPROM to write
8519 * words - number of words to write
8520 * data - words to write to the EEPROM
8521 *****************************************************************************/
8522static int32_t
8523e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8524 uint16_t *data)
8525{
8526 uint32_t i = 0;
8527 int32_t error = E1000_SUCCESS;
8528
8529 error = e1000_get_software_flag(hw);
8530 if (error != E1000_SUCCESS)
8531 return error;
8532
8533 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8534 * allocated. Subsequent reads to the modified words are read from
8535 * this cached structure as well. Writes will only go into this
8536 * cached structure unless it's followed by a call to
8537 * e1000_update_eeprom_checksum() where it will commit the changes
8538 * and clear the "modified" field.
8539 */
8540 if (hw->eeprom_shadow_ram != NULL) {
8541 for (i = 0; i < words; i++) {
8542 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8543 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8544 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8545 } else {
8546 error = -E1000_ERR_EEPROM;
8547 break;
8548 }
8549 }
8550 } else {
8551 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8552 * as they don't perform any NVM writes. An attempt in doing so
8553 * will result in this error.
8554 */
8555 error = -E1000_ERR_EEPROM;
8556 }
8557
8558 e1000_release_software_flag(hw);
8559
8560 return error;
8561}
8562
8563/******************************************************************************
8564 * This function does initial flash setup so that a new read/write/erase cycle
8565 * can be started.
8566 *
8567 * hw - The pointer to the hw structure
8568 ****************************************************************************/
8569static int32_t
8570e1000_ich8_cycle_init(struct e1000_hw *hw)
8571{
8572 union ich8_hws_flash_status hsfsts;
8573 int32_t error = E1000_ERR_EEPROM;
8574 int32_t i = 0;
8575
8576 DEBUGFUNC("e1000_ich8_cycle_init");
8577
8578 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8579
8580 /* May be check the Flash Des Valid bit in Hw status */
8581 if (hsfsts.hsf_status.fldesvalid == 0) {
8582 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8583 return error;
8584 }
8585
8586 /* Clear FCERR in Hw status by writing 1 */
8587 /* Clear DAEL in Hw status by writing a 1 */
8588 hsfsts.hsf_status.flcerr = 1;
8589 hsfsts.hsf_status.dael = 1;
8590
8591 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8592
8593 /* Either we should have a hardware SPI cycle in progress bit to check
8594 * against, in order to start a new cycle or FDONE bit should be changed
8595 * in the hardware so that it is 1 after harware reset, which can then be
8596 * used as an indication whether a cycle is in progress or has been
8597 * completed .. we should also have some software semaphore mechanism to
8598 * guard FDONE or the cycle in progress bit so that two threads access to
8599 * those bits can be sequentiallized or a way so that 2 threads dont
8600 * start the cycle at the same time */
8601
8602 if (hsfsts.hsf_status.flcinprog == 0) {
8603 /* There is no cycle running at present, so we can start a cycle */
8604 /* Begin by setting Flash Cycle Done. */
8605 hsfsts.hsf_status.flcdone = 1;
8606 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8607 error = E1000_SUCCESS;
8608 } else {
8609 /* otherwise poll for sometime so the current cycle has a chance
8610 * to end before giving up. */
8611 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8612 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8613 if (hsfsts.hsf_status.flcinprog == 0) {
8614 error = E1000_SUCCESS;
8615 break;
8616 }
8617 udelay(1);
8618 }
8619 if (error == E1000_SUCCESS) {
8620 /* Successful in waiting for previous cycle to timeout,
8621 * now set the Flash Cycle Done. */
8622 hsfsts.hsf_status.flcdone = 1;
8623 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8624 } else {
8625 DEBUGOUT("Flash controller busy, cannot get access");
8626 }
8627 }
8628 return error;
8629}
8630
8631/******************************************************************************
8632 * This function starts a flash cycle and waits for its completion
8633 *
8634 * hw - The pointer to the hw structure
8635 ****************************************************************************/
8636static int32_t
8637e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8638{
8639 union ich8_hws_flash_ctrl hsflctl;
8640 union ich8_hws_flash_status hsfsts;
8641 int32_t error = E1000_ERR_EEPROM;
8642 uint32_t i = 0;
8643
8644 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8645 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8646 hsflctl.hsf_ctrl.flcgo = 1;
8647 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8648
8649 /* wait till FDONE bit is set to 1 */
8650 do {
8651 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8652 if (hsfsts.hsf_status.flcdone == 1)
8653 break;
8654 udelay(1);
8655 i++;
8656 } while (i < timeout);
8657 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8658 error = E1000_SUCCESS;
8659 }
8660 return error;
8661}
8662
8663/******************************************************************************
8664 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8665 *
8666 * hw - The pointer to the hw structure
8667 * index - The index of the byte or word to read.
8668 * size - Size of data to read, 1=byte 2=word
8669 * data - Pointer to the word to store the value read.
8670 *****************************************************************************/
8671static int32_t
8672e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8673 uint32_t size, uint16_t* data)
8674{
8675 union ich8_hws_flash_status hsfsts;
8676 union ich8_hws_flash_ctrl hsflctl;
8677 uint32_t flash_linear_address;
8678 uint32_t flash_data = 0;
8679 int32_t error = -E1000_ERR_EEPROM;
8680 int32_t count = 0;
8681
8682 DEBUGFUNC("e1000_read_ich8_data");
8683
8684 if (size < 1 || size > 2 || data == 0x0 ||
8685 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8686 return error;
8687
8688 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8689 hw->flash_base_addr;
8690
8691 do {
8692 udelay(1);
8693 /* Steps */
8694 error = e1000_ich8_cycle_init(hw);
8695 if (error != E1000_SUCCESS)
8696 break;
8697
8698 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8700 hsflctl.hsf_ctrl.fldbcount = size - 1;
8701 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8702 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8703
8704 /* Write the last 24 bits of index into Flash Linear address field in
8705 * Flash Address */
8706 /* TODO: TBD maybe check the index against the size of flash */
8707
8708 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8709
8710 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8711
8712 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8713 * sequence a few more times, else read in (shift in) the Flash Data0,
8714 * the order is least significant byte first msb to lsb */
8715 if (error == E1000_SUCCESS) {
8716 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8717 if (size == 1) {
8718 *data = (uint8_t)(flash_data & 0x000000FF);
8719 } else if (size == 2) {
8720 *data = (uint16_t)(flash_data & 0x0000FFFF);
8721 }
8722 break;
8723 } else {
8724 /* If we've gotten here, then things are probably completely hosed,
8725 * but if the error condition is detected, it won't hurt to give
8726 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8727 */
8728 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8729 if (hsfsts.hsf_status.flcerr == 1) {
8730 /* Repeat for some time before giving up. */
8731 continue;
8732 } else if (hsfsts.hsf_status.flcdone == 0) {
8733 DEBUGOUT("Timeout error - flash cycle did not complete.");
8734 break;
8735 }
8736 }
8737 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8738
8739 return error;
8740}
8741
8742/******************************************************************************
8743 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8744 *
8745 * hw - The pointer to the hw structure
8746 * index - The index of the byte/word to read.
8747 * size - Size of data to read, 1=byte 2=word
8748 * data - The byte(s) to write to the NVM.
8749 *****************************************************************************/
8750static int32_t
8751e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8752 uint16_t data)
8753{
8754 union ich8_hws_flash_status hsfsts;
8755 union ich8_hws_flash_ctrl hsflctl;
8756 uint32_t flash_linear_address;
8757 uint32_t flash_data = 0;
8758 int32_t error = -E1000_ERR_EEPROM;
8759 int32_t count = 0;
8760
8761 DEBUGFUNC("e1000_write_ich8_data");
8762
8763 if (size < 1 || size > 2 || data > size * 0xff ||
8764 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8765 return error;
8766
8767 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8768 hw->flash_base_addr;
8769
8770 do {
8771 udelay(1);
8772 /* Steps */
8773 error = e1000_ich8_cycle_init(hw);
8774 if (error != E1000_SUCCESS)
8775 break;
8776
8777 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8778 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8779 hsflctl.hsf_ctrl.fldbcount = size -1;
8780 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8781 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8782
8783 /* Write the last 24 bits of index into Flash Linear address field in
8784 * Flash Address */
8785 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8786
8787 if (size == 1)
8788 flash_data = (uint32_t)data & 0x00FF;
8789 else
8790 flash_data = (uint32_t)data;
8791
8792 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8793
8794 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8795 * sequence a few more times else done */
8796 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8797 if (error == E1000_SUCCESS) {
8798 break;
8799 } else {
8800 /* If we're here, then things are most likely completely hosed,
8801 * but if the error condition is detected, it won't hurt to give
8802 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8803 */
8804 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8805 if (hsfsts.hsf_status.flcerr == 1) {
8806 /* Repeat for some time before giving up. */
8807 continue;
8808 } else if (hsfsts.hsf_status.flcdone == 0) {
8809 DEBUGOUT("Timeout error - flash cycle did not complete.");
8810 break;
8811 }
8812 }
8813 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8814
8815 return error;
8816}
8817
8818/******************************************************************************
8819 * Reads a single byte from the NVM using the ICH8 flash access registers.
8820 *
8821 * hw - pointer to e1000_hw structure
8822 * index - The index of the byte to read.
8823 * data - Pointer to a byte to store the value read.
8824 *****************************************************************************/
8825static int32_t
8826e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8827{
8828 int32_t status = E1000_SUCCESS;
8829 uint16_t word = 0;
8830
8831 status = e1000_read_ich8_data(hw, index, 1, &word);
8832 if (status == E1000_SUCCESS) {
8833 *data = (uint8_t)word;
8834 }
8835
8836 return status;
8837}
8838
8839/******************************************************************************
8840 * Writes a single byte to the NVM using the ICH8 flash access registers.
8841 * Performs verification by reading back the value and then going through
8842 * a retry algorithm before giving up.
8843 *
8844 * hw - pointer to e1000_hw structure
8845 * index - The index of the byte to write.
8846 * byte - The byte to write to the NVM.
8847 *****************************************************************************/
8848static int32_t
8849e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8850{
8851 int32_t error = E1000_SUCCESS;
8852 int32_t program_retries;
8853 uint8_t temp_byte;
8854
8855 e1000_write_ich8_byte(hw, index, byte);
8856 udelay(100);
8857
8858 for (program_retries = 0; program_retries < 100; program_retries++) {
8859 e1000_read_ich8_byte(hw, index, &temp_byte);
8860 if (temp_byte == byte)
8861 break;
8862 udelay(10);
8863 e1000_write_ich8_byte(hw, index, byte);
8864 udelay(100);
8865 }
8866 if (program_retries == 100)
8867 error = E1000_ERR_EEPROM;
8868
8869 return error;
8870}
8871
8872/******************************************************************************
8873 * Writes a single byte to the NVM using the ICH8 flash access registers.
8874 *
8875 * hw - pointer to e1000_hw structure
8876 * index - The index of the byte to read.
8877 * data - The byte to write to the NVM.
8878 *****************************************************************************/
8879static int32_t
8880e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8881{
8882 int32_t status = E1000_SUCCESS;
8883 uint16_t word = (uint16_t)data;
8884
8885 status = e1000_write_ich8_data(hw, index, 1, word);
8886
8887 return status;
8888}
8889
8890/******************************************************************************
8891 * Reads a word from the NVM using the ICH8 flash access registers.
8892 *
8893 * hw - pointer to e1000_hw structure
8894 * index - The starting byte index of the word to read.
8895 * data - Pointer to a word to store the value read.
8896 *****************************************************************************/
8897static int32_t
8898e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8899{
8900 int32_t status = E1000_SUCCESS;
8901 status = e1000_read_ich8_data(hw, index, 2, data);
8902 return status;
8903}
8904
8905/******************************************************************************
8906 * Writes a word to the NVM using the ICH8 flash access registers.
8907 *
8908 * hw - pointer to e1000_hw structure
8909 * index - The starting byte index of the word to read.
8910 * data - The word to write to the NVM.
8911 *****************************************************************************/
8912#if 0
8913int32_t
8914e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8915{
8916 int32_t status = E1000_SUCCESS;
8917 status = e1000_write_ich8_data(hw, index, 2, data);
8918 return status;
8919}
8920#endif /* 0 */
8921
8922/******************************************************************************
8923 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8924 * segment N is 4096 * N + flash_reg_addr.
8925 *
8926 * hw - pointer to e1000_hw structure
8927 * segment - 0 for first segment, 1 for second segment, etc.
8928 *****************************************************************************/
8929static int32_t
8930e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8931{
8932 union ich8_hws_flash_status hsfsts;
8933 union ich8_hws_flash_ctrl hsflctl;
8934 uint32_t flash_linear_address;
8935 int32_t count = 0;
8936 int32_t error = E1000_ERR_EEPROM;
8937 int32_t iteration, seg_size;
8938 int32_t sector_size;
8939 int32_t j = 0;
8940 int32_t error_flag = 0;
8941
8942 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8943
8944 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8945 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8946 * consecutive sectors. The start index for the nth Hw sector can be
8947 * calculated as = segment * 4096 + n * 256
8948 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8949 * The start index for the nth Hw sector can be calculated
8950 * as = segment * 4096
8951 * 10: Error condition
8952 * 11: The Hw sector size is much bigger than the size asked to
8953 * erase...error condition */
8954 if (hsfsts.hsf_status.berasesz == 0x0) {
8955 /* Hw sector size 256 */
8956 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8957 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8958 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8959 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8960 iteration = 1;
8961 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8962 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8963 iteration = 1;
8964 } else {
8965 return error;
8966 }
8967
8968 for (j = 0; j < iteration ; j++) {
8969 do {
8970 count++;
8971 /* Steps */
8972 error = e1000_ich8_cycle_init(hw);
8973 if (error != E1000_SUCCESS) {
8974 error_flag = 1;
8975 break;
8976 }
8977
8978 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8979 * Control */
8980 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8981 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8982 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8983
8984 /* Write the last 24 bits of an index within the block into Flash
8985 * Linear address field in Flash Address. This probably needs to
8986 * be calculated here based off the on-chip segment size and the
8987 * software segment size assumed (4K) */
8988 /* TBD */
8989 flash_linear_address = segment * sector_size + j * seg_size;
8990 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8991 flash_linear_address += hw->flash_base_addr;
8992
8993 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8994
8995 error = e1000_ich8_flash_cycle(hw, 1000000);
8996 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8997 * sequence a few more times else Done */
8998 if (error == E1000_SUCCESS) {
8999 break;
9000 } else {
9001 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
9002 if (hsfsts.hsf_status.flcerr == 1) {
9003 /* repeat for some time before giving up */
9004 continue;
9005 } else if (hsfsts.hsf_status.flcdone == 0) {
9006 error_flag = 1;
9007 break;
9008 }
9009 }
9010 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
9011 if (error_flag == 1)
9012 break;
9013 }
9014 if (error_flag != 1)
9015 error = E1000_SUCCESS;
9016 return error;
9017}
9018
9019/******************************************************************************
9020 *
9021 * Reverse duplex setting without breaking the link.
9022 *
9023 * hw: Struct containing variables accessed by shared code
9024 *
9025 *****************************************************************************/
9026#if 0
9027int32_t
9028e1000_duplex_reversal(struct e1000_hw *hw)
9029{
9030 int32_t ret_val;
9031 uint16_t phy_data;
9032
9033 if (hw->phy_type != e1000_phy_igp_3)
9034 return E1000_SUCCESS;
9035
9036 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9037 if (ret_val)
9038 return ret_val;
9039
9040 phy_data ^= MII_CR_FULL_DUPLEX;
9041
9042 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9043 if (ret_val)
9044 return ret_val;
9045
9046 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9047 if (ret_val)
9048 return ret_val;
9049
9050 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9051 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9052
9053 return ret_val;
9054}
9055#endif /* 0 */
9056
9057static int32_t
9058e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9059 uint32_t cnf_base_addr, uint32_t cnf_size)
9060{
9061 uint32_t ret_val = E1000_SUCCESS;
9062 uint16_t word_addr, reg_data, reg_addr;
9063 uint16_t i;
9064
9065 /* cnf_base_addr is in DWORD */
9066 word_addr = (uint16_t)(cnf_base_addr << 1);
9067
9068 /* cnf_size is returned in size of dwords */
9069 for (i = 0; i < cnf_size; i++) {
9070 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9071 if (ret_val)
9072 return ret_val;
9073
9074 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9075 if (ret_val)
9076 return ret_val;
9077
9078 ret_val = e1000_get_software_flag(hw);
9079 if (ret_val != E1000_SUCCESS)
9080 return ret_val;
9081
9082 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9083
9084 e1000_release_software_flag(hw);
9085 }
9086
9087 return ret_val;
9088}
9089
9090
9091static int32_t
9092e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9093{
9094 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9095
9096 if (hw->phy_type != e1000_phy_igp_3)
9097 return E1000_SUCCESS;
9098
9099 /* Check if SW needs configure the PHY */
9100 reg_data = E1000_READ_REG(hw, FEXTNVM);
9101 if (!(reg_data & FEXTNVM_SW_CONFIG))
9102 return E1000_SUCCESS;
9103
9104 /* Wait for basic configuration completes before proceeding*/
9105 loop = 0;
9106 do {
9107 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9108 udelay(100);
9109 loop++;
9110 } while ((!reg_data) && (loop < 50));
9111
9112 /* Clear the Init Done bit for the next init event */
9113 reg_data = E1000_READ_REG(hw, STATUS);
9114 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9115 E1000_WRITE_REG(hw, STATUS, reg_data);
9116
9117 /* Make sure HW does not configure LCD from PHY extended configuration
9118 before SW configuration */
9119 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9120 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9121 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9122 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9123 cnf_size >>= 16;
9124 if (cnf_size) {
9125 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9126 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9127 /* cnf_base_addr is in DWORD */
9128 cnf_base_addr >>= 16;
9129
9130 /* Configure LCD from extended configuration region. */
9131 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9132 cnf_size);
9133 if (ret_val)
9134 return ret_val;
9135 }
9136 }
9137
9138 return E1000_SUCCESS;
9139}
9140
9141
7559 9142
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 467c9ed944f8..375b95518c31 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -62,6 +62,7 @@ typedef enum {
62 e1000_82572, 62 e1000_82572,
63 e1000_82573, 63 e1000_82573,
64 e1000_80003es2lan, 64 e1000_80003es2lan,
65 e1000_ich8lan,
65 e1000_num_macs 66 e1000_num_macs
66} e1000_mac_type; 67} e1000_mac_type;
67 68
@@ -70,6 +71,7 @@ typedef enum {
70 e1000_eeprom_spi, 71 e1000_eeprom_spi,
71 e1000_eeprom_microwire, 72 e1000_eeprom_microwire,
72 e1000_eeprom_flash, 73 e1000_eeprom_flash,
74 e1000_eeprom_ich8,
73 e1000_eeprom_none, /* No NVM support */ 75 e1000_eeprom_none, /* No NVM support */
74 e1000_num_eeprom_types 76 e1000_num_eeprom_types
75} e1000_eeprom_type; 77} e1000_eeprom_type;
@@ -98,6 +100,11 @@ typedef enum {
98 e1000_fc_default = 0xFF 100 e1000_fc_default = 0xFF
99} e1000_fc_type; 101} e1000_fc_type;
100 102
103struct e1000_shadow_ram {
104 uint16_t eeprom_word;
105 boolean_t modified;
106};
107
101/* PCI bus types */ 108/* PCI bus types */
102typedef enum { 109typedef enum {
103 e1000_bus_type_unknown = 0, 110 e1000_bus_type_unknown = 0,
@@ -218,6 +225,8 @@ typedef enum {
218 e1000_phy_igp, 225 e1000_phy_igp,
219 e1000_phy_igp_2, 226 e1000_phy_igp_2,
220 e1000_phy_gg82563, 227 e1000_phy_gg82563,
228 e1000_phy_igp_3,
229 e1000_phy_ife,
221 e1000_phy_undefined = 0xFF 230 e1000_phy_undefined = 0xFF
222} e1000_phy_type; 231} e1000_phy_type;
223 232
@@ -313,10 +322,9 @@ int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy
313int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 322int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
314int32_t e1000_phy_hw_reset(struct e1000_hw *hw); 323int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
315int32_t e1000_phy_reset(struct e1000_hw *hw); 324int32_t e1000_phy_reset(struct e1000_hw *hw);
325void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
316int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 326int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
317int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 327int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
318int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
319int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
320 328
321/* EEPROM Functions */ 329/* EEPROM Functions */
322int32_t e1000_init_eeprom_params(struct e1000_hw *hw); 330int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
@@ -331,6 +339,7 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
331#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 339#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
332#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 340#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
333#define E1000_MNG_IAMT_MODE 0x3 341#define E1000_MNG_IAMT_MODE 0x3
342#define E1000_MNG_ICH_IAMT_MODE 0x2
334#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 343#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335 344
336#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 345#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
@@ -386,11 +395,8 @@ int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
386int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 395int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
387int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); 396int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
388int32_t e1000_read_mac_addr(struct e1000_hw * hw); 397int32_t e1000_read_mac_addr(struct e1000_hw * hw);
389int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
390void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
391 398
392/* Filters (multicast, vlan, receive) */ 399/* Filters (multicast, vlan, receive) */
393void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
394uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr); 400uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
395void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value); 401void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
396void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index); 402void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
@@ -401,6 +407,7 @@ int32_t e1000_setup_led(struct e1000_hw *hw);
401int32_t e1000_cleanup_led(struct e1000_hw *hw); 407int32_t e1000_cleanup_led(struct e1000_hw *hw);
402int32_t e1000_led_on(struct e1000_hw *hw); 408int32_t e1000_led_on(struct e1000_hw *hw);
403int32_t e1000_led_off(struct e1000_hw *hw); 409int32_t e1000_led_off(struct e1000_hw *hw);
410int32_t e1000_blink_led_start(struct e1000_hw *hw);
404 411
405/* Adaptive IFS Functions */ 412/* Adaptive IFS Functions */
406 413
@@ -414,15 +421,16 @@ void e1000_pci_clear_mwi(struct e1000_hw *hw);
414void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 421void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
415void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value); 422void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
416/* Port I/O is only supported on 82544 and newer */ 423/* Port I/O is only supported on 82544 and newer */
417uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
418uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
419void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); 424void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
420void e1000_enable_pciex_master(struct e1000_hw *hw);
421int32_t e1000_disable_pciex_master(struct e1000_hw *hw); 425int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
422int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
423void e1000_release_software_semaphore(struct e1000_hw *hw);
424int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); 426int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
425 427
428
429#define E1000_READ_REG_IO(a, reg) \
430 e1000_read_reg_io((a), E1000_##reg)
431#define E1000_WRITE_REG_IO(a, reg, val) \
432 e1000_write_reg_io((a), E1000_##reg, val)
433
426/* PCI Device IDs */ 434/* PCI Device IDs */
427#define E1000_DEV_ID_82542 0x1000 435#define E1000_DEV_ID_82542 0x1000
428#define E1000_DEV_ID_82543GC_FIBER 0x1001 436#define E1000_DEV_ID_82543GC_FIBER 0x1001
@@ -446,6 +454,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
446#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 454#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
447#define E1000_DEV_ID_82541EI 0x1013 455#define E1000_DEV_ID_82541EI 0x1013
448#define E1000_DEV_ID_82541EI_MOBILE 0x1018 456#define E1000_DEV_ID_82541EI_MOBILE 0x1018
457#define E1000_DEV_ID_82541ER_LOM 0x1014
449#define E1000_DEV_ID_82541ER 0x1078 458#define E1000_DEV_ID_82541ER 0x1078
450#define E1000_DEV_ID_82547GI 0x1075 459#define E1000_DEV_ID_82547GI 0x1075
451#define E1000_DEV_ID_82541GI 0x1076 460#define E1000_DEV_ID_82541GI 0x1076
@@ -457,18 +466,28 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
457#define E1000_DEV_ID_82546GB_PCIE 0x108A 466#define E1000_DEV_ID_82546GB_PCIE 0x108A
458#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 467#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
459#define E1000_DEV_ID_82547EI 0x1019 468#define E1000_DEV_ID_82547EI 0x1019
469#define E1000_DEV_ID_82547EI_MOBILE 0x101A
460#define E1000_DEV_ID_82571EB_COPPER 0x105E 470#define E1000_DEV_ID_82571EB_COPPER 0x105E
461#define E1000_DEV_ID_82571EB_FIBER 0x105F 471#define E1000_DEV_ID_82571EB_FIBER 0x105F
462#define E1000_DEV_ID_82571EB_SERDES 0x1060 472#define E1000_DEV_ID_82571EB_SERDES 0x1060
463#define E1000_DEV_ID_82572EI_COPPER 0x107D 473#define E1000_DEV_ID_82572EI_COPPER 0x107D
464#define E1000_DEV_ID_82572EI_FIBER 0x107E 474#define E1000_DEV_ID_82572EI_FIBER 0x107E
465#define E1000_DEV_ID_82572EI_SERDES 0x107F 475#define E1000_DEV_ID_82572EI_SERDES 0x107F
476#define E1000_DEV_ID_82572EI 0x10B9
466#define E1000_DEV_ID_82573E 0x108B 477#define E1000_DEV_ID_82573E 0x108B
467#define E1000_DEV_ID_82573E_IAMT 0x108C 478#define E1000_DEV_ID_82573E_IAMT 0x108C
468#define E1000_DEV_ID_82573L 0x109A 479#define E1000_DEV_ID_82573L 0x109A
469#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 480#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
470#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 481#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
471#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 482#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
483#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
484#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
485
486#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
487#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
488#define E1000_DEV_ID_ICH8_IGP_C 0x104B
489#define E1000_DEV_ID_ICH8_IFE 0x104C
490#define E1000_DEV_ID_ICH8_IGP_M 0x104D
472 491
473 492
474#define NODE_ADDRESS_SIZE 6 493#define NODE_ADDRESS_SIZE 6
@@ -539,6 +558,14 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
539 E1000_IMS_RXSEQ | \ 558 E1000_IMS_RXSEQ | \
540 E1000_IMS_LSC) 559 E1000_IMS_LSC)
541 560
561/* Additional interrupts need to be handled for e1000_ich8lan:
562 DSW = The FW changed the status of the DISSW bit in FWSM
563 PHYINT = The LAN connected device generates an interrupt
564 EPRST = Manageability reset event */
565#define IMS_ICH8LAN_ENABLE_MASK (\
566 E1000_IMS_DSW | \
567 E1000_IMS_PHYINT | \
568 E1000_IMS_EPRST)
542 569
543/* Number of high/low register pairs in the RAR. The RAR (Receive Address 570/* Number of high/low register pairs in the RAR. The RAR (Receive Address
544 * Registers) holds the directed and multicast addresses that we monitor. We 571 * Registers) holds the directed and multicast addresses that we monitor. We
@@ -546,6 +573,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
546 * E1000_RAR_ENTRIES - 1 multicast addresses. 573 * E1000_RAR_ENTRIES - 1 multicast addresses.
547 */ 574 */
548#define E1000_RAR_ENTRIES 15 575#define E1000_RAR_ENTRIES 15
576#define E1000_RAR_ENTRIES_ICH8LAN 7
549 577
550#define MIN_NUMBER_OF_DESCRIPTORS 8 578#define MIN_NUMBER_OF_DESCRIPTORS 8
551#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 579#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
@@ -767,6 +795,9 @@ struct e1000_data_desc {
767#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 795#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
768#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 796#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
769 797
798#define E1000_NUM_UNICAST_ICH8LAN 7
799#define E1000_MC_TBL_SIZE_ICH8LAN 32
800
770 801
771/* Receive Address Register */ 802/* Receive Address Register */
772struct e1000_rar { 803struct e1000_rar {
@@ -776,6 +807,7 @@ struct e1000_rar {
776 807
777/* Number of entries in the Multicast Table Array (MTA). */ 808/* Number of entries in the Multicast Table Array (MTA). */
778#define E1000_NUM_MTA_REGISTERS 128 809#define E1000_NUM_MTA_REGISTERS 128
810#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
779 811
780/* IPv4 Address Table Entry */ 812/* IPv4 Address Table Entry */
781struct e1000_ipv4_at_entry { 813struct e1000_ipv4_at_entry {
@@ -786,6 +818,7 @@ struct e1000_ipv4_at_entry {
786/* Four wakeup IP addresses are supported */ 818/* Four wakeup IP addresses are supported */
787#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 819#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
788#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 820#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
821#define E1000_IP4AT_SIZE_ICH8LAN 3
789#define E1000_IP6AT_SIZE 1 822#define E1000_IP6AT_SIZE 1
790 823
791/* IPv6 Address Table Entry */ 824/* IPv6 Address Table Entry */
@@ -844,6 +877,7 @@ struct e1000_ffvt_entry {
844#define E1000_FLA 0x0001C /* Flash Access - RW */ 877#define E1000_FLA 0x0001C /* Flash Access - RW */
845#define E1000_MDIC 0x00020 /* MDI Control - RW */ 878#define E1000_MDIC 0x00020 /* MDI Control - RW */
846#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 879#define E1000_SCTL 0x00024 /* SerDes Control - RW */
880#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
847#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 881#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
848#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 882#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
849#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 883#define E1000_FCT 0x00030 /* Flow Control Type - RW */
@@ -872,6 +906,8 @@ struct e1000_ffvt_entry {
872#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 906#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
873#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 907#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
874#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 908#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
909#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
910#define FEXTNVM_SW_CONFIG 0x0001
875#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 911#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
876#define E1000_PBS 0x01008 /* Packet Buffer Size */ 912#define E1000_PBS 0x01008 /* Packet Buffer Size */
877#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 913#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
@@ -899,11 +935,13 @@ struct e1000_ffvt_entry {
899#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 935#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
900#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 936#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
901#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 937#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
902#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 938#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
939#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
903#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 940#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
904#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 941#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
905#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 942#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
906#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 943#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
944#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
907#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 945#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
908#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 946#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
909#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 947#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
@@ -1050,6 +1088,7 @@ struct e1000_ffvt_entry {
1050#define E1000_82542_FLA E1000_FLA 1088#define E1000_82542_FLA E1000_FLA
1051#define E1000_82542_MDIC E1000_MDIC 1089#define E1000_82542_MDIC E1000_MDIC
1052#define E1000_82542_SCTL E1000_SCTL 1090#define E1000_82542_SCTL E1000_SCTL
1091#define E1000_82542_FEXTNVM E1000_FEXTNVM
1053#define E1000_82542_FCAL E1000_FCAL 1092#define E1000_82542_FCAL E1000_FCAL
1054#define E1000_82542_FCAH E1000_FCAH 1093#define E1000_82542_FCAH E1000_FCAH
1055#define E1000_82542_FCT E1000_FCT 1094#define E1000_82542_FCT E1000_FCT
@@ -1073,6 +1112,19 @@ struct e1000_ffvt_entry {
1073#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1112#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1074#define E1000_82542_RDH0 E1000_82542_RDH 1113#define E1000_82542_RDH0 E1000_82542_RDH
1075#define E1000_82542_RDT0 E1000_82542_RDT 1114#define E1000_82542_RDT0 E1000_82542_RDT
1115#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1116 * RX Control - RW */
1117#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1118#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1119#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1120#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1121#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1122#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1123#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1124#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1125#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1126#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1127#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1076#define E1000_82542_RDTR1 0x00130 1128#define E1000_82542_RDTR1 0x00130
1077#define E1000_82542_RDBAL1 0x00138 1129#define E1000_82542_RDBAL1 0x00138
1078#define E1000_82542_RDBAH1 0x0013C 1130#define E1000_82542_RDBAH1 0x0013C
@@ -1110,11 +1162,14 @@ struct e1000_ffvt_entry {
1110#define E1000_82542_FLOP E1000_FLOP 1162#define E1000_82542_FLOP E1000_FLOP
1111#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL 1163#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1112#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE 1164#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1165#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1113#define E1000_82542_ERT E1000_ERT 1166#define E1000_82542_ERT E1000_ERT
1114#define E1000_82542_RXDCTL E1000_RXDCTL 1167#define E1000_82542_RXDCTL E1000_RXDCTL
1168#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1115#define E1000_82542_RADV E1000_RADV 1169#define E1000_82542_RADV E1000_RADV
1116#define E1000_82542_RSRPD E1000_RSRPD 1170#define E1000_82542_RSRPD E1000_RSRPD
1117#define E1000_82542_TXDMAC E1000_TXDMAC 1171#define E1000_82542_TXDMAC E1000_TXDMAC
1172#define E1000_82542_KABGTXD E1000_KABGTXD
1118#define E1000_82542_TDFHS E1000_TDFHS 1173#define E1000_82542_TDFHS E1000_TDFHS
1119#define E1000_82542_TDFTS E1000_TDFTS 1174#define E1000_82542_TDFTS E1000_TDFTS
1120#define E1000_82542_TDFPC E1000_TDFPC 1175#define E1000_82542_TDFPC E1000_TDFPC
@@ -1310,13 +1365,16 @@ struct e1000_hw_stats {
1310 1365
1311/* Structure containing variables used by the shared code (e1000_hw.c) */ 1366/* Structure containing variables used by the shared code (e1000_hw.c) */
1312struct e1000_hw { 1367struct e1000_hw {
1313 uint8_t __iomem *hw_addr; 1368 uint8_t *hw_addr;
1314 uint8_t *flash_address; 1369 uint8_t *flash_address;
1315 e1000_mac_type mac_type; 1370 e1000_mac_type mac_type;
1316 e1000_phy_type phy_type; 1371 e1000_phy_type phy_type;
1317 uint32_t phy_init_script; 1372 uint32_t phy_init_script;
1318 e1000_media_type media_type; 1373 e1000_media_type media_type;
1319 void *back; 1374 void *back;
1375 struct e1000_shadow_ram *eeprom_shadow_ram;
1376 uint32_t flash_bank_size;
1377 uint32_t flash_base_addr;
1320 e1000_fc_type fc; 1378 e1000_fc_type fc;
1321 e1000_bus_speed bus_speed; 1379 e1000_bus_speed bus_speed;
1322 e1000_bus_width bus_width; 1380 e1000_bus_width bus_width;
@@ -1328,6 +1386,7 @@ struct e1000_hw {
1328 uint32_t asf_firmware_present; 1386 uint32_t asf_firmware_present;
1329 uint32_t eeprom_semaphore_present; 1387 uint32_t eeprom_semaphore_present;
1330 uint32_t swfw_sync_present; 1388 uint32_t swfw_sync_present;
1389 uint32_t swfwhw_semaphore_present;
1331 unsigned long io_base; 1390 unsigned long io_base;
1332 uint32_t phy_id; 1391 uint32_t phy_id;
1333 uint32_t phy_revision; 1392 uint32_t phy_revision;
@@ -1387,6 +1446,7 @@ struct e1000_hw {
1387 boolean_t in_ifs_mode; 1446 boolean_t in_ifs_mode;
1388 boolean_t mng_reg_access_disabled; 1447 boolean_t mng_reg_access_disabled;
1389 boolean_t leave_av_bit_off; 1448 boolean_t leave_av_bit_off;
1449 boolean_t kmrn_lock_loss_workaround_disabled;
1390}; 1450};
1391 1451
1392 1452
@@ -1435,6 +1495,7 @@ struct e1000_hw {
1435#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1495#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1436#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1496#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1437#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1497#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1498#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1438 1499
1439/* Device Status */ 1500/* Device Status */
1440#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1501#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
@@ -1449,6 +1510,8 @@ struct e1000_hw {
1449#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1510#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1450#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1511#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1451#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1512#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1513#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1514 by EEPROM/Flash */
1452#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1515#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1453#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1516#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1454#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1517#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
@@ -1506,6 +1569,10 @@ struct e1000_hw {
1506#define E1000_STM_OPCODE 0xDB00 1569#define E1000_STM_OPCODE 0xDB00
1507#define E1000_HICR_FW_RESET 0xC0 1570#define E1000_HICR_FW_RESET 0xC0
1508 1571
1572#define E1000_SHADOW_RAM_WORDS 2048
1573#define E1000_ICH8_NVM_SIG_WORD 0x13
1574#define E1000_ICH8_NVM_SIG_MASK 0xC0
1575
1509/* EEPROM Read */ 1576/* EEPROM Read */
1510#define E1000_EERD_START 0x00000001 /* Start Read */ 1577#define E1000_EERD_START 0x00000001 /* Start Read */
1511#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1578#define E1000_EERD_DONE 0x00000010 /* Read Done */
@@ -1551,7 +1618,6 @@ struct e1000_hw {
1551#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1618#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1552#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1619#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1553#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1620#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1554#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1555#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1621#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1556#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1622#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1557#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1623#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
@@ -1591,12 +1657,31 @@ struct e1000_hw {
1591#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1657#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1592 1658
1593/* In-Band Control */ 1659/* In-Band Control */
1660#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1594#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1661#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1595 1662
1596/* Half-Duplex Control */ 1663/* Half-Duplex Control */
1597#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1664#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1598#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1665#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1599 1666
1667#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1668
1669#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1670#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1671
1672#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1673#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1674#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1675
1676#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1677
1678#define E1000_PHY_CTRL_SPD_EN 0x00000001
1679#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1680#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1681#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1682#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1683#define E1000_PHY_CTRL_B2B_EN 0x00000080
1684
1600/* LED Control */ 1685/* LED Control */
1601#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1686#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1602#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1687#define E1000_LEDCTL_LED0_MODE_SHIFT 0
@@ -1666,6 +1751,9 @@ struct e1000_hw {
1666#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1751#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1667#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1752#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1668#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1753#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1754#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1755#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1756#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1669 1757
1670/* Interrupt Cause Set */ 1758/* Interrupt Cause Set */
1671#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1759#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1692,6 +1780,9 @@ struct e1000_hw {
1692#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1780#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1693#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1781#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1694#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1782#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1783#define E1000_ICS_DSW E1000_ICR_DSW
1784#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1785#define E1000_ICS_EPRST E1000_ICR_EPRST
1695 1786
1696/* Interrupt Mask Set */ 1787/* Interrupt Mask Set */
1697#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1788#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1718,6 +1809,9 @@ struct e1000_hw {
1718#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1809#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1719#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1810#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1720#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1811#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1812#define E1000_IMS_DSW E1000_ICR_DSW
1813#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1814#define E1000_IMS_EPRST E1000_ICR_EPRST
1721 1815
1722/* Interrupt Mask Clear */ 1816/* Interrupt Mask Clear */
1723#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1817#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1744,6 +1838,9 @@ struct e1000_hw {
1744#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1838#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1745#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1839#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1746#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1840#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1841#define E1000_IMC_DSW E1000_ICR_DSW
1842#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1843#define E1000_IMC_EPRST E1000_ICR_EPRST
1747 1844
1748/* Receive Control */ 1845/* Receive Control */
1749#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1846#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1918,9 +2015,10 @@ struct e1000_hw {
1918#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2015#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1919#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2016#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1920#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2017#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1921#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000 2018#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
1922#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2019#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1923#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2020#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2021#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1924 2022
1925/* Definitions for power management and wakeup registers */ 2023/* Definitions for power management and wakeup registers */
1926/* Wake Up Control */ 2024/* Wake Up Control */
@@ -2010,6 +2108,15 @@ struct e1000_hw {
2010#define E1000_FWSM_MODE_SHIFT 1 2108#define E1000_FWSM_MODE_SHIFT 1
2011#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2109#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2012 2110
2111#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2112#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2113#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2114#define E1000_FWSM_SKUEL_SHIFT 29
2115#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2116#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2117#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2118#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2119
2013/* FFLT Debug Register */ 2120/* FFLT Debug Register */
2014#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2121#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2015 2122
@@ -2082,6 +2189,8 @@ struct e1000_host_command_info {
2082 E1000_GCR_TXDSCW_NO_SNOOP | \ 2189 E1000_GCR_TXDSCW_NO_SNOOP | \
2083 E1000_GCR_TXDSCR_NO_SNOOP) 2190 E1000_GCR_TXDSCR_NO_SNOOP)
2084 2191
2192#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2193
2085#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2194#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2086/* Function Active and Power State to MNG */ 2195/* Function Active and Power State to MNG */
2087#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2196#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
@@ -2140,8 +2249,10 @@ struct e1000_host_command_info {
2140#define EEPROM_PHY_CLASS_WORD 0x0007 2249#define EEPROM_PHY_CLASS_WORD 0x0007
2141#define EEPROM_INIT_CONTROL1_REG 0x000A 2250#define EEPROM_INIT_CONTROL1_REG 0x000A
2142#define EEPROM_INIT_CONTROL2_REG 0x000F 2251#define EEPROM_INIT_CONTROL2_REG 0x000F
2252#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2143#define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2253#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2144#define EEPROM_INIT_3GIO_3 0x001A 2254#define EEPROM_INIT_3GIO_3 0x001A
2255#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2145#define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2256#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2146#define EEPROM_CFG 0x0012 2257#define EEPROM_CFG 0x0012
2147#define EEPROM_FLASH_VERSION 0x0032 2258#define EEPROM_FLASH_VERSION 0x0032
@@ -2153,10 +2264,16 @@ struct e1000_host_command_info {
2153/* Word definitions for ID LED Settings */ 2264/* Word definitions for ID LED Settings */
2154#define ID_LED_RESERVED_0000 0x0000 2265#define ID_LED_RESERVED_0000 0x0000
2155#define ID_LED_RESERVED_FFFF 0xFFFF 2266#define ID_LED_RESERVED_FFFF 0xFFFF
2267#define ID_LED_RESERVED_82573 0xF746
2268#define ID_LED_DEFAULT_82573 0x1811
2156#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2269#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2157 (ID_LED_OFF1_OFF2 << 8) | \ 2270 (ID_LED_OFF1_OFF2 << 8) | \
2158 (ID_LED_DEF1_DEF2 << 4) | \ 2271 (ID_LED_DEF1_DEF2 << 4) | \
2159 (ID_LED_DEF1_DEF2)) 2272 (ID_LED_DEF1_DEF2))
2273#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2274 (ID_LED_DEF1_OFF2 << 8) | \
2275 (ID_LED_DEF1_ON2 << 4) | \
2276 (ID_LED_DEF1_DEF2))
2160#define ID_LED_DEF1_DEF2 0x1 2277#define ID_LED_DEF1_DEF2 0x1
2161#define ID_LED_DEF1_ON2 0x2 2278#define ID_LED_DEF1_ON2 0x2
2162#define ID_LED_DEF1_OFF2 0x3 2279#define ID_LED_DEF1_OFF2 0x3
@@ -2191,6 +2308,11 @@ struct e1000_host_command_info {
2191#define EEPROM_WORD0F_ASM_DIR 0x2000 2308#define EEPROM_WORD0F_ASM_DIR 0x2000
2192#define EEPROM_WORD0F_ANE 0x0800 2309#define EEPROM_WORD0F_ANE 0x0800
2193#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2310#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2311#define EEPROM_WORD0F_LPLU 0x0001
2312
2313/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2314#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2315#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2194 2316
2195/* Mask bits for fields in Word 0x1a of the EEPROM */ 2317/* Mask bits for fields in Word 0x1a of the EEPROM */
2196#define EEPROM_WORD1A_ASPM_MASK 0x000C 2318#define EEPROM_WORD1A_ASPM_MASK 0x000C
@@ -2265,23 +2387,29 @@ struct e1000_host_command_info {
2265#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2387#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2266#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2388#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2267#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2389#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2268#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 2390#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2269 2391
2270#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2392#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2271#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2393#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2272#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2394#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2395#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2396#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2273 2397
2274/* PBA constants */ 2398/* PBA constants */
2399#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2275#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2400#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2276#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2401#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2277#define E1000_PBA_22K 0x0016 2402#define E1000_PBA_22K 0x0016
2278#define E1000_PBA_24K 0x0018 2403#define E1000_PBA_24K 0x0018
2279#define E1000_PBA_30K 0x001E 2404#define E1000_PBA_30K 0x001E
2280#define E1000_PBA_32K 0x0020 2405#define E1000_PBA_32K 0x0020
2406#define E1000_PBA_34K 0x0022
2281#define E1000_PBA_38K 0x0026 2407#define E1000_PBA_38K 0x0026
2282#define E1000_PBA_40K 0x0028 2408#define E1000_PBA_40K 0x0028
2283#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2409#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2284 2410
2411#define E1000_PBS_16K E1000_PBA_16K
2412
2285/* Flow Control Constants */ 2413/* Flow Control Constants */
2286#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2414#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2287#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2415#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
@@ -2336,7 +2464,7 @@ struct e1000_host_command_info {
2336/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2464/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2337#define AUTO_READ_DONE_TIMEOUT 10 2465#define AUTO_READ_DONE_TIMEOUT 10
2338/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2466/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2339#define PHY_CFG_TIMEOUT 40 2467#define PHY_CFG_TIMEOUT 100
2340 2468
2341#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2469#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2342 2470
@@ -2764,6 +2892,17 @@ struct e1000_host_command_info {
2764#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2892#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2765#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2893#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2766 2894
2895/* M88EC018 Rev 2 specific DownShift settings */
2896#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2897#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2898#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2899#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2900#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2901#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2902#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2903#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2904#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2905
2767/* IGP01E1000 Specific Port Config Register - R/W */ 2906/* IGP01E1000 Specific Port Config Register - R/W */
2768#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 2907#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2769#define IGP01E1000_PSCFR_PRE_EN 0x0020 2908#define IGP01E1000_PSCFR_PRE_EN 0x0020
@@ -2990,6 +3129,221 @@ struct e1000_host_command_info {
2990#define L1LXT971A_PHY_ID 0x001378E0 3129#define L1LXT971A_PHY_ID 0x001378E0
2991#define GG82563_E_PHY_ID 0x01410CA0 3130#define GG82563_E_PHY_ID 0x01410CA0
2992 3131
3132
3133/* Bits...
3134 * 15-5: page
3135 * 4-0: register offset
3136 */
3137#define PHY_PAGE_SHIFT 5
3138#define PHY_REG(page, reg) \
3139 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3140
3141#define IGP3_PHY_PORT_CTRL \
3142 PHY_REG(769, 17) /* Port General Configuration */
3143#define IGP3_PHY_RATE_ADAPT_CTRL \
3144 PHY_REG(769, 25) /* Rate Adapter Control Register */
3145
3146#define IGP3_KMRN_FIFO_CTRL_STATS \
3147 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3148#define IGP3_KMRN_POWER_MNG_CTRL \
3149 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3150#define IGP3_KMRN_INBAND_CTRL \
3151 PHY_REG(770, 18) /* KMRN Inband Control Register */
3152#define IGP3_KMRN_DIAG \
3153 PHY_REG(770, 19) /* KMRN Diagnostic register */
3154#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3155#define IGP3_KMRN_ACK_TIMEOUT \
3156 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3157
3158#define IGP3_VR_CTRL \
3159 PHY_REG(776, 18) /* Voltage regulator control register */
3160#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3161
3162#define IGP3_CAPABILITY \
3163 PHY_REG(776, 19) /* IGP3 Capability Register */
3164
3165/* Capabilities for SKU Control */
3166#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3167#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3168#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3169#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3170#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3171#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3172#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3173#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3174#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3175#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3176
3177#define IGP3_PPC_JORDAN_EN 0x0001
3178#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3179
3180#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3181#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3182#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3183#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3184
3185#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3186#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3187
3188#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3189#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3190
3191#define IGP03E1000_E_PHY_ID 0x02A80390
3192#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3193#define IFE_PLUS_E_PHY_ID 0x02A80320
3194#define IFE_C_E_PHY_ID 0x02A80310
3195
3196#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3197#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3198#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3199#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3200#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3201#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3202#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3203#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3204#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3205#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3206#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3207#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3208#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3209
3210#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3211#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3212#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3213#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3214#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3215#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3216#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3217#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3218
3219#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3220#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3221#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3222#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3223#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3224#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3225
3226#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3227#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3228#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3229#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3230#define IFE_PMC_MDIX_MODE_SHIFT 6
3231#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3232
3233#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3234#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3235#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3236#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3237#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3238#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3239#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3240#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3241#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3242#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3243#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3244
3245#define ICH8_FLASH_COMMAND_TIMEOUT 500 /* 500 ms , should be adjusted */
3246#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles , should be adjusted */
3247#define ICH8_FLASH_SEG_SIZE_256 256
3248#define ICH8_FLASH_SEG_SIZE_4K 4096
3249#define ICH8_FLASH_SEG_SIZE_64K 65536
3250
3251#define ICH8_CYCLE_READ 0x0
3252#define ICH8_CYCLE_RESERVED 0x1
3253#define ICH8_CYCLE_WRITE 0x2
3254#define ICH8_CYCLE_ERASE 0x3
3255
3256#define ICH8_FLASH_GFPREG 0x0000
3257#define ICH8_FLASH_HSFSTS 0x0004
3258#define ICH8_FLASH_HSFCTL 0x0006
3259#define ICH8_FLASH_FADDR 0x0008
3260#define ICH8_FLASH_FDATA0 0x0010
3261#define ICH8_FLASH_FRACC 0x0050
3262#define ICH8_FLASH_FREG0 0x0054
3263#define ICH8_FLASH_FREG1 0x0058
3264#define ICH8_FLASH_FREG2 0x005C
3265#define ICH8_FLASH_FREG3 0x0060
3266#define ICH8_FLASH_FPR0 0x0074
3267#define ICH8_FLASH_FPR1 0x0078
3268#define ICH8_FLASH_SSFSTS 0x0090
3269#define ICH8_FLASH_SSFCTL 0x0092
3270#define ICH8_FLASH_PREOP 0x0094
3271#define ICH8_FLASH_OPTYPE 0x0096
3272#define ICH8_FLASH_OPMENU 0x0098
3273
3274#define ICH8_FLASH_REG_MAPSIZE 0x00A0
3275#define ICH8_FLASH_SECTOR_SIZE 4096
3276#define ICH8_GFPREG_BASE_MASK 0x1FFF
3277#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3278
3279/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3280/* Offset 04h HSFSTS */
3281union ich8_hws_flash_status {
3282 struct ich8_hsfsts {
3283#ifdef E1000_BIG_ENDIAN
3284 uint16_t reserved2 :6;
3285 uint16_t fldesvalid :1;
3286 uint16_t flockdn :1;
3287 uint16_t flcdone :1;
3288 uint16_t flcerr :1;
3289 uint16_t dael :1;
3290 uint16_t berasesz :2;
3291 uint16_t flcinprog :1;
3292 uint16_t reserved1 :2;
3293#else
3294 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3295 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3296 uint16_t dael :1; /* bit 2 Direct Access error Log */
3297 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3298 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3299 uint16_t reserved1 :2; /* bit 13:6 Reserved */
3300 uint16_t reserved2 :6; /* bit 13:6 Reserved */
3301 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3302 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3303#endif
3304 } hsf_status;
3305 uint16_t regval;
3306};
3307
3308/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3309/* Offset 06h FLCTL */
3310union ich8_hws_flash_ctrl {
3311 struct ich8_hsflctl {
3312#ifdef E1000_BIG_ENDIAN
3313 uint16_t fldbcount :2;
3314 uint16_t flockdn :6;
3315 uint16_t flcgo :1;
3316 uint16_t flcycle :2;
3317 uint16_t reserved :5;
3318#else
3319 uint16_t flcgo :1; /* 0 Flash Cycle Go */
3320 uint16_t flcycle :2; /* 2:1 Flash Cycle */
3321 uint16_t reserved :5; /* 7:3 Reserved */
3322 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3323 uint16_t flockdn :6; /* 15:10 Reserved */
3324#endif
3325 } hsf_ctrl;
3326 uint16_t regval;
3327};
3328
3329/* ICH8 Flash Region Access Permissions */
3330union ich8_hws_flash_regacc {
3331 struct ich8_flracc {
3332#ifdef E1000_BIG_ENDIAN
3333 uint32_t gmwag :8;
3334 uint32_t gmrag :8;
3335 uint32_t grwa :8;
3336 uint32_t grra :8;
3337#else
3338 uint32_t grra :8; /* 0:7 GbE region Read Access */
3339 uint32_t grwa :8; /* 8:15 GbE region Write Access */
3340 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3341 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3342#endif
3343 } hsf_flregacc;
3344 uint16_t regval;
3345};
3346
2993/* Miscellaneous PHY bit definitions. */ 3347/* Miscellaneous PHY bit definitions. */
2994#define PHY_PREAMBLE 0xFFFFFFFF 3348#define PHY_PREAMBLE 0xFFFFFFFF
2995#define PHY_SOF 0x01 3349#define PHY_SOF 0x01
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index f77624f5f17b..726f43d55937 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -36,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
36#else 36#else
37#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
38#endif 38#endif
39#define DRV_VERSION "7.0.38-k4"DRIVERNAPI 39#define DRV_VERSION "7.1.9-k4"DRIVERNAPI
40char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
42 42
@@ -73,6 +73,11 @@ static struct pci_device_id e1000_pci_tbl[] = {
73 INTEL_E1000_ETHERNET_DEVICE(0x1026), 73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027), 74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028), 75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
76 INTEL_E1000_ETHERNET_DEVICE(0x1049),
77 INTEL_E1000_ETHERNET_DEVICE(0x104A),
78 INTEL_E1000_ETHERNET_DEVICE(0x104B),
79 INTEL_E1000_ETHERNET_DEVICE(0x104C),
80 INTEL_E1000_ETHERNET_DEVICE(0x104D),
76 INTEL_E1000_ETHERNET_DEVICE(0x105E), 81 INTEL_E1000_ETHERNET_DEVICE(0x105E),
77 INTEL_E1000_ETHERNET_DEVICE(0x105F), 82 INTEL_E1000_ETHERNET_DEVICE(0x105F),
78 INTEL_E1000_ETHERNET_DEVICE(0x1060), 83 INTEL_E1000_ETHERNET_DEVICE(0x1060),
@@ -96,6 +101,8 @@ static struct pci_device_id e1000_pci_tbl[] = {
96 INTEL_E1000_ETHERNET_DEVICE(0x109A), 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
97 INTEL_E1000_ETHERNET_DEVICE(0x10B5), 102 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
98 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 103 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
105 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
99 /* required last entry */ 106 /* required last entry */
100 {0,} 107 {0,}
101}; 108};
@@ -133,7 +140,6 @@ static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
133static void e1000_set_multi(struct net_device *netdev); 140static void e1000_set_multi(struct net_device *netdev);
134static void e1000_update_phy_info(unsigned long data); 141static void e1000_update_phy_info(unsigned long data);
135static void e1000_watchdog(unsigned long data); 142static void e1000_watchdog(unsigned long data);
136static void e1000_watchdog_task(struct e1000_adapter *adapter);
137static void e1000_82547_tx_fifo_stall(unsigned long data); 143static void e1000_82547_tx_fifo_stall(unsigned long data);
138static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 144static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
139static struct net_device_stats * e1000_get_stats(struct net_device *netdev); 145static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
@@ -178,8 +184,8 @@ static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
178static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); 184static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
179static void e1000_restore_vlan(struct e1000_adapter *adapter); 185static void e1000_restore_vlan(struct e1000_adapter *adapter);
180 186
181#ifdef CONFIG_PM
182static int e1000_suspend(struct pci_dev *pdev, pm_message_t state); 187static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
188#ifdef CONFIG_PM
183static int e1000_resume(struct pci_dev *pdev); 189static int e1000_resume(struct pci_dev *pdev);
184#endif 190#endif
185static void e1000_shutdown(struct pci_dev *pdev); 191static void e1000_shutdown(struct pci_dev *pdev);
@@ -206,8 +212,8 @@ static struct pci_driver e1000_driver = {
206 .probe = e1000_probe, 212 .probe = e1000_probe,
207 .remove = __devexit_p(e1000_remove), 213 .remove = __devexit_p(e1000_remove),
208 /* Power Managment Hooks */ 214 /* Power Managment Hooks */
209#ifdef CONFIG_PM
210 .suspend = e1000_suspend, 215 .suspend = e1000_suspend,
216#ifdef CONFIG_PM
211 .resume = e1000_resume, 217 .resume = e1000_resume,
212#endif 218#endif
213 .shutdown = e1000_shutdown, 219 .shutdown = e1000_shutdown,
@@ -261,6 +267,44 @@ e1000_exit_module(void)
261 267
262module_exit(e1000_exit_module); 268module_exit(e1000_exit_module);
263 269
270static int e1000_request_irq(struct e1000_adapter *adapter)
271{
272 struct net_device *netdev = adapter->netdev;
273 int flags, err = 0;
274
275 flags = IRQF_SHARED;
276#ifdef CONFIG_PCI_MSI
277 if (adapter->hw.mac_type > e1000_82547_rev_2) {
278 adapter->have_msi = TRUE;
279 if ((err = pci_enable_msi(adapter->pdev))) {
280 DPRINTK(PROBE, ERR,
281 "Unable to allocate MSI interrupt Error: %d\n", err);
282 adapter->have_msi = FALSE;
283 }
284 }
285 if (adapter->have_msi)
286 flags &= ~IRQF_SHARED;
287#endif
288 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
289 netdev->name, netdev)))
290 DPRINTK(PROBE, ERR,
291 "Unable to allocate interrupt Error: %d\n", err);
292
293 return err;
294}
295
296static void e1000_free_irq(struct e1000_adapter *adapter)
297{
298 struct net_device *netdev = adapter->netdev;
299
300 free_irq(adapter->pdev->irq, netdev);
301
302#ifdef CONFIG_PCI_MSI
303 if (adapter->have_msi)
304 pci_disable_msi(adapter->pdev);
305#endif
306}
307
264/** 308/**
265 * e1000_irq_disable - Mask off interrupt generation on the NIC 309 * e1000_irq_disable - Mask off interrupt generation on the NIC
266 * @adapter: board private structure 310 * @adapter: board private structure
@@ -329,6 +373,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
329{ 373{
330 uint32_t ctrl_ext; 374 uint32_t ctrl_ext;
331 uint32_t swsm; 375 uint32_t swsm;
376 uint32_t extcnf;
332 377
333 /* Let firmware taken over control of h/w */ 378 /* Let firmware taken over control of h/w */
334 switch (adapter->hw.mac_type) { 379 switch (adapter->hw.mac_type) {
@@ -343,6 +388,11 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
343 swsm = E1000_READ_REG(&adapter->hw, SWSM); 388 swsm = E1000_READ_REG(&adapter->hw, SWSM);
344 E1000_WRITE_REG(&adapter->hw, SWSM, 389 E1000_WRITE_REG(&adapter->hw, SWSM,
345 swsm & ~E1000_SWSM_DRV_LOAD); 390 swsm & ~E1000_SWSM_DRV_LOAD);
391 case e1000_ich8lan:
392 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
393 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
394 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
395 break;
346 default: 396 default:
347 break; 397 break;
348 } 398 }
@@ -364,6 +414,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
364{ 414{
365 uint32_t ctrl_ext; 415 uint32_t ctrl_ext;
366 uint32_t swsm; 416 uint32_t swsm;
417 uint32_t extcnf;
367 /* Let firmware know the driver has taken over */ 418 /* Let firmware know the driver has taken over */
368 switch (adapter->hw.mac_type) { 419 switch (adapter->hw.mac_type) {
369 case e1000_82571: 420 case e1000_82571:
@@ -378,6 +429,11 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
378 E1000_WRITE_REG(&adapter->hw, SWSM, 429 E1000_WRITE_REG(&adapter->hw, SWSM,
379 swsm | E1000_SWSM_DRV_LOAD); 430 swsm | E1000_SWSM_DRV_LOAD);
380 break; 431 break;
432 case e1000_ich8lan:
433 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
434 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
435 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
436 break;
381 default: 437 default:
382 break; 438 break;
383 } 439 }
@@ -387,18 +443,10 @@ int
387e1000_up(struct e1000_adapter *adapter) 443e1000_up(struct e1000_adapter *adapter)
388{ 444{
389 struct net_device *netdev = adapter->netdev; 445 struct net_device *netdev = adapter->netdev;
390 int i, err; 446 int i;
391 447
392 /* hardware has been reset, we need to reload some things */ 448 /* hardware has been reset, we need to reload some things */
393 449
394 /* Reset the PHY if it was previously powered down */
395 if (adapter->hw.media_type == e1000_media_type_copper) {
396 uint16_t mii_reg;
397 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
398 if (mii_reg & MII_CR_POWER_DOWN)
399 e1000_phy_hw_reset(&adapter->hw);
400 }
401
402 e1000_set_multi(netdev); 450 e1000_set_multi(netdev);
403 451
404 e1000_restore_vlan(adapter); 452 e1000_restore_vlan(adapter);
@@ -415,24 +463,6 @@ e1000_up(struct e1000_adapter *adapter)
415 E1000_DESC_UNUSED(ring)); 463 E1000_DESC_UNUSED(ring));
416 } 464 }
417 465
418#ifdef CONFIG_PCI_MSI
419 if (adapter->hw.mac_type > e1000_82547_rev_2) {
420 adapter->have_msi = TRUE;
421 if ((err = pci_enable_msi(adapter->pdev))) {
422 DPRINTK(PROBE, ERR,
423 "Unable to allocate MSI interrupt Error: %d\n", err);
424 adapter->have_msi = FALSE;
425 }
426 }
427#endif
428 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
429 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
430 netdev->name, netdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate interrupt Error: %d\n", err);
433 return err;
434 }
435
436 adapter->tx_queue_len = netdev->tx_queue_len; 466 adapter->tx_queue_len = netdev->tx_queue_len;
437 467
438 mod_timer(&adapter->watchdog_timer, jiffies); 468 mod_timer(&adapter->watchdog_timer, jiffies);
@@ -445,21 +475,60 @@ e1000_up(struct e1000_adapter *adapter)
445 return 0; 475 return 0;
446} 476}
447 477
478/**
479 * e1000_power_up_phy - restore link in case the phy was powered down
480 * @adapter: address of board private structure
481 *
482 * The phy may be powered down to save power and turn off link when the
483 * driver is unloaded and wake on lan is not enabled (among others)
484 * *** this routine MUST be followed by a call to e1000_reset ***
485 *
486 **/
487
488static void e1000_power_up_phy(struct e1000_adapter *adapter)
489{
490 uint16_t mii_reg = 0;
491
492 /* Just clear the power down bit to wake the phy back up */
493 if (adapter->hw.media_type == e1000_media_type_copper) {
494 /* according to the manual, the phy will retain its
495 * settings across a power-down/up cycle */
496 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
497 mii_reg &= ~MII_CR_POWER_DOWN;
498 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
499 }
500}
501
502static void e1000_power_down_phy(struct e1000_adapter *adapter)
503{
504 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
505 e1000_check_mng_mode(&adapter->hw);
506 /* Power down the PHY so no link is implied when interface is down
507 * The PHY cannot be powered down if any of the following is TRUE
508 * (a) WoL is enabled
509 * (b) AMT is active
510 * (c) SoL/IDER session is active */
511 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
512 adapter->hw.mac_type != e1000_ich8lan &&
513 adapter->hw.media_type == e1000_media_type_copper &&
514 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
515 !mng_mode_enabled &&
516 !e1000_check_phy_reset_block(&adapter->hw)) {
517 uint16_t mii_reg = 0;
518 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
519 mii_reg |= MII_CR_POWER_DOWN;
520 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
521 mdelay(1);
522 }
523}
524
448void 525void
449e1000_down(struct e1000_adapter *adapter) 526e1000_down(struct e1000_adapter *adapter)
450{ 527{
451 struct net_device *netdev = adapter->netdev; 528 struct net_device *netdev = adapter->netdev;
452 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
453 e1000_check_mng_mode(&adapter->hw);
454 529
455 e1000_irq_disable(adapter); 530 e1000_irq_disable(adapter);
456 531
457 free_irq(adapter->pdev->irq, netdev);
458#ifdef CONFIG_PCI_MSI
459 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
460 adapter->have_msi == TRUE)
461 pci_disable_msi(adapter->pdev);
462#endif
463 del_timer_sync(&adapter->tx_fifo_stall_timer); 532 del_timer_sync(&adapter->tx_fifo_stall_timer);
464 del_timer_sync(&adapter->watchdog_timer); 533 del_timer_sync(&adapter->watchdog_timer);
465 del_timer_sync(&adapter->phy_info_timer); 534 del_timer_sync(&adapter->phy_info_timer);
@@ -476,23 +545,17 @@ e1000_down(struct e1000_adapter *adapter)
476 e1000_reset(adapter); 545 e1000_reset(adapter);
477 e1000_clean_all_tx_rings(adapter); 546 e1000_clean_all_tx_rings(adapter);
478 e1000_clean_all_rx_rings(adapter); 547 e1000_clean_all_rx_rings(adapter);
548}
479 549
480 /* Power down the PHY so no link is implied when interface is down * 550void
481 * The PHY cannot be powered down if any of the following is TRUE * 551e1000_reinit_locked(struct e1000_adapter *adapter)
482 * (a) WoL is enabled 552{
483 * (b) AMT is active 553 WARN_ON(in_interrupt());
484 * (c) SoL/IDER session is active */ 554 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
485 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 && 555 msleep(1);
486 adapter->hw.media_type == e1000_media_type_copper && 556 e1000_down(adapter);
487 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) && 557 e1000_up(adapter);
488 !mng_mode_enabled && 558 clear_bit(__E1000_RESETTING, &adapter->flags);
489 !e1000_check_phy_reset_block(&adapter->hw)) {
490 uint16_t mii_reg;
491 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
492 mii_reg |= MII_CR_POWER_DOWN;
493 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
494 mdelay(1);
495 }
496} 559}
497 560
498void 561void
@@ -518,6 +581,9 @@ e1000_reset(struct e1000_adapter *adapter)
518 case e1000_82573: 581 case e1000_82573:
519 pba = E1000_PBA_12K; 582 pba = E1000_PBA_12K;
520 break; 583 break;
584 case e1000_ich8lan:
585 pba = E1000_PBA_8K;
586 break;
521 default: 587 default:
522 pba = E1000_PBA_48K; 588 pba = E1000_PBA_48K;
523 break; 589 break;
@@ -542,6 +608,12 @@ e1000_reset(struct e1000_adapter *adapter)
542 /* Set the FC high water mark to 90% of the FIFO size. 608 /* Set the FC high water mark to 90% of the FIFO size.
543 * Required to clear last 3 LSB */ 609 * Required to clear last 3 LSB */
544 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8; 610 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
611 /* We can't use 90% on small FIFOs because the remainder
612 * would be less than 1 full frame. In this case, we size
613 * it to allow at least a full frame above the high water
614 * mark. */
615 if (pba < E1000_PBA_16K)
616 fc_high_water_mark = (pba * 1024) - 1600;
545 617
546 adapter->hw.fc_high_water = fc_high_water_mark; 618 adapter->hw.fc_high_water = fc_high_water_mark;
547 adapter->hw.fc_low_water = fc_high_water_mark - 8; 619 adapter->hw.fc_low_water = fc_high_water_mark - 8;
@@ -564,6 +636,23 @@ e1000_reset(struct e1000_adapter *adapter)
564 636
565 e1000_reset_adaptive(&adapter->hw); 637 e1000_reset_adaptive(&adapter->hw);
566 e1000_phy_get_info(&adapter->hw, &adapter->phy_info); 638 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
639
640 if (!adapter->smart_power_down &&
641 (adapter->hw.mac_type == e1000_82571 ||
642 adapter->hw.mac_type == e1000_82572)) {
643 uint16_t phy_data = 0;
644 /* speed up time to link by disabling smart power down, ignore
645 * the return value of this function because there is nothing
646 * different we would do if it failed */
647 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
648 &phy_data);
649 phy_data &= ~IGP02E1000_PM_SPD;
650 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
651 phy_data);
652 }
653
654 if (adapter->hw.mac_type < e1000_ich8lan)
655 /* FIXME: this code is duplicate and wrong for PCI Express */
567 if (adapter->en_mng_pt) { 656 if (adapter->en_mng_pt) {
568 manc = E1000_READ_REG(&adapter->hw, MANC); 657 manc = E1000_READ_REG(&adapter->hw, MANC);
569 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST); 658 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
@@ -590,6 +679,7 @@ e1000_probe(struct pci_dev *pdev,
590 struct net_device *netdev; 679 struct net_device *netdev;
591 struct e1000_adapter *adapter; 680 struct e1000_adapter *adapter;
592 unsigned long mmio_start, mmio_len; 681 unsigned long mmio_start, mmio_len;
682 unsigned long flash_start, flash_len;
593 683
594 static int cards_found = 0; 684 static int cards_found = 0;
595 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 685 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
@@ -599,10 +689,12 @@ e1000_probe(struct pci_dev *pdev,
599 if ((err = pci_enable_device(pdev))) 689 if ((err = pci_enable_device(pdev)))
600 return err; 690 return err;
601 691
602 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { 692 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
693 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
603 pci_using_dac = 1; 694 pci_using_dac = 1;
604 } else { 695 } else {
605 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { 696 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
697 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
606 E1000_ERR("No usable DMA configuration, aborting\n"); 698 E1000_ERR("No usable DMA configuration, aborting\n");
607 return err; 699 return err;
608 } 700 }
@@ -682,6 +774,19 @@ e1000_probe(struct pci_dev *pdev,
682 if ((err = e1000_sw_init(adapter))) 774 if ((err = e1000_sw_init(adapter)))
683 goto err_sw_init; 775 goto err_sw_init;
684 776
777 /* Flash BAR mapping must happen after e1000_sw_init
778 * because it depends on mac_type */
779 if ((adapter->hw.mac_type == e1000_ich8lan) &&
780 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
781 flash_start = pci_resource_start(pdev, 1);
782 flash_len = pci_resource_len(pdev, 1);
783 adapter->hw.flash_address = ioremap(flash_start, flash_len);
784 if (!adapter->hw.flash_address) {
785 err = -EIO;
786 goto err_flashmap;
787 }
788 }
789
685 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 790 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
686 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 791 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
687 792
@@ -700,6 +805,8 @@ e1000_probe(struct pci_dev *pdev,
700 NETIF_F_HW_VLAN_TX | 805 NETIF_F_HW_VLAN_TX |
701 NETIF_F_HW_VLAN_RX | 806 NETIF_F_HW_VLAN_RX |
702 NETIF_F_HW_VLAN_FILTER; 807 NETIF_F_HW_VLAN_FILTER;
808 if (adapter->hw.mac_type == e1000_ich8lan)
809 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
703 } 810 }
704 811
705#ifdef NETIF_F_TSO 812#ifdef NETIF_F_TSO
@@ -715,11 +822,17 @@ e1000_probe(struct pci_dev *pdev,
715 if (pci_using_dac) 822 if (pci_using_dac)
716 netdev->features |= NETIF_F_HIGHDMA; 823 netdev->features |= NETIF_F_HIGHDMA;
717 824
718 /* hard_start_xmit is safe against parallel locking */
719 netdev->features |= NETIF_F_LLTX; 825 netdev->features |= NETIF_F_LLTX;
720 826
721 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw); 827 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
722 828
829 /* initialize eeprom parameters */
830
831 if (e1000_init_eeprom_params(&adapter->hw)) {
832 E1000_ERR("EEPROM initialization failed\n");
833 return -EIO;
834 }
835
723 /* before reading the EEPROM, reset the controller to 836 /* before reading the EEPROM, reset the controller to
724 * put the device in a known good starting state */ 837 * put the device in a known good starting state */
725 838
@@ -758,9 +871,6 @@ e1000_probe(struct pci_dev *pdev,
758 adapter->watchdog_timer.function = &e1000_watchdog; 871 adapter->watchdog_timer.function = &e1000_watchdog;
759 adapter->watchdog_timer.data = (unsigned long) adapter; 872 adapter->watchdog_timer.data = (unsigned long) adapter;
760 873
761 INIT_WORK(&adapter->watchdog_task,
762 (void (*)(void *))e1000_watchdog_task, adapter);
763
764 init_timer(&adapter->phy_info_timer); 874 init_timer(&adapter->phy_info_timer);
765 adapter->phy_info_timer.function = &e1000_update_phy_info; 875 adapter->phy_info_timer.function = &e1000_update_phy_info;
766 adapter->phy_info_timer.data = (unsigned long) adapter; 876 adapter->phy_info_timer.data = (unsigned long) adapter;
@@ -790,6 +900,11 @@ e1000_probe(struct pci_dev *pdev,
790 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 900 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
791 eeprom_apme_mask = E1000_EEPROM_82544_APM; 901 eeprom_apme_mask = E1000_EEPROM_82544_APM;
792 break; 902 break;
903 case e1000_ich8lan:
904 e1000_read_eeprom(&adapter->hw,
905 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
906 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
907 break;
793 case e1000_82546: 908 case e1000_82546:
794 case e1000_82546_rev_3: 909 case e1000_82546_rev_3:
795 case e1000_82571: 910 case e1000_82571:
@@ -849,6 +964,9 @@ e1000_probe(struct pci_dev *pdev,
849 return 0; 964 return 0;
850 965
851err_register: 966err_register:
967 if (adapter->hw.flash_address)
968 iounmap(adapter->hw.flash_address);
969err_flashmap:
852err_sw_init: 970err_sw_init:
853err_eeprom: 971err_eeprom:
854 iounmap(adapter->hw.hw_addr); 972 iounmap(adapter->hw.hw_addr);
@@ -882,6 +1000,7 @@ e1000_remove(struct pci_dev *pdev)
882 flush_scheduled_work(); 1000 flush_scheduled_work();
883 1001
884 if (adapter->hw.mac_type >= e1000_82540 && 1002 if (adapter->hw.mac_type >= e1000_82540 &&
1003 adapter->hw.mac_type != e1000_ich8lan &&
885 adapter->hw.media_type == e1000_media_type_copper) { 1004 adapter->hw.media_type == e1000_media_type_copper) {
886 manc = E1000_READ_REG(&adapter->hw, MANC); 1005 manc = E1000_READ_REG(&adapter->hw, MANC);
887 if (manc & E1000_MANC_SMBUS_EN) { 1006 if (manc & E1000_MANC_SMBUS_EN) {
@@ -910,6 +1029,8 @@ e1000_remove(struct pci_dev *pdev)
910#endif 1029#endif
911 1030
912 iounmap(adapter->hw.hw_addr); 1031 iounmap(adapter->hw.hw_addr);
1032 if (adapter->hw.flash_address)
1033 iounmap(adapter->hw.flash_address);
913 pci_release_regions(pdev); 1034 pci_release_regions(pdev);
914 1035
915 free_netdev(netdev); 1036 free_netdev(netdev);
@@ -947,7 +1068,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
947 1068
948 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 1069 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
949 1070
950 adapter->rx_buffer_len = MAXIMUM_ETHERNET_FRAME_SIZE; 1071 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
951 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128; 1072 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
952 hw->max_frame_size = netdev->mtu + 1073 hw->max_frame_size = netdev->mtu +
953 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 1074 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
@@ -960,13 +1081,6 @@ e1000_sw_init(struct e1000_adapter *adapter)
960 return -EIO; 1081 return -EIO;
961 } 1082 }
962 1083
963 /* initialize eeprom parameters */
964
965 if (e1000_init_eeprom_params(hw)) {
966 E1000_ERR("EEPROM initialization failed\n");
967 return -EIO;
968 }
969
970 switch (hw->mac_type) { 1084 switch (hw->mac_type) {
971 default: 1085 default:
972 break; 1086 break;
@@ -1078,6 +1192,10 @@ e1000_open(struct net_device *netdev)
1078 struct e1000_adapter *adapter = netdev_priv(netdev); 1192 struct e1000_adapter *adapter = netdev_priv(netdev);
1079 int err; 1193 int err;
1080 1194
1195 /* disallow open during test */
1196 if (test_bit(__E1000_DRIVER_TESTING, &adapter->flags))
1197 return -EBUSY;
1198
1081 /* allocate transmit descriptors */ 1199 /* allocate transmit descriptors */
1082 1200
1083 if ((err = e1000_setup_all_tx_resources(adapter))) 1201 if ((err = e1000_setup_all_tx_resources(adapter)))
@@ -1088,6 +1206,12 @@ e1000_open(struct net_device *netdev)
1088 if ((err = e1000_setup_all_rx_resources(adapter))) 1206 if ((err = e1000_setup_all_rx_resources(adapter)))
1089 goto err_setup_rx; 1207 goto err_setup_rx;
1090 1208
1209 err = e1000_request_irq(adapter);
1210 if (err)
1211 goto err_up;
1212
1213 e1000_power_up_phy(adapter);
1214
1091 if ((err = e1000_up(adapter))) 1215 if ((err = e1000_up(adapter)))
1092 goto err_up; 1216 goto err_up;
1093 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 1217 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
@@ -1131,7 +1255,10 @@ e1000_close(struct net_device *netdev)
1131{ 1255{
1132 struct e1000_adapter *adapter = netdev_priv(netdev); 1256 struct e1000_adapter *adapter = netdev_priv(netdev);
1133 1257
1258 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1134 e1000_down(adapter); 1259 e1000_down(adapter);
1260 e1000_power_down_phy(adapter);
1261 e1000_free_irq(adapter);
1135 1262
1136 e1000_free_all_tx_resources(adapter); 1263 e1000_free_all_tx_resources(adapter);
1137 e1000_free_all_rx_resources(adapter); 1264 e1000_free_all_rx_resources(adapter);
@@ -1189,8 +1316,7 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
1189 int size; 1316 int size;
1190 1317
1191 size = sizeof(struct e1000_buffer) * txdr->count; 1318 size = sizeof(struct e1000_buffer) * txdr->count;
1192 1319 txdr->buffer_info = vmalloc(size);
1193 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1194 if (!txdr->buffer_info) { 1320 if (!txdr->buffer_info) {
1195 DPRINTK(PROBE, ERR, 1321 DPRINTK(PROBE, ERR,
1196 "Unable to allocate memory for the transmit descriptor ring\n"); 1322 "Unable to allocate memory for the transmit descriptor ring\n");
@@ -1302,11 +1428,11 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1302 tdba = adapter->tx_ring[0].dma; 1428 tdba = adapter->tx_ring[0].dma;
1303 tdlen = adapter->tx_ring[0].count * 1429 tdlen = adapter->tx_ring[0].count *
1304 sizeof(struct e1000_tx_desc); 1430 sizeof(struct e1000_tx_desc);
1305 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1306 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1307 E1000_WRITE_REG(hw, TDLEN, tdlen); 1431 E1000_WRITE_REG(hw, TDLEN, tdlen);
1308 E1000_WRITE_REG(hw, TDH, 0); 1432 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1433 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1309 E1000_WRITE_REG(hw, TDT, 0); 1434 E1000_WRITE_REG(hw, TDT, 0);
1435 E1000_WRITE_REG(hw, TDH, 0);
1310 adapter->tx_ring[0].tdh = E1000_TDH; 1436 adapter->tx_ring[0].tdh = E1000_TDH;
1311 adapter->tx_ring[0].tdt = E1000_TDT; 1437 adapter->tx_ring[0].tdt = E1000_TDT;
1312 break; 1438 break;
@@ -1418,7 +1544,7 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter,
1418 int size, desc_len; 1544 int size, desc_len;
1419 1545
1420 size = sizeof(struct e1000_buffer) * rxdr->count; 1546 size = sizeof(struct e1000_buffer) * rxdr->count;
1421 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus)); 1547 rxdr->buffer_info = vmalloc(size);
1422 if (!rxdr->buffer_info) { 1548 if (!rxdr->buffer_info) {
1423 DPRINTK(PROBE, ERR, 1549 DPRINTK(PROBE, ERR,
1424 "Unable to allocate memory for the receive descriptor ring\n"); 1550 "Unable to allocate memory for the receive descriptor ring\n");
@@ -1560,9 +1686,6 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1560 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 1686 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1561 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 1687 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1562 1688
1563 if (adapter->hw.mac_type > e1000_82543)
1564 rctl |= E1000_RCTL_SECRC;
1565
1566 if (adapter->hw.tbi_compatibility_on == 1) 1689 if (adapter->hw.tbi_compatibility_on == 1)
1567 rctl |= E1000_RCTL_SBP; 1690 rctl |= E1000_RCTL_SBP;
1568 else 1691 else
@@ -1628,7 +1751,7 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1628 rfctl |= E1000_RFCTL_IPV6_DIS; 1751 rfctl |= E1000_RFCTL_IPV6_DIS;
1629 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl); 1752 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1630 1753
1631 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC; 1754 rctl |= E1000_RCTL_DTYP_PS;
1632 1755
1633 psrctl |= adapter->rx_ps_bsize0 >> 1756 psrctl |= adapter->rx_ps_bsize0 >>
1634 E1000_PSRCTL_BSIZE0_SHIFT; 1757 E1000_PSRCTL_BSIZE0_SHIFT;
@@ -1712,11 +1835,11 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1712 case 1: 1835 case 1:
1713 default: 1836 default:
1714 rdba = adapter->rx_ring[0].dma; 1837 rdba = adapter->rx_ring[0].dma;
1715 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1716 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1717 E1000_WRITE_REG(hw, RDLEN, rdlen); 1838 E1000_WRITE_REG(hw, RDLEN, rdlen);
1718 E1000_WRITE_REG(hw, RDH, 0); 1839 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1840 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1719 E1000_WRITE_REG(hw, RDT, 0); 1841 E1000_WRITE_REG(hw, RDT, 0);
1842 E1000_WRITE_REG(hw, RDH, 0);
1720 adapter->rx_ring[0].rdh = E1000_RDH; 1843 adapter->rx_ring[0].rdh = E1000_RDH;
1721 adapter->rx_ring[0].rdt = E1000_RDT; 1844 adapter->rx_ring[0].rdt = E1000_RDT;
1722 break; 1845 break;
@@ -1741,9 +1864,6 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1741 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 1864 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1742 } 1865 }
1743 1866
1744 if (hw->mac_type == e1000_82573)
1745 E1000_WRITE_REG(hw, ERT, 0x0100);
1746
1747 /* Enable Receives */ 1867 /* Enable Receives */
1748 E1000_WRITE_REG(hw, RCTL, rctl); 1868 E1000_WRITE_REG(hw, RCTL, rctl);
1749} 1869}
@@ -2083,6 +2203,12 @@ e1000_set_multi(struct net_device *netdev)
2083 uint32_t rctl; 2203 uint32_t rctl;
2084 uint32_t hash_value; 2204 uint32_t hash_value;
2085 int i, rar_entries = E1000_RAR_ENTRIES; 2205 int i, rar_entries = E1000_RAR_ENTRIES;
2206 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2207 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2208 E1000_NUM_MTA_REGISTERS;
2209
2210 if (adapter->hw.mac_type == e1000_ich8lan)
2211 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
2086 2212
2087 /* reserve RAR[14] for LAA over-write work-around */ 2213 /* reserve RAR[14] for LAA over-write work-around */
2088 if (adapter->hw.mac_type == e1000_82571) 2214 if (adapter->hw.mac_type == e1000_82571)
@@ -2121,14 +2247,18 @@ e1000_set_multi(struct net_device *netdev)
2121 mc_ptr = mc_ptr->next; 2247 mc_ptr = mc_ptr->next;
2122 } else { 2248 } else {
2123 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0); 2249 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2250 E1000_WRITE_FLUSH(hw);
2124 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0); 2251 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2252 E1000_WRITE_FLUSH(hw);
2125 } 2253 }
2126 } 2254 }
2127 2255
2128 /* clear the old settings from the multicast hash table */ 2256 /* clear the old settings from the multicast hash table */
2129 2257
2130 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++) 2258 for (i = 0; i < mta_reg_count; i++) {
2131 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 2259 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2260 E1000_WRITE_FLUSH(hw);
2261 }
2132 2262
2133 /* load any remaining addresses into the hash table */ 2263 /* load any remaining addresses into the hash table */
2134 2264
@@ -2201,19 +2331,19 @@ static void
2201e1000_watchdog(unsigned long data) 2331e1000_watchdog(unsigned long data)
2202{ 2332{
2203 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 2333 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2204
2205 /* Do the rest outside of interrupt context */
2206 schedule_work(&adapter->watchdog_task);
2207}
2208
2209static void
2210e1000_watchdog_task(struct e1000_adapter *adapter)
2211{
2212 struct net_device *netdev = adapter->netdev; 2334 struct net_device *netdev = adapter->netdev;
2213 struct e1000_tx_ring *txdr = adapter->tx_ring; 2335 struct e1000_tx_ring *txdr = adapter->tx_ring;
2214 uint32_t link, tctl; 2336 uint32_t link, tctl;
2215 2337 int32_t ret_val;
2216 e1000_check_for_link(&adapter->hw); 2338
2339 ret_val = e1000_check_for_link(&adapter->hw);
2340 if ((ret_val == E1000_ERR_PHY) &&
2341 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2342 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2343 /* See e1000_kumeran_lock_loss_workaround() */
2344 DPRINTK(LINK, INFO,
2345 "Gigabit has been disabled, downgrading speed\n");
2346 }
2217 if (adapter->hw.mac_type == e1000_82573) { 2347 if (adapter->hw.mac_type == e1000_82573) {
2218 e1000_enable_tx_pkt_filtering(&adapter->hw); 2348 e1000_enable_tx_pkt_filtering(&adapter->hw);
2219 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) 2349 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
@@ -2394,7 +2524,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2394 uint8_t ipcss, ipcso, tucss, tucso, hdr_len; 2524 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2395 int err; 2525 int err;
2396 2526
2397 if (skb_shinfo(skb)->gso_size) { 2527 if (skb_is_gso(skb)) {
2398 if (skb_header_cloned(skb)) { 2528 if (skb_header_cloned(skb)) {
2399 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 2529 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2400 if (err) 2530 if (err)
@@ -2519,7 +2649,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2519 * tso gets written back prematurely before the data is fully 2649 * tso gets written back prematurely before the data is fully
2520 * DMA'd to the controller */ 2650 * DMA'd to the controller */
2521 if (!skb->data_len && tx_ring->last_tx_tso && 2651 if (!skb->data_len && tx_ring->last_tx_tso &&
2522 !skb_shinfo(skb)->gso_size) { 2652 !skb_is_gso(skb)) {
2523 tx_ring->last_tx_tso = 0; 2653 tx_ring->last_tx_tso = 0;
2524 size -= 4; 2654 size -= 4;
2525 } 2655 }
@@ -2779,9 +2909,10 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2779 case e1000_82571: 2909 case e1000_82571:
2780 case e1000_82572: 2910 case e1000_82572:
2781 case e1000_82573: 2911 case e1000_82573:
2912 case e1000_ich8lan:
2782 pull_size = min((unsigned int)4, skb->data_len); 2913 pull_size = min((unsigned int)4, skb->data_len);
2783 if (!__pskb_pull_tail(skb, pull_size)) { 2914 if (!__pskb_pull_tail(skb, pull_size)) {
2784 printk(KERN_ERR 2915 DPRINTK(DRV, ERR,
2785 "__pskb_pull_tail failed.\n"); 2916 "__pskb_pull_tail failed.\n");
2786 dev_kfree_skb_any(skb); 2917 dev_kfree_skb_any(skb);
2787 return NETDEV_TX_OK; 2918 return NETDEV_TX_OK;
@@ -2806,8 +2937,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2806 2937
2807#ifdef NETIF_F_TSO 2938#ifdef NETIF_F_TSO
2808 /* Controller Erratum workaround */ 2939 /* Controller Erratum workaround */
2809 if (!skb->data_len && tx_ring->last_tx_tso && 2940 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
2810 !skb_shinfo(skb)->gso_size)
2811 count++; 2941 count++;
2812#endif 2942#endif
2813 2943
@@ -2919,8 +3049,7 @@ e1000_reset_task(struct net_device *netdev)
2919{ 3049{
2920 struct e1000_adapter *adapter = netdev_priv(netdev); 3050 struct e1000_adapter *adapter = netdev_priv(netdev);
2921 3051
2922 e1000_down(adapter); 3052 e1000_reinit_locked(adapter);
2923 e1000_up(adapter);
2924} 3053}
2925 3054
2926/** 3055/**
@@ -2964,6 +3093,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2964 /* Adapter-specific max frame size limits. */ 3093 /* Adapter-specific max frame size limits. */
2965 switch (adapter->hw.mac_type) { 3094 switch (adapter->hw.mac_type) {
2966 case e1000_undefined ... e1000_82542_rev2_1: 3095 case e1000_undefined ... e1000_82542_rev2_1:
3096 case e1000_ich8lan:
2967 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { 3097 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2968 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); 3098 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2969 return -EINVAL; 3099 return -EINVAL;
@@ -2997,7 +3127,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2997 break; 3127 break;
2998 } 3128 }
2999 3129
3000 /* NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN 3130 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3001 * means we reserve 2 more, this pushes us to allocate from the next 3131 * means we reserve 2 more, this pushes us to allocate from the next
3002 * larger slab size 3132 * larger slab size
3003 * i.e. RXBUFFER_2048 --> size-4096 slab */ 3133 * i.e. RXBUFFER_2048 --> size-4096 slab */
@@ -3018,7 +3148,6 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3018 adapter->rx_buffer_len = E1000_RXBUFFER_16384; 3148 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3019 3149
3020 /* adjust allocation if LPE protects us, and we aren't using SBP */ 3150 /* adjust allocation if LPE protects us, and we aren't using SBP */
3021#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
3022 if (!adapter->hw.tbi_compatibility_on && 3151 if (!adapter->hw.tbi_compatibility_on &&
3023 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) || 3152 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3024 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))) 3153 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
@@ -3026,10 +3155,8 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3026 3155
3027 netdev->mtu = new_mtu; 3156 netdev->mtu = new_mtu;
3028 3157
3029 if (netif_running(netdev)) { 3158 if (netif_running(netdev))
3030 e1000_down(adapter); 3159 e1000_reinit_locked(adapter);
3031 e1000_up(adapter);
3032 }
3033 3160
3034 adapter->hw.max_frame_size = max_frame; 3161 adapter->hw.max_frame_size = max_frame;
3035 3162
@@ -3074,12 +3201,15 @@ e1000_update_stats(struct e1000_adapter *adapter)
3074 adapter->stats.bprc += E1000_READ_REG(hw, BPRC); 3201 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3075 adapter->stats.mprc += E1000_READ_REG(hw, MPRC); 3202 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3076 adapter->stats.roc += E1000_READ_REG(hw, ROC); 3203 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3204
3205 if (adapter->hw.mac_type != e1000_ich8lan) {
3077 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64); 3206 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3078 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127); 3207 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3079 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255); 3208 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3080 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511); 3209 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3081 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023); 3210 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3082 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522); 3211 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3212 }
3083 3213
3084 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS); 3214 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3085 adapter->stats.mpc += E1000_READ_REG(hw, MPC); 3215 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
@@ -3107,12 +3237,16 @@ e1000_update_stats(struct e1000_adapter *adapter)
3107 adapter->stats.totl += E1000_READ_REG(hw, TOTL); 3237 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3108 adapter->stats.toth += E1000_READ_REG(hw, TOTH); 3238 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3109 adapter->stats.tpr += E1000_READ_REG(hw, TPR); 3239 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3240
3241 if (adapter->hw.mac_type != e1000_ich8lan) {
3110 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64); 3242 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3111 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127); 3243 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3112 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255); 3244 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3113 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511); 3245 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3114 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023); 3246 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3115 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522); 3247 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3248 }
3249
3116 adapter->stats.mptc += E1000_READ_REG(hw, MPTC); 3250 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3117 adapter->stats.bptc += E1000_READ_REG(hw, BPTC); 3251 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3118 3252
@@ -3134,6 +3268,8 @@ e1000_update_stats(struct e1000_adapter *adapter)
3134 if (hw->mac_type > e1000_82547_rev_2) { 3268 if (hw->mac_type > e1000_82547_rev_2) {
3135 adapter->stats.iac += E1000_READ_REG(hw, IAC); 3269 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3136 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); 3270 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3271
3272 if (adapter->hw.mac_type != e1000_ich8lan) {
3137 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); 3273 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3138 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); 3274 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3139 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); 3275 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
@@ -3141,6 +3277,7 @@ e1000_update_stats(struct e1000_adapter *adapter)
3141 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); 3277 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3142 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); 3278 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3143 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); 3279 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3280 }
3144 } 3281 }
3145 3282
3146 /* Fill out the OS statistics structure */ 3283 /* Fill out the OS statistics structure */
@@ -3249,8 +3386,8 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
3249 E1000_WRITE_REG(hw, IMC, ~0); 3386 E1000_WRITE_REG(hw, IMC, ~0);
3250 E1000_WRITE_FLUSH(hw); 3387 E1000_WRITE_FLUSH(hw);
3251 } 3388 }
3252 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0]))) 3389 if (likely(netif_rx_schedule_prep(netdev)))
3253 __netif_rx_schedule(&adapter->polling_netdev[0]); 3390 __netif_rx_schedule(netdev);
3254 else 3391 else
3255 e1000_irq_enable(adapter); 3392 e1000_irq_enable(adapter);
3256#else 3393#else
@@ -3293,34 +3430,26 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3293{ 3430{
3294 struct e1000_adapter *adapter; 3431 struct e1000_adapter *adapter;
3295 int work_to_do = min(*budget, poll_dev->quota); 3432 int work_to_do = min(*budget, poll_dev->quota);
3296 int tx_cleaned = 0, i = 0, work_done = 0; 3433 int tx_cleaned = 0, work_done = 0;
3297 3434
3298 /* Must NOT use netdev_priv macro here. */ 3435 /* Must NOT use netdev_priv macro here. */
3299 adapter = poll_dev->priv; 3436 adapter = poll_dev->priv;
3300 3437
3301 /* Keep link state information with original netdev */ 3438 /* Keep link state information with original netdev */
3302 if (!netif_carrier_ok(adapter->netdev)) 3439 if (!netif_carrier_ok(poll_dev))
3303 goto quit_polling; 3440 goto quit_polling;
3304 3441
3305 while (poll_dev != &adapter->polling_netdev[i]) { 3442 /* e1000_clean is called per-cpu. This lock protects
3306 i++; 3443 * tx_ring[0] from being cleaned by multiple cpus
3307 BUG_ON(i == adapter->num_rx_queues); 3444 * simultaneously. A failure obtaining the lock means
3445 * tx_ring[0] is currently being cleaned anyway. */
3446 if (spin_trylock(&adapter->tx_queue_lock)) {
3447 tx_cleaned = e1000_clean_tx_irq(adapter,
3448 &adapter->tx_ring[0]);
3449 spin_unlock(&adapter->tx_queue_lock);
3308 } 3450 }
3309 3451
3310 if (likely(adapter->num_tx_queues == 1)) { 3452 adapter->clean_rx(adapter, &adapter->rx_ring[0],
3311 /* e1000_clean is called per-cpu. This lock protects
3312 * tx_ring[0] from being cleaned by multiple cpus
3313 * simultaneously. A failure obtaining the lock means
3314 * tx_ring[0] is currently being cleaned anyway. */
3315 if (spin_trylock(&adapter->tx_queue_lock)) {
3316 tx_cleaned = e1000_clean_tx_irq(adapter,
3317 &adapter->tx_ring[0]);
3318 spin_unlock(&adapter->tx_queue_lock);
3319 }
3320 } else
3321 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3322
3323 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3324 &work_done, work_to_do); 3453 &work_done, work_to_do);
3325 3454
3326 *budget -= work_done; 3455 *budget -= work_done;
@@ -3328,7 +3457,7 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3328 3457
3329 /* If no Tx and not enough Rx work done, exit the polling mode */ 3458 /* If no Tx and not enough Rx work done, exit the polling mode */
3330 if ((!tx_cleaned && (work_done == 0)) || 3459 if ((!tx_cleaned && (work_done == 0)) ||
3331 !netif_running(adapter->netdev)) { 3460 !netif_running(poll_dev)) {
3332quit_polling: 3461quit_polling:
3333 netif_rx_complete(poll_dev); 3462 netif_rx_complete(poll_dev);
3334 e1000_irq_enable(adapter); 3463 e1000_irq_enable(adapter);
@@ -3543,11 +3672,15 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3543 3672
3544 length = le16_to_cpu(rx_desc->length); 3673 length = le16_to_cpu(rx_desc->length);
3545 3674
3675 /* adjust length to remove Ethernet CRC */
3676 length -= 4;
3677
3546 if (unlikely(!(status & E1000_RXD_STAT_EOP))) { 3678 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3547 /* All receives must fit into a single buffer */ 3679 /* All receives must fit into a single buffer */
3548 E1000_DBG("%s: Receive packet consumed multiple" 3680 E1000_DBG("%s: Receive packet consumed multiple"
3549 " buffers\n", netdev->name); 3681 " buffers\n", netdev->name);
3550 dev_kfree_skb_irq(skb); 3682 /* recycle */
3683 buffer_info-> skb = skb;
3551 goto next_desc; 3684 goto next_desc;
3552 } 3685 }
3553 3686
@@ -3575,7 +3708,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3575#define E1000_CB_LENGTH 256 3708#define E1000_CB_LENGTH 256
3576 if (length < E1000_CB_LENGTH) { 3709 if (length < E1000_CB_LENGTH) {
3577 struct sk_buff *new_skb = 3710 struct sk_buff *new_skb =
3578 dev_alloc_skb(length + NET_IP_ALIGN); 3711 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
3579 if (new_skb) { 3712 if (new_skb) {
3580 skb_reserve(new_skb, NET_IP_ALIGN); 3713 skb_reserve(new_skb, NET_IP_ALIGN);
3581 new_skb->dev = netdev; 3714 new_skb->dev = netdev;
@@ -3675,7 +3808,6 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3675 buffer_info = &rx_ring->buffer_info[i]; 3808 buffer_info = &rx_ring->buffer_info[i];
3676 3809
3677 while (staterr & E1000_RXD_STAT_DD) { 3810 while (staterr & E1000_RXD_STAT_DD) {
3678 buffer_info = &rx_ring->buffer_info[i];
3679 ps_page = &rx_ring->ps_page[i]; 3811 ps_page = &rx_ring->ps_page[i];
3680 ps_page_dma = &rx_ring->ps_page_dma[i]; 3812 ps_page_dma = &rx_ring->ps_page_dma[i];
3681#ifdef CONFIG_E1000_NAPI 3813#ifdef CONFIG_E1000_NAPI
@@ -3747,8 +3879,9 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3747 pci_dma_sync_single_for_device(pdev, 3879 pci_dma_sync_single_for_device(pdev,
3748 ps_page_dma->ps_page_dma[0], 3880 ps_page_dma->ps_page_dma[0],
3749 PAGE_SIZE, PCI_DMA_FROMDEVICE); 3881 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3882 /* remove the CRC */
3883 l1 -= 4;
3750 skb_put(skb, l1); 3884 skb_put(skb, l1);
3751 length += l1;
3752 goto copydone; 3885 goto copydone;
3753 } /* if */ 3886 } /* if */
3754 } 3887 }
@@ -3767,6 +3900,10 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3767 skb->truesize += length; 3900 skb->truesize += length;
3768 } 3901 }
3769 3902
3903 /* strip the ethernet crc, problem is we're using pages now so
3904 * this whole operation can get a little cpu intensive */
3905 pskb_trim(skb, skb->len - 4);
3906
3770copydone: 3907copydone:
3771 e1000_rx_checksum(adapter, staterr, 3908 e1000_rx_checksum(adapter, staterr,
3772 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); 3909 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
@@ -3842,7 +3979,7 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3842 3979
3843 while (cleaned_count--) { 3980 while (cleaned_count--) {
3844 if (!(skb = buffer_info->skb)) 3981 if (!(skb = buffer_info->skb))
3845 skb = dev_alloc_skb(bufsz); 3982 skb = netdev_alloc_skb(netdev, bufsz);
3846 else { 3983 else {
3847 skb_trim(skb, 0); 3984 skb_trim(skb, 0);
3848 goto map_skb; 3985 goto map_skb;
@@ -3860,7 +3997,7 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3860 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes " 3997 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3861 "at %p\n", bufsz, skb->data); 3998 "at %p\n", bufsz, skb->data);
3862 /* Try again, without freeing the previous */ 3999 /* Try again, without freeing the previous */
3863 skb = dev_alloc_skb(bufsz); 4000 skb = netdev_alloc_skb(netdev, bufsz);
3864 /* Failed allocation, critical failure */ 4001 /* Failed allocation, critical failure */
3865 if (!skb) { 4002 if (!skb) {
3866 dev_kfree_skb(oldskb); 4003 dev_kfree_skb(oldskb);
@@ -3984,7 +4121,8 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3984 rx_desc->read.buffer_addr[j+1] = ~0; 4121 rx_desc->read.buffer_addr[j+1] = ~0;
3985 } 4122 }
3986 4123
3987 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN); 4124 skb = netdev_alloc_skb(netdev,
4125 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3988 4126
3989 if (unlikely(!skb)) { 4127 if (unlikely(!skb)) {
3990 adapter->alloc_rx_buff_failed++; 4128 adapter->alloc_rx_buff_failed++;
@@ -4180,10 +4318,9 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4180 return retval; 4318 return retval;
4181 } 4319 }
4182 } 4320 }
4183 if (netif_running(adapter->netdev)) { 4321 if (netif_running(adapter->netdev))
4184 e1000_down(adapter); 4322 e1000_reinit_locked(adapter);
4185 e1000_up(adapter); 4323 else
4186 } else
4187 e1000_reset(adapter); 4324 e1000_reset(adapter);
4188 break; 4325 break;
4189 case M88E1000_PHY_SPEC_CTRL: 4326 case M88E1000_PHY_SPEC_CTRL:
@@ -4200,10 +4337,9 @@ e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4200 case PHY_CTRL: 4337 case PHY_CTRL:
4201 if (mii_reg & MII_CR_POWER_DOWN) 4338 if (mii_reg & MII_CR_POWER_DOWN)
4202 break; 4339 break;
4203 if (netif_running(adapter->netdev)) { 4340 if (netif_running(adapter->netdev))
4204 e1000_down(adapter); 4341 e1000_reinit_locked(adapter);
4205 e1000_up(adapter); 4342 else
4206 } else
4207 e1000_reset(adapter); 4343 e1000_reset(adapter);
4208 break; 4344 break;
4209 } 4345 }
@@ -4250,11 +4386,13 @@ e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4250 pci_write_config_word(adapter->pdev, reg, *value); 4386 pci_write_config_word(adapter->pdev, reg, *value);
4251} 4387}
4252 4388
4389#if 0
4253uint32_t 4390uint32_t
4254e1000_io_read(struct e1000_hw *hw, unsigned long port) 4391e1000_io_read(struct e1000_hw *hw, unsigned long port)
4255{ 4392{
4256 return inl(port); 4393 return inl(port);
4257} 4394}
4395#endif /* 0 */
4258 4396
4259void 4397void
4260e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 4398e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
@@ -4277,18 +4415,21 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4277 ctrl |= E1000_CTRL_VME; 4415 ctrl |= E1000_CTRL_VME;
4278 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4416 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4279 4417
4418 if (adapter->hw.mac_type != e1000_ich8lan) {
4280 /* enable VLAN receive filtering */ 4419 /* enable VLAN receive filtering */
4281 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4420 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4282 rctl |= E1000_RCTL_VFE; 4421 rctl |= E1000_RCTL_VFE;
4283 rctl &= ~E1000_RCTL_CFIEN; 4422 rctl &= ~E1000_RCTL_CFIEN;
4284 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4423 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4285 e1000_update_mng_vlan(adapter); 4424 e1000_update_mng_vlan(adapter);
4425 }
4286 } else { 4426 } else {
4287 /* disable VLAN tag insert/strip */ 4427 /* disable VLAN tag insert/strip */
4288 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 4428 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4289 ctrl &= ~E1000_CTRL_VME; 4429 ctrl &= ~E1000_CTRL_VME;
4290 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4430 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4291 4431
4432 if (adapter->hw.mac_type != e1000_ich8lan) {
4292 /* disable VLAN filtering */ 4433 /* disable VLAN filtering */
4293 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4434 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4294 rctl &= ~E1000_RCTL_VFE; 4435 rctl &= ~E1000_RCTL_VFE;
@@ -4297,6 +4438,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4297 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4438 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4298 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4439 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4299 } 4440 }
4441 }
4300 } 4442 }
4301 4443
4302 e1000_irq_enable(adapter); 4444 e1000_irq_enable(adapter);
@@ -4458,12 +4600,16 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4458 struct e1000_adapter *adapter = netdev_priv(netdev); 4600 struct e1000_adapter *adapter = netdev_priv(netdev);
4459 uint32_t ctrl, ctrl_ext, rctl, manc, status; 4601 uint32_t ctrl, ctrl_ext, rctl, manc, status;
4460 uint32_t wufc = adapter->wol; 4602 uint32_t wufc = adapter->wol;
4603#ifdef CONFIG_PM
4461 int retval = 0; 4604 int retval = 0;
4605#endif
4462 4606
4463 netif_device_detach(netdev); 4607 netif_device_detach(netdev);
4464 4608
4465 if (netif_running(netdev)) 4609 if (netif_running(netdev)) {
4610 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
4466 e1000_down(adapter); 4611 e1000_down(adapter);
4612 }
4467 4613
4468#ifdef CONFIG_PM 4614#ifdef CONFIG_PM
4469 /* Implement our own version of pci_save_state(pdev) because pci- 4615 /* Implement our own version of pci_save_state(pdev) because pci-
@@ -4521,7 +4667,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4521 pci_enable_wake(pdev, PCI_D3cold, 0); 4667 pci_enable_wake(pdev, PCI_D3cold, 0);
4522 } 4668 }
4523 4669
4670 /* FIXME: this code is incorrect for PCI Express */
4524 if (adapter->hw.mac_type >= e1000_82540 && 4671 if (adapter->hw.mac_type >= e1000_82540 &&
4672 adapter->hw.mac_type != e1000_ich8lan &&
4525 adapter->hw.media_type == e1000_media_type_copper) { 4673 adapter->hw.media_type == e1000_media_type_copper) {
4526 manc = E1000_READ_REG(&adapter->hw, MANC); 4674 manc = E1000_READ_REG(&adapter->hw, MANC);
4527 if (manc & E1000_MANC_SMBUS_EN) { 4675 if (manc & E1000_MANC_SMBUS_EN) {
@@ -4532,6 +4680,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4532 } 4680 }
4533 } 4681 }
4534 4682
4683 if (adapter->hw.phy_type == e1000_phy_igp_3)
4684 e1000_phy_powerdown_workaround(&adapter->hw);
4685
4535 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4686 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4536 * would have already happened in close and is redundant. */ 4687 * would have already happened in close and is redundant. */
4537 e1000_release_hw_control(adapter); 4688 e1000_release_hw_control(adapter);
@@ -4567,7 +4718,9 @@ e1000_resume(struct pci_dev *pdev)
4567 4718
4568 netif_device_attach(netdev); 4719 netif_device_attach(netdev);
4569 4720
4721 /* FIXME: this code is incorrect for PCI Express */
4570 if (adapter->hw.mac_type >= e1000_82540 && 4722 if (adapter->hw.mac_type >= e1000_82540 &&
4723 adapter->hw.mac_type != e1000_ich8lan &&
4571 adapter->hw.media_type == e1000_media_type_copper) { 4724 adapter->hw.media_type == e1000_media_type_copper) {
4572 manc = E1000_READ_REG(&adapter->hw, MANC); 4725 manc = E1000_READ_REG(&adapter->hw, MANC);
4573 manc &= ~(E1000_MANC_ARP_EN); 4726 manc &= ~(E1000_MANC_ARP_EN);
@@ -4601,6 +4754,7 @@ static void
4601e1000_netpoll(struct net_device *netdev) 4754e1000_netpoll(struct net_device *netdev)
4602{ 4755{
4603 struct e1000_adapter *adapter = netdev_priv(netdev); 4756 struct e1000_adapter *adapter = netdev_priv(netdev);
4757
4604 disable_irq(adapter->pdev->irq); 4758 disable_irq(adapter->pdev->irq);
4605 e1000_intr(adapter->pdev->irq, netdev, NULL); 4759 e1000_intr(adapter->pdev->irq, netdev, NULL);
4606 e1000_clean_tx_irq(adapter, adapter->tx_ring); 4760 e1000_clean_tx_irq(adapter, adapter->tx_ring);
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 048d052be29d..2d3e8b06cab0 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -127,4 +127,17 @@ typedef enum {
127 127
128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 128#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
129 129
130#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
131 writel((value), ((a)->flash_address + reg)))
132
133#define E1000_READ_ICH8_REG(a, reg) ( \
134 readl((a)->flash_address + reg))
135
136#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
137 writew((value), ((a)->flash_address + reg)))
138
139#define E1000_READ_ICH8_REG16(a, reg) ( \
140 readw((a)->flash_address + reg))
141
142
130#endif /* _E1000_OSDEP_H_ */ 143#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index e55f8969a0fb..0ef413172c68 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -45,6 +45,16 @@
45 */ 45 */
46 46
47#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 47#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
48/* Module Parameters are always initialized to -1, so that the driver
49 * can tell the difference between no user specified value or the
50 * user asking for the default value.
51 * The true default values are loaded in when e1000_check_options is called.
52 *
53 * This is a GCC extension to ANSI C.
54 * See the item "Labeled Elements in Initializers" in the section
55 * "Extensions to the C Language Family" of the GCC documentation.
56 */
57
48#define E1000_PARAM(X, desc) \ 58#define E1000_PARAM(X, desc) \
49 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 59 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
50 static int num_##X = 0; \ 60 static int num_##X = 0; \
@@ -183,6 +193,24 @@ E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
183 193
184E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 194E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
185 195
196/* Enable Smart Power Down of the PHY
197 *
198 * Valid Range: 0, 1
199 *
200 * Default Value: 0 (disabled)
201 */
202
203E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
204
205/* Enable Kumeran Lock Loss workaround
206 *
207 * Valid Range: 0, 1
208 *
209 * Default Value: 1 (enabled)
210 */
211
212E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
213
186#define AUTONEG_ADV_DEFAULT 0x2F 214#define AUTONEG_ADV_DEFAULT 0x2F
187#define AUTONEG_ADV_MASK 0x2F 215#define AUTONEG_ADV_MASK 0x2F
188#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL 216#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
@@ -296,6 +324,7 @@ e1000_check_options(struct e1000_adapter *adapter)
296 DPRINTK(PROBE, NOTICE, 324 DPRINTK(PROBE, NOTICE,
297 "Warning: no configuration for board #%i\n", bd); 325 "Warning: no configuration for board #%i\n", bd);
298 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n"); 326 DPRINTK(PROBE, NOTICE, "Using defaults for all values\n");
327 bd = E1000_MAX_NIC;
299 } 328 }
300 329
301 { /* Transmit Descriptor Count */ 330 { /* Transmit Descriptor Count */
@@ -313,14 +342,9 @@ e1000_check_options(struct e1000_adapter *adapter)
313 opt.arg.r.max = mac_type < e1000_82544 ? 342 opt.arg.r.max = mac_type < e1000_82544 ?
314 E1000_MAX_TXD : E1000_MAX_82544_TXD; 343 E1000_MAX_TXD : E1000_MAX_82544_TXD;
315 344
316 if (num_TxDescriptors > bd) { 345 tx_ring->count = TxDescriptors[bd];
317 tx_ring->count = TxDescriptors[bd]; 346 e1000_validate_option(&tx_ring->count, &opt, adapter);
318 e1000_validate_option(&tx_ring->count, &opt, adapter); 347 E1000_ROUNDUP(tx_ring->count, REQ_TX_DESCRIPTOR_MULTIPLE);
319 E1000_ROUNDUP(tx_ring->count,
320 REQ_TX_DESCRIPTOR_MULTIPLE);
321 } else {
322 tx_ring->count = opt.def;
323 }
324 for (i = 0; i < adapter->num_tx_queues; i++) 348 for (i = 0; i < adapter->num_tx_queues; i++)
325 tx_ring[i].count = tx_ring->count; 349 tx_ring[i].count = tx_ring->count;
326 } 350 }
@@ -339,14 +363,9 @@ e1000_check_options(struct e1000_adapter *adapter)
339 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD : 363 opt.arg.r.max = mac_type < e1000_82544 ? E1000_MAX_RXD :
340 E1000_MAX_82544_RXD; 364 E1000_MAX_82544_RXD;
341 365
342 if (num_RxDescriptors > bd) { 366 rx_ring->count = RxDescriptors[bd];
343 rx_ring->count = RxDescriptors[bd]; 367 e1000_validate_option(&rx_ring->count, &opt, adapter);
344 e1000_validate_option(&rx_ring->count, &opt, adapter); 368 E1000_ROUNDUP(rx_ring->count, REQ_RX_DESCRIPTOR_MULTIPLE);
345 E1000_ROUNDUP(rx_ring->count,
346 REQ_RX_DESCRIPTOR_MULTIPLE);
347 } else {
348 rx_ring->count = opt.def;
349 }
350 for (i = 0; i < adapter->num_rx_queues; i++) 369 for (i = 0; i < adapter->num_rx_queues; i++)
351 rx_ring[i].count = rx_ring->count; 370 rx_ring[i].count = rx_ring->count;
352 } 371 }
@@ -358,13 +377,9 @@ e1000_check_options(struct e1000_adapter *adapter)
358 .def = OPTION_ENABLED 377 .def = OPTION_ENABLED
359 }; 378 };
360 379
361 if (num_XsumRX > bd) { 380 int rx_csum = XsumRX[bd];
362 int rx_csum = XsumRX[bd]; 381 e1000_validate_option(&rx_csum, &opt, adapter);
363 e1000_validate_option(&rx_csum, &opt, adapter); 382 adapter->rx_csum = rx_csum;
364 adapter->rx_csum = rx_csum;
365 } else {
366 adapter->rx_csum = opt.def;
367 }
368 } 383 }
369 { /* Flow Control */ 384 { /* Flow Control */
370 385
@@ -384,13 +399,9 @@ e1000_check_options(struct e1000_adapter *adapter)
384 .p = fc_list }} 399 .p = fc_list }}
385 }; 400 };
386 401
387 if (num_FlowControl > bd) { 402 int fc = FlowControl[bd];
388 int fc = FlowControl[bd]; 403 e1000_validate_option(&fc, &opt, adapter);
389 e1000_validate_option(&fc, &opt, adapter); 404 adapter->hw.fc = adapter->hw.original_fc = fc;
390 adapter->hw.fc = adapter->hw.original_fc = fc;
391 } else {
392 adapter->hw.fc = adapter->hw.original_fc = opt.def;
393 }
394 } 405 }
395 { /* Transmit Interrupt Delay */ 406 { /* Transmit Interrupt Delay */
396 struct e1000_option opt = { 407 struct e1000_option opt = {
@@ -402,13 +413,8 @@ e1000_check_options(struct e1000_adapter *adapter)
402 .max = MAX_TXDELAY }} 413 .max = MAX_TXDELAY }}
403 }; 414 };
404 415
405 if (num_TxIntDelay > bd) { 416 adapter->tx_int_delay = TxIntDelay[bd];
406 adapter->tx_int_delay = TxIntDelay[bd]; 417 e1000_validate_option(&adapter->tx_int_delay, &opt, adapter);
407 e1000_validate_option(&adapter->tx_int_delay, &opt,
408 adapter);
409 } else {
410 adapter->tx_int_delay = opt.def;
411 }
412 } 418 }
413 { /* Transmit Absolute Interrupt Delay */ 419 { /* Transmit Absolute Interrupt Delay */
414 struct e1000_option opt = { 420 struct e1000_option opt = {
@@ -420,13 +426,9 @@ e1000_check_options(struct e1000_adapter *adapter)
420 .max = MAX_TXABSDELAY }} 426 .max = MAX_TXABSDELAY }}
421 }; 427 };
422 428
423 if (num_TxAbsIntDelay > bd) { 429 adapter->tx_abs_int_delay = TxAbsIntDelay[bd];
424 adapter->tx_abs_int_delay = TxAbsIntDelay[bd]; 430 e1000_validate_option(&adapter->tx_abs_int_delay, &opt,
425 e1000_validate_option(&adapter->tx_abs_int_delay, &opt, 431 adapter);
426 adapter);
427 } else {
428 adapter->tx_abs_int_delay = opt.def;
429 }
430 } 432 }
431 { /* Receive Interrupt Delay */ 433 { /* Receive Interrupt Delay */
432 struct e1000_option opt = { 434 struct e1000_option opt = {
@@ -438,13 +440,8 @@ e1000_check_options(struct e1000_adapter *adapter)
438 .max = MAX_RXDELAY }} 440 .max = MAX_RXDELAY }}
439 }; 441 };
440 442
441 if (num_RxIntDelay > bd) { 443 adapter->rx_int_delay = RxIntDelay[bd];
442 adapter->rx_int_delay = RxIntDelay[bd]; 444 e1000_validate_option(&adapter->rx_int_delay, &opt, adapter);
443 e1000_validate_option(&adapter->rx_int_delay, &opt,
444 adapter);
445 } else {
446 adapter->rx_int_delay = opt.def;
447 }
448 } 445 }
449 { /* Receive Absolute Interrupt Delay */ 446 { /* Receive Absolute Interrupt Delay */
450 struct e1000_option opt = { 447 struct e1000_option opt = {
@@ -456,13 +453,9 @@ e1000_check_options(struct e1000_adapter *adapter)
456 .max = MAX_RXABSDELAY }} 453 .max = MAX_RXABSDELAY }}
457 }; 454 };
458 455
459 if (num_RxAbsIntDelay > bd) { 456 adapter->rx_abs_int_delay = RxAbsIntDelay[bd];
460 adapter->rx_abs_int_delay = RxAbsIntDelay[bd]; 457 e1000_validate_option(&adapter->rx_abs_int_delay, &opt,
461 e1000_validate_option(&adapter->rx_abs_int_delay, &opt, 458 adapter);
462 adapter);
463 } else {
464 adapter->rx_abs_int_delay = opt.def;
465 }
466 } 459 }
467 { /* Interrupt Throttling Rate */ 460 { /* Interrupt Throttling Rate */
468 struct e1000_option opt = { 461 struct e1000_option opt = {
@@ -474,26 +467,44 @@ e1000_check_options(struct e1000_adapter *adapter)
474 .max = MAX_ITR }} 467 .max = MAX_ITR }}
475 }; 468 };
476 469
477 if (num_InterruptThrottleRate > bd) { 470 adapter->itr = InterruptThrottleRate[bd];
478 adapter->itr = InterruptThrottleRate[bd]; 471 switch (adapter->itr) {
479 switch (adapter->itr) { 472 case 0:
480 case 0: 473 DPRINTK(PROBE, INFO, "%s turned off\n", opt.name);
481 DPRINTK(PROBE, INFO, "%s turned off\n", 474 break;
482 opt.name); 475 case 1:
483 break; 476 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
484 case 1: 477 opt.name);
485 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 478 break;
486 opt.name); 479 default:
487 break; 480 e1000_validate_option(&adapter->itr, &opt, adapter);
488 default: 481 break;
489 e1000_validate_option(&adapter->itr, &opt,
490 adapter);
491 break;
492 }
493 } else {
494 adapter->itr = opt.def;
495 } 482 }
496 } 483 }
484 { /* Smart Power Down */
485 struct e1000_option opt = {
486 .type = enable_option,
487 .name = "PHY Smart Power Down",
488 .err = "defaulting to Disabled",
489 .def = OPTION_DISABLED
490 };
491
492 int spd = SmartPowerDownEnable[bd];
493 e1000_validate_option(&spd, &opt, adapter);
494 adapter->smart_power_down = spd;
495 }
496 { /* Kumeran Lock Loss Workaround */
497 struct e1000_option opt = {
498 .type = enable_option,
499 .name = "Kumeran Lock Loss Workaround",
500 .err = "defaulting to Enabled",
501 .def = OPTION_ENABLED
502 };
503
504 int kmrn_lock_loss = KumeranLockLoss[bd];
505 e1000_validate_option(&kmrn_lock_loss, &opt, adapter);
506 adapter->hw.kmrn_lock_loss_workaround_disabled = !kmrn_lock_loss;
507 }
497 508
498 switch (adapter->hw.media_type) { 509 switch (adapter->hw.media_type) {
499 case e1000_media_type_fiber: 510 case e1000_media_type_fiber:
@@ -519,17 +530,18 @@ static void __devinit
519e1000_check_fiber_options(struct e1000_adapter *adapter) 530e1000_check_fiber_options(struct e1000_adapter *adapter)
520{ 531{
521 int bd = adapter->bd_number; 532 int bd = adapter->bd_number;
522 if (num_Speed > bd) { 533 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
534 if ((Speed[bd] != OPTION_UNSET)) {
523 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, " 535 DPRINTK(PROBE, INFO, "Speed not valid for fiber adapters, "
524 "parameter ignored\n"); 536 "parameter ignored\n");
525 } 537 }
526 538
527 if (num_Duplex > bd) { 539 if ((Duplex[bd] != OPTION_UNSET)) {
528 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, " 540 DPRINTK(PROBE, INFO, "Duplex not valid for fiber adapters, "
529 "parameter ignored\n"); 541 "parameter ignored\n");
530 } 542 }
531 543
532 if ((num_AutoNeg > bd) && (AutoNeg[bd] != 0x20)) { 544 if ((AutoNeg[bd] != OPTION_UNSET) && (AutoNeg[bd] != 0x20)) {
533 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is " 545 DPRINTK(PROBE, INFO, "AutoNeg other than 1000/Full is "
534 "not valid for fiber adapters, " 546 "not valid for fiber adapters, "
535 "parameter ignored\n"); 547 "parameter ignored\n");
@@ -548,6 +560,7 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
548{ 560{
549 int speed, dplx, an; 561 int speed, dplx, an;
550 int bd = adapter->bd_number; 562 int bd = adapter->bd_number;
563 bd = bd > E1000_MAX_NIC ? E1000_MAX_NIC : bd;
551 564
552 { /* Speed */ 565 { /* Speed */
553 struct e1000_opt_list speed_list[] = {{ 0, "" }, 566 struct e1000_opt_list speed_list[] = {{ 0, "" },
@@ -564,12 +577,8 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
564 .p = speed_list }} 577 .p = speed_list }}
565 }; 578 };
566 579
567 if (num_Speed > bd) { 580 speed = Speed[bd];
568 speed = Speed[bd]; 581 e1000_validate_option(&speed, &opt, adapter);
569 e1000_validate_option(&speed, &opt, adapter);
570 } else {
571 speed = opt.def;
572 }
573 } 582 }
574 { /* Duplex */ 583 { /* Duplex */
575 struct e1000_opt_list dplx_list[] = {{ 0, "" }, 584 struct e1000_opt_list dplx_list[] = {{ 0, "" },
@@ -591,15 +600,11 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
591 "Speed/Duplex/AutoNeg parameter ignored.\n"); 600 "Speed/Duplex/AutoNeg parameter ignored.\n");
592 return; 601 return;
593 } 602 }
594 if (num_Duplex > bd) { 603 dplx = Duplex[bd];
595 dplx = Duplex[bd]; 604 e1000_validate_option(&dplx, &opt, adapter);
596 e1000_validate_option(&dplx, &opt, adapter);
597 } else {
598 dplx = opt.def;
599 }
600 } 605 }
601 606
602 if ((num_AutoNeg > bd) && (speed != 0 || dplx != 0)) { 607 if (AutoNeg[bd] != OPTION_UNSET && (speed != 0 || dplx != 0)) {
603 DPRINTK(PROBE, INFO, 608 DPRINTK(PROBE, INFO,
604 "AutoNeg specified along with Speed or Duplex, " 609 "AutoNeg specified along with Speed or Duplex, "
605 "parameter ignored\n"); 610 "parameter ignored\n");
@@ -648,19 +653,15 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
648 .p = an_list }} 653 .p = an_list }}
649 }; 654 };
650 655
651 if (num_AutoNeg > bd) { 656 an = AutoNeg[bd];
652 an = AutoNeg[bd]; 657 e1000_validate_option(&an, &opt, adapter);
653 e1000_validate_option(&an, &opt, adapter);
654 } else {
655 an = opt.def;
656 }
657 adapter->hw.autoneg_advertised = an; 658 adapter->hw.autoneg_advertised = an;
658 } 659 }
659 660
660 switch (speed + dplx) { 661 switch (speed + dplx) {
661 case 0: 662 case 0:
662 adapter->hw.autoneg = adapter->fc_autoneg = 1; 663 adapter->hw.autoneg = adapter->fc_autoneg = 1;
663 if ((num_Speed > bd) && (speed != 0 || dplx != 0)) 664 if (Speed[bd] != OPTION_UNSET || Duplex[bd] != OPTION_UNSET)
664 DPRINTK(PROBE, INFO, 665 DPRINTK(PROBE, INFO,
665 "Speed and duplex autonegotiation enabled\n"); 666 "Speed and duplex autonegotiation enabled\n");
666 break; 667 break;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 22:03:39 -0500