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authorDavid Howells <dhowells@redhat.com>2006-12-05 09:37:56 -0500
committerDavid Howells <dhowells@warthog.cambridge.redhat.com>2006-12-05 09:37:56 -0500
commit4c1ac1b49122b805adfa4efc620592f68dccf5db (patch)
tree87557f4bc2fd4fe65b7570489c2f610c45c0adcd /drivers/net/e1000
parentc4028958b6ecad064b1a6303a6a5906d4fe48d73 (diff)
parentd916faace3efc0bf19fe9a615a1ab8fa1a24cd93 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/infiniband/core/iwcm.c drivers/net/chelsio/cxgb2.c drivers/net/wireless/bcm43xx/bcm43xx_main.c drivers/net/wireless/prism54/islpci_eth.c drivers/usb/core/hub.h drivers/usb/input/hid-core.c net/core/netpoll.c Fix up merge failures with Linus's head and fix new compilation failures. Signed-Off-By: David Howells <dhowells@redhat.com>
Diffstat (limited to 'drivers/net/e1000')
-rw-r--r--drivers/net/e1000/e1000.h17
-rw-r--r--drivers/net/e1000/e1000_ethtool.c36
-rw-r--r--drivers/net/e1000/e1000_hw.c139
-rw-r--r--drivers/net/e1000/e1000_hw.h90
-rw-r--r--drivers/net/e1000/e1000_main.c490
-rw-r--r--drivers/net/e1000/e1000_osdep.h9
-rw-r--r--drivers/net/e1000/e1000_param.c98
7 files changed, 583 insertions, 296 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 7ecce438d258..f091042b146e 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -59,6 +59,9 @@
59#include <linux/capability.h> 59#include <linux/capability.h>
60#include <linux/in.h> 60#include <linux/in.h>
61#include <linux/ip.h> 61#include <linux/ip.h>
62#ifdef NETIF_F_TSO6
63#include <linux/ipv6.h>
64#endif
62#include <linux/tcp.h> 65#include <linux/tcp.h>
63#include <linux/udp.h> 66#include <linux/udp.h>
64#include <net/pkt_sched.h> 67#include <net/pkt_sched.h>
@@ -254,6 +257,17 @@ struct e1000_adapter {
254 spinlock_t tx_queue_lock; 257 spinlock_t tx_queue_lock;
255#endif 258#endif
256 atomic_t irq_sem; 259 atomic_t irq_sem;
260 unsigned int detect_link;
261 unsigned int total_tx_bytes;
262 unsigned int total_tx_packets;
263 unsigned int total_rx_bytes;
264 unsigned int total_rx_packets;
265 /* Interrupt Throttle Rate */
266 uint32_t itr;
267 uint32_t itr_setting;
268 uint16_t tx_itr;
269 uint16_t rx_itr;
270
257 struct work_struct reset_task; 271 struct work_struct reset_task;
258 uint8_t fc_autoneg; 272 uint8_t fc_autoneg;
259 273
@@ -262,6 +276,7 @@ struct e1000_adapter {
262 276
263 /* TX */ 277 /* TX */
264 struct e1000_tx_ring *tx_ring; /* One per active queue */ 278 struct e1000_tx_ring *tx_ring; /* One per active queue */
279 unsigned int restart_queue;
265 unsigned long tx_queue_len; 280 unsigned long tx_queue_len;
266 uint32_t txd_cmd; 281 uint32_t txd_cmd;
267 uint32_t tx_int_delay; 282 uint32_t tx_int_delay;
@@ -310,8 +325,6 @@ struct e1000_adapter {
310 uint64_t gorcl_old; 325 uint64_t gorcl_old;
311 uint16_t rx_ps_bsize0; 326 uint16_t rx_ps_bsize0;
312 327
313 /* Interrupt Throttle Rate */
314 uint32_t itr;
315 328
316 /* OS defined structs */ 329 /* OS defined structs */
317 struct net_device *netdev; 330 struct net_device *netdev;
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index c564adbd669b..da459f7177c6 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -85,6 +85,7 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
85 { "tx_single_coll_ok", E1000_STAT(stats.scc) }, 85 { "tx_single_coll_ok", E1000_STAT(stats.scc) },
86 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) }, 86 { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
87 { "tx_timeout_count", E1000_STAT(tx_timeout_count) }, 87 { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
88 { "tx_restart_queue", E1000_STAT(restart_queue) },
88 { "rx_long_length_errors", E1000_STAT(stats.roc) }, 89 { "rx_long_length_errors", E1000_STAT(stats.roc) },
89 { "rx_short_length_errors", E1000_STAT(stats.ruc) }, 90 { "rx_short_length_errors", E1000_STAT(stats.ruc) },
90 { "rx_align_errors", E1000_STAT(stats.algnerrc) }, 91 { "rx_align_errors", E1000_STAT(stats.algnerrc) },
@@ -133,9 +134,7 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
133 134
134 if (hw->autoneg == 1) { 135 if (hw->autoneg == 1) {
135 ecmd->advertising |= ADVERTISED_Autoneg; 136 ecmd->advertising |= ADVERTISED_Autoneg;
136
137 /* the e1000 autoneg seems to match ethtool nicely */ 137 /* the e1000 autoneg seems to match ethtool nicely */
138
139 ecmd->advertising |= hw->autoneg_advertised; 138 ecmd->advertising |= hw->autoneg_advertised;
140 } 139 }
141 140
@@ -285,7 +284,7 @@ e1000_set_pauseparam(struct net_device *netdev,
285 e1000_reset(adapter); 284 e1000_reset(adapter);
286 } else 285 } else
287 retval = ((hw->media_type == e1000_media_type_fiber) ? 286 retval = ((hw->media_type == e1000_media_type_fiber) ?
288 e1000_setup_link(hw) : e1000_force_mac_fc(hw)); 287 e1000_setup_link(hw) : e1000_force_mac_fc(hw));
289 288
290 clear_bit(__E1000_RESETTING, &adapter->flags); 289 clear_bit(__E1000_RESETTING, &adapter->flags);
291 return retval; 290 return retval;
@@ -350,6 +349,13 @@ e1000_set_tso(struct net_device *netdev, uint32_t data)
350 else 349 else
351 netdev->features &= ~NETIF_F_TSO; 350 netdev->features &= ~NETIF_F_TSO;
352 351
352#ifdef NETIF_F_TSO6
353 if (data)
354 netdev->features |= NETIF_F_TSO6;
355 else
356 netdev->features &= ~NETIF_F_TSO6;
357#endif
358
353 DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled"); 359 DPRINTK(PROBE, INFO, "TSO is %s\n", data ? "Enabled" : "Disabled");
354 adapter->tso_force = TRUE; 360 adapter->tso_force = TRUE;
355 return 0; 361 return 0;
@@ -774,7 +780,7 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
774 /* The status register is Read Only, so a write should fail. 780 /* The status register is Read Only, so a write should fail.
775 * Some bits that get toggled are ignored. 781 * Some bits that get toggled are ignored.
776 */ 782 */
777 switch (adapter->hw.mac_type) { 783 switch (adapter->hw.mac_type) {
778 /* there are several bits on newer hardware that are r/w */ 784 /* there are several bits on newer hardware that are r/w */
779 case e1000_82571: 785 case e1000_82571:
780 case e1000_82572: 786 case e1000_82572:
@@ -802,12 +808,14 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
802 } 808 }
803 /* restore previous status */ 809 /* restore previous status */
804 E1000_WRITE_REG(&adapter->hw, STATUS, before); 810 E1000_WRITE_REG(&adapter->hw, STATUS, before);
811
805 if (adapter->hw.mac_type != e1000_ich8lan) { 812 if (adapter->hw.mac_type != e1000_ich8lan) {
806 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 813 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
807 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 814 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
808 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); 815 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
809 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); 816 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
810 } 817 }
818
811 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); 819 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
812 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); 820 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
813 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); 821 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -820,8 +828,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
820 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); 828 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
821 829
822 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); 830 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
831
823 before = (adapter->hw.mac_type == e1000_ich8lan ? 832 before = (adapter->hw.mac_type == e1000_ich8lan ?
824 0x06C3B33E : 0x06DFB3FE); 833 0x06C3B33E : 0x06DFB3FE);
825 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB); 834 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
826 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); 835 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
827 836
@@ -834,10 +843,10 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
834 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 843 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
835 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); 844 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
836 value = (adapter->hw.mac_type == e1000_ich8lan ? 845 value = (adapter->hw.mac_type == e1000_ich8lan ?
837 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES); 846 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
838 for (i = 0; i < value; i++) { 847 for (i = 0; i < value; i++) {
839 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, 848 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
840 0xFFFFFFFF); 849 0xFFFFFFFF);
841 } 850 }
842 851
843 } else { 852 } else {
@@ -883,8 +892,7 @@ e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
883} 892}
884 893
885static irqreturn_t 894static irqreturn_t
886e1000_test_intr(int irq, 895e1000_test_intr(int irq, void *data)
887 void *data)
888{ 896{
889 struct net_device *netdev = (struct net_device *) data; 897 struct net_device *netdev = (struct net_device *) data;
890 struct e1000_adapter *adapter = netdev_priv(netdev); 898 struct e1000_adapter *adapter = netdev_priv(netdev);
@@ -905,11 +913,11 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
905 913
906 /* NOTE: we don't test MSI interrupts here, yet */ 914 /* NOTE: we don't test MSI interrupts here, yet */
907 /* Hook up test interrupt handler just for this test */ 915 /* Hook up test interrupt handler just for this test */
908 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, 916 if (!request_irq(irq, &e1000_test_intr, IRQF_PROBE_SHARED, netdev->name,
909 netdev->name, netdev)) 917 netdev))
910 shared_int = FALSE; 918 shared_int = FALSE;
911 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED, 919 else if (request_irq(irq, &e1000_test_intr, IRQF_SHARED,
912 netdev->name, netdev)) { 920 netdev->name, netdev)) {
913 *data = 1; 921 *data = 1;
914 return -1; 922 return -1;
915 } 923 }
@@ -925,6 +933,7 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
925 933
926 if (adapter->hw.mac_type == e1000_ich8lan && i == 8) 934 if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
927 continue; 935 continue;
936
928 /* Interrupt to test */ 937 /* Interrupt to test */
929 mask = 1 << i; 938 mask = 1 << i;
930 939
@@ -1674,7 +1683,7 @@ e1000_diag_test(struct net_device *netdev,
1674 if (e1000_link_test(adapter, &data[4])) 1683 if (e1000_link_test(adapter, &data[4]))
1675 eth_test->flags |= ETH_TEST_FL_FAILED; 1684 eth_test->flags |= ETH_TEST_FL_FAILED;
1676 1685
1677 /* Offline tests aren't run; pass by default */ 1686 /* Online tests aren't run; pass by default */
1678 data[0] = 0; 1687 data[0] = 0;
1679 data[1] = 0; 1688 data[1] = 0;
1680 data[2] = 0; 1689 data[2] = 0;
@@ -1717,6 +1726,7 @@ static int e1000_wol_exclusion(struct e1000_adapter *adapter, struct ethtool_wol
1717 retval = 0; 1726 retval = 0;
1718 break; 1727 break;
1719 case E1000_DEV_ID_82571EB_QUAD_COPPER: 1728 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1729 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1720 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 1730 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1721 /* quad port adapters only support WoL on port A */ 1731 /* quad port adapters only support WoL on port A */
1722 if (!adapter->quad_port_a) { 1732 if (!adapter->quad_port_a) {
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 65077f39da69..3655d902b0bd 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -385,6 +385,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
385 case E1000_DEV_ID_82571EB_FIBER: 385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES: 386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER: 387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
388 hw->mac_type = e1000_82571; 389 hw->mac_type = e1000_82571;
389 break; 390 break;
390 case E1000_DEV_ID_82572EI_COPPER: 391 case E1000_DEV_ID_82572EI_COPPER:
@@ -408,6 +409,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
408 case E1000_DEV_ID_ICH8_IGP_AMT: 409 case E1000_DEV_ID_ICH8_IGP_AMT:
409 case E1000_DEV_ID_ICH8_IGP_C: 410 case E1000_DEV_ID_ICH8_IGP_C:
410 case E1000_DEV_ID_ICH8_IFE: 411 case E1000_DEV_ID_ICH8_IFE:
412 case E1000_DEV_ID_ICH8_IFE_GT:
413 case E1000_DEV_ID_ICH8_IFE_G:
411 case E1000_DEV_ID_ICH8_IGP_M: 414 case E1000_DEV_ID_ICH8_IGP_M:
412 hw->mac_type = e1000_ich8lan; 415 hw->mac_type = e1000_ich8lan;
413 break; 416 break;
@@ -2367,6 +2370,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2367 2370
2368 /* Need to reset the PHY or these changes will be ignored */ 2371 /* Need to reset the PHY or these changes will be ignored */
2369 mii_ctrl_reg |= MII_CR_RESET; 2372 mii_ctrl_reg |= MII_CR_RESET;
2373
2370 /* Disable MDI-X support for 10/100 */ 2374 /* Disable MDI-X support for 10/100 */
2371 } else if (hw->phy_type == e1000_phy_ife) { 2375 } else if (hw->phy_type == e1000_phy_ife) {
2372 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 2376 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
@@ -2379,6 +2383,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2379 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 2383 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2380 if (ret_val) 2384 if (ret_val)
2381 return ret_val; 2385 return ret_val;
2386
2382 } else { 2387 } else {
2383 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2388 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2384 * forced whenever speed or duplex are forced. 2389 * forced whenever speed or duplex are forced.
@@ -3868,7 +3873,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3868* 3873*
3869* hw - Struct containing variables accessed by shared code 3874* hw - Struct containing variables accessed by shared code
3870* 3875*
3871* Sets bit 15 of the MII Control regiser 3876* Sets bit 15 of the MII Control register
3872******************************************************************************/ 3877******************************************************************************/
3873int32_t 3878int32_t
3874e1000_phy_reset(struct e1000_hw *hw) 3879e1000_phy_reset(struct e1000_hw *hw)
@@ -3940,14 +3945,15 @@ e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3940 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3945 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3941 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3946 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3942 3947
3943 /* Write VR power-down enable */ 3948 /* Write VR power-down enable - bits 9:8 should be 10b */
3944 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3945 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data | 3950 phy_data |= (1 << 9);
3946 IGP3_VR_CTRL_MODE_SHUT); 3951 phy_data &= ~(1 << 8);
3952 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3947 3953
3948 /* Read it back and test */ 3954 /* Read it back and test */
3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); 3955 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3950 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry) 3956 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3951 break; 3957 break;
3952 3958
3953 /* Issue PHY reset and repeat at most one more time */ 3959 /* Issue PHY reset and repeat at most one more time */
@@ -4549,7 +4555,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4549 case e1000_ich8lan: 4555 case e1000_ich8lan:
4550 { 4556 {
4551 int32_t i = 0; 4557 int32_t i = 0;
4552 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); 4558 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4553 4559
4554 eeprom->type = e1000_eeprom_ich8; 4560 eeprom->type = e1000_eeprom_ich8;
4555 eeprom->use_eerd = FALSE; 4561 eeprom->use_eerd = FALSE;
@@ -4565,12 +4571,14 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4565 } 4571 }
4566 } 4572 }
4567 4573
4568 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) * 4574 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4569 ICH8_FLASH_SECTOR_SIZE; 4575 ICH_FLASH_SECTOR_SIZE;
4576
4577 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4578 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4579
4580 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4570 4581
4571 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4572 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4573 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4574 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4582 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4575 4583
4576 break; 4584 break;
@@ -5620,8 +5628,8 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5620 * signature is valid. We want to do this after the write 5628 * signature is valid. We want to do this after the write
5621 * has completed so that we don't mark the segment valid 5629 * has completed so that we don't mark the segment valid
5622 * while the write is still in progress */ 5630 * while the write is still in progress */
5623 if (i == E1000_ICH8_NVM_SIG_WORD) 5631 if (i == E1000_ICH_NVM_SIG_WORD)
5624 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; 5632 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5625 5633
5626 error = e1000_verify_write_ich8_byte(hw, 5634 error = e1000_verify_write_ich8_byte(hw,
5627 (i << 1) + new_bank_offset + 1, high_byte); 5635 (i << 1) + new_bank_offset + 1, high_byte);
@@ -5643,18 +5651,18 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5643 * erase as well since these bits are 11 to start with 5651 * erase as well since these bits are 11 to start with
5644 * and we need to change bit 14 to 0b */ 5652 * and we need to change bit 14 to 0b */
5645 e1000_read_ich8_byte(hw, 5653 e1000_read_ich8_byte(hw,
5646 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5654 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5647 &high_byte); 5655 &high_byte);
5648 high_byte &= 0xBF; 5656 high_byte &= 0xBF;
5649 error = e1000_verify_write_ich8_byte(hw, 5657 error = e1000_verify_write_ich8_byte(hw,
5650 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); 5658 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5651 /* And invalidate the previously valid segment by setting 5659 /* And invalidate the previously valid segment by setting
5652 * its signature word (0x13) high_byte to 0b. This can be 5660 * its signature word (0x13) high_byte to 0b. This can be
5653 * done without an erase because flash erase sets all bits 5661 * done without an erase because flash erase sets all bits
5654 * to 1's. We can write 1's to 0's without an erase */ 5662 * to 1's. We can write 1's to 0's without an erase */
5655 if (error == E1000_SUCCESS) { 5663 if (error == E1000_SUCCESS) {
5656 error = e1000_verify_write_ich8_byte(hw, 5664 error = e1000_verify_write_ich8_byte(hw,
5657 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); 5665 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5658 } 5666 }
5659 5667
5660 /* Clear the now not used entry in the cache */ 5668 /* Clear the now not used entry in the cache */
@@ -5841,6 +5849,7 @@ e1000_mta_set(struct e1000_hw *hw,
5841 hash_reg = (hash_value >> 5) & 0x7F; 5849 hash_reg = (hash_value >> 5) & 0x7F;
5842 if (hw->mac_type == e1000_ich8lan) 5850 if (hw->mac_type == e1000_ich8lan)
5843 hash_reg &= 0x1F; 5851 hash_reg &= 0x1F;
5852
5844 hash_bit = hash_value & 0x1F; 5853 hash_bit = hash_value & 0x1F;
5845 5854
5846 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5855 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -6026,6 +6035,7 @@ e1000_id_led_init(struct e1000_hw * hw)
6026 else 6035 else
6027 eeprom_data = ID_LED_DEFAULT; 6036 eeprom_data = ID_LED_DEFAULT;
6028 } 6037 }
6038
6029 for (i = 0; i < 4; i++) { 6039 for (i = 0; i < 4; i++) {
6030 temp = (eeprom_data >> (i << 2)) & led_mask; 6040 temp = (eeprom_data >> (i << 2)) & led_mask;
6031 switch (temp) { 6041 switch (temp) {
@@ -8486,7 +8496,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8486 8496
8487 DEBUGFUNC("e1000_ich8_cycle_init"); 8497 DEBUGFUNC("e1000_ich8_cycle_init");
8488 8498
8489 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8499 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8490 8500
8491 /* May be check the Flash Des Valid bit in Hw status */ 8501 /* May be check the Flash Des Valid bit in Hw status */
8492 if (hsfsts.hsf_status.fldesvalid == 0) { 8502 if (hsfsts.hsf_status.fldesvalid == 0) {
@@ -8499,7 +8509,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8499 hsfsts.hsf_status.flcerr = 1; 8509 hsfsts.hsf_status.flcerr = 1;
8500 hsfsts.hsf_status.dael = 1; 8510 hsfsts.hsf_status.dael = 1;
8501 8511
8502 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8512 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8503 8513
8504 /* Either we should have a hardware SPI cycle in progress bit to check 8514 /* Either we should have a hardware SPI cycle in progress bit to check
8505 * against, in order to start a new cycle or FDONE bit should be changed 8515 * against, in order to start a new cycle or FDONE bit should be changed
@@ -8514,13 +8524,13 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8514 /* There is no cycle running at present, so we can start a cycle */ 8524 /* There is no cycle running at present, so we can start a cycle */
8515 /* Begin by setting Flash Cycle Done. */ 8525 /* Begin by setting Flash Cycle Done. */
8516 hsfsts.hsf_status.flcdone = 1; 8526 hsfsts.hsf_status.flcdone = 1;
8517 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8527 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8518 error = E1000_SUCCESS; 8528 error = E1000_SUCCESS;
8519 } else { 8529 } else {
8520 /* otherwise poll for sometime so the current cycle has a chance 8530 /* otherwise poll for sometime so the current cycle has a chance
8521 * to end before giving up. */ 8531 * to end before giving up. */
8522 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) { 8532 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8523 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8533 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8524 if (hsfsts.hsf_status.flcinprog == 0) { 8534 if (hsfsts.hsf_status.flcinprog == 0) {
8525 error = E1000_SUCCESS; 8535 error = E1000_SUCCESS;
8526 break; 8536 break;
@@ -8531,7 +8541,7 @@ e1000_ich8_cycle_init(struct e1000_hw *hw)
8531 /* Successful in waiting for previous cycle to timeout, 8541 /* Successful in waiting for previous cycle to timeout,
8532 * now set the Flash Cycle Done. */ 8542 * now set the Flash Cycle Done. */
8533 hsfsts.hsf_status.flcdone = 1; 8543 hsfsts.hsf_status.flcdone = 1;
8534 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval); 8544 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8535 } else { 8545 } else {
8536 DEBUGOUT("Flash controller busy, cannot get access"); 8546 DEBUGOUT("Flash controller busy, cannot get access");
8537 } 8547 }
@@ -8553,13 +8563,13 @@ e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8553 uint32_t i = 0; 8563 uint32_t i = 0;
8554 8564
8555 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 8565 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8556 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8566 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8557 hsflctl.hsf_ctrl.flcgo = 1; 8567 hsflctl.hsf_ctrl.flcgo = 1;
8558 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8568 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8559 8569
8560 /* wait till FDONE bit is set to 1 */ 8570 /* wait till FDONE bit is set to 1 */
8561 do { 8571 do {
8562 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8572 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8563 if (hsfsts.hsf_status.flcdone == 1) 8573 if (hsfsts.hsf_status.flcdone == 1)
8564 break; 8574 break;
8565 udelay(1); 8575 udelay(1);
@@ -8593,10 +8603,10 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8593 DEBUGFUNC("e1000_read_ich8_data"); 8603 DEBUGFUNC("e1000_read_ich8_data");
8594 8604
8595 if (size < 1 || size > 2 || data == 0x0 || 8605 if (size < 1 || size > 2 || data == 0x0 ||
8596 index > ICH8_FLASH_LINEAR_ADDR_MASK) 8606 index > ICH_FLASH_LINEAR_ADDR_MASK)
8597 return error; 8607 return error;
8598 8608
8599 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + 8609 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8600 hw->flash_base_addr; 8610 hw->flash_base_addr;
8601 8611
8602 do { 8612 do {
@@ -8606,25 +8616,25 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8606 if (error != E1000_SUCCESS) 8616 if (error != E1000_SUCCESS)
8607 break; 8617 break;
8608 8618
8609 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8619 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8610 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8620 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8611 hsflctl.hsf_ctrl.fldbcount = size - 1; 8621 hsflctl.hsf_ctrl.fldbcount = size - 1;
8612 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ; 8622 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8613 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8623 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8614 8624
8615 /* Write the last 24 bits of index into Flash Linear address field in 8625 /* Write the last 24 bits of index into Flash Linear address field in
8616 * Flash Address */ 8626 * Flash Address */
8617 /* TODO: TBD maybe check the index against the size of flash */ 8627 /* TODO: TBD maybe check the index against the size of flash */
8618 8628
8619 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8629 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8620 8630
8621 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); 8631 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8622 8632
8623 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole 8633 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8624 * sequence a few more times, else read in (shift in) the Flash Data0, 8634 * sequence a few more times, else read in (shift in) the Flash Data0,
8625 * the order is least significant byte first msb to lsb */ 8635 * the order is least significant byte first msb to lsb */
8626 if (error == E1000_SUCCESS) { 8636 if (error == E1000_SUCCESS) {
8627 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0); 8637 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8628 if (size == 1) { 8638 if (size == 1) {
8629 *data = (uint8_t)(flash_data & 0x000000FF); 8639 *data = (uint8_t)(flash_data & 0x000000FF);
8630 } else if (size == 2) { 8640 } else if (size == 2) {
@@ -8634,9 +8644,9 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8634 } else { 8644 } else {
8635 /* If we've gotten here, then things are probably completely hosed, 8645 /* If we've gotten here, then things are probably completely hosed,
8636 * but if the error condition is detected, it won't hurt to give 8646 * but if the error condition is detected, it won't hurt to give
8637 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. 8647 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8638 */ 8648 */
8639 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8649 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8640 if (hsfsts.hsf_status.flcerr == 1) { 8650 if (hsfsts.hsf_status.flcerr == 1) {
8641 /* Repeat for some time before giving up. */ 8651 /* Repeat for some time before giving up. */
8642 continue; 8652 continue;
@@ -8645,7 +8655,7 @@ e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8645 break; 8655 break;
8646 } 8656 }
8647 } 8657 }
8648 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); 8658 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8649 8659
8650 return error; 8660 return error;
8651} 8661}
@@ -8672,10 +8682,10 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8672 DEBUGFUNC("e1000_write_ich8_data"); 8682 DEBUGFUNC("e1000_write_ich8_data");
8673 8683
8674 if (size < 1 || size > 2 || data > size * 0xff || 8684 if (size < 1 || size > 2 || data > size * 0xff ||
8675 index > ICH8_FLASH_LINEAR_ADDR_MASK) 8685 index > ICH_FLASH_LINEAR_ADDR_MASK)
8676 return error; 8686 return error;
8677 8687
8678 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) + 8688 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8679 hw->flash_base_addr; 8689 hw->flash_base_addr;
8680 8690
8681 do { 8691 do {
@@ -8685,34 +8695,34 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8685 if (error != E1000_SUCCESS) 8695 if (error != E1000_SUCCESS)
8686 break; 8696 break;
8687 8697
8688 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8698 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8689 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 8699 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8690 hsflctl.hsf_ctrl.fldbcount = size -1; 8700 hsflctl.hsf_ctrl.fldbcount = size -1;
8691 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE; 8701 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8692 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8702 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8693 8703
8694 /* Write the last 24 bits of index into Flash Linear address field in 8704 /* Write the last 24 bits of index into Flash Linear address field in
8695 * Flash Address */ 8705 * Flash Address */
8696 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8706 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8697 8707
8698 if (size == 1) 8708 if (size == 1)
8699 flash_data = (uint32_t)data & 0x00FF; 8709 flash_data = (uint32_t)data & 0x00FF;
8700 else 8710 else
8701 flash_data = (uint32_t)data; 8711 flash_data = (uint32_t)data;
8702 8712
8703 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data); 8713 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8704 8714
8705 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole 8715 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8706 * sequence a few more times else done */ 8716 * sequence a few more times else done */
8707 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT); 8717 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8708 if (error == E1000_SUCCESS) { 8718 if (error == E1000_SUCCESS) {
8709 break; 8719 break;
8710 } else { 8720 } else {
8711 /* If we're here, then things are most likely completely hosed, 8721 /* If we're here, then things are most likely completely hosed,
8712 * but if the error condition is detected, it won't hurt to give 8722 * but if the error condition is detected, it won't hurt to give
8713 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times. 8723 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8714 */ 8724 */
8715 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8725 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8716 if (hsfsts.hsf_status.flcerr == 1) { 8726 if (hsfsts.hsf_status.flcerr == 1) {
8717 /* Repeat for some time before giving up. */ 8727 /* Repeat for some time before giving up. */
8718 continue; 8728 continue;
@@ -8721,7 +8731,7 @@ e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8721 break; 8731 break;
8722 } 8732 }
8723 } 8733 }
8724 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT); 8734 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8725 8735
8726 return error; 8736 return error;
8727} 8737}
@@ -8840,7 +8850,7 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8840 int32_t j = 0; 8850 int32_t j = 0;
8841 int32_t error_flag = 0; 8851 int32_t error_flag = 0;
8842 8852
8843 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8853 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8844 8854
8845 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8855 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8846 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8856 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
@@ -8853,19 +8863,14 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8853 * 11: The Hw sector size is 64K bytes */ 8863 * 11: The Hw sector size is 64K bytes */
8854 if (hsfsts.hsf_status.berasesz == 0x0) { 8864 if (hsfsts.hsf_status.berasesz == 0x0) {
8855 /* Hw sector size 256 */ 8865 /* Hw sector size 256 */
8856 sub_sector_size = ICH8_FLASH_SEG_SIZE_256; 8866 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8857 bank_size = ICH8_FLASH_SECTOR_SIZE; 8867 bank_size = ICH_FLASH_SECTOR_SIZE;
8858 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; 8868 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8859 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8869 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8860 bank_size = ICH8_FLASH_SEG_SIZE_4K; 8870 bank_size = ICH_FLASH_SEG_SIZE_4K;
8861 iteration = 1;
8862 } else if (hw->mac_type != e1000_ich8lan &&
8863 hsfsts.hsf_status.berasesz == 0x2) {
8864 /* 8K erase size invalid for ICH8 - added in for ICH9 */
8865 bank_size = ICH9_FLASH_SEG_SIZE_8K;
8866 iteration = 1; 8871 iteration = 1;
8867 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8872 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8868 bank_size = ICH8_FLASH_SEG_SIZE_64K; 8873 bank_size = ICH_FLASH_SEG_SIZE_64K;
8869 iteration = 1; 8874 iteration = 1;
8870 } else { 8875 } else {
8871 return error; 8876 return error;
@@ -8883,9 +8888,9 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8883 8888
8884 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash 8889 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8885 * Control */ 8890 * Control */
8886 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL); 8891 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8887 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE; 8892 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8888 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval); 8893 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8889 8894
8890 /* Write the last 24 bits of an index within the block into Flash 8895 /* Write the last 24 bits of an index within the block into Flash
8891 * Linear address field in Flash Address. This probably needs to 8896 * Linear address field in Flash Address. This probably needs to
@@ -8893,17 +8898,17 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8893 * the software bank size (4, 8 or 64 KBytes) */ 8898 * the software bank size (4, 8 or 64 KBytes) */
8894 flash_linear_address = bank * bank_size + j * sub_sector_size; 8899 flash_linear_address = bank * bank_size + j * sub_sector_size;
8895 flash_linear_address += hw->flash_base_addr; 8900 flash_linear_address += hw->flash_base_addr;
8896 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK; 8901 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8897 8902
8898 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8903 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8899 8904
8900 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_ERASE_TIMEOUT); 8905 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8901 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8906 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8902 * sequence a few more times else Done */ 8907 * sequence a few more times else Done */
8903 if (error == E1000_SUCCESS) { 8908 if (error == E1000_SUCCESS) {
8904 break; 8909 break;
8905 } else { 8910 } else {
8906 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS); 8911 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8907 if (hsfsts.hsf_status.flcerr == 1) { 8912 if (hsfsts.hsf_status.flcerr == 1) {
8908 /* repeat for some time before giving up */ 8913 /* repeat for some time before giving up */
8909 continue; 8914 continue;
@@ -8912,7 +8917,7 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8912 break; 8917 break;
8913 } 8918 }
8914 } 8919 }
8915 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 8920 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8916 if (error_flag == 1) 8921 if (error_flag == 1)
8917 break; 8922 break;
8918 } 8923 }
@@ -9013,5 +9018,3 @@ e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9013 return E1000_SUCCESS; 9018 return E1000_SUCCESS;
9014} 9019}
9015 9020
9016
9017
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 449a60303e07..3321fb13bfa9 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -128,11 +128,13 @@ typedef enum {
128/* PCI bus widths */ 128/* PCI bus widths */
129typedef enum { 129typedef enum {
130 e1000_bus_width_unknown = 0, 130 e1000_bus_width_unknown = 0,
131 /* These PCIe values should literally match the possible return values
132 * from config space */
133 e1000_bus_width_pciex_1 = 1,
134 e1000_bus_width_pciex_2 = 2,
135 e1000_bus_width_pciex_4 = 4,
131 e1000_bus_width_32, 136 e1000_bus_width_32,
132 e1000_bus_width_64, 137 e1000_bus_width_64,
133 e1000_bus_width_pciex_1,
134 e1000_bus_width_pciex_2,
135 e1000_bus_width_pciex_4,
136 e1000_bus_width_reserved 138 e1000_bus_width_reserved
137} e1000_bus_width; 139} e1000_bus_width;
138 140
@@ -326,6 +328,7 @@ int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
326int32_t e1000_phy_reset(struct e1000_hw *hw); 328int32_t e1000_phy_reset(struct e1000_hw *hw);
327int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 329int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
328int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 330int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
331
329void e1000_phy_powerdown_workaround(struct e1000_hw *hw); 332void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
330 333
331/* EEPROM Functions */ 334/* EEPROM Functions */
@@ -390,7 +393,6 @@ int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
390 uint16_t length); 393 uint16_t length);
391boolean_t e1000_check_mng_mode(struct e1000_hw *hw); 394boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
392boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 395boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
393
394int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 396int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
395int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 397int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
396int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 398int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
@@ -473,6 +475,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
473#define E1000_DEV_ID_82571EB_FIBER 0x105F 475#define E1000_DEV_ID_82571EB_FIBER 0x105F
474#define E1000_DEV_ID_82571EB_SERDES 0x1060 476#define E1000_DEV_ID_82571EB_SERDES 0x1060
475#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 477#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
478#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
476#define E1000_DEV_ID_82572EI_COPPER 0x107D 479#define E1000_DEV_ID_82572EI_COPPER 0x107D
477#define E1000_DEV_ID_82572EI_FIBER 0x107E 480#define E1000_DEV_ID_82572EI_FIBER 0x107E
478#define E1000_DEV_ID_82572EI_SERDES 0x107F 481#define E1000_DEV_ID_82572EI_SERDES 0x107F
@@ -490,6 +493,8 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
490#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 493#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
491#define E1000_DEV_ID_ICH8_IGP_C 0x104B 494#define E1000_DEV_ID_ICH8_IGP_C 0x104B
492#define E1000_DEV_ID_ICH8_IFE 0x104C 495#define E1000_DEV_ID_ICH8_IFE 0x104C
496#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
497#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
493#define E1000_DEV_ID_ICH8_IGP_M 0x104D 498#define E1000_DEV_ID_ICH8_IGP_M 0x104D
494 499
495 500
@@ -576,6 +581,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
576 * E1000_RAR_ENTRIES - 1 multicast addresses. 581 * E1000_RAR_ENTRIES - 1 multicast addresses.
577 */ 582 */
578#define E1000_RAR_ENTRIES 15 583#define E1000_RAR_ENTRIES 15
584
579#define E1000_RAR_ENTRIES_ICH8LAN 6 585#define E1000_RAR_ENTRIES_ICH8LAN 6
580 586
581#define MIN_NUMBER_OF_DESCRIPTORS 8 587#define MIN_NUMBER_OF_DESCRIPTORS 8
@@ -1335,9 +1341,9 @@ struct e1000_hw_stats {
1335 uint64_t gotch; 1341 uint64_t gotch;
1336 uint64_t rnbc; 1342 uint64_t rnbc;
1337 uint64_t ruc; 1343 uint64_t ruc;
1344 uint64_t rfc;
1338 uint64_t roc; 1345 uint64_t roc;
1339 uint64_t rlerrc; 1346 uint64_t rlerrc;
1340 uint64_t rfc;
1341 uint64_t rjc; 1347 uint64_t rjc;
1342 uint64_t mgprc; 1348 uint64_t mgprc;
1343 uint64_t mgpdc; 1349 uint64_t mgpdc;
@@ -1577,8 +1583,8 @@ struct e1000_hw {
1577#define E1000_HICR_FW_RESET 0xC0 1583#define E1000_HICR_FW_RESET 0xC0
1578 1584
1579#define E1000_SHADOW_RAM_WORDS 2048 1585#define E1000_SHADOW_RAM_WORDS 2048
1580#define E1000_ICH8_NVM_SIG_WORD 0x13 1586#define E1000_ICH_NVM_SIG_WORD 0x13
1581#define E1000_ICH8_NVM_SIG_MASK 0xC0 1587#define E1000_ICH_NVM_SIG_MASK 0xC0
1582 1588
1583/* EEPROM Read */ 1589/* EEPROM Read */
1584#define E1000_EERD_START 0x00000001 /* Start Read */ 1590#define E1000_EERD_START 0x00000001 /* Start Read */
@@ -3172,6 +3178,7 @@ struct e1000_host_command_info {
3172#define IGP3_VR_CTRL \ 3178#define IGP3_VR_CTRL \
3173 PHY_REG(776, 18) /* Voltage regulator control register */ 3179 PHY_REG(776, 18) /* Voltage regulator control register */
3174#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 3180#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3181#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
3175 3182
3176#define IGP3_CAPABILITY \ 3183#define IGP3_CAPABILITY \
3177 PHY_REG(776, 19) /* IGP3 Capability Register */ 3184 PHY_REG(776, 19) /* IGP3 Capability Register */
@@ -3256,41 +3263,40 @@ struct e1000_host_command_info {
3256#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3263#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3257#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3264#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3258 3265
3259#define ICH8_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 3266#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3260#define ICH8_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 3267#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3261#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 3268#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3262#define ICH8_FLASH_SEG_SIZE_256 256 3269#define ICH_FLASH_SEG_SIZE_256 256
3263#define ICH8_FLASH_SEG_SIZE_4K 4096 3270#define ICH_FLASH_SEG_SIZE_4K 4096
3264#define ICH9_FLASH_SEG_SIZE_8K 8192 3271#define ICH_FLASH_SEG_SIZE_64K 65536
3265#define ICH8_FLASH_SEG_SIZE_64K 65536 3272
3266 3273#define ICH_CYCLE_READ 0x0
3267#define ICH8_CYCLE_READ 0x0 3274#define ICH_CYCLE_RESERVED 0x1
3268#define ICH8_CYCLE_RESERVED 0x1 3275#define ICH_CYCLE_WRITE 0x2
3269#define ICH8_CYCLE_WRITE 0x2 3276#define ICH_CYCLE_ERASE 0x3
3270#define ICH8_CYCLE_ERASE 0x3 3277
3271 3278#define ICH_FLASH_GFPREG 0x0000
3272#define ICH8_FLASH_GFPREG 0x0000 3279#define ICH_FLASH_HSFSTS 0x0004
3273#define ICH8_FLASH_HSFSTS 0x0004 3280#define ICH_FLASH_HSFCTL 0x0006
3274#define ICH8_FLASH_HSFCTL 0x0006 3281#define ICH_FLASH_FADDR 0x0008
3275#define ICH8_FLASH_FADDR 0x0008 3282#define ICH_FLASH_FDATA0 0x0010
3276#define ICH8_FLASH_FDATA0 0x0010 3283#define ICH_FLASH_FRACC 0x0050
3277#define ICH8_FLASH_FRACC 0x0050 3284#define ICH_FLASH_FREG0 0x0054
3278#define ICH8_FLASH_FREG0 0x0054 3285#define ICH_FLASH_FREG1 0x0058
3279#define ICH8_FLASH_FREG1 0x0058 3286#define ICH_FLASH_FREG2 0x005C
3280#define ICH8_FLASH_FREG2 0x005C 3287#define ICH_FLASH_FREG3 0x0060
3281#define ICH8_FLASH_FREG3 0x0060 3288#define ICH_FLASH_FPR0 0x0074
3282#define ICH8_FLASH_FPR0 0x0074 3289#define ICH_FLASH_FPR1 0x0078
3283#define ICH8_FLASH_FPR1 0x0078 3290#define ICH_FLASH_SSFSTS 0x0090
3284#define ICH8_FLASH_SSFSTS 0x0090 3291#define ICH_FLASH_SSFCTL 0x0092
3285#define ICH8_FLASH_SSFCTL 0x0092 3292#define ICH_FLASH_PREOP 0x0094
3286#define ICH8_FLASH_PREOP 0x0094 3293#define ICH_FLASH_OPTYPE 0x0096
3287#define ICH8_FLASH_OPTYPE 0x0096 3294#define ICH_FLASH_OPMENU 0x0098
3288#define ICH8_FLASH_OPMENU 0x0098 3295
3289 3296#define ICH_FLASH_REG_MAPSIZE 0x00A0
3290#define ICH8_FLASH_REG_MAPSIZE 0x00A0 3297#define ICH_FLASH_SECTOR_SIZE 4096
3291#define ICH8_FLASH_SECTOR_SIZE 4096 3298#define ICH_GFPREG_BASE_MASK 0x1FFF
3292#define ICH8_GFPREG_BASE_MASK 0x1FFF 3299#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3293#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3294 3300
3295/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 3301/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3296/* Offset 04h HSFSTS */ 3302/* Offset 04h HSFSTS */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 03294400bc90..73f3a85fd238 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -27,6 +27,7 @@
27*******************************************************************************/ 27*******************************************************************************/
28 28
29#include "e1000.h" 29#include "e1000.h"
30#include <net/ip6_checksum.h>
30 31
31char e1000_driver_name[] = "e1000"; 32char e1000_driver_name[] = "e1000";
32static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
@@ -35,7 +36,7 @@ static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
35#else 36#else
36#define DRIVERNAPI "-NAPI" 37#define DRIVERNAPI "-NAPI"
37#endif 38#endif
38#define DRV_VERSION "7.2.9-k4"DRIVERNAPI 39#define DRV_VERSION "7.3.15-k2"DRIVERNAPI
39char e1000_driver_version[] = DRV_VERSION; 40char e1000_driver_version[] = DRV_VERSION;
40static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
41 42
@@ -103,6 +104,9 @@ static struct pci_device_id e1000_pci_tbl[] = {
103 INTEL_E1000_ETHERNET_DEVICE(0x10B9), 104 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BA), 105 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
105 INTEL_E1000_ETHERNET_DEVICE(0x10BB), 106 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
107 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
108 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
109 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
106 /* required last entry */ 110 /* required last entry */
107 {0,} 111 {0,}
108}; 112};
@@ -154,6 +158,9 @@ static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
154static int e1000_change_mtu(struct net_device *netdev, int new_mtu); 158static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
155static int e1000_set_mac(struct net_device *netdev, void *p); 159static int e1000_set_mac(struct net_device *netdev, void *p);
156static irqreturn_t e1000_intr(int irq, void *data); 160static irqreturn_t e1000_intr(int irq, void *data);
161#ifdef CONFIG_PCI_MSI
162static irqreturn_t e1000_intr_msi(int irq, void *data);
163#endif
157static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter, 164static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
158 struct e1000_tx_ring *tx_ring); 165 struct e1000_tx_ring *tx_ring);
159#ifdef CONFIG_E1000_NAPI 166#ifdef CONFIG_E1000_NAPI
@@ -285,7 +292,7 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
285 292
286 flags = IRQF_SHARED; 293 flags = IRQF_SHARED;
287#ifdef CONFIG_PCI_MSI 294#ifdef CONFIG_PCI_MSI
288 if (adapter->hw.mac_type > e1000_82547_rev_2) { 295 if (adapter->hw.mac_type >= e1000_82571) {
289 adapter->have_msi = TRUE; 296 adapter->have_msi = TRUE;
290 if ((err = pci_enable_msi(adapter->pdev))) { 297 if ((err = pci_enable_msi(adapter->pdev))) {
291 DPRINTK(PROBE, ERR, 298 DPRINTK(PROBE, ERR,
@@ -293,8 +300,14 @@ static int e1000_request_irq(struct e1000_adapter *adapter)
293 adapter->have_msi = FALSE; 300 adapter->have_msi = FALSE;
294 } 301 }
295 } 302 }
296 if (adapter->have_msi) 303 if (adapter->have_msi) {
297 flags &= ~IRQF_SHARED; 304 flags &= ~IRQF_SHARED;
305 err = request_irq(adapter->pdev->irq, &e1000_intr_msi, flags,
306 netdev->name, netdev);
307 if (err)
308 DPRINTK(PROBE, ERR,
309 "Unable to allocate interrupt Error: %d\n", err);
310 } else
298#endif 311#endif
299 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags, 312 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
300 netdev->name, netdev))) 313 netdev->name, netdev)))
@@ -375,7 +388,7 @@ e1000_update_mng_vlan(struct e1000_adapter *adapter)
375 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 388 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
376 * For ASF and Pass Through versions of f/w this means that the 389 * For ASF and Pass Through versions of f/w this means that the
377 * driver is no longer loaded. For AMT version (only with 82573) i 390 * driver is no longer loaded. For AMT version (only with 82573) i
378 * of the f/w this means that the netowrk i/f is closed. 391 * of the f/w this means that the network i/f is closed.
379 * 392 *
380 **/ 393 **/
381 394
@@ -416,7 +429,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
416 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 429 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
417 * For ASF and Pass Through versions of f/w this means that 430 * For ASF and Pass Through versions of f/w this means that
418 * the driver is loaded. For AMT version (only with 82573) 431 * the driver is loaded. For AMT version (only with 82573)
419 * of the f/w this means that the netowrk i/f is open. 432 * of the f/w this means that the network i/f is open.
420 * 433 *
421 **/ 434 **/
422 435
@@ -426,6 +439,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
426 uint32_t ctrl_ext; 439 uint32_t ctrl_ext;
427 uint32_t swsm; 440 uint32_t swsm;
428 uint32_t extcnf; 441 uint32_t extcnf;
442
429 /* Let firmware know the driver has taken over */ 443 /* Let firmware know the driver has taken over */
430 switch (adapter->hw.mac_type) { 444 switch (adapter->hw.mac_type) {
431 case e1000_82571: 445 case e1000_82571:
@@ -601,9 +615,6 @@ void
601e1000_reset(struct e1000_adapter *adapter) 615e1000_reset(struct e1000_adapter *adapter)
602{ 616{
603 uint32_t pba, manc; 617 uint32_t pba, manc;
604#ifdef DISABLE_MULR
605 uint32_t tctl;
606#endif
607 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF; 618 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
608 619
609 /* Repartition Pba for greater than 9k mtu 620 /* Repartition Pba for greater than 9k mtu
@@ -670,12 +681,7 @@ e1000_reset(struct e1000_adapter *adapter)
670 e1000_reset_hw(&adapter->hw); 681 e1000_reset_hw(&adapter->hw);
671 if (adapter->hw.mac_type >= e1000_82544) 682 if (adapter->hw.mac_type >= e1000_82544)
672 E1000_WRITE_REG(&adapter->hw, WUC, 0); 683 E1000_WRITE_REG(&adapter->hw, WUC, 0);
673#ifdef DISABLE_MULR
674 /* disable Multiple Reads in Transmit Control Register for debugging */
675 tctl = E1000_READ_REG(hw, TCTL);
676 E1000_WRITE_REG(hw, TCTL, tctl & ~E1000_TCTL_MULR);
677 684
678#endif
679 if (e1000_init_hw(&adapter->hw)) 685 if (e1000_init_hw(&adapter->hw))
680 DPRINTK(PROBE, ERR, "Hardware Error\n"); 686 DPRINTK(PROBE, ERR, "Hardware Error\n");
681 e1000_update_mng_vlan(adapter); 687 e1000_update_mng_vlan(adapter);
@@ -851,9 +857,9 @@ e1000_probe(struct pci_dev *pdev,
851 (adapter->hw.mac_type != e1000_82547)) 857 (adapter->hw.mac_type != e1000_82547))
852 netdev->features |= NETIF_F_TSO; 858 netdev->features |= NETIF_F_TSO;
853 859
854#ifdef NETIF_F_TSO_IPV6 860#ifdef NETIF_F_TSO6
855 if (adapter->hw.mac_type > e1000_82547_rev_2) 861 if (adapter->hw.mac_type > e1000_82547_rev_2)
856 netdev->features |= NETIF_F_TSO_IPV6; 862 netdev->features |= NETIF_F_TSO6;
857#endif 863#endif
858#endif 864#endif
859 if (pci_using_dac) 865 if (pci_using_dac)
@@ -967,6 +973,7 @@ e1000_probe(struct pci_dev *pdev,
967 break; 973 break;
968 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 974 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
969 case E1000_DEV_ID_82571EB_QUAD_COPPER: 975 case E1000_DEV_ID_82571EB_QUAD_COPPER:
976 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
970 /* if quad port adapter, disable WoL on all but port A */ 977 /* if quad port adapter, disable WoL on all but port A */
971 if (global_quad_port_a != 0) 978 if (global_quad_port_a != 0)
972 adapter->eeprom_wol = 0; 979 adapter->eeprom_wol = 0;
@@ -1278,12 +1285,10 @@ e1000_open(struct net_device *netdev)
1278 return -EBUSY; 1285 return -EBUSY;
1279 1286
1280 /* allocate transmit descriptors */ 1287 /* allocate transmit descriptors */
1281
1282 if ((err = e1000_setup_all_tx_resources(adapter))) 1288 if ((err = e1000_setup_all_tx_resources(adapter)))
1283 goto err_setup_tx; 1289 goto err_setup_tx;
1284 1290
1285 /* allocate receive descriptors */ 1291 /* allocate receive descriptors */
1286
1287 if ((err = e1000_setup_all_rx_resources(adapter))) 1292 if ((err = e1000_setup_all_rx_resources(adapter)))
1288 goto err_setup_rx; 1293 goto err_setup_rx;
1289 1294
@@ -1568,6 +1573,8 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1568 1573
1569 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { 1574 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1570 tarc = E1000_READ_REG(hw, TARC0); 1575 tarc = E1000_READ_REG(hw, TARC0);
1576 /* set the speed mode bit, we'll clear it if we're not at
1577 * gigabit link later */
1571 tarc |= (1 << 21); 1578 tarc |= (1 << 21);
1572 E1000_WRITE_REG(hw, TARC0, tarc); 1579 E1000_WRITE_REG(hw, TARC0, tarc);
1573 } else if (hw->mac_type == e1000_80003es2lan) { 1580 } else if (hw->mac_type == e1000_80003es2lan) {
@@ -1582,8 +1589,11 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1582 e1000_config_collision_dist(hw); 1589 e1000_config_collision_dist(hw);
1583 1590
1584 /* Setup Transmit Descriptor Settings for eop descriptor */ 1591 /* Setup Transmit Descriptor Settings for eop descriptor */
1585 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP | 1592 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1586 E1000_TXD_CMD_IFCS; 1593
1594 /* only set IDE if we are delaying interrupts using the timers */
1595 if (adapter->tx_int_delay)
1596 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1587 1597
1588 if (hw->mac_type < e1000_82543) 1598 if (hw->mac_type < e1000_82543)
1589 adapter->txd_cmd |= E1000_TXD_CMD_RPS; 1599 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
@@ -1820,8 +1830,11 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1820 /* Configure extra packet-split registers */ 1830 /* Configure extra packet-split registers */
1821 rfctl = E1000_READ_REG(&adapter->hw, RFCTL); 1831 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1822 rfctl |= E1000_RFCTL_EXTEN; 1832 rfctl |= E1000_RFCTL_EXTEN;
1823 /* disable IPv6 packet split support */ 1833 /* disable packet split support for IPv6 extension headers,
1824 rfctl |= E1000_RFCTL_IPV6_DIS; 1834 * because some malformed IPv6 headers can hang the RX */
1835 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1836 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1837
1825 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl); 1838 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1826 1839
1827 rctl |= E1000_RCTL_DTYP_PS; 1840 rctl |= E1000_RCTL_DTYP_PS;
@@ -1884,7 +1897,7 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1884 1897
1885 if (hw->mac_type >= e1000_82540) { 1898 if (hw->mac_type >= e1000_82540) {
1886 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); 1899 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1887 if (adapter->itr > 1) 1900 if (adapter->itr_setting != 0)
1888 E1000_WRITE_REG(hw, ITR, 1901 E1000_WRITE_REG(hw, ITR,
1889 1000000000 / (adapter->itr * 256)); 1902 1000000000 / (adapter->itr * 256));
1890 } 1903 }
@@ -1894,11 +1907,11 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1894 /* Reset delay timers after every interrupt */ 1907 /* Reset delay timers after every interrupt */
1895 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR; 1908 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1896#ifdef CONFIG_E1000_NAPI 1909#ifdef CONFIG_E1000_NAPI
1897 /* Auto-Mask interrupts upon ICR read. */ 1910 /* Auto-Mask interrupts upon ICR access */
1898 ctrl_ext |= E1000_CTRL_EXT_IAME; 1911 ctrl_ext |= E1000_CTRL_EXT_IAME;
1912 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1899#endif 1913#endif
1900 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1914 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1901 E1000_WRITE_REG(hw, IAM, ~0);
1902 E1000_WRITE_FLUSH(hw); 1915 E1000_WRITE_FLUSH(hw);
1903 } 1916 }
1904 1917
@@ -1937,6 +1950,12 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1937 E1000_WRITE_REG(hw, RXCSUM, rxcsum); 1950 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1938 } 1951 }
1939 1952
1953 /* enable early receives on 82573, only takes effect if using > 2048
1954 * byte total frame size. for example only for jumbo frames */
1955#define E1000_ERT_2048 0x100
1956 if (hw->mac_type == e1000_82573)
1957 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
1958
1940 /* Enable Receives */ 1959 /* Enable Receives */
1941 E1000_WRITE_REG(hw, RCTL, rctl); 1960 E1000_WRITE_REG(hw, RCTL, rctl);
1942} 1961}
@@ -1990,10 +2009,13 @@ e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1990 buffer_info->dma, 2009 buffer_info->dma,
1991 buffer_info->length, 2010 buffer_info->length,
1992 PCI_DMA_TODEVICE); 2011 PCI_DMA_TODEVICE);
2012 buffer_info->dma = 0;
1993 } 2013 }
1994 if (buffer_info->skb) 2014 if (buffer_info->skb) {
1995 dev_kfree_skb_any(buffer_info->skb); 2015 dev_kfree_skb_any(buffer_info->skb);
1996 memset(buffer_info, 0, sizeof(struct e1000_buffer)); 2016 buffer_info->skb = NULL;
2017 }
2018 /* buffer_info must be completely set up in the transmit path */
1997} 2019}
1998 2020
1999/** 2021/**
@@ -2417,6 +2439,7 @@ e1000_watchdog(unsigned long data)
2417 DPRINTK(LINK, INFO, 2439 DPRINTK(LINK, INFO,
2418 "Gigabit has been disabled, downgrading speed\n"); 2440 "Gigabit has been disabled, downgrading speed\n");
2419 } 2441 }
2442
2420 if (adapter->hw.mac_type == e1000_82573) { 2443 if (adapter->hw.mac_type == e1000_82573) {
2421 e1000_enable_tx_pkt_filtering(&adapter->hw); 2444 e1000_enable_tx_pkt_filtering(&adapter->hw);
2422 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) 2445 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
@@ -2461,13 +2484,12 @@ e1000_watchdog(unsigned long data)
2461 if ((adapter->hw.mac_type == e1000_82571 || 2484 if ((adapter->hw.mac_type == e1000_82571 ||
2462 adapter->hw.mac_type == e1000_82572) && 2485 adapter->hw.mac_type == e1000_82572) &&
2463 txb2b == 0) { 2486 txb2b == 0) {
2464#define SPEED_MODE_BIT (1 << 21)
2465 uint32_t tarc0; 2487 uint32_t tarc0;
2466 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 2488 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2467 tarc0 &= ~SPEED_MODE_BIT; 2489 tarc0 &= ~(1 << 21);
2468 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 2490 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2469 } 2491 }
2470 2492
2471#ifdef NETIF_F_TSO 2493#ifdef NETIF_F_TSO
2472 /* disable TSO for pcie and 10/100 speeds, to avoid 2494 /* disable TSO for pcie and 10/100 speeds, to avoid
2473 * some hardware issues */ 2495 * some hardware issues */
@@ -2479,9 +2501,15 @@ e1000_watchdog(unsigned long data)
2479 DPRINTK(PROBE,INFO, 2501 DPRINTK(PROBE,INFO,
2480 "10/100 speed: disabling TSO\n"); 2502 "10/100 speed: disabling TSO\n");
2481 netdev->features &= ~NETIF_F_TSO; 2503 netdev->features &= ~NETIF_F_TSO;
2504#ifdef NETIF_F_TSO6
2505 netdev->features &= ~NETIF_F_TSO6;
2506#endif
2482 break; 2507 break;
2483 case SPEED_1000: 2508 case SPEED_1000:
2484 netdev->features |= NETIF_F_TSO; 2509 netdev->features |= NETIF_F_TSO;
2510#ifdef NETIF_F_TSO6
2511 netdev->features |= NETIF_F_TSO6;
2512#endif
2485 break; 2513 break;
2486 default: 2514 default:
2487 /* oops */ 2515 /* oops */
@@ -2548,19 +2576,6 @@ e1000_watchdog(unsigned long data)
2548 } 2576 }
2549 } 2577 }
2550 2578
2551 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2552 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2553 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2554 * asymmetrical Tx or Rx gets ITR=8000; everyone
2555 * else is between 2000-8000. */
2556 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2557 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2558 adapter->gotcl - adapter->gorcl :
2559 adapter->gorcl - adapter->gotcl) / 10000;
2560 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2561 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2562 }
2563
2564 /* Cause software interrupt to ensure rx ring is cleaned */ 2579 /* Cause software interrupt to ensure rx ring is cleaned */
2565 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0); 2580 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2566 2581
@@ -2576,6 +2591,135 @@ e1000_watchdog(unsigned long data)
2576 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ); 2591 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2577} 2592}
2578 2593
2594enum latency_range {
2595 lowest_latency = 0,
2596 low_latency = 1,
2597 bulk_latency = 2,
2598 latency_invalid = 255
2599};
2600
2601/**
2602 * e1000_update_itr - update the dynamic ITR value based on statistics
2603 * Stores a new ITR value based on packets and byte
2604 * counts during the last interrupt. The advantage of per interrupt
2605 * computation is faster updates and more accurate ITR for the current
2606 * traffic pattern. Constants in this function were computed
2607 * based on theoretical maximum wire speed and thresholds were set based
2608 * on testing data as well as attempting to minimize response time
2609 * while increasing bulk throughput.
2610 * this functionality is controlled by the InterruptThrottleRate module
2611 * parameter (see e1000_param.c)
2612 * @adapter: pointer to adapter
2613 * @itr_setting: current adapter->itr
2614 * @packets: the number of packets during this measurement interval
2615 * @bytes: the number of bytes during this measurement interval
2616 **/
2617static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2618 uint16_t itr_setting,
2619 int packets,
2620 int bytes)
2621{
2622 unsigned int retval = itr_setting;
2623 struct e1000_hw *hw = &adapter->hw;
2624
2625 if (unlikely(hw->mac_type < e1000_82540))
2626 goto update_itr_done;
2627
2628 if (packets == 0)
2629 goto update_itr_done;
2630
2631
2632 switch (itr_setting) {
2633 case lowest_latency:
2634 if ((packets < 5) && (bytes > 512))
2635 retval = low_latency;
2636 break;
2637 case low_latency: /* 50 usec aka 20000 ints/s */
2638 if (bytes > 10000) {
2639 if ((packets < 10) ||
2640 ((bytes/packets) > 1200))
2641 retval = bulk_latency;
2642 else if ((packets > 35))
2643 retval = lowest_latency;
2644 } else if (packets <= 2 && bytes < 512)
2645 retval = lowest_latency;
2646 break;
2647 case bulk_latency: /* 250 usec aka 4000 ints/s */
2648 if (bytes > 25000) {
2649 if (packets > 35)
2650 retval = low_latency;
2651 } else {
2652 if (bytes < 6000)
2653 retval = low_latency;
2654 }
2655 break;
2656 }
2657
2658update_itr_done:
2659 return retval;
2660}
2661
2662static void e1000_set_itr(struct e1000_adapter *adapter)
2663{
2664 struct e1000_hw *hw = &adapter->hw;
2665 uint16_t current_itr;
2666 uint32_t new_itr = adapter->itr;
2667
2668 if (unlikely(hw->mac_type < e1000_82540))
2669 return;
2670
2671 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2672 if (unlikely(adapter->link_speed != SPEED_1000)) {
2673 current_itr = 0;
2674 new_itr = 4000;
2675 goto set_itr_now;
2676 }
2677
2678 adapter->tx_itr = e1000_update_itr(adapter,
2679 adapter->tx_itr,
2680 adapter->total_tx_packets,
2681 adapter->total_tx_bytes);
2682 adapter->rx_itr = e1000_update_itr(adapter,
2683 adapter->rx_itr,
2684 adapter->total_rx_packets,
2685 adapter->total_rx_bytes);
2686
2687 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2688
2689 /* conservative mode eliminates the lowest_latency setting */
2690 if (current_itr == lowest_latency && (adapter->itr_setting == 3))
2691 current_itr = low_latency;
2692
2693 switch (current_itr) {
2694 /* counts and packets in update_itr are dependent on these numbers */
2695 case lowest_latency:
2696 new_itr = 70000;
2697 break;
2698 case low_latency:
2699 new_itr = 20000; /* aka hwitr = ~200 */
2700 break;
2701 case bulk_latency:
2702 new_itr = 4000;
2703 break;
2704 default:
2705 break;
2706 }
2707
2708set_itr_now:
2709 if (new_itr != adapter->itr) {
2710 /* this attempts to bias the interrupt rate towards Bulk
2711 * by adding intermediate steps when interrupt rate is
2712 * increasing */
2713 new_itr = new_itr > adapter->itr ?
2714 min(adapter->itr + (new_itr >> 2), new_itr) :
2715 new_itr;
2716 adapter->itr = new_itr;
2717 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2718 }
2719
2720 return;
2721}
2722
2579#define E1000_TX_FLAGS_CSUM 0x00000001 2723#define E1000_TX_FLAGS_CSUM 0x00000001
2580#define E1000_TX_FLAGS_VLAN 0x00000002 2724#define E1000_TX_FLAGS_VLAN 0x00000002
2581#define E1000_TX_FLAGS_TSO 0x00000004 2725#define E1000_TX_FLAGS_TSO 0x00000004
@@ -2616,7 +2760,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2616 0); 2760 0);
2617 cmd_length = E1000_TXD_CMD_IP; 2761 cmd_length = E1000_TXD_CMD_IP;
2618 ipcse = skb->h.raw - skb->data - 1; 2762 ipcse = skb->h.raw - skb->data - 1;
2619#ifdef NETIF_F_TSO_IPV6 2763#ifdef NETIF_F_TSO6
2620 } else if (skb->protocol == htons(ETH_P_IPV6)) { 2764 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2621 skb->nh.ipv6h->payload_len = 0; 2765 skb->nh.ipv6h->payload_len = 0;
2622 skb->h.th->check = 2766 skb->h.th->check =
@@ -2652,6 +2796,7 @@ e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2652 context_desc->cmd_and_length = cpu_to_le32(cmd_length); 2796 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2653 2797
2654 buffer_info->time_stamp = jiffies; 2798 buffer_info->time_stamp = jiffies;
2799 buffer_info->next_to_watch = i;
2655 2800
2656 if (++i == tx_ring->count) i = 0; 2801 if (++i == tx_ring->count) i = 0;
2657 tx_ring->next_to_use = i; 2802 tx_ring->next_to_use = i;
@@ -2680,12 +2825,13 @@ e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2680 context_desc = E1000_CONTEXT_DESC(*tx_ring, i); 2825 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
2681 2826
2682 context_desc->upper_setup.tcp_fields.tucss = css; 2827 context_desc->upper_setup.tcp_fields.tucss = css;
2683 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum; 2828 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
2684 context_desc->upper_setup.tcp_fields.tucse = 0; 2829 context_desc->upper_setup.tcp_fields.tucse = 0;
2685 context_desc->tcp_seg_setup.data = 0; 2830 context_desc->tcp_seg_setup.data = 0;
2686 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT); 2831 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2687 2832
2688 buffer_info->time_stamp = jiffies; 2833 buffer_info->time_stamp = jiffies;
2834 buffer_info->next_to_watch = i;
2689 2835
2690 if (unlikely(++i == tx_ring->count)) i = 0; 2836 if (unlikely(++i == tx_ring->count)) i = 0;
2691 tx_ring->next_to_use = i; 2837 tx_ring->next_to_use = i;
@@ -2754,6 +2900,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2754 size, 2900 size,
2755 PCI_DMA_TODEVICE); 2901 PCI_DMA_TODEVICE);
2756 buffer_info->time_stamp = jiffies; 2902 buffer_info->time_stamp = jiffies;
2903 buffer_info->next_to_watch = i;
2757 2904
2758 len -= size; 2905 len -= size;
2759 offset += size; 2906 offset += size;
@@ -2793,6 +2940,7 @@ e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2793 size, 2940 size,
2794 PCI_DMA_TODEVICE); 2941 PCI_DMA_TODEVICE);
2795 buffer_info->time_stamp = jiffies; 2942 buffer_info->time_stamp = jiffies;
2943 buffer_info->next_to_watch = i;
2796 2944
2797 len -= size; 2945 len -= size;
2798 offset += size; 2946 offset += size;
@@ -2858,6 +3006,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2858 3006
2859 tx_ring->next_to_use = i; 3007 tx_ring->next_to_use = i;
2860 writel(i, adapter->hw.hw_addr + tx_ring->tdt); 3008 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
3009 /* we need this if more than one processor can write to our tail
3010 * at a time, it syncronizes IO on IA64/Altix systems */
3011 mmiowb();
2861} 3012}
2862 3013
2863/** 3014/**
@@ -2951,6 +3102,7 @@ static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
2951 3102
2952 /* A reprieve! */ 3103 /* A reprieve! */
2953 netif_start_queue(netdev); 3104 netif_start_queue(netdev);
3105 ++adapter->restart_queue;
2954 return 0; 3106 return 0;
2955} 3107}
2956 3108
@@ -3009,9 +3161,9 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3009 max_per_txd = min(mss << 2, max_per_txd); 3161 max_per_txd = min(mss << 2, max_per_txd);
3010 max_txd_pwr = fls(max_per_txd) - 1; 3162 max_txd_pwr = fls(max_per_txd) - 1;
3011 3163
3012 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data 3164 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3013 * points to just header, pull a few bytes of payload from 3165 * points to just header, pull a few bytes of payload from
3014 * frags into skb->data */ 3166 * frags into skb->data */
3015 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); 3167 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
3016 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) { 3168 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
3017 switch (adapter->hw.mac_type) { 3169 switch (adapter->hw.mac_type) {
@@ -3316,12 +3468,12 @@ e1000_update_stats(struct e1000_adapter *adapter)
3316 adapter->stats.roc += E1000_READ_REG(hw, ROC); 3468 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3317 3469
3318 if (adapter->hw.mac_type != e1000_ich8lan) { 3470 if (adapter->hw.mac_type != e1000_ich8lan) {
3319 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64); 3471 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3320 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127); 3472 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3321 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255); 3473 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3322 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511); 3474 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3323 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023); 3475 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3324 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522); 3476 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3325 } 3477 }
3326 3478
3327 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS); 3479 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
@@ -3352,12 +3504,12 @@ e1000_update_stats(struct e1000_adapter *adapter)
3352 adapter->stats.tpr += E1000_READ_REG(hw, TPR); 3504 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3353 3505
3354 if (adapter->hw.mac_type != e1000_ich8lan) { 3506 if (adapter->hw.mac_type != e1000_ich8lan) {
3355 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64); 3507 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3356 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127); 3508 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3357 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255); 3509 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3358 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511); 3510 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3359 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023); 3511 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3360 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522); 3512 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3361 } 3513 }
3362 3514
3363 adapter->stats.mptc += E1000_READ_REG(hw, MPTC); 3515 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
@@ -3383,18 +3535,17 @@ e1000_update_stats(struct e1000_adapter *adapter)
3383 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); 3535 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3384 3536
3385 if (adapter->hw.mac_type != e1000_ich8lan) { 3537 if (adapter->hw.mac_type != e1000_ich8lan) {
3386 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); 3538 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3387 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); 3539 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3388 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); 3540 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3389 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC); 3541 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3390 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); 3542 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3391 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); 3543 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3392 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); 3544 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3393 } 3545 }
3394 } 3546 }
3395 3547
3396 /* Fill out the OS statistics structure */ 3548 /* Fill out the OS statistics structure */
3397
3398 adapter->net_stats.rx_packets = adapter->stats.gprc; 3549 adapter->net_stats.rx_packets = adapter->stats.gprc;
3399 adapter->net_stats.tx_packets = adapter->stats.gptc; 3550 adapter->net_stats.tx_packets = adapter->stats.gptc;
3400 adapter->net_stats.rx_bytes = adapter->stats.gorcl; 3551 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
@@ -3426,7 +3577,6 @@ e1000_update_stats(struct e1000_adapter *adapter)
3426 /* Tx Dropped needs to be maintained elsewhere */ 3577 /* Tx Dropped needs to be maintained elsewhere */
3427 3578
3428 /* Phy Stats */ 3579 /* Phy Stats */
3429
3430 if (hw->media_type == e1000_media_type_copper) { 3580 if (hw->media_type == e1000_media_type_copper) {
3431 if ((adapter->link_speed == SPEED_1000) && 3581 if ((adapter->link_speed == SPEED_1000) &&
3432 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 3582 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
@@ -3442,6 +3592,95 @@ e1000_update_stats(struct e1000_adapter *adapter)
3442 3592
3443 spin_unlock_irqrestore(&adapter->stats_lock, flags); 3593 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3444} 3594}
3595#ifdef CONFIG_PCI_MSI
3596
3597/**
3598 * e1000_intr_msi - Interrupt Handler
3599 * @irq: interrupt number
3600 * @data: pointer to a network interface device structure
3601 **/
3602
3603static
3604irqreturn_t e1000_intr_msi(int irq, void *data)
3605{
3606 struct net_device *netdev = data;
3607 struct e1000_adapter *adapter = netdev_priv(netdev);
3608 struct e1000_hw *hw = &adapter->hw;
3609#ifndef CONFIG_E1000_NAPI
3610 int i;
3611#endif
3612
3613 /* this code avoids the read of ICR but has to get 1000 interrupts
3614 * at every link change event before it will notice the change */
3615 if (++adapter->detect_link >= 1000) {
3616 uint32_t icr = E1000_READ_REG(hw, ICR);
3617#ifdef CONFIG_E1000_NAPI
3618 /* read ICR disables interrupts using IAM, so keep up with our
3619 * enable/disable accounting */
3620 atomic_inc(&adapter->irq_sem);
3621#endif
3622 adapter->detect_link = 0;
3623 if ((icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) &&
3624 (icr & E1000_ICR_INT_ASSERTED)) {
3625 hw->get_link_status = 1;
3626 /* 80003ES2LAN workaround--
3627 * For packet buffer work-around on link down event;
3628 * disable receives here in the ISR and
3629 * reset adapter in watchdog
3630 */
3631 if (netif_carrier_ok(netdev) &&
3632 (adapter->hw.mac_type == e1000_80003es2lan)) {
3633 /* disable receives */
3634 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3635 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3636 }
3637 /* guard against interrupt when we're going down */
3638 if (!test_bit(__E1000_DOWN, &adapter->flags))
3639 mod_timer(&adapter->watchdog_timer,
3640 jiffies + 1);
3641 }
3642 } else {
3643 E1000_WRITE_REG(hw, ICR, (0xffffffff & ~(E1000_ICR_RXSEQ |
3644 E1000_ICR_LSC)));
3645 /* bummer we have to flush here, but things break otherwise as
3646 * some event appears to be lost or delayed and throughput
3647 * drops. In almost all tests this flush is un-necessary */
3648 E1000_WRITE_FLUSH(hw);
3649#ifdef CONFIG_E1000_NAPI
3650 /* Interrupt Auto-Mask (IAM)...upon writing ICR, interrupts are
3651 * masked. No need for the IMC write, but it does mean we
3652 * should account for it ASAP. */
3653 atomic_inc(&adapter->irq_sem);
3654#endif
3655 }
3656
3657#ifdef CONFIG_E1000_NAPI
3658 if (likely(netif_rx_schedule_prep(netdev))) {
3659 adapter->total_tx_bytes = 0;
3660 adapter->total_tx_packets = 0;
3661 adapter->total_rx_bytes = 0;
3662 adapter->total_rx_packets = 0;
3663 __netif_rx_schedule(netdev);
3664 } else
3665 e1000_irq_enable(adapter);
3666#else
3667 adapter->total_tx_bytes = 0;
3668 adapter->total_rx_bytes = 0;
3669 adapter->total_tx_packets = 0;
3670 adapter->total_rx_packets = 0;
3671
3672 for (i = 0; i < E1000_MAX_INTR; i++)
3673 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3674 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
3675 break;
3676
3677 if (likely(adapter->itr_setting & 3))
3678 e1000_set_itr(adapter);
3679#endif
3680
3681 return IRQ_HANDLED;
3682}
3683#endif
3445 3684
3446/** 3685/**
3447 * e1000_intr - Interrupt Handler 3686 * e1000_intr - Interrupt Handler
@@ -3458,7 +3697,17 @@ e1000_intr(int irq, void *data)
3458 uint32_t rctl, icr = E1000_READ_REG(hw, ICR); 3697 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
3459#ifndef CONFIG_E1000_NAPI 3698#ifndef CONFIG_E1000_NAPI
3460 int i; 3699 int i;
3461#else 3700#endif
3701 if (unlikely(!icr))
3702 return IRQ_NONE; /* Not our interrupt */
3703
3704#ifdef CONFIG_E1000_NAPI
3705 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3706 * not set, then the adapter didn't send an interrupt */
3707 if (unlikely(hw->mac_type >= e1000_82571 &&
3708 !(icr & E1000_ICR_INT_ASSERTED)))
3709 return IRQ_NONE;
3710
3462 /* Interrupt Auto-Mask...upon reading ICR, 3711 /* Interrupt Auto-Mask...upon reading ICR,
3463 * interrupts are masked. No need for the 3712 * interrupts are masked. No need for the
3464 * IMC write, but it does mean we should 3713 * IMC write, but it does mean we should
@@ -3467,14 +3716,6 @@ e1000_intr(int irq, void *data)
3467 atomic_inc(&adapter->irq_sem); 3716 atomic_inc(&adapter->irq_sem);
3468#endif 3717#endif
3469 3718
3470 if (unlikely(!icr)) {
3471#ifdef CONFIG_E1000_NAPI
3472 if (hw->mac_type >= e1000_82571)
3473 e1000_irq_enable(adapter);
3474#endif
3475 return IRQ_NONE; /* Not our interrupt */
3476 }
3477
3478 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { 3719 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3479 hw->get_link_status = 1; 3720 hw->get_link_status = 1;
3480 /* 80003ES2LAN workaround-- 3721 /* 80003ES2LAN workaround--
@@ -3495,13 +3736,20 @@ e1000_intr(int irq, void *data)
3495 3736
3496#ifdef CONFIG_E1000_NAPI 3737#ifdef CONFIG_E1000_NAPI
3497 if (unlikely(hw->mac_type < e1000_82571)) { 3738 if (unlikely(hw->mac_type < e1000_82571)) {
3739 /* disable interrupts, without the synchronize_irq bit */
3498 atomic_inc(&adapter->irq_sem); 3740 atomic_inc(&adapter->irq_sem);
3499 E1000_WRITE_REG(hw, IMC, ~0); 3741 E1000_WRITE_REG(hw, IMC, ~0);
3500 E1000_WRITE_FLUSH(hw); 3742 E1000_WRITE_FLUSH(hw);
3501 } 3743 }
3502 if (likely(netif_rx_schedule_prep(netdev))) 3744 if (likely(netif_rx_schedule_prep(netdev))) {
3745 adapter->total_tx_bytes = 0;
3746 adapter->total_tx_packets = 0;
3747 adapter->total_rx_bytes = 0;
3748 adapter->total_rx_packets = 0;
3503 __netif_rx_schedule(netdev); 3749 __netif_rx_schedule(netdev);
3504 else 3750 } else
3751 /* this really should not happen! if it does it is basically a
3752 * bug, but not a hard error, so enable ints and continue */
3505 e1000_irq_enable(adapter); 3753 e1000_irq_enable(adapter);
3506#else 3754#else
3507 /* Writing IMC and IMS is needed for 82547. 3755 /* Writing IMC and IMS is needed for 82547.
@@ -3519,16 +3767,23 @@ e1000_intr(int irq, void *data)
3519 E1000_WRITE_REG(hw, IMC, ~0); 3767 E1000_WRITE_REG(hw, IMC, ~0);
3520 } 3768 }
3521 3769
3770 adapter->total_tx_bytes = 0;
3771 adapter->total_rx_bytes = 0;
3772 adapter->total_tx_packets = 0;
3773 adapter->total_rx_packets = 0;
3774
3522 for (i = 0; i < E1000_MAX_INTR; i++) 3775 for (i = 0; i < E1000_MAX_INTR; i++)
3523 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) & 3776 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3524 !e1000_clean_tx_irq(adapter, adapter->tx_ring))) 3777 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
3525 break; 3778 break;
3526 3779
3780 if (likely(adapter->itr_setting & 3))
3781 e1000_set_itr(adapter);
3782
3527 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) 3783 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3528 e1000_irq_enable(adapter); 3784 e1000_irq_enable(adapter);
3529 3785
3530#endif 3786#endif
3531
3532 return IRQ_HANDLED; 3787 return IRQ_HANDLED;
3533} 3788}
3534 3789
@@ -3572,6 +3827,8 @@ e1000_clean(struct net_device *poll_dev, int *budget)
3572 if ((!tx_cleaned && (work_done == 0)) || 3827 if ((!tx_cleaned && (work_done == 0)) ||
3573 !netif_running(poll_dev)) { 3828 !netif_running(poll_dev)) {
3574quit_polling: 3829quit_polling:
3830 if (likely(adapter->itr_setting & 3))
3831 e1000_set_itr(adapter);
3575 netif_rx_complete(poll_dev); 3832 netif_rx_complete(poll_dev);
3576 e1000_irq_enable(adapter); 3833 e1000_irq_enable(adapter);
3577 return 0; 3834 return 0;
@@ -3598,6 +3855,7 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3598 unsigned int count = 0; 3855 unsigned int count = 0;
3599#endif 3856#endif
3600 boolean_t cleaned = FALSE; 3857 boolean_t cleaned = FALSE;
3858 unsigned int total_tx_bytes=0, total_tx_packets=0;
3601 3859
3602 i = tx_ring->next_to_clean; 3860 i = tx_ring->next_to_clean;
3603 eop = tx_ring->buffer_info[i].next_to_watch; 3861 eop = tx_ring->buffer_info[i].next_to_watch;
@@ -3609,13 +3867,19 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3609 buffer_info = &tx_ring->buffer_info[i]; 3867 buffer_info = &tx_ring->buffer_info[i];
3610 cleaned = (i == eop); 3868 cleaned = (i == eop);
3611 3869
3870 if (cleaned) {
3871 /* this packet count is wrong for TSO but has a
3872 * tendency to make dynamic ITR change more
3873 * towards bulk */
3874 total_tx_packets++;
3875 total_tx_bytes += buffer_info->skb->len;
3876 }
3612 e1000_unmap_and_free_tx_resource(adapter, buffer_info); 3877 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
3613 memset(tx_desc, 0, sizeof(struct e1000_tx_desc)); 3878 tx_desc->upper.data = 0;
3614 3879
3615 if (unlikely(++i == tx_ring->count)) i = 0; 3880 if (unlikely(++i == tx_ring->count)) i = 0;
3616 } 3881 }
3617 3882
3618
3619 eop = tx_ring->buffer_info[i].next_to_watch; 3883 eop = tx_ring->buffer_info[i].next_to_watch;
3620 eop_desc = E1000_TX_DESC(*tx_ring, eop); 3884 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3621#ifdef CONFIG_E1000_NAPI 3885#ifdef CONFIG_E1000_NAPI
@@ -3634,8 +3898,10 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3634 * sees the new next_to_clean. 3898 * sees the new next_to_clean.
3635 */ 3899 */
3636 smp_mb(); 3900 smp_mb();
3637 if (netif_queue_stopped(netdev)) 3901 if (netif_queue_stopped(netdev)) {
3638 netif_wake_queue(netdev); 3902 netif_wake_queue(netdev);
3903 ++adapter->restart_queue;
3904 }
3639 } 3905 }
3640 3906
3641 if (adapter->detect_tx_hung) { 3907 if (adapter->detect_tx_hung) {
@@ -3673,6 +3939,8 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter,
3673 netif_stop_queue(netdev); 3939 netif_stop_queue(netdev);
3674 } 3940 }
3675 } 3941 }
3942 adapter->total_tx_bytes += total_tx_bytes;
3943 adapter->total_tx_packets += total_tx_packets;
3676 return cleaned; 3944 return cleaned;
3677} 3945}
3678 3946
@@ -3752,6 +4020,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3752 unsigned int i; 4020 unsigned int i;
3753 int cleaned_count = 0; 4021 int cleaned_count = 0;
3754 boolean_t cleaned = FALSE; 4022 boolean_t cleaned = FALSE;
4023 unsigned int total_rx_bytes=0, total_rx_packets=0;
3755 4024
3756 i = rx_ring->next_to_clean; 4025 i = rx_ring->next_to_clean;
3757 rx_desc = E1000_RX_DESC(*rx_ring, i); 4026 rx_desc = E1000_RX_DESC(*rx_ring, i);
@@ -3760,6 +4029,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3760 while (rx_desc->status & E1000_RXD_STAT_DD) { 4029 while (rx_desc->status & E1000_RXD_STAT_DD) {
3761 struct sk_buff *skb; 4030 struct sk_buff *skb;
3762 u8 status; 4031 u8 status;
4032
3763#ifdef CONFIG_E1000_NAPI 4033#ifdef CONFIG_E1000_NAPI
3764 if (*work_done >= work_to_do) 4034 if (*work_done >= work_to_do)
3765 break; 4035 break;
@@ -3817,6 +4087,10 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3817 * done after the TBI_ACCEPT workaround above */ 4087 * done after the TBI_ACCEPT workaround above */
3818 length -= 4; 4088 length -= 4;
3819 4089
4090 /* probably a little skewed due to removing CRC */
4091 total_rx_bytes += length;
4092 total_rx_packets++;
4093
3820 /* code added for copybreak, this should improve 4094 /* code added for copybreak, this should improve
3821 * performance for small packets with large amounts 4095 * performance for small packets with large amounts
3822 * of reassembly being done in the stack */ 4096 * of reassembly being done in the stack */
@@ -3832,12 +4106,11 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter,
3832 /* save the skb in buffer_info as good */ 4106 /* save the skb in buffer_info as good */
3833 buffer_info->skb = skb; 4107 buffer_info->skb = skb;
3834 skb = new_skb; 4108 skb = new_skb;
3835 skb_put(skb, length);
3836 } 4109 }
3837 } else 4110 /* else just continue with the old one */
3838 skb_put(skb, length); 4111 }
3839
3840 /* end copybreak code */ 4112 /* end copybreak code */
4113 skb_put(skb, length);
3841 4114
3842 /* Receive Checksum Offload */ 4115 /* Receive Checksum Offload */
3843 e1000_rx_checksum(adapter, 4116 e1000_rx_checksum(adapter,
@@ -3886,6 +4159,8 @@ next_desc:
3886 if (cleaned_count) 4159 if (cleaned_count)
3887 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); 4160 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3888 4161
4162 adapter->total_rx_packets += total_rx_packets;
4163 adapter->total_rx_bytes += total_rx_bytes;
3889 return cleaned; 4164 return cleaned;
3890} 4165}
3891 4166
@@ -3915,6 +4190,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3915 uint32_t length, staterr; 4190 uint32_t length, staterr;
3916 int cleaned_count = 0; 4191 int cleaned_count = 0;
3917 boolean_t cleaned = FALSE; 4192 boolean_t cleaned = FALSE;
4193 unsigned int total_rx_bytes=0, total_rx_packets=0;
3918 4194
3919 i = rx_ring->next_to_clean; 4195 i = rx_ring->next_to_clean;
3920 rx_desc = E1000_RX_DESC_PS(*rx_ring, i); 4196 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
@@ -3999,7 +4275,7 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3999 goto copydone; 4275 goto copydone;
4000 } /* if */ 4276 } /* if */
4001 } 4277 }
4002 4278
4003 for (j = 0; j < adapter->rx_ps_pages; j++) { 4279 for (j = 0; j < adapter->rx_ps_pages; j++) {
4004 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j]))) 4280 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
4005 break; 4281 break;
@@ -4019,6 +4295,9 @@ e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4019 pskb_trim(skb, skb->len - 4); 4295 pskb_trim(skb, skb->len - 4);
4020 4296
4021copydone: 4297copydone:
4298 total_rx_bytes += skb->len;
4299 total_rx_packets++;
4300
4022 e1000_rx_checksum(adapter, staterr, 4301 e1000_rx_checksum(adapter, staterr,
4023 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb); 4302 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
4024 skb->protocol = eth_type_trans(skb, netdev); 4303 skb->protocol = eth_type_trans(skb, netdev);
@@ -4067,6 +4346,8 @@ next_desc:
4067 if (cleaned_count) 4346 if (cleaned_count)
4068 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count); 4347 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4069 4348
4349 adapter->total_rx_packets += total_rx_packets;
4350 adapter->total_rx_bytes += total_rx_bytes;
4070 return cleaned; 4351 return cleaned;
4071} 4352}
4072 4353
@@ -4234,7 +4515,7 @@ e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
4234 } 4515 }
4235 4516
4236 skb = netdev_alloc_skb(netdev, 4517 skb = netdev_alloc_skb(netdev,
4237 adapter->rx_ps_bsize0 + NET_IP_ALIGN); 4518 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
4238 4519
4239 if (unlikely(!skb)) { 4520 if (unlikely(!skb)) {
4240 adapter->alloc_rx_buff_failed++; 4521 adapter->alloc_rx_buff_failed++;
@@ -4511,7 +4792,6 @@ e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4511 return E1000_SUCCESS; 4792 return E1000_SUCCESS;
4512} 4793}
4513 4794
4514
4515void 4795void
4516e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 4796e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4517{ 4797{
@@ -4534,12 +4814,12 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4534 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4814 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4535 4815
4536 if (adapter->hw.mac_type != e1000_ich8lan) { 4816 if (adapter->hw.mac_type != e1000_ich8lan) {
4537 /* enable VLAN receive filtering */ 4817 /* enable VLAN receive filtering */
4538 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4818 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4539 rctl |= E1000_RCTL_VFE; 4819 rctl |= E1000_RCTL_VFE;
4540 rctl &= ~E1000_RCTL_CFIEN; 4820 rctl &= ~E1000_RCTL_CFIEN;
4541 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4821 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4542 e1000_update_mng_vlan(adapter); 4822 e1000_update_mng_vlan(adapter);
4543 } 4823 }
4544 } else { 4824 } else {
4545 /* disable VLAN tag insert/strip */ 4825 /* disable VLAN tag insert/strip */
@@ -4548,14 +4828,16 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4548 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4828 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4549 4829
4550 if (adapter->hw.mac_type != e1000_ich8lan) { 4830 if (adapter->hw.mac_type != e1000_ich8lan) {
4551 /* disable VLAN filtering */ 4831 /* disable VLAN filtering */
4552 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4832 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4553 rctl &= ~E1000_RCTL_VFE; 4833 rctl &= ~E1000_RCTL_VFE;
4554 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4834 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4555 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) { 4835 if (adapter->mng_vlan_id !=
4556 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4836 (uint16_t)E1000_MNG_VLAN_NONE) {
4557 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4837 e1000_vlan_rx_kill_vid(netdev,
4558 } 4838 adapter->mng_vlan_id);
4839 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4840 }
4559 } 4841 }
4560 } 4842 }
4561 4843
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index a464cb290621..18afc0c25dac 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -107,17 +107,16 @@ typedef enum {
107 107
108#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 108#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
109 109
110#define E1000_WRITE_ICH8_REG(a, reg, value) ( \ 110#define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
111 writel((value), ((a)->flash_address + reg))) 111 writel((value), ((a)->flash_address + reg)))
112 112
113#define E1000_READ_ICH8_REG(a, reg) ( \ 113#define E1000_READ_ICH_FLASH_REG(a, reg) ( \
114 readl((a)->flash_address + reg)) 114 readl((a)->flash_address + reg))
115 115
116#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \ 116#define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
117 writew((value), ((a)->flash_address + reg))) 117 writew((value), ((a)->flash_address + reg)))
118 118
119#define E1000_READ_ICH8_REG16(a, reg) ( \ 119#define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
120 readw((a)->flash_address + reg)) 120 readw((a)->flash_address + reg))
121 121
122
123#endif /* _E1000_OSDEP_H_ */ 122#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 9c3c1acefccc..cbfcd7f2889f 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -44,16 +44,6 @@
44 */ 44 */
45 45
46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 46#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
47/* Module Parameters are always initialized to -1, so that the driver
48 * can tell the difference between no user specified value or the
49 * user asking for the default value.
50 * The true default values are loaded in when e1000_check_options is called.
51 *
52 * This is a GCC extension to ANSI C.
53 * See the item "Labeled Elements in Initializers" in the section
54 * "Extensions to the C Language Family" of the GCC documentation.
55 */
56
57#define E1000_PARAM(X, desc) \ 47#define E1000_PARAM(X, desc) \
58 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \ 48 static int __devinitdata X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
59 static int num_##X = 0; \ 49 static int num_##X = 0; \
@@ -67,7 +57,6 @@
67 * 57 *
68 * Default Value: 256 58 * Default Value: 256
69 */ 59 */
70
71E1000_PARAM(TxDescriptors, "Number of transmit descriptors"); 60E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
72 61
73/* Receive Descriptor Count 62/* Receive Descriptor Count
@@ -77,7 +66,6 @@ E1000_PARAM(TxDescriptors, "Number of transmit descriptors");
77 * 66 *
78 * Default Value: 256 67 * Default Value: 256
79 */ 68 */
80
81E1000_PARAM(RxDescriptors, "Number of receive descriptors"); 69E1000_PARAM(RxDescriptors, "Number of receive descriptors");
82 70
83/* User Specified Speed Override 71/* User Specified Speed Override
@@ -90,7 +78,6 @@ E1000_PARAM(RxDescriptors, "Number of receive descriptors");
90 * 78 *
91 * Default Value: 0 79 * Default Value: 0
92 */ 80 */
93
94E1000_PARAM(Speed, "Speed setting"); 81E1000_PARAM(Speed, "Speed setting");
95 82
96/* User Specified Duplex Override 83/* User Specified Duplex Override
@@ -102,7 +89,6 @@ E1000_PARAM(Speed, "Speed setting");
102 * 89 *
103 * Default Value: 0 90 * Default Value: 0
104 */ 91 */
105
106E1000_PARAM(Duplex, "Duplex setting"); 92E1000_PARAM(Duplex, "Duplex setting");
107 93
108/* Auto-negotiation Advertisement Override 94/* Auto-negotiation Advertisement Override
@@ -119,8 +105,9 @@ E1000_PARAM(Duplex, "Duplex setting");
119 * 105 *
120 * Default Value: 0x2F (copper); 0x20 (fiber) 106 * Default Value: 0x2F (copper); 0x20 (fiber)
121 */ 107 */
122
123E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting"); 108E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
109#define AUTONEG_ADV_DEFAULT 0x2F
110#define AUTONEG_ADV_MASK 0x2F
124 111
125/* User Specified Flow Control Override 112/* User Specified Flow Control Override
126 * 113 *
@@ -132,8 +119,8 @@ E1000_PARAM(AutoNeg, "Advertised auto-negotiation setting");
132 * 119 *
133 * Default Value: Read flow control settings from the EEPROM 120 * Default Value: Read flow control settings from the EEPROM
134 */ 121 */
135
136E1000_PARAM(FlowControl, "Flow Control setting"); 122E1000_PARAM(FlowControl, "Flow Control setting");
123#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
137 124
138/* XsumRX - Receive Checksum Offload Enable/Disable 125/* XsumRX - Receive Checksum Offload Enable/Disable
139 * 126 *
@@ -144,53 +131,54 @@ E1000_PARAM(FlowControl, "Flow Control setting");
144 * 131 *
145 * Default Value: 1 132 * Default Value: 1
146 */ 133 */
147
148E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload"); 134E1000_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
149 135
150/* Transmit Interrupt Delay in units of 1.024 microseconds 136/* Transmit Interrupt Delay in units of 1.024 microseconds
137 * Tx interrupt delay needs to typically be set to something non zero
151 * 138 *
152 * Valid Range: 0-65535 139 * Valid Range: 0-65535
153 *
154 * Default Value: 64
155 */ 140 */
156
157E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay"); 141E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
142#define DEFAULT_TIDV 8
143#define MAX_TXDELAY 0xFFFF
144#define MIN_TXDELAY 0
158 145
159/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds 146/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
160 * 147 *
161 * Valid Range: 0-65535 148 * Valid Range: 0-65535
162 *
163 * Default Value: 0
164 */ 149 */
165
166E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay"); 150E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
151#define DEFAULT_TADV 32
152#define MAX_TXABSDELAY 0xFFFF
153#define MIN_TXABSDELAY 0
167 154
168/* Receive Interrupt Delay in units of 1.024 microseconds 155/* Receive Interrupt Delay in units of 1.024 microseconds
156 * hardware will likely hang if you set this to anything but zero.
169 * 157 *
170 * Valid Range: 0-65535 158 * Valid Range: 0-65535
171 *
172 * Default Value: 0
173 */ 159 */
174
175E1000_PARAM(RxIntDelay, "Receive Interrupt Delay"); 160E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
161#define DEFAULT_RDTR 0
162#define MAX_RXDELAY 0xFFFF
163#define MIN_RXDELAY 0
176 164
177/* Receive Absolute Interrupt Delay in units of 1.024 microseconds 165/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
178 * 166 *
179 * Valid Range: 0-65535 167 * Valid Range: 0-65535
180 *
181 * Default Value: 128
182 */ 168 */
183
184E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay"); 169E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
170#define DEFAULT_RADV 8
171#define MAX_RXABSDELAY 0xFFFF
172#define MIN_RXABSDELAY 0
185 173
186/* Interrupt Throttle Rate (interrupts/sec) 174/* Interrupt Throttle Rate (interrupts/sec)
187 * 175 *
188 * Valid Range: 100-100000 (0=off, 1=dynamic) 176 * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
189 *
190 * Default Value: 8000
191 */ 177 */
192
193E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate"); 178E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
179#define DEFAULT_ITR 3
180#define MAX_ITR 100000
181#define MIN_ITR 100
194 182
195/* Enable Smart Power Down of the PHY 183/* Enable Smart Power Down of the PHY
196 * 184 *
@@ -198,7 +186,6 @@ E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
198 * 186 *
199 * Default Value: 0 (disabled) 187 * Default Value: 0 (disabled)
200 */ 188 */
201
202E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); 189E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
203 190
204/* Enable Kumeran Lock Loss workaround 191/* Enable Kumeran Lock Loss workaround
@@ -207,33 +194,8 @@ E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
207 * 194 *
208 * Default Value: 1 (enabled) 195 * Default Value: 1 (enabled)
209 */ 196 */
210
211E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); 197E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
212 198
213#define AUTONEG_ADV_DEFAULT 0x2F
214#define AUTONEG_ADV_MASK 0x2F
215#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
216
217#define DEFAULT_RDTR 0
218#define MAX_RXDELAY 0xFFFF
219#define MIN_RXDELAY 0
220
221#define DEFAULT_RADV 128
222#define MAX_RXABSDELAY 0xFFFF
223#define MIN_RXABSDELAY 0
224
225#define DEFAULT_TIDV 64
226#define MAX_TXDELAY 0xFFFF
227#define MIN_TXDELAY 0
228
229#define DEFAULT_TADV 64
230#define MAX_TXABSDELAY 0xFFFF
231#define MIN_TXABSDELAY 0
232
233#define DEFAULT_ITR 8000
234#define MAX_ITR 100000
235#define MIN_ITR 100
236
237struct e1000_option { 199struct e1000_option {
238 enum { enable_option, range_option, list_option } type; 200 enum { enable_option, range_option, list_option } type;
239 char *name; 201 char *name;
@@ -510,15 +472,27 @@ e1000_check_options(struct e1000_adapter *adapter)
510 break; 472 break;
511 case 1: 473 case 1:
512 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 474 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
513 opt.name); 475 opt.name);
476 adapter->itr_setting = adapter->itr;
477 adapter->itr = 20000;
478 break;
479 case 3:
480 DPRINTK(PROBE, INFO,
481 "%s set to dynamic conservative mode\n",
482 opt.name);
483 adapter->itr_setting = adapter->itr;
484 adapter->itr = 20000;
514 break; 485 break;
515 default: 486 default:
516 e1000_validate_option(&adapter->itr, &opt, 487 e1000_validate_option(&adapter->itr, &opt,
517 adapter); 488 adapter);
489 /* save the setting, because the dynamic bits change itr */
490 adapter->itr_setting = adapter->itr;
518 break; 491 break;
519 } 492 }
520 } else { 493 } else {
521 adapter->itr = opt.def; 494 adapter->itr_setting = opt.def;
495 adapter->itr = 20000;
522 } 496 }
523 } 497 }
524 { /* Smart Power Down */ 498 { /* Smart Power Down */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 00:38:22 -0500