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authorAuke Kok <auke-jan.h.kok@intel.com>2006-06-27 12:07:08 -0400
committerAuke Kok <juke-jan.h.kok@intel.com>2006-06-27 12:07:08 -0400
commit4ca213a6957318219822c024c8e4c61b3e42a7dc (patch)
tree9bef34eab2afb685c9e61d0a34bab6ff5c0811f3 /drivers/net/e1000/e1000_main.c
parent17231712ab89fa085bc235ef19c1e6e0c163e4fc (diff)
e1000: force register write flushes to circumvent broken platforms
A certain AMD64 bridge (8132) has an option to turn on write combining which breaks our adapter. To circumvent this we need to flush every write. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net/e1000/e1000_main.c')
-rw-r--r--drivers/net/e1000/e1000_main.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index c58fafd1c4be..c44ed6f4ba78 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -1370,11 +1370,11 @@ e1000_configure_tx(struct e1000_adapter *adapter)
1370 tdba = adapter->tx_ring[0].dma; 1370 tdba = adapter->tx_ring[0].dma;
1371 tdlen = adapter->tx_ring[0].count * 1371 tdlen = adapter->tx_ring[0].count *
1372 sizeof(struct e1000_tx_desc); 1372 sizeof(struct e1000_tx_desc);
1373 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1374 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1375 E1000_WRITE_REG(hw, TDLEN, tdlen); 1373 E1000_WRITE_REG(hw, TDLEN, tdlen);
1376 E1000_WRITE_REG(hw, TDH, 0); 1374 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1375 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1377 E1000_WRITE_REG(hw, TDT, 0); 1376 E1000_WRITE_REG(hw, TDT, 0);
1377 E1000_WRITE_REG(hw, TDH, 0);
1378 adapter->tx_ring[0].tdh = E1000_TDH; 1378 adapter->tx_ring[0].tdh = E1000_TDH;
1379 adapter->tx_ring[0].tdt = E1000_TDT; 1379 adapter->tx_ring[0].tdt = E1000_TDT;
1380 break; 1380 break;
@@ -1780,11 +1780,11 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1780 case 1: 1780 case 1:
1781 default: 1781 default:
1782 rdba = adapter->rx_ring[0].dma; 1782 rdba = adapter->rx_ring[0].dma;
1783 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1784 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1785 E1000_WRITE_REG(hw, RDLEN, rdlen); 1783 E1000_WRITE_REG(hw, RDLEN, rdlen);
1786 E1000_WRITE_REG(hw, RDH, 0); 1784 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1785 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1787 E1000_WRITE_REG(hw, RDT, 0); 1786 E1000_WRITE_REG(hw, RDT, 0);
1787 E1000_WRITE_REG(hw, RDH, 0);
1788 adapter->rx_ring[0].rdh = E1000_RDH; 1788 adapter->rx_ring[0].rdh = E1000_RDH;
1789 adapter->rx_ring[0].rdt = E1000_RDT; 1789 adapter->rx_ring[0].rdt = E1000_RDT;
1790 break; 1790 break;
@@ -2189,14 +2189,18 @@ e1000_set_multi(struct net_device *netdev)
2189 mc_ptr = mc_ptr->next; 2189 mc_ptr = mc_ptr->next;
2190 } else { 2190 } else {
2191 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0); 2191 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2192 E1000_WRITE_FLUSH(hw);
2192 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0); 2193 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2194 E1000_WRITE_FLUSH(hw);
2193 } 2195 }
2194 } 2196 }
2195 2197
2196 /* clear the old settings from the multicast hash table */ 2198 /* clear the old settings from the multicast hash table */
2197 2199
2198 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++) 2200 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
2199 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 2201 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2202 E1000_WRITE_FLUSH(hw);
2203 }
2200 2204
2201 /* load any remaining addresses into the hash table */ 2205 /* load any remaining addresses into the hash table */
2202 2206