diff options
author | Jesse Brandeburg <jesse.brandeburg@intel.com> | 2006-01-18 16:01:39 -0500 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2006-01-18 16:17:58 -0500 |
commit | 96838a40f02950f4ff501f62a7e59ac4d508e8b7 (patch) | |
tree | 9a86ecbe58a1d63159fc6c8c10223efa0344586d /drivers/net/e1000/e1000_hw.h | |
parent | 6150f038158ad8ad4b74d6b76a67e2f68fd1d8e2 (diff) |
[PATCH] e1000: Fix whitespace
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
-rw-r--r-- | drivers/net/e1000/e1000_hw.h | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h index 09a7c80dd508..f1219dd9dbac 100644 --- a/drivers/net/e1000/e1000_hw.h +++ b/drivers/net/e1000/e1000_hw.h | |||
@@ -902,14 +902,14 @@ struct e1000_ffvt_entry { | |||
902 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ | 902 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ |
903 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ | 903 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ |
904 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | 904 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
905 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ | 905 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ |
906 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ | 906 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ |
907 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ | 907 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ |
908 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ | 908 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ |
909 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ | 909 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ |
910 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ | 910 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ |
911 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ | 911 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ |
912 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ | 912 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ |
913 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | 913 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
914 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | 914 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
915 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | 915 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
@@ -1764,7 +1764,6 @@ struct e1000_hw { | |||
1764 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ | 1764 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
1765 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. | 1765 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. |
1766 | still to be processed. */ | 1766 | still to be processed. */ |
1767 | |||
1768 | /* Transmit Configuration Word */ | 1767 | /* Transmit Configuration Word */ |
1769 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | 1768 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ |
1770 | #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ | 1769 | #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ |