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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/e1000/e1000_hw.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
-rw-r--r--drivers/net/e1000/e1000_hw.h2144
1 files changed, 2144 insertions, 0 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
new file mode 100644
index 000000000000..f397e637a3c5
--- /dev/null
+++ b/drivers/net/e1000/e1000_hw.h
@@ -0,0 +1,2144 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
60 e1000_num_macs
61} e1000_mac_type;
62
63typedef enum {
64 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi,
66 e1000_eeprom_microwire,
67 e1000_num_eeprom_types
68} e1000_eeprom_type;
69
70/* Media Types */
71typedef enum {
72 e1000_media_type_copper = 0,
73 e1000_media_type_fiber = 1,
74 e1000_media_type_internal_serdes = 2,
75 e1000_num_media_types
76} e1000_media_type;
77
78typedef enum {
79 e1000_10_half = 0,
80 e1000_10_full = 1,
81 e1000_100_half = 2,
82 e1000_100_full = 3
83} e1000_speed_duplex_type;
84
85/* Flow Control Settings */
86typedef enum {
87 e1000_fc_none = 0,
88 e1000_fc_rx_pause = 1,
89 e1000_fc_tx_pause = 2,
90 e1000_fc_full = 3,
91 e1000_fc_default = 0xFF
92} e1000_fc_type;
93
94/* PCI bus types */
95typedef enum {
96 e1000_bus_type_unknown = 0,
97 e1000_bus_type_pci,
98 e1000_bus_type_pcix,
99 e1000_bus_type_reserved
100} e1000_bus_type;
101
102/* PCI bus speeds */
103typedef enum {
104 e1000_bus_speed_unknown = 0,
105 e1000_bus_speed_33,
106 e1000_bus_speed_66,
107 e1000_bus_speed_100,
108 e1000_bus_speed_120,
109 e1000_bus_speed_133,
110 e1000_bus_speed_reserved
111} e1000_bus_speed;
112
113/* PCI bus widths */
114typedef enum {
115 e1000_bus_width_unknown = 0,
116 e1000_bus_width_32,
117 e1000_bus_width_64,
118 e1000_bus_width_reserved
119} e1000_bus_width;
120
121/* PHY status info structure and supporting enums */
122typedef enum {
123 e1000_cable_length_50 = 0,
124 e1000_cable_length_50_80,
125 e1000_cable_length_80_110,
126 e1000_cable_length_110_140,
127 e1000_cable_length_140,
128 e1000_cable_length_undefined = 0xFF
129} e1000_cable_length;
130
131typedef enum {
132 e1000_igp_cable_length_10 = 10,
133 e1000_igp_cable_length_20 = 20,
134 e1000_igp_cable_length_30 = 30,
135 e1000_igp_cable_length_40 = 40,
136 e1000_igp_cable_length_50 = 50,
137 e1000_igp_cable_length_60 = 60,
138 e1000_igp_cable_length_70 = 70,
139 e1000_igp_cable_length_80 = 80,
140 e1000_igp_cable_length_90 = 90,
141 e1000_igp_cable_length_100 = 100,
142 e1000_igp_cable_length_110 = 110,
143 e1000_igp_cable_length_120 = 120,
144 e1000_igp_cable_length_130 = 130,
145 e1000_igp_cable_length_140 = 140,
146 e1000_igp_cable_length_150 = 150,
147 e1000_igp_cable_length_160 = 160,
148 e1000_igp_cable_length_170 = 170,
149 e1000_igp_cable_length_180 = 180
150} e1000_igp_cable_length;
151
152typedef enum {
153 e1000_10bt_ext_dist_enable_normal = 0,
154 e1000_10bt_ext_dist_enable_lower,
155 e1000_10bt_ext_dist_enable_undefined = 0xFF
156} e1000_10bt_ext_dist_enable;
157
158typedef enum {
159 e1000_rev_polarity_normal = 0,
160 e1000_rev_polarity_reversed,
161 e1000_rev_polarity_undefined = 0xFF
162} e1000_rev_polarity;
163
164typedef enum {
165 e1000_downshift_normal = 0,
166 e1000_downshift_activated,
167 e1000_downshift_undefined = 0xFF
168} e1000_downshift;
169
170typedef enum {
171 e1000_smart_speed_default = 0,
172 e1000_smart_speed_on,
173 e1000_smart_speed_off
174} e1000_smart_speed;
175
176typedef enum {
177 e1000_polarity_reversal_enabled = 0,
178 e1000_polarity_reversal_disabled,
179 e1000_polarity_reversal_undefined = 0xFF
180} e1000_polarity_reversal;
181
182typedef enum {
183 e1000_auto_x_mode_manual_mdi = 0,
184 e1000_auto_x_mode_manual_mdix,
185 e1000_auto_x_mode_auto1,
186 e1000_auto_x_mode_auto2,
187 e1000_auto_x_mode_undefined = 0xFF
188} e1000_auto_x_mode;
189
190typedef enum {
191 e1000_1000t_rx_status_not_ok = 0,
192 e1000_1000t_rx_status_ok,
193 e1000_1000t_rx_status_undefined = 0xFF
194} e1000_1000t_rx_status;
195
196typedef enum {
197 e1000_phy_m88 = 0,
198 e1000_phy_igp,
199 e1000_phy_undefined = 0xFF
200} e1000_phy_type;
201
202typedef enum {
203 e1000_ms_hw_default = 0,
204 e1000_ms_force_master,
205 e1000_ms_force_slave,
206 e1000_ms_auto
207} e1000_ms_type;
208
209typedef enum {
210 e1000_ffe_config_enabled = 0,
211 e1000_ffe_config_active,
212 e1000_ffe_config_blocked
213} e1000_ffe_config;
214
215typedef enum {
216 e1000_dsp_config_disabled = 0,
217 e1000_dsp_config_enabled,
218 e1000_dsp_config_activated,
219 e1000_dsp_config_undefined = 0xFF
220} e1000_dsp_config;
221
222struct e1000_phy_info {
223 e1000_cable_length cable_length;
224 e1000_10bt_ext_dist_enable extended_10bt_distance;
225 e1000_rev_polarity cable_polarity;
226 e1000_downshift downshift;
227 e1000_polarity_reversal polarity_correction;
228 e1000_auto_x_mode mdix_mode;
229 e1000_1000t_rx_status local_rx;
230 e1000_1000t_rx_status remote_rx;
231};
232
233struct e1000_phy_stats {
234 uint32_t idle_errors;
235 uint32_t receive_errors;
236};
237
238struct e1000_eeprom_info {
239 e1000_eeprom_type type;
240 uint16_t word_size;
241 uint16_t opcode_bits;
242 uint16_t address_bits;
243 uint16_t delay_usec;
244 uint16_t page_size;
245};
246
247
248
249/* Error Codes */
250#define E1000_SUCCESS 0
251#define E1000_ERR_EEPROM 1
252#define E1000_ERR_PHY 2
253#define E1000_ERR_CONFIG 3
254#define E1000_ERR_PARAM 4
255#define E1000_ERR_MAC_TYPE 5
256#define E1000_ERR_PHY_TYPE 6
257
258/* Function prototypes */
259/* Initialization */
260int32_t e1000_reset_hw(struct e1000_hw *hw);
261int32_t e1000_init_hw(struct e1000_hw *hw);
262int32_t e1000_set_mac_type(struct e1000_hw *hw);
263void e1000_set_media_type(struct e1000_hw *hw);
264
265/* Link Configuration */
266int32_t e1000_setup_link(struct e1000_hw *hw);
267int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
268void e1000_config_collision_dist(struct e1000_hw *hw);
269int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
270int32_t e1000_check_for_link(struct e1000_hw *hw);
271int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
272int32_t e1000_wait_autoneg(struct e1000_hw *hw);
273int32_t e1000_force_mac_fc(struct e1000_hw *hw);
274
275/* PHY */
276int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
277int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
278void e1000_phy_hw_reset(struct e1000_hw *hw);
279int32_t e1000_phy_reset(struct e1000_hw *hw);
280int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
281int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
282int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
283int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
284int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
285int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
286int32_t e1000_check_downshift(struct e1000_hw *hw);
287int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
288
289/* EEPROM Functions */
290void e1000_init_eeprom_params(struct e1000_hw *hw);
291int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
292int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
293int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
294int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
295int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
296int32_t e1000_read_mac_addr(struct e1000_hw * hw);
297
298/* Filters (multicast, vlan, receive) */
299void e1000_init_rx_addrs(struct e1000_hw *hw);
300void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
301uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
302void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
303void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
304void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
305void e1000_clear_vfta(struct e1000_hw *hw);
306
307/* LED functions */
308int32_t e1000_setup_led(struct e1000_hw *hw);
309int32_t e1000_cleanup_led(struct e1000_hw *hw);
310int32_t e1000_led_on(struct e1000_hw *hw);
311int32_t e1000_led_off(struct e1000_hw *hw);
312
313/* Adaptive IFS Functions */
314
315/* Everything else */
316uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
317void e1000_clear_hw_cntrs(struct e1000_hw *hw);
318void e1000_reset_adaptive(struct e1000_hw *hw);
319void e1000_update_adaptive(struct e1000_hw *hw);
320void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
321void e1000_get_bus_info(struct e1000_hw *hw);
322void e1000_pci_set_mwi(struct e1000_hw *hw);
323void e1000_pci_clear_mwi(struct e1000_hw *hw);
324void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
325void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
326/* Port I/O is only supported on 82544 and newer */
327uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
328uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
329void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
330void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
331int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
332int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
333
334#define E1000_READ_REG_IO(a, reg) \
335 e1000_read_reg_io((a), E1000_##reg)
336#define E1000_WRITE_REG_IO(a, reg, val) \
337 e1000_write_reg_io((a), E1000_##reg, val)
338
339/* PCI Device IDs */
340#define E1000_DEV_ID_82542 0x1000
341#define E1000_DEV_ID_82543GC_FIBER 0x1001
342#define E1000_DEV_ID_82543GC_COPPER 0x1004
343#define E1000_DEV_ID_82544EI_COPPER 0x1008
344#define E1000_DEV_ID_82544EI_FIBER 0x1009
345#define E1000_DEV_ID_82544GC_COPPER 0x100C
346#define E1000_DEV_ID_82544GC_LOM 0x100D
347#define E1000_DEV_ID_82540EM 0x100E
348#define E1000_DEV_ID_82540EM_LOM 0x1015
349#define E1000_DEV_ID_82540EP_LOM 0x1016
350#define E1000_DEV_ID_82540EP 0x1017
351#define E1000_DEV_ID_82540EP_LP 0x101E
352#define E1000_DEV_ID_82545EM_COPPER 0x100F
353#define E1000_DEV_ID_82545EM_FIBER 0x1011
354#define E1000_DEV_ID_82545GM_COPPER 0x1026
355#define E1000_DEV_ID_82545GM_FIBER 0x1027
356#define E1000_DEV_ID_82545GM_SERDES 0x1028
357#define E1000_DEV_ID_82546EB_COPPER 0x1010
358#define E1000_DEV_ID_82546EB_FIBER 0x1012
359#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
360#define E1000_DEV_ID_82541EI 0x1013
361#define E1000_DEV_ID_82541EI_MOBILE 0x1018
362#define E1000_DEV_ID_82541ER 0x1078
363#define E1000_DEV_ID_82547GI 0x1075
364#define E1000_DEV_ID_82541GI 0x1076
365#define E1000_DEV_ID_82541GI_MOBILE 0x1077
366#define E1000_DEV_ID_82541GI_LF 0x107C
367#define E1000_DEV_ID_82546GB_COPPER 0x1079
368#define E1000_DEV_ID_82546GB_FIBER 0x107A
369#define E1000_DEV_ID_82546GB_SERDES 0x107B
370#define E1000_DEV_ID_82546GB_PCIE 0x108A
371#define E1000_DEV_ID_82547EI 0x1019
372
373#define NODE_ADDRESS_SIZE 6
374#define ETH_LENGTH_OF_ADDRESS 6
375
376/* MAC decode size is 128K - This is the size of BAR0 */
377#define MAC_DECODE_SIZE (128 * 1024)
378
379#define E1000_82542_2_0_REV_ID 2
380#define E1000_82542_2_1_REV_ID 3
381#define E1000_REVISION_0 0
382#define E1000_REVISION_1 1
383#define E1000_REVISION_2 2
384
385#define SPEED_10 10
386#define SPEED_100 100
387#define SPEED_1000 1000
388#define HALF_DUPLEX 1
389#define FULL_DUPLEX 2
390
391/* The sizes (in bytes) of a ethernet packet */
392#define ENET_HEADER_SIZE 14
393#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
394#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
395#define ETHERNET_FCS_SIZE 4
396#define MAXIMUM_ETHERNET_PACKET_SIZE \
397 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
398#define MINIMUM_ETHERNET_PACKET_SIZE \
399 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
400#define CRC_LENGTH ETHERNET_FCS_SIZE
401#define MAX_JUMBO_FRAME_SIZE 0x3F00
402
403
404/* 802.1q VLAN Packet Sizes */
405#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
406
407/* Ethertype field values */
408#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
409#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
410#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
411
412/* Packet Header defines */
413#define IP_PROTOCOL_TCP 6
414#define IP_PROTOCOL_UDP 0x11
415
416/* This defines the bits that are set in the Interrupt Mask
417 * Set/Read Register. Each bit is documented below:
418 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
419 * o RXSEQ = Receive Sequence Error
420 */
421#define POLL_IMS_ENABLE_MASK ( \
422 E1000_IMS_RXDMT0 | \
423 E1000_IMS_RXSEQ)
424
425/* This defines the bits that are set in the Interrupt Mask
426 * Set/Read Register. Each bit is documented below:
427 * o RXT0 = Receiver Timer Interrupt (ring 0)
428 * o TXDW = Transmit Descriptor Written Back
429 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
430 * o RXSEQ = Receive Sequence Error
431 * o LSC = Link Status Change
432 */
433#define IMS_ENABLE_MASK ( \
434 E1000_IMS_RXT0 | \
435 E1000_IMS_TXDW | \
436 E1000_IMS_RXDMT0 | \
437 E1000_IMS_RXSEQ | \
438 E1000_IMS_LSC)
439
440/* Number of high/low register pairs in the RAR. The RAR (Receive Address
441 * Registers) holds the directed and multicast addresses that we monitor. We
442 * reserve one of these spots for our directed address, allowing us room for
443 * E1000_RAR_ENTRIES - 1 multicast addresses.
444 */
445#define E1000_RAR_ENTRIES 15
446
447#define MIN_NUMBER_OF_DESCRIPTORS 8
448#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
449
450/* Receive Descriptor */
451struct e1000_rx_desc {
452 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
453 uint16_t length; /* Length of data DMAed into data buffer */
454 uint16_t csum; /* Packet checksum */
455 uint8_t status; /* Descriptor status */
456 uint8_t errors; /* Descriptor Errors */
457 uint16_t special;
458};
459
460/* Receive Decriptor bit definitions */
461#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
462#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
463#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
464#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
465#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
466#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
467#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
468#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
469#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
470#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
471#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
472#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
473#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
474#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
475#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
476#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
477#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
478#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
479#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
480
481/* mask to determine if packets should be dropped due to frame errors */
482#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
483 E1000_RXD_ERR_CE | \
484 E1000_RXD_ERR_SE | \
485 E1000_RXD_ERR_SEQ | \
486 E1000_RXD_ERR_CXE | \
487 E1000_RXD_ERR_RXE)
488
489/* Transmit Descriptor */
490struct e1000_tx_desc {
491 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
492 union {
493 uint32_t data;
494 struct {
495 uint16_t length; /* Data buffer length */
496 uint8_t cso; /* Checksum offset */
497 uint8_t cmd; /* Descriptor control */
498 } flags;
499 } lower;
500 union {
501 uint32_t data;
502 struct {
503 uint8_t status; /* Descriptor status */
504 uint8_t css; /* Checksum start */
505 uint16_t special;
506 } fields;
507 } upper;
508};
509
510/* Transmit Descriptor bit definitions */
511#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
512#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
513#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
514#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
515#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
516#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
517#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
518#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
519#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
520#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
521#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
522#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
523#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
524#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
525#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
526#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
527#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
528#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
529#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
530#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
531
532/* Offload Context Descriptor */
533struct e1000_context_desc {
534 union {
535 uint32_t ip_config;
536 struct {
537 uint8_t ipcss; /* IP checksum start */
538 uint8_t ipcso; /* IP checksum offset */
539 uint16_t ipcse; /* IP checksum end */
540 } ip_fields;
541 } lower_setup;
542 union {
543 uint32_t tcp_config;
544 struct {
545 uint8_t tucss; /* TCP checksum start */
546 uint8_t tucso; /* TCP checksum offset */
547 uint16_t tucse; /* TCP checksum end */
548 } tcp_fields;
549 } upper_setup;
550 uint32_t cmd_and_length; /* */
551 union {
552 uint32_t data;
553 struct {
554 uint8_t status; /* Descriptor status */
555 uint8_t hdr_len; /* Header length */
556 uint16_t mss; /* Maximum segment size */
557 } fields;
558 } tcp_seg_setup;
559};
560
561/* Offload data descriptor */
562struct e1000_data_desc {
563 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
564 union {
565 uint32_t data;
566 struct {
567 uint16_t length; /* Data buffer length */
568 uint8_t typ_len_ext; /* */
569 uint8_t cmd; /* */
570 } flags;
571 } lower;
572 union {
573 uint32_t data;
574 struct {
575 uint8_t status; /* Descriptor status */
576 uint8_t popts; /* Packet Options */
577 uint16_t special; /* */
578 } fields;
579 } upper;
580};
581
582/* Filters */
583#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
584#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
585#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
586
587
588/* Receive Address Register */
589struct e1000_rar {
590 volatile uint32_t low; /* receive address low */
591 volatile uint32_t high; /* receive address high */
592};
593
594/* Number of entries in the Multicast Table Array (MTA). */
595#define E1000_NUM_MTA_REGISTERS 128
596
597/* IPv4 Address Table Entry */
598struct e1000_ipv4_at_entry {
599 volatile uint32_t ipv4_addr; /* IP Address (RW) */
600 volatile uint32_t reserved;
601};
602
603/* Four wakeup IP addresses are supported */
604#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
605#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
606#define E1000_IP6AT_SIZE 1
607
608/* IPv6 Address Table Entry */
609struct e1000_ipv6_at_entry {
610 volatile uint8_t ipv6_addr[16];
611};
612
613/* Flexible Filter Length Table Entry */
614struct e1000_fflt_entry {
615 volatile uint32_t length; /* Flexible Filter Length (RW) */
616 volatile uint32_t reserved;
617};
618
619/* Flexible Filter Mask Table Entry */
620struct e1000_ffmt_entry {
621 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
622 volatile uint32_t reserved;
623};
624
625/* Flexible Filter Value Table Entry */
626struct e1000_ffvt_entry {
627 volatile uint32_t value; /* Flexible Filter Value (RW) */
628 volatile uint32_t reserved;
629};
630
631/* Four Flexible Filters are supported */
632#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
633
634/* Each Flexible Filter is at most 128 (0x80) bytes in length */
635#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
636
637#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
638#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
639#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
640
641/* Register Set. (82543, 82544)
642 *
643 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
644 * These registers are physically located on the NIC, but are mapped into the
645 * host memory address space.
646 *
647 * RW - register is both readable and writable
648 * RO - register is read only
649 * WO - register is write only
650 * R/clr - register is read only and is cleared when read
651 * A - register array
652 */
653#define E1000_CTRL 0x00000 /* Device Control - RW */
654#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
655#define E1000_STATUS 0x00008 /* Device Status - RO */
656#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
657#define E1000_EERD 0x00014 /* EEPROM Read - RW */
658#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
659#define E1000_FLA 0x0001C /* Flash Access - RW */
660#define E1000_MDIC 0x00020 /* MDI Control - RW */
661#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
662#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
663#define E1000_FCT 0x00030 /* Flow Control Type - RW */
664#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
665#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
666#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
667#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
668#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
669#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
670#define E1000_RCTL 0x00100 /* RX Control - RW */
671#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
672#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
673#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
674#define E1000_TCTL 0x00400 /* TX Control - RW */
675#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
676#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
677#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
678#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
679#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
680#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
681#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
682#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
683#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
684#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
685#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
686#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
687#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
688#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
689#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
690#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
691#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
692#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
693#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
694#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
695#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
696#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
697#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
698#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
699#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
700#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
701#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
702#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
703#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
704#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
705#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
706#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
707#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
708#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
709#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
710#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
711#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
712#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
713#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
714#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
715#define E1000_COLC 0x04028 /* Collision Count - R/clr */
716#define E1000_DC 0x04030 /* Defer Count - R/clr */
717#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
718#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
719#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
720#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
721#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
722#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
723#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
724#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
725#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
726#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
727#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
728#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
729#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
730#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
731#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
732#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
733#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
734#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
735#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
736#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
737#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
738#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
739#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
740#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
741#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
742#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
743#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
744#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
745#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
746#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
747#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
748#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
749#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
750#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
751#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
752#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
753#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
754#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
755#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
756#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
757#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
758#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
759#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
760#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
761#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
762#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
763#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
764#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
765#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
766#define E1000_RA 0x05400 /* Receive Address - RW Array */
767#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
768#define E1000_WUC 0x05800 /* Wakeup Control - RW */
769#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
770#define E1000_WUS 0x05810 /* Wakeup Status - RO */
771#define E1000_MANC 0x05820 /* Management Control - RW */
772#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
773#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
774#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
775#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
776#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
777#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
778#define E1000_HOST_IF 0x08800 /* Host Interface */
779#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
780#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
781
782/* Register Set (82542)
783 *
784 * Some of the 82542 registers are located at different offsets than they are
785 * in more current versions of the 8254x. Despite the difference in location,
786 * the registers function in the same manner.
787 */
788#define E1000_82542_CTRL E1000_CTRL
789#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
790#define E1000_82542_STATUS E1000_STATUS
791#define E1000_82542_EECD E1000_EECD
792#define E1000_82542_EERD E1000_EERD
793#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
794#define E1000_82542_FLA E1000_FLA
795#define E1000_82542_MDIC E1000_MDIC
796#define E1000_82542_FCAL E1000_FCAL
797#define E1000_82542_FCAH E1000_FCAH
798#define E1000_82542_FCT E1000_FCT
799#define E1000_82542_VET E1000_VET
800#define E1000_82542_RA 0x00040
801#define E1000_82542_ICR E1000_ICR
802#define E1000_82542_ITR E1000_ITR
803#define E1000_82542_ICS E1000_ICS
804#define E1000_82542_IMS E1000_IMS
805#define E1000_82542_IMC E1000_IMC
806#define E1000_82542_RCTL E1000_RCTL
807#define E1000_82542_RDTR 0x00108
808#define E1000_82542_RDBAL 0x00110
809#define E1000_82542_RDBAH 0x00114
810#define E1000_82542_RDLEN 0x00118
811#define E1000_82542_RDH 0x00120
812#define E1000_82542_RDT 0x00128
813#define E1000_82542_FCRTH 0x00160
814#define E1000_82542_FCRTL 0x00168
815#define E1000_82542_FCTTV E1000_FCTTV
816#define E1000_82542_TXCW E1000_TXCW
817#define E1000_82542_RXCW E1000_RXCW
818#define E1000_82542_MTA 0x00200
819#define E1000_82542_TCTL E1000_TCTL
820#define E1000_82542_TIPG E1000_TIPG
821#define E1000_82542_TDBAL 0x00420
822#define E1000_82542_TDBAH 0x00424
823#define E1000_82542_TDLEN 0x00428
824#define E1000_82542_TDH 0x00430
825#define E1000_82542_TDT 0x00438
826#define E1000_82542_TIDV 0x00440
827#define E1000_82542_TBT E1000_TBT
828#define E1000_82542_AIT E1000_AIT
829#define E1000_82542_VFTA 0x00600
830#define E1000_82542_LEDCTL E1000_LEDCTL
831#define E1000_82542_PBA E1000_PBA
832#define E1000_82542_RXDCTL E1000_RXDCTL
833#define E1000_82542_RADV E1000_RADV
834#define E1000_82542_RSRPD E1000_RSRPD
835#define E1000_82542_TXDMAC E1000_TXDMAC
836#define E1000_82542_TDFHS E1000_TDFHS
837#define E1000_82542_TDFTS E1000_TDFTS
838#define E1000_82542_TDFPC E1000_TDFPC
839#define E1000_82542_TXDCTL E1000_TXDCTL
840#define E1000_82542_TADV E1000_TADV
841#define E1000_82542_TSPMT E1000_TSPMT
842#define E1000_82542_CRCERRS E1000_CRCERRS
843#define E1000_82542_ALGNERRC E1000_ALGNERRC
844#define E1000_82542_SYMERRS E1000_SYMERRS
845#define E1000_82542_RXERRC E1000_RXERRC
846#define E1000_82542_MPC E1000_MPC
847#define E1000_82542_SCC E1000_SCC
848#define E1000_82542_ECOL E1000_ECOL
849#define E1000_82542_MCC E1000_MCC
850#define E1000_82542_LATECOL E1000_LATECOL
851#define E1000_82542_COLC E1000_COLC
852#define E1000_82542_DC E1000_DC
853#define E1000_82542_TNCRS E1000_TNCRS
854#define E1000_82542_SEC E1000_SEC
855#define E1000_82542_CEXTERR E1000_CEXTERR
856#define E1000_82542_RLEC E1000_RLEC
857#define E1000_82542_XONRXC E1000_XONRXC
858#define E1000_82542_XONTXC E1000_XONTXC
859#define E1000_82542_XOFFRXC E1000_XOFFRXC
860#define E1000_82542_XOFFTXC E1000_XOFFTXC
861#define E1000_82542_FCRUC E1000_FCRUC
862#define E1000_82542_PRC64 E1000_PRC64
863#define E1000_82542_PRC127 E1000_PRC127
864#define E1000_82542_PRC255 E1000_PRC255
865#define E1000_82542_PRC511 E1000_PRC511
866#define E1000_82542_PRC1023 E1000_PRC1023
867#define E1000_82542_PRC1522 E1000_PRC1522
868#define E1000_82542_GPRC E1000_GPRC
869#define E1000_82542_BPRC E1000_BPRC
870#define E1000_82542_MPRC E1000_MPRC
871#define E1000_82542_GPTC E1000_GPTC
872#define E1000_82542_GORCL E1000_GORCL
873#define E1000_82542_GORCH E1000_GORCH
874#define E1000_82542_GOTCL E1000_GOTCL
875#define E1000_82542_GOTCH E1000_GOTCH
876#define E1000_82542_RNBC E1000_RNBC
877#define E1000_82542_RUC E1000_RUC
878#define E1000_82542_RFC E1000_RFC
879#define E1000_82542_ROC E1000_ROC
880#define E1000_82542_RJC E1000_RJC
881#define E1000_82542_MGTPRC E1000_MGTPRC
882#define E1000_82542_MGTPDC E1000_MGTPDC
883#define E1000_82542_MGTPTC E1000_MGTPTC
884#define E1000_82542_TORL E1000_TORL
885#define E1000_82542_TORH E1000_TORH
886#define E1000_82542_TOTL E1000_TOTL
887#define E1000_82542_TOTH E1000_TOTH
888#define E1000_82542_TPR E1000_TPR
889#define E1000_82542_TPT E1000_TPT
890#define E1000_82542_PTC64 E1000_PTC64
891#define E1000_82542_PTC127 E1000_PTC127
892#define E1000_82542_PTC255 E1000_PTC255
893#define E1000_82542_PTC511 E1000_PTC511
894#define E1000_82542_PTC1023 E1000_PTC1023
895#define E1000_82542_PTC1522 E1000_PTC1522
896#define E1000_82542_MPTC E1000_MPTC
897#define E1000_82542_BPTC E1000_BPTC
898#define E1000_82542_TSCTC E1000_TSCTC
899#define E1000_82542_TSCTFC E1000_TSCTFC
900#define E1000_82542_RXCSUM E1000_RXCSUM
901#define E1000_82542_WUC E1000_WUC
902#define E1000_82542_WUFC E1000_WUFC
903#define E1000_82542_WUS E1000_WUS
904#define E1000_82542_MANC E1000_MANC
905#define E1000_82542_IPAV E1000_IPAV
906#define E1000_82542_IP4AT E1000_IP4AT
907#define E1000_82542_IP6AT E1000_IP6AT
908#define E1000_82542_WUPL E1000_WUPL
909#define E1000_82542_WUPM E1000_WUPM
910#define E1000_82542_FFLT E1000_FFLT
911#define E1000_82542_TDFH 0x08010
912#define E1000_82542_TDFT 0x08018
913#define E1000_82542_FFMT E1000_FFMT
914#define E1000_82542_FFVT E1000_FFVT
915#define E1000_82542_HOST_IF E1000_HOST_IF
916
917/* Statistics counters collected by the MAC */
918struct e1000_hw_stats {
919 uint64_t crcerrs;
920 uint64_t algnerrc;
921 uint64_t symerrs;
922 uint64_t rxerrc;
923 uint64_t mpc;
924 uint64_t scc;
925 uint64_t ecol;
926 uint64_t mcc;
927 uint64_t latecol;
928 uint64_t colc;
929 uint64_t dc;
930 uint64_t tncrs;
931 uint64_t sec;
932 uint64_t cexterr;
933 uint64_t rlec;
934 uint64_t xonrxc;
935 uint64_t xontxc;
936 uint64_t xoffrxc;
937 uint64_t xofftxc;
938 uint64_t fcruc;
939 uint64_t prc64;
940 uint64_t prc127;
941 uint64_t prc255;
942 uint64_t prc511;
943 uint64_t prc1023;
944 uint64_t prc1522;
945 uint64_t gprc;
946 uint64_t bprc;
947 uint64_t mprc;
948 uint64_t gptc;
949 uint64_t gorcl;
950 uint64_t gorch;
951 uint64_t gotcl;
952 uint64_t gotch;
953 uint64_t rnbc;
954 uint64_t ruc;
955 uint64_t rfc;
956 uint64_t roc;
957 uint64_t rjc;
958 uint64_t mgprc;
959 uint64_t mgpdc;
960 uint64_t mgptc;
961 uint64_t torl;
962 uint64_t torh;
963 uint64_t totl;
964 uint64_t toth;
965 uint64_t tpr;
966 uint64_t tpt;
967 uint64_t ptc64;
968 uint64_t ptc127;
969 uint64_t ptc255;
970 uint64_t ptc511;
971 uint64_t ptc1023;
972 uint64_t ptc1522;
973 uint64_t mptc;
974 uint64_t bptc;
975 uint64_t tsctc;
976 uint64_t tsctfc;
977};
978
979/* Structure containing variables used by the shared code (e1000_hw.c) */
980struct e1000_hw {
981 uint8_t __iomem *hw_addr;
982 e1000_mac_type mac_type;
983 e1000_phy_type phy_type;
984 uint32_t phy_init_script;
985 e1000_media_type media_type;
986 void *back;
987 e1000_fc_type fc;
988 e1000_bus_speed bus_speed;
989 e1000_bus_width bus_width;
990 e1000_bus_type bus_type;
991 struct e1000_eeprom_info eeprom;
992 e1000_ms_type master_slave;
993 e1000_ms_type original_master_slave;
994 e1000_ffe_config ffe_config_state;
995 uint32_t asf_firmware_present;
996 unsigned long io_base;
997 uint32_t phy_id;
998 uint32_t phy_revision;
999 uint32_t phy_addr;
1000 uint32_t original_fc;
1001 uint32_t txcw;
1002 uint32_t autoneg_failed;
1003 uint32_t max_frame_size;
1004 uint32_t min_frame_size;
1005 uint32_t mc_filter_type;
1006 uint32_t num_mc_addrs;
1007 uint32_t collision_delta;
1008 uint32_t tx_packet_delta;
1009 uint32_t ledctl_default;
1010 uint32_t ledctl_mode1;
1011 uint32_t ledctl_mode2;
1012 uint16_t phy_spd_default;
1013 uint16_t autoneg_advertised;
1014 uint16_t pci_cmd_word;
1015 uint16_t fc_high_water;
1016 uint16_t fc_low_water;
1017 uint16_t fc_pause_time;
1018 uint16_t current_ifs_val;
1019 uint16_t ifs_min_val;
1020 uint16_t ifs_max_val;
1021 uint16_t ifs_step_size;
1022 uint16_t ifs_ratio;
1023 uint16_t device_id;
1024 uint16_t vendor_id;
1025 uint16_t subsystem_id;
1026 uint16_t subsystem_vendor_id;
1027 uint8_t revision_id;
1028 uint8_t autoneg;
1029 uint8_t mdix;
1030 uint8_t forced_speed_duplex;
1031 uint8_t wait_autoneg_complete;
1032 uint8_t dma_fairness;
1033 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1034 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1035 boolean_t disable_polarity_correction;
1036 boolean_t speed_downgraded;
1037 e1000_smart_speed smart_speed;
1038 e1000_dsp_config dsp_config_state;
1039 boolean_t get_link_status;
1040 boolean_t serdes_link_down;
1041 boolean_t tbi_compatibility_en;
1042 boolean_t tbi_compatibility_on;
1043 boolean_t phy_reset_disable;
1044 boolean_t fc_send_xon;
1045 boolean_t fc_strict_ieee;
1046 boolean_t report_tx_early;
1047 boolean_t adaptive_ifs;
1048 boolean_t ifs_params_forced;
1049 boolean_t in_ifs_mode;
1050};
1051
1052
1053#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1054#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1055/* Register Bit Masks */
1056/* Device Control */
1057#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1058#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1059#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1060#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1061#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1062#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1063#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1064#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1065#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1066#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1067#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1068#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1069#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1070#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1071#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1072#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1073#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1074#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1075#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1076#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1077#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1078#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1079#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1080#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1081#define E1000_CTRL_RST 0x04000000 /* Global reset */
1082#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1083#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1084#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1085#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1086#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1087
1088/* Device Status */
1089#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1090#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1091#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1092#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1093#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1094#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1095#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1096#define E1000_STATUS_SPEED_MASK 0x000000C0
1097#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1098#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1099#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1100#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1101#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1102#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1103#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1104#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1105#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1106
1107/* Constants used to intrepret the masked PCI-X bus speed. */
1108#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1109#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1110#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1111
1112/* EEPROM/Flash Control */
1113#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1114#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1115#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1116#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1117#define E1000_EECD_FWE_MASK 0x00000030
1118#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1119#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1120#define E1000_EECD_FWE_SHIFT 4
1121#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1122#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1123#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1124#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1125#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1126 * (0-small, 1-large) */
1127#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1128#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1129#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1130#endif
1131
1132/* EEPROM Read */
1133#define E1000_EERD_START 0x00000001 /* Start Read */
1134#define E1000_EERD_DONE 0x00000010 /* Read Done */
1135#define E1000_EERD_ADDR_SHIFT 8
1136#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1137#define E1000_EERD_DATA_SHIFT 16
1138#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1139
1140/* SPI EEPROM Status Register */
1141#define EEPROM_STATUS_RDY_SPI 0x01
1142#define EEPROM_STATUS_WEN_SPI 0x02
1143#define EEPROM_STATUS_BP0_SPI 0x04
1144#define EEPROM_STATUS_BP1_SPI 0x08
1145#define EEPROM_STATUS_WPEN_SPI 0x80
1146
1147/* Extended Device Control */
1148#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1149#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1150#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1151#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1152#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1153#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1154#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1155#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1156#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1157#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1158#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1159#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1160#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1161#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1162#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1163#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1164#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1165#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1166#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1167#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1168#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1169#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1170#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1171#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1172#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1173#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1174
1175/* MDI Control */
1176#define E1000_MDIC_DATA_MASK 0x0000FFFF
1177#define E1000_MDIC_REG_MASK 0x001F0000
1178#define E1000_MDIC_REG_SHIFT 16
1179#define E1000_MDIC_PHY_MASK 0x03E00000
1180#define E1000_MDIC_PHY_SHIFT 21
1181#define E1000_MDIC_OP_WRITE 0x04000000
1182#define E1000_MDIC_OP_READ 0x08000000
1183#define E1000_MDIC_READY 0x10000000
1184#define E1000_MDIC_INT_EN 0x20000000
1185#define E1000_MDIC_ERROR 0x40000000
1186
1187/* LED Control */
1188#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1189#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1190#define E1000_LEDCTL_LED0_IVRT 0x00000040
1191#define E1000_LEDCTL_LED0_BLINK 0x00000080
1192#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1193#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1194#define E1000_LEDCTL_LED1_IVRT 0x00004000
1195#define E1000_LEDCTL_LED1_BLINK 0x00008000
1196#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1197#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1198#define E1000_LEDCTL_LED2_IVRT 0x00400000
1199#define E1000_LEDCTL_LED2_BLINK 0x00800000
1200#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1201#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1202#define E1000_LEDCTL_LED3_IVRT 0x40000000
1203#define E1000_LEDCTL_LED3_BLINK 0x80000000
1204
1205#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1206#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1207#define E1000_LEDCTL_MODE_LINK_UP 0x2
1208#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1209#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1210#define E1000_LEDCTL_MODE_LINK_10 0x5
1211#define E1000_LEDCTL_MODE_LINK_100 0x6
1212#define E1000_LEDCTL_MODE_LINK_1000 0x7
1213#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1214#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1215#define E1000_LEDCTL_MODE_COLLISION 0xA
1216#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1217#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1218#define E1000_LEDCTL_MODE_PAUSED 0xD
1219#define E1000_LEDCTL_MODE_LED_ON 0xE
1220#define E1000_LEDCTL_MODE_LED_OFF 0xF
1221
1222/* Receive Address */
1223#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1224
1225/* Interrupt Cause Read */
1226#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1227#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1228#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1229#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1230#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1231#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1232#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1233#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1234#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1235#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1236#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1237#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1238#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1239#define E1000_ICR_TXD_LOW 0x00008000
1240#define E1000_ICR_SRPD 0x00010000
1241
1242/* Interrupt Cause Set */
1243#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1244#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1245#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1246#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1247#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1248#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1249#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1250#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1251#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1252#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1253#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1254#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1255#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1256#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1257#define E1000_ICS_SRPD E1000_ICR_SRPD
1258
1259/* Interrupt Mask Set */
1260#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1261#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1262#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1263#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1264#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1265#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1266#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1267#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1268#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1269#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1270#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1271#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1272#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1273#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1274#define E1000_IMS_SRPD E1000_ICR_SRPD
1275
1276/* Interrupt Mask Clear */
1277#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1278#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1279#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1280#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1281#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1282#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1283#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1284#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1285#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1286#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1287#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1288#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1289#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1290#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1291#define E1000_IMC_SRPD E1000_ICR_SRPD
1292
1293/* Receive Control */
1294#define E1000_RCTL_RST 0x00000001 /* Software reset */
1295#define E1000_RCTL_EN 0x00000002 /* enable */
1296#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1297#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1298#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1299#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1300#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1301#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1302#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1303#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1304#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1305#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1306#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1307#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1308#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1309#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1310#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1311#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1312#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1313#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1314/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1315#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1316#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1317#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1318#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1319/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1320#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1321#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1322#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1323#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1324#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1325#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1326#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1327#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1328#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1329#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1330
1331/* Receive Descriptor */
1332#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1333#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1334#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1335#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1336#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1337
1338/* Flow Control */
1339#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1340#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1341#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1342#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1343
1344/* Receive Descriptor Control */
1345#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1346#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1347#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1348#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1349
1350/* Transmit Descriptor Control */
1351#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1352#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1353#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1354#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1355#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1356#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1357
1358/* Transmit Configuration Word */
1359#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1360#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1361#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1362#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1363#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1364#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1365#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1366#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1367#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1368#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1369
1370/* Receive Configuration Word */
1371#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1372#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1373#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1374#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1375#define E1000_RXCW_C 0x20000000 /* Receive config */
1376#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1377#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1378
1379/* Transmit Control */
1380#define E1000_TCTL_RST 0x00000001 /* software reset */
1381#define E1000_TCTL_EN 0x00000002 /* enable tx */
1382#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1383#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1384#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1385#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1386#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1387#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1388#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1389#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1390
1391/* Receive Checksum Control */
1392#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1393#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1394#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1395#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1396
1397/* Definitions for power management and wakeup registers */
1398/* Wake Up Control */
1399#define E1000_WUC_APME 0x00000001 /* APM Enable */
1400#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1401#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1402#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1403#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1404
1405/* Wake Up Filter Control */
1406#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1407#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1408#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1409#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1410#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1411#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1412#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1413#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1414#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1415#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1416#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1417#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1418#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1419#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1420#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1421
1422/* Wake Up Status */
1423#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1424#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1425#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1426#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1427#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1428#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1429#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1430#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1431#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1432#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1433#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1434#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1435#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1436
1437/* Management Control */
1438#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1439#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1440#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1441#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1442#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1443#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1444#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1445#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1446#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1447#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1448 * Filtering */
1449#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1450#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1451#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1452#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1453 * filtering */
1454#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1455 * memory */
1456#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1457#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1458#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1459#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1460#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1461#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1462
1463#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1464#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1465
1466/* Wake Up Packet Length */
1467#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1468
1469#define E1000_MDALIGN 4096
1470
1471/* EEPROM Commands - Microwire */
1472#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1473#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1474#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1475#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1476#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1477
1478/* EEPROM Commands - SPI */
1479#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1480#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */
1481#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */
1482#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
1483#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */
1484#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */
1485#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */
1486#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */
1487
1488/* EEPROM Size definitions */
1489#define EEPROM_SIZE_16KB 0x1800
1490#define EEPROM_SIZE_8KB 0x1400
1491#define EEPROM_SIZE_4KB 0x1000
1492#define EEPROM_SIZE_2KB 0x0C00
1493#define EEPROM_SIZE_1KB 0x0800
1494#define EEPROM_SIZE_512B 0x0400
1495#define EEPROM_SIZE_128B 0x0000
1496#define EEPROM_SIZE_MASK 0x1C00
1497
1498/* EEPROM Word Offsets */
1499#define EEPROM_COMPAT 0x0003
1500#define EEPROM_ID_LED_SETTINGS 0x0004
1501#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1502#define EEPROM_PHY_CLASS_WORD 0x0007
1503#define EEPROM_INIT_CONTROL1_REG 0x000A
1504#define EEPROM_INIT_CONTROL2_REG 0x000F
1505#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
1506#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
1507#define EEPROM_CFG 0x0012
1508#define EEPROM_FLASH_VERSION 0x0032
1509#define EEPROM_CHECKSUM_REG 0x003F
1510
1511/* Word definitions for ID LED Settings */
1512#define ID_LED_RESERVED_0000 0x0000
1513#define ID_LED_RESERVED_FFFF 0xFFFF
1514#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1515 (ID_LED_OFF1_OFF2 << 8) | \
1516 (ID_LED_DEF1_DEF2 << 4) | \
1517 (ID_LED_DEF1_DEF2))
1518#define ID_LED_DEF1_DEF2 0x1
1519#define ID_LED_DEF1_ON2 0x2
1520#define ID_LED_DEF1_OFF2 0x3
1521#define ID_LED_ON1_DEF2 0x4
1522#define ID_LED_ON1_ON2 0x5
1523#define ID_LED_ON1_OFF2 0x6
1524#define ID_LED_OFF1_DEF2 0x7
1525#define ID_LED_OFF1_ON2 0x8
1526#define ID_LED_OFF1_OFF2 0x9
1527
1528#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1529#define IGP_ACTIVITY_LED_ENABLE 0x0300
1530#define IGP_LED3_MODE 0x07000000
1531
1532
1533/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
1534#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
1535
1536/* Mask bit for PHY class in Word 7 of the EEPROM */
1537#define EEPROM_PHY_CLASS_A 0x8000
1538
1539/* Mask bits for fields in Word 0x0a of the EEPROM */
1540#define EEPROM_WORD0A_ILOS 0x0010
1541#define EEPROM_WORD0A_SWDPIO 0x01E0
1542#define EEPROM_WORD0A_LRST 0x0200
1543#define EEPROM_WORD0A_FD 0x0400
1544#define EEPROM_WORD0A_66MHZ 0x0800
1545
1546/* Mask bits for fields in Word 0x0f of the EEPROM */
1547#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1548#define EEPROM_WORD0F_PAUSE 0x1000
1549#define EEPROM_WORD0F_ASM_DIR 0x2000
1550#define EEPROM_WORD0F_ANE 0x0800
1551#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1552
1553/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
1554#define EEPROM_SUM 0xBABA
1555
1556/* EEPROM Map defines (WORD OFFSETS)*/
1557#define EEPROM_NODE_ADDRESS_BYTE_0 0
1558#define EEPROM_PBA_BYTE_1 8
1559
1560#define EEPROM_RESERVED_WORD 0xFFFF
1561
1562/* EEPROM Map Sizes (Byte Counts) */
1563#define PBA_SIZE 4
1564
1565/* Collision related configuration parameters */
1566#define E1000_COLLISION_THRESHOLD 15
1567#define E1000_CT_SHIFT 4
1568#define E1000_COLLISION_DISTANCE 64
1569#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1570#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1571#define E1000_COLD_SHIFT 12
1572
1573/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1574#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1575#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1576
1577/* Default values for the transmit IPG register */
1578#define DEFAULT_82542_TIPG_IPGT 10
1579#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1580#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1581
1582#define E1000_TIPG_IPGT_MASK 0x000003FF
1583#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1584#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1585
1586#define DEFAULT_82542_TIPG_IPGR1 2
1587#define DEFAULT_82543_TIPG_IPGR1 8
1588#define E1000_TIPG_IPGR1_SHIFT 10
1589
1590#define DEFAULT_82542_TIPG_IPGR2 10
1591#define DEFAULT_82543_TIPG_IPGR2 6
1592#define E1000_TIPG_IPGR2_SHIFT 20
1593
1594#define E1000_TXDMAC_DPP 0x00000001
1595
1596/* Adaptive IFS defines */
1597#define TX_THRESHOLD_START 8
1598#define TX_THRESHOLD_INCREMENT 10
1599#define TX_THRESHOLD_DECREMENT 1
1600#define TX_THRESHOLD_STOP 190
1601#define TX_THRESHOLD_DISABLE 0
1602#define TX_THRESHOLD_TIMER_MS 10000
1603#define MIN_NUM_XMITS 1000
1604#define IFS_MAX 80
1605#define IFS_STEP 10
1606#define IFS_MIN 40
1607#define IFS_RATIO 4
1608
1609/* PBA constants */
1610#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1611#define E1000_PBA_22K 0x0016
1612#define E1000_PBA_24K 0x0018
1613#define E1000_PBA_30K 0x001E
1614#define E1000_PBA_40K 0x0028
1615#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1616
1617/* Flow Control Constants */
1618#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1619#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1620#define FLOW_CONTROL_TYPE 0x8808
1621
1622/* The historical defaults for the flow control values are given below. */
1623#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
1624#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
1625#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1626
1627/* PCIX Config space */
1628#define PCIX_COMMAND_REGISTER 0xE6
1629#define PCIX_STATUS_REGISTER_LO 0xE8
1630#define PCIX_STATUS_REGISTER_HI 0xEA
1631
1632#define PCIX_COMMAND_MMRBC_MASK 0x000C
1633#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1634#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1635#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1636#define PCIX_STATUS_HI_MMRBC_4K 0x3
1637#define PCIX_STATUS_HI_MMRBC_2K 0x2
1638
1639
1640/* Number of bits required to shift right the "pause" bits from the
1641 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
1642 */
1643#define PAUSE_SHIFT 5
1644
1645/* Number of bits required to shift left the "SWDPIO" bits from the
1646 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
1647 */
1648#define SWDPIO_SHIFT 17
1649
1650/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
1651 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
1652 */
1653#define SWDPIO__EXT_SHIFT 4
1654
1655/* Number of bits required to shift left the "ILOS" bit from the EEPROM
1656 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
1657 */
1658#define ILOS_SHIFT 3
1659
1660
1661#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1662
1663/* Number of milliseconds we wait for auto-negotiation to complete */
1664#define LINK_UP_TIMEOUT 500
1665
1666#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1667
1668/* The carrier extension symbol, as received by the NIC. */
1669#define CARRIER_EXTENSION 0x0F
1670
1671/* TBI_ACCEPT macro definition:
1672 *
1673 * This macro requires:
1674 * adapter = a pointer to struct e1000_hw
1675 * status = the 8 bit status field of the RX descriptor with EOP set
1676 * error = the 8 bit error field of the RX descriptor with EOP set
1677 * length = the sum of all the length fields of the RX descriptors that
1678 * make up the current frame
1679 * last_byte = the last byte of the frame DMAed by the hardware
1680 * max_frame_length = the maximum frame length we want to accept.
1681 * min_frame_length = the minimum frame length we want to accept.
1682 *
1683 * This macro is a conditional that should be used in the interrupt
1684 * handler's Rx processing routine when RxErrors have been detected.
1685 *
1686 * Typical use:
1687 * ...
1688 * if (TBI_ACCEPT) {
1689 * accept_frame = TRUE;
1690 * e1000_tbi_adjust_stats(adapter, MacAddress);
1691 * frame_length--;
1692 * } else {
1693 * accept_frame = FALSE;
1694 * }
1695 * ...
1696 */
1697
1698#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1699 ((adapter)->tbi_compatibility_on && \
1700 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1701 ((last_byte) == CARRIER_EXTENSION) && \
1702 (((status) & E1000_RXD_STAT_VP) ? \
1703 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1704 ((length) <= ((adapter)->max_frame_size + 1))) : \
1705 (((length) > (adapter)->min_frame_size) && \
1706 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1707
1708
1709/* Structures, enums, and macros for the PHY */
1710
1711/* Bit definitions for the Management Data IO (MDIO) and Management Data
1712 * Clock (MDC) pins in the Device Control Register.
1713 */
1714#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1715#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1716#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1717#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1718#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1719#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1720#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1721#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1722
1723/* PHY 1000 MII Register/Bit Definitions */
1724/* PHY Registers defined by IEEE */
1725#define PHY_CTRL 0x00 /* Control Register */
1726#define PHY_STATUS 0x01 /* Status Regiser */
1727#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1728#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1729#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1730#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1731#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1732#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
1733#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1734#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1735#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1736#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1737
1738#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1739#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
1740
1741/* M88E1000 Specific Registers */
1742#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
1743#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
1744#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
1745#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
1746#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1747#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1748
1749#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1750#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
1751#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
1752#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1753#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1754
1755#define IGP01E1000_IEEE_REGS_PAGE 0x0000
1756#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1757#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1758
1759/* IGP01E1000 Specific Registers */
1760#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
1761#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
1762#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
1763#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1764#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1765#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
1766#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1767
1768/* IGP01E1000 AGC Registers - stores the cable length values*/
1769#define IGP01E1000_PHY_AGC_A 0x1172
1770#define IGP01E1000_PHY_AGC_B 0x1272
1771#define IGP01E1000_PHY_AGC_C 0x1472
1772#define IGP01E1000_PHY_AGC_D 0x1872
1773
1774/* IGP01E1000 DSP Reset Register */
1775#define IGP01E1000_PHY_DSP_RESET 0x1F33
1776#define IGP01E1000_PHY_DSP_SET 0x1F71
1777#define IGP01E1000_PHY_DSP_FFE 0x1F35
1778
1779#define IGP01E1000_PHY_CHANNEL_NUM 4
1780#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1781#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1782#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
1783#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
1784
1785#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
1786#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
1787
1788#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
1789#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
1790#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
1791#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
1792
1793#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
1794/* IGP01E1000 PCS Initialization register - stores the polarity status when
1795 * speed = 1000 Mbps. */
1796#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
1797#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
1798
1799#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
1800
1801
1802/* PHY Control Register */
1803#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1804#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
1805#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
1806#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
1807#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
1808#define MII_CR_POWER_DOWN 0x0800 /* Power down */
1809#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
1810#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
1811#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
1812#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1813
1814/* PHY Status Register */
1815#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
1816#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
1817#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
1818#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
1819#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
1820#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
1821#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1822#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
1823#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
1824#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
1825#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
1826#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
1827#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
1828#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
1829#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1830
1831/* Autoneg Advertisement Register */
1832#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
1833#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
1834#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
1835#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
1836#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
1837#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
1838#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
1839#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
1840#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
1841#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1842
1843/* Link Partner Ability Register (Base Page) */
1844#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1845#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
1846#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
1847#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
1848#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
1849#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
1850#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
1851#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
1852#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
1853#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
1854#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1855
1856/* Autoneg Expansion Register */
1857#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
1858#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
1859#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
1860#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1861#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1862
1863/* Next Page TX Register */
1864#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1865#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
1866 * of different NP
1867 */
1868#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1869 * 0 = cannot comply with msg
1870 */
1871#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1872#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1873 * 0 = sending last NP
1874 */
1875
1876/* Link Partner Next Page Register */
1877#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
1878#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
1879 * of different NP
1880 */
1881#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
1882 * 0 = cannot comply with msg
1883 */
1884#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
1885#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
1886#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
1887 * 0 = sending last NP
1888 */
1889
1890/* 1000BASE-T Control Register */
1891#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
1892#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
1893#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
1894#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
1895 /* 0=DTE device */
1896#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
1897 /* 0=Configure PHY as Slave */
1898#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
1899 /* 0=Automatic Master/Slave config */
1900#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1901#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
1902#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1903#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1904#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1905
1906/* 1000BASE-T Status Register */
1907#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
1908#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
1909#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1910#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1911#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1912#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1913#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
1914#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1915#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1916#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
1917#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1918#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
1919#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
1920
1921/* Extended Status Register */
1922#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
1923#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
1924#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
1925#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1926
1927#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
1928#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
1929
1930#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
1931 /* (0=enable, 1=disable) */
1932
1933/* M88E1000 PHY Specific Control Register */
1934#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
1935#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
1936#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
1937#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
1938 * 0=CLK125 toggling
1939 */
1940#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1941 /* Manual MDI configuration */
1942#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1943#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1944 * 100BASE-TX/10BASE-T:
1945 * MDI Mode
1946 */
1947#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1948 * all speeds.
1949 */
1950#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1951 /* 1=Enable Extended 10BASE-T distance
1952 * (Lower 10BASE-T RX Threshold)
1953 * 0=Normal 10BASE-T RX Threshold */
1954#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1955 /* 1=5-Bit interface in 100BASE-TX
1956 * 0=MII interface in 100BASE-TX */
1957#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1958#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1959#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1960
1961#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1962#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
1963#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1964
1965/* M88E1000 PHY Specific Status Register */
1966#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
1967#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1968#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1969#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1970#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
1971 * 3=110-140M;4=>140M */
1972#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1973#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1974#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
1975#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1976#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1977#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
1978#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1979#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1980
1981#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1982#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
1983#define M88E1000_PSSR_MDIX_SHIFT 6
1984#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1985
1986/* M88E1000 Extended PHY Specific Control Register */
1987#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1988#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
1989 * Will assert lost lock and bring
1990 * link down if idle not seen
1991 * within 1ms in 1000BASE-T
1992 */
1993/* Number of times we will attempt to autonegotiate before downshifting if we
1994 * are the master */
1995#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1996#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1997#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1998#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1999#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2000/* Number of times we will attempt to autonegotiate before downshifting if we
2001 * are the slave */
2002#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2003#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2004#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2005#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2006#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2007#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2008#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2009#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2010
2011/* IGP01E1000 Specific Port Config Register - R/W */
2012#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2013#define IGP01E1000_PSCFR_PRE_EN 0x0020
2014#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2015#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2016#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2017#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2018
2019/* IGP01E1000 Specific Port Status Register - R/O */
2020#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2021#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2022#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2023#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2024#define IGP01E1000_PSSR_LINK_UP 0x0400
2025#define IGP01E1000_PSSR_MDIX 0x0800
2026#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2027#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2028#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2029#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2030#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2031#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2032
2033/* IGP01E1000 Specific Port Control Register - R/W */
2034#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2035#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2036#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2037#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2038#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2039#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2040
2041/* IGP01E1000 Specific Port Link Health Register */
2042#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2043#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2044#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2045#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2046#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2047#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2048#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2049#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2050#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2051#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2052#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2053#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2054#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2055#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2056
2057/* IGP01E1000 Channel Quality Register */
2058#define IGP01E1000_MSE_CHANNEL_D 0x000F
2059#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2060#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2061#define IGP01E1000_MSE_CHANNEL_A 0xF000
2062
2063/* IGP01E1000 DSP reset macros */
2064#define DSP_RESET_ENABLE 0x0
2065#define DSP_RESET_DISABLE 0x2
2066#define E1000_MAX_DSP_RESETS 10
2067
2068/* IGP01E1000 AGC Registers */
2069
2070#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2071
2072/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2073#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2074
2075/* The precision of the length is +/- 10 meters */
2076#define IGP01E1000_AGC_RANGE 10
2077
2078/* IGP01E1000 PCS Initialization register */
2079/* bits 3:6 in the PCS registers stores the channels polarity */
2080#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2081
2082/* IGP01E1000 GMII FIFO Register */
2083#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2084 * on Link-Up */
2085#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2086
2087/* IGP01E1000 Analog Register */
2088#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2089#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2090#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2091#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2092
2093#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2094#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2095#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2096#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2097#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2098
2099#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2100#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2101#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2102#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2103
2104
2105/* Bit definitions for valid PHY IDs. */
2106/* I = Integrated
2107 * E = External
2108 */
2109#define M88E1000_E_PHY_ID 0x01410C50
2110#define M88E1000_I_PHY_ID 0x01410C30
2111#define M88E1011_I_PHY_ID 0x01410C20
2112#define IGP01E1000_I_PHY_ID 0x02A80380
2113#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2114#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2115#define M88E1011_I_REV_4 0x04
2116
2117/* Miscellaneous PHY bit definitions. */
2118#define PHY_PREAMBLE 0xFFFFFFFF
2119#define PHY_SOF 0x01
2120#define PHY_OP_READ 0x02
2121#define PHY_OP_WRITE 0x01
2122#define PHY_TURNAROUND 0x02
2123#define PHY_PREAMBLE_SIZE 32
2124#define MII_CR_SPEED_1000 0x0040
2125#define MII_CR_SPEED_100 0x2000
2126#define MII_CR_SPEED_10 0x0000
2127#define E1000_PHY_ADDRESS 0x01
2128#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2129#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2130#define PHY_REVISION_MASK 0xFFFFFFF0
2131#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2132#define REG4_SPEED_MASK 0x01E0
2133#define REG9_SPEED_MASK 0x0300
2134#define ADVERTISE_10_HALF 0x0001
2135#define ADVERTISE_10_FULL 0x0002
2136#define ADVERTISE_100_HALF 0x0004
2137#define ADVERTISE_100_FULL 0x0008
2138#define ADVERTISE_1000_HALF 0x0010
2139#define ADVERTISE_1000_FULL 0x0020
2140#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2141#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2142#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2143
2144#endif /* _E1000_HW_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 13:00:21 -0500