diff options
author | Auke Kok <auke\\\-jan.h.kok@intel.com> | 2006-08-28 17:56:16 -0400 |
---|---|---|
committer | Auke Kok <juke-jan.h.kok@intel.com> | 2006-08-28 17:56:16 -0400 |
commit | 8fc897b00a7d81ffaa24e18881c2d6b10698ab0b (patch) | |
tree | 3dac8c72398e8a23228b2a5edd5c926c2a58675d /drivers/net/e1000/e1000_hw.h | |
parent | 699a71238856b19091503c671bac8abb1e3f9a3a (diff) |
e1000: Whitespace cleanup, cosmetic changes
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net/e1000/e1000_hw.h')
-rw-r--r-- | drivers/net/e1000/e1000_hw.h | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h index 375b95518c31..4f74242746fa 100644 --- a/drivers/net/e1000/e1000_hw.h +++ b/drivers/net/e1000/e1000_hw.h | |||
@@ -336,9 +336,9 @@ uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); | |||
336 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ | 336 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ |
337 | 337 | ||
338 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ | 338 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ |
339 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ | 339 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ |
340 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ | 340 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ |
341 | #define E1000_MNG_IAMT_MODE 0x3 | 341 | #define E1000_MNG_IAMT_MODE 0x3 |
342 | #define E1000_MNG_ICH_IAMT_MODE 0x2 | 342 | #define E1000_MNG_ICH_IAMT_MODE 0x2 |
343 | #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ | 343 | #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ |
344 | 344 | ||
@@ -385,7 +385,7 @@ struct e1000_host_mng_dhcp_cookie{ | |||
385 | #endif | 385 | #endif |
386 | 386 | ||
387 | int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, | 387 | int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, |
388 | uint16_t length); | 388 | uint16_t length); |
389 | boolean_t e1000_check_mng_mode(struct e1000_hw *hw); | 389 | boolean_t e1000_check_mng_mode(struct e1000_hw *hw); |
390 | boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); | 390 | boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); |
391 | 391 | ||
@@ -523,7 +523,7 @@ int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); | |||
523 | 523 | ||
524 | 524 | ||
525 | /* 802.1q VLAN Packet Sizes */ | 525 | /* 802.1q VLAN Packet Sizes */ |
526 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ | 526 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ |
527 | 527 | ||
528 | /* Ethertype field values */ | 528 | /* Ethertype field values */ |
529 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ | 529 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ |
@@ -697,6 +697,7 @@ union e1000_rx_desc_packet_split { | |||
697 | E1000_RXDEXT_STATERR_CXE | \ | 697 | E1000_RXDEXT_STATERR_CXE | \ |
698 | E1000_RXDEXT_STATERR_RXE) | 698 | E1000_RXDEXT_STATERR_RXE) |
699 | 699 | ||
700 | |||
700 | /* Transmit Descriptor */ | 701 | /* Transmit Descriptor */ |
701 | struct e1000_tx_desc { | 702 | struct e1000_tx_desc { |
702 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | 703 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ |
@@ -2086,7 +2087,7 @@ struct e1000_hw { | |||
2086 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address | 2087 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address |
2087 | * filtering */ | 2088 | * filtering */ |
2088 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ | 2089 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ |
2089 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ | 2090 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ |
2090 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ | 2091 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ |
2091 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ | 2092 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ |
2092 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ | 2093 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ |
@@ -2172,7 +2173,7 @@ struct e1000_host_command_info { | |||
2172 | 2173 | ||
2173 | #define E1000_MDALIGN 4096 | 2174 | #define E1000_MDALIGN 4096 |
2174 | 2175 | ||
2175 | /* PCI-Ex registers */ | 2176 | /* PCI-Ex registers*/ |
2176 | 2177 | ||
2177 | /* PCI-Ex Control Register */ | 2178 | /* PCI-Ex Control Register */ |
2178 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 | 2179 | #define E1000_GCR_RXD_NO_SNOOP 0x00000001 |
@@ -2224,7 +2225,7 @@ struct e1000_host_command_info { | |||
2224 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ | 2225 | #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ |
2225 | 2226 | ||
2226 | /* EEPROM Commands - SPI */ | 2227 | /* EEPROM Commands - SPI */ |
2227 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | 2228 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
2228 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ | 2229 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ |
2229 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ | 2230 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
2230 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ | 2231 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
@@ -3082,10 +3083,10 @@ struct e1000_host_command_info { | |||
3082 | 3083 | ||
3083 | /* DSP Distance Register (Page 5, Register 26) */ | 3084 | /* DSP Distance Register (Page 5, Register 26) */ |
3084 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; | 3085 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; |
3085 | 1 = 50-80M; | 3086 | 1 = 50-80M; |
3086 | 2 = 80-110M; | 3087 | 2 = 80-110M; |
3087 | 3 = 110-140M; | 3088 | 3 = 110-140M; |
3088 | 4 = >140M */ | 3089 | 4 = >140M */ |
3089 | 3090 | ||
3090 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | 3091 | /* Kumeran Mode Control Register (Page 193, Register 16) */ |
3091 | #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ | 3092 | #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ |