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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-02 11:56:58 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-02 11:56:58 -0400
commit95f3eff6997ae4a6754c1d874ec0a414d97c44d1 (patch)
tree0aba758649b4f56264cbe9736f6db18a98b9cc1f /drivers/net/e1000/e1000_hw.c
parent44f549217cd26daf7063984ae4ee6e46beca9c41 (diff)
parent2c81fbc4cfc895e80c18fffdc04a3d870eb16cb8 (diff)
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (37 commits) [netdrvr] hp100: encapsulate all non-module code drivers/net/wireless/{airo,ipw2100}: fix error handling bugs [netdrvr] phy: Fix bugs in error handling [PATCH] spidernet: Use pci_dma_mapping_error() [PATCH] sky2: version 1.9 [PATCH] sky2: fragmented receive for large MTU [PATCH] sky2: use netif_tx_lock instead of LLTX [PATCH] sky2: incremental transmit completion [PATCH] sky2: name irq after eth for irqbalance [PATCH] sky2: workarounds for some 88e806x chips [PATCH] sky2: use standard pci register capabilties for error register [PATCH] sky2: gigabit full duplex negotiation e100, e1000, ixgb: increment version numbers ixgb: convert to netdev_priv(netdev) ixgb: combine more rx descriptors to improve performance e1000: possible memory leak in e1000_set_ringparam e1000: Janitor: Use #defined values for literals e1000: don't strip vlan ID if 8021q claims it e1000: rework polarity, NVM, eeprom code and fixes. e1000: driver state fixes (race fix) ...
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c1074
1 files changed, 483 insertions, 591 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 10b8c8c25325..65077f39da69 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -1,25 +1,24 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2006 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms and conditions of the GNU General Public License,
8 Software Foundation; either version 2 of the License, or (at your option) 8 version 2, as published by the Free Software Foundation.
9 any later version. 9
10 10 This program is distributed in the hope it will be useful, but WITHOUT
11 This program is distributed in the hope that it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details. 13 more details.
15 14
16 You should have received a copy of the GNU General Public License along with 15 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59 16 this program; if not, write to the Free Software Foundation, Inc.,
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 18
20 The full GNU General Public License is included in this distribution in the 19 The full GNU General Public License is included in this distribution in
21 file called LICENSE. 20 the file called "COPYING".
22 21
23 Contact Information: 22 Contact Information:
24 Linux NICS <linux.nics@intel.com> 23 Linux NICS <linux.nics@intel.com>
25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
@@ -34,6 +33,63 @@
34 33
35#include "e1000_hw.h" 34#include "e1000_hw.h"
36 35
36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static int32_t e1000_check_downshift(struct e1000_hw *hw);
45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw);
48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60static int32_t e1000_id_led_init(struct e1000_hw *hw);
61static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63static void e1000_init_rx_addrs(struct e1000_hw *hw);
64static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86static void e1000_release_software_flag(struct e1000_hw *hw);
87static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
37static int32_t e1000_set_phy_type(struct e1000_hw *hw); 93static int32_t e1000_set_phy_type(struct e1000_hw *hw);
38static void e1000_phy_init_script(struct e1000_hw *hw); 94static void e1000_phy_init_script(struct e1000_hw *hw);
39static int32_t e1000_setup_copper_link(struct e1000_hw *hw); 95static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
@@ -70,69 +126,10 @@ static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
70static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 126static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
71static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); 127static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
72static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); 128static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
73static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
74static int32_t e1000_check_downshift(struct e1000_hw *hw);
75static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
76static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
77static void e1000_clear_vfta(struct e1000_hw *hw);
78static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
79static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
80 boolean_t link_up);
81static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
82static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
83static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
84static int32_t e1000_get_cable_length(struct e1000_hw *hw,
85 uint16_t *min_length,
86 uint16_t *max_length);
87static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
88static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
89static int32_t e1000_id_led_init(struct e1000_hw * hw);
90static void e1000_init_rx_addrs(struct e1000_hw *hw);
91static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
92static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
93static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
94static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
95 uint16_t words, uint16_t *data);
96static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
97static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
98static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
99
100static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 uint32_t value);
102
103#define E1000_WRITE_REG_IO(a, reg, val) \
104 e1000_write_reg_io((a), E1000_##reg, val)
105static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, 129static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
106 uint16_t duplex); 130 uint16_t duplex);
107static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 131static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
108 132
109static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
110 uint32_t segment);
111static int32_t e1000_get_software_flag(struct e1000_hw *hw);
112static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
113static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
114static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
115static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
116 uint16_t words, uint16_t *data);
117static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
118 uint8_t* data);
119static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
120 uint16_t *data);
121static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
122 uint16_t *data);
123static void e1000_release_software_flag(struct e1000_hw *hw);
124static void e1000_release_software_semaphore(struct e1000_hw *hw);
125static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
126 uint32_t no_snoop);
127static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
128 uint32_t index, uint8_t byte);
129static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
130 uint16_t words, uint16_t *data);
131static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
132 uint8_t data);
133static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
134 uint16_t data);
135
136/* IGP cable length table */ 133/* IGP cable length table */
137static const 134static const
138uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 135uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
@@ -156,13 +153,12 @@ uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
156 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
157 104, 109, 114, 118, 121, 124}; 154 104, 109, 114, 118, 121, 124};
158 155
159
160/****************************************************************************** 156/******************************************************************************
161 * Set the phy type member in the hw struct. 157 * Set the phy type member in the hw struct.
162 * 158 *
163 * hw - Struct containing variables accessed by shared code 159 * hw - Struct containing variables accessed by shared code
164 *****************************************************************************/ 160 *****************************************************************************/
165int32_t 161static int32_t
166e1000_set_phy_type(struct e1000_hw *hw) 162e1000_set_phy_type(struct e1000_hw *hw)
167{ 163{
168 DEBUGFUNC("e1000_set_phy_type"); 164 DEBUGFUNC("e1000_set_phy_type");
@@ -208,7 +204,6 @@ e1000_set_phy_type(struct e1000_hw *hw)
208 return E1000_SUCCESS; 204 return E1000_SUCCESS;
209} 205}
210 206
211
212/****************************************************************************** 207/******************************************************************************
213 * IGP phy init script - initializes the GbE PHY 208 * IGP phy init script - initializes the GbE PHY
214 * 209 *
@@ -667,19 +662,12 @@ e1000_reset_hw(struct e1000_hw *hw)
667 E1000_WRITE_FLUSH(hw); 662 E1000_WRITE_FLUSH(hw);
668 } 663 }
669 /* fall through */ 664 /* fall through */
670 case e1000_82571: 665 default:
671 case e1000_82572: 666 /* Auto read done will delay 5ms or poll based on mac type */
672 case e1000_ich8lan:
673 case e1000_80003es2lan:
674 ret_val = e1000_get_auto_rd_done(hw); 667 ret_val = e1000_get_auto_rd_done(hw);
675 if (ret_val) 668 if (ret_val)
676 /* We don't want to continue accessing MAC registers. */
677 return ret_val; 669 return ret_val;
678 break; 670 break;
679 default:
680 /* Wait for EEPROM reload (it happens automatically) */
681 msleep(5);
682 break;
683 } 671 }
684 672
685 /* Disable HW ARPs on ASF enabled adapters */ 673 /* Disable HW ARPs on ASF enabled adapters */
@@ -722,6 +710,123 @@ e1000_reset_hw(struct e1000_hw *hw)
722} 710}
723 711
724/****************************************************************************** 712/******************************************************************************
713 *
714 * Initialize a number of hardware-dependent bits
715 *
716 * hw: Struct containing variables accessed by shared code
717 *
718 * This function contains hardware limitation workarounds for PCI-E adapters
719 *
720 *****************************************************************************/
721static void
722e1000_initialize_hardware_bits(struct e1000_hw *hw)
723{
724 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
725 /* Settings common to all PCI-express silicon */
726 uint32_t reg_ctrl, reg_ctrl_ext;
727 uint32_t reg_tarc0, reg_tarc1;
728 uint32_t reg_tctl;
729 uint32_t reg_txdctl, reg_txdctl1;
730
731 /* link autonegotiation/sync workarounds */
732 reg_tarc0 = E1000_READ_REG(hw, TARC0);
733 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
734
735 /* Enable not-done TX descriptor counting */
736 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
737 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
738 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
739 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
740 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
741 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
742
743 switch (hw->mac_type) {
744 case e1000_82571:
745 case e1000_82572:
746 /* Clear PHY TX compatible mode bits */
747 reg_tarc1 = E1000_READ_REG(hw, TARC1);
748 reg_tarc1 &= ~((1 << 30)|(1 << 29));
749
750 /* link autonegotiation/sync workarounds */
751 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
752
753 /* TX ring control fixes */
754 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
755
756 /* Multiple read bit is reversed polarity */
757 reg_tctl = E1000_READ_REG(hw, TCTL);
758 if (reg_tctl & E1000_TCTL_MULR)
759 reg_tarc1 &= ~(1 << 28);
760 else
761 reg_tarc1 |= (1 << 28);
762
763 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
764 break;
765 case e1000_82573:
766 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
767 reg_ctrl_ext &= ~(1 << 23);
768 reg_ctrl_ext |= (1 << 22);
769
770 /* TX byte count fix */
771 reg_ctrl = E1000_READ_REG(hw, CTRL);
772 reg_ctrl &= ~(1 << 29);
773
774 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
775 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
776 break;
777 case e1000_80003es2lan:
778 /* improve small packet performace for fiber/serdes */
779 if ((hw->media_type == e1000_media_type_fiber) ||
780 (hw->media_type == e1000_media_type_internal_serdes)) {
781 reg_tarc0 &= ~(1 << 20);
782 }
783
784 /* Multiple read bit is reversed polarity */
785 reg_tctl = E1000_READ_REG(hw, TCTL);
786 reg_tarc1 = E1000_READ_REG(hw, TARC1);
787 if (reg_tctl & E1000_TCTL_MULR)
788 reg_tarc1 &= ~(1 << 28);
789 else
790 reg_tarc1 |= (1 << 28);
791
792 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
793 break;
794 case e1000_ich8lan:
795 /* Reduce concurrent DMA requests to 3 from 4 */
796 if ((hw->revision_id < 3) ||
797 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
798 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
799 reg_tarc0 |= ((1 << 29)|(1 << 28));
800
801 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
802 reg_ctrl_ext |= (1 << 22);
803 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
804
805 /* workaround TX hang with TSO=on */
806 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
807
808 /* Multiple read bit is reversed polarity */
809 reg_tctl = E1000_READ_REG(hw, TCTL);
810 reg_tarc1 = E1000_READ_REG(hw, TARC1);
811 if (reg_tctl & E1000_TCTL_MULR)
812 reg_tarc1 &= ~(1 << 28);
813 else
814 reg_tarc1 |= (1 << 28);
815
816 /* workaround TX hang with TSO=on */
817 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
818
819 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
820 break;
821 default:
822 break;
823 }
824
825 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
826 }
827}
828
829/******************************************************************************
725 * Performs basic configuration of the adapter. 830 * Performs basic configuration of the adapter.
726 * 831 *
727 * hw - Struct containing variables accessed by shared code 832 * hw - Struct containing variables accessed by shared code
@@ -749,14 +854,13 @@ e1000_init_hw(struct e1000_hw *hw)
749 DEBUGFUNC("e1000_init_hw"); 854 DEBUGFUNC("e1000_init_hw");
750 855
751 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ 856 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
752 if (hw->mac_type == e1000_ich8lan) { 857 if ((hw->mac_type == e1000_ich8lan) &&
753 reg_data = E1000_READ_REG(hw, TARC0); 858 ((hw->revision_id < 3) ||
754 reg_data |= 0x30000000; 859 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
755 E1000_WRITE_REG(hw, TARC0, reg_data); 860 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
756 861 reg_data = E1000_READ_REG(hw, STATUS);
757 reg_data = E1000_READ_REG(hw, STATUS); 862 reg_data &= ~0x80000000;
758 reg_data &= ~0x80000000; 863 E1000_WRITE_REG(hw, STATUS, reg_data);
759 E1000_WRITE_REG(hw, STATUS, reg_data);
760 } 864 }
761 865
762 /* Initialize Identification LED */ 866 /* Initialize Identification LED */
@@ -769,6 +873,9 @@ e1000_init_hw(struct e1000_hw *hw)
769 /* Set the media type and TBI compatibility */ 873 /* Set the media type and TBI compatibility */
770 e1000_set_media_type(hw); 874 e1000_set_media_type(hw);
771 875
876 /* Must be called after e1000_set_media_type because media_type is used */
877 e1000_initialize_hardware_bits(hw);
878
772 /* Disabling VLAN filtering. */ 879 /* Disabling VLAN filtering. */
773 DEBUGOUT("Initializing the IEEE VLAN\n"); 880 DEBUGOUT("Initializing the IEEE VLAN\n");
774 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 881 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
@@ -860,17 +967,6 @@ e1000_init_hw(struct e1000_hw *hw)
860 if (hw->mac_type > e1000_82544) { 967 if (hw->mac_type > e1000_82544) {
861 ctrl = E1000_READ_REG(hw, TXDCTL); 968 ctrl = E1000_READ_REG(hw, TXDCTL);
862 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 969 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
863 switch (hw->mac_type) {
864 default:
865 break;
866 case e1000_82571:
867 case e1000_82572:
868 case e1000_82573:
869 case e1000_ich8lan:
870 case e1000_80003es2lan:
871 ctrl |= E1000_TXDCTL_COUNT_DESC;
872 break;
873 }
874 E1000_WRITE_REG(hw, TXDCTL, ctrl); 970 E1000_WRITE_REG(hw, TXDCTL, ctrl);
875 } 971 }
876 972
@@ -908,8 +1004,6 @@ e1000_init_hw(struct e1000_hw *hw)
908 case e1000_ich8lan: 1004 case e1000_ich8lan:
909 ctrl = E1000_READ_REG(hw, TXDCTL1); 1005 ctrl = E1000_READ_REG(hw, TXDCTL1);
910 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1006 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
911 if (hw->mac_type >= e1000_82571)
912 ctrl |= E1000_TXDCTL_COUNT_DESC;
913 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1007 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
914 break; 1008 break;
915 } 1009 }
@@ -1018,11 +1112,11 @@ e1000_setup_link(struct e1000_hw *hw)
1018 * control setting, then the variable hw->fc will 1112 * control setting, then the variable hw->fc will
1019 * be initialized based on a value in the EEPROM. 1113 * be initialized based on a value in the EEPROM.
1020 */ 1114 */
1021 if (hw->fc == e1000_fc_default) { 1115 if (hw->fc == E1000_FC_DEFAULT) {
1022 switch (hw->mac_type) { 1116 switch (hw->mac_type) {
1023 case e1000_ich8lan: 1117 case e1000_ich8lan:
1024 case e1000_82573: 1118 case e1000_82573:
1025 hw->fc = e1000_fc_full; 1119 hw->fc = E1000_FC_FULL;
1026 break; 1120 break;
1027 default: 1121 default:
1028 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1122 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
@@ -1032,12 +1126,12 @@ e1000_setup_link(struct e1000_hw *hw)
1032 return -E1000_ERR_EEPROM; 1126 return -E1000_ERR_EEPROM;
1033 } 1127 }
1034 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1128 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1035 hw->fc = e1000_fc_none; 1129 hw->fc = E1000_FC_NONE;
1036 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1130 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1037 EEPROM_WORD0F_ASM_DIR) 1131 EEPROM_WORD0F_ASM_DIR)
1038 hw->fc = e1000_fc_tx_pause; 1132 hw->fc = E1000_FC_TX_PAUSE;
1039 else 1133 else
1040 hw->fc = e1000_fc_full; 1134 hw->fc = E1000_FC_FULL;
1041 break; 1135 break;
1042 } 1136 }
1043 } 1137 }
@@ -1047,10 +1141,10 @@ e1000_setup_link(struct e1000_hw *hw)
1047 * hub or switch with different Flow Control capabilities. 1141 * hub or switch with different Flow Control capabilities.
1048 */ 1142 */
1049 if (hw->mac_type == e1000_82542_rev2_0) 1143 if (hw->mac_type == e1000_82542_rev2_0)
1050 hw->fc &= (~e1000_fc_tx_pause); 1144 hw->fc &= (~E1000_FC_TX_PAUSE);
1051 1145
1052 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 1146 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1053 hw->fc &= (~e1000_fc_rx_pause); 1147 hw->fc &= (~E1000_FC_RX_PAUSE);
1054 1148
1055 hw->original_fc = hw->fc; 1149 hw->original_fc = hw->fc;
1056 1150
@@ -1102,7 +1196,7 @@ e1000_setup_link(struct e1000_hw *hw)
1102 * ability to transmit pause frames in not enabled, then these 1196 * ability to transmit pause frames in not enabled, then these
1103 * registers will be set to 0. 1197 * registers will be set to 0.
1104 */ 1198 */
1105 if (!(hw->fc & e1000_fc_tx_pause)) { 1199 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1106 E1000_WRITE_REG(hw, FCRTL, 0); 1200 E1000_WRITE_REG(hw, FCRTL, 0);
1107 E1000_WRITE_REG(hw, FCRTH, 0); 1201 E1000_WRITE_REG(hw, FCRTH, 0);
1108 } else { 1202 } else {
@@ -1149,11 +1243,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1149 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) 1243 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1150 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1244 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1151 1245
1152 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 1246 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1153 * set when the optics detect a signal. On older adapters, it will be 1247 * set when the optics detect a signal. On older adapters, it will be
1154 * cleared when there is a signal. This applies to fiber media only. 1248 * cleared when there is a signal. This applies to fiber media only.
1155 * If we're on serdes media, adjust the output amplitude to value set in 1249 * If we're on serdes media, adjust the output amplitude to value
1156 * the EEPROM. 1250 * set in the EEPROM.
1157 */ 1251 */
1158 ctrl = E1000_READ_REG(hw, CTRL); 1252 ctrl = E1000_READ_REG(hw, CTRL);
1159 if (hw->media_type == e1000_media_type_fiber) 1253 if (hw->media_type == e1000_media_type_fiber)
@@ -1189,11 +1283,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1189 * 3: Both Rx and TX flow control (symmetric) are enabled. 1283 * 3: Both Rx and TX flow control (symmetric) are enabled.
1190 */ 1284 */
1191 switch (hw->fc) { 1285 switch (hw->fc) {
1192 case e1000_fc_none: 1286 case E1000_FC_NONE:
1193 /* Flow control is completely disabled by a software over-ride. */ 1287 /* Flow control is completely disabled by a software over-ride. */
1194 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1288 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1195 break; 1289 break;
1196 case e1000_fc_rx_pause: 1290 case E1000_FC_RX_PAUSE:
1197 /* RX Flow control is enabled and TX Flow control is disabled by a 1291 /* RX Flow control is enabled and TX Flow control is disabled by a
1198 * software over-ride. Since there really isn't a way to advertise 1292 * software over-ride. Since there really isn't a way to advertise
1199 * that we are capable of RX Pause ONLY, we will advertise that we 1293 * that we are capable of RX Pause ONLY, we will advertise that we
@@ -1202,13 +1296,13 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1202 */ 1296 */
1203 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1297 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1204 break; 1298 break;
1205 case e1000_fc_tx_pause: 1299 case E1000_FC_TX_PAUSE:
1206 /* TX Flow control is enabled, and RX Flow control is disabled, by a 1300 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1207 * software over-ride. 1301 * software over-ride.
1208 */ 1302 */
1209 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1303 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1210 break; 1304 break;
1211 case e1000_fc_full: 1305 case E1000_FC_FULL:
1212 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1306 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1213 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1307 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1214 break; 1308 break;
@@ -2124,13 +2218,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2124 * in the EEPROM is used. 2218 * in the EEPROM is used.
2125 */ 2219 */
2126 switch (hw->fc) { 2220 switch (hw->fc) {
2127 case e1000_fc_none: /* 0 */ 2221 case E1000_FC_NONE: /* 0 */
2128 /* Flow control (RX & TX) is completely disabled by a 2222 /* Flow control (RX & TX) is completely disabled by a
2129 * software over-ride. 2223 * software over-ride.
2130 */ 2224 */
2131 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2225 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2132 break; 2226 break;
2133 case e1000_fc_rx_pause: /* 1 */ 2227 case E1000_FC_RX_PAUSE: /* 1 */
2134 /* RX Flow control is enabled, and TX Flow control is 2228 /* RX Flow control is enabled, and TX Flow control is
2135 * disabled, by a software over-ride. 2229 * disabled, by a software over-ride.
2136 */ 2230 */
@@ -2142,14 +2236,14 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2142 */ 2236 */
2143 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2237 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2144 break; 2238 break;
2145 case e1000_fc_tx_pause: /* 2 */ 2239 case E1000_FC_TX_PAUSE: /* 2 */
2146 /* TX Flow control is enabled, and RX Flow control is 2240 /* TX Flow control is enabled, and RX Flow control is
2147 * disabled, by a software over-ride. 2241 * disabled, by a software over-ride.
2148 */ 2242 */
2149 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2243 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2150 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2244 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2151 break; 2245 break;
2152 case e1000_fc_full: /* 3 */ 2246 case E1000_FC_FULL: /* 3 */
2153 /* Flow control (both RX and TX) is enabled by a software 2247 /* Flow control (both RX and TX) is enabled by a software
2154 * over-ride. 2248 * over-ride.
2155 */ 2249 */
@@ -2193,7 +2287,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2193 DEBUGFUNC("e1000_phy_force_speed_duplex"); 2287 DEBUGFUNC("e1000_phy_force_speed_duplex");
2194 2288
2195 /* Turn off Flow control if we are forcing speed and duplex. */ 2289 /* Turn off Flow control if we are forcing speed and duplex. */
2196 hw->fc = e1000_fc_none; 2290 hw->fc = E1000_FC_NONE;
2197 2291
2198 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2292 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2199 2293
@@ -2547,18 +2641,18 @@ e1000_force_mac_fc(struct e1000_hw *hw)
2547 */ 2641 */
2548 2642
2549 switch (hw->fc) { 2643 switch (hw->fc) {
2550 case e1000_fc_none: 2644 case E1000_FC_NONE:
2551 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 2645 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2552 break; 2646 break;
2553 case e1000_fc_rx_pause: 2647 case E1000_FC_RX_PAUSE:
2554 ctrl &= (~E1000_CTRL_TFCE); 2648 ctrl &= (~E1000_CTRL_TFCE);
2555 ctrl |= E1000_CTRL_RFCE; 2649 ctrl |= E1000_CTRL_RFCE;
2556 break; 2650 break;
2557 case e1000_fc_tx_pause: 2651 case E1000_FC_TX_PAUSE:
2558 ctrl &= (~E1000_CTRL_RFCE); 2652 ctrl &= (~E1000_CTRL_RFCE);
2559 ctrl |= E1000_CTRL_TFCE; 2653 ctrl |= E1000_CTRL_TFCE;
2560 break; 2654 break;
2561 case e1000_fc_full: 2655 case E1000_FC_FULL:
2562 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 2656 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2563 break; 2657 break;
2564 default: 2658 default:
@@ -2657,14 +2751,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2657 * LOCAL DEVICE | LINK PARTNER 2751 * LOCAL DEVICE | LINK PARTNER
2658 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2752 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2659 *-------|---------|-------|---------|-------------------- 2753 *-------|---------|-------|---------|--------------------
2660 * 0 | 0 | DC | DC | e1000_fc_none 2754 * 0 | 0 | DC | DC | E1000_FC_NONE
2661 * 0 | 1 | 0 | DC | e1000_fc_none 2755 * 0 | 1 | 0 | DC | E1000_FC_NONE
2662 * 0 | 1 | 1 | 0 | e1000_fc_none 2756 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2663 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2757 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2664 * 1 | 0 | 0 | DC | e1000_fc_none 2758 * 1 | 0 | 0 | DC | E1000_FC_NONE
2665 * 1 | DC | 1 | DC | e1000_fc_full 2759 * 1 | DC | 1 | DC | E1000_FC_FULL
2666 * 1 | 1 | 0 | 0 | e1000_fc_none 2760 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2667 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2761 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2668 * 2762 *
2669 */ 2763 */
2670 /* Are both PAUSE bits set to 1? If so, this implies 2764 /* Are both PAUSE bits set to 1? If so, this implies
@@ -2676,7 +2770,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2676 * LOCAL DEVICE | LINK PARTNER 2770 * LOCAL DEVICE | LINK PARTNER
2677 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2771 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2678 *-------|---------|-------|---------|-------------------- 2772 *-------|---------|-------|---------|--------------------
2679 * 1 | DC | 1 | DC | e1000_fc_full 2773 * 1 | DC | 1 | DC | E1000_FC_FULL
2680 * 2774 *
2681 */ 2775 */
2682 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2776 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
@@ -2687,11 +2781,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2687 * ONLY. Hence, we must now check to see if we need to 2781 * ONLY. Hence, we must now check to see if we need to
2688 * turn OFF the TRANSMISSION of PAUSE frames. 2782 * turn OFF the TRANSMISSION of PAUSE frames.
2689 */ 2783 */
2690 if (hw->original_fc == e1000_fc_full) { 2784 if (hw->original_fc == E1000_FC_FULL) {
2691 hw->fc = e1000_fc_full; 2785 hw->fc = E1000_FC_FULL;
2692 DEBUGOUT("Flow Control = FULL.\n"); 2786 DEBUGOUT("Flow Control = FULL.\n");
2693 } else { 2787 } else {
2694 hw->fc = e1000_fc_rx_pause; 2788 hw->fc = E1000_FC_RX_PAUSE;
2695 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2789 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2696 } 2790 }
2697 } 2791 }
@@ -2700,14 +2794,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2700 * LOCAL DEVICE | LINK PARTNER 2794 * LOCAL DEVICE | LINK PARTNER
2701 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2795 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2702 *-------|---------|-------|---------|-------------------- 2796 *-------|---------|-------|---------|--------------------
2703 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 2797 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2704 * 2798 *
2705 */ 2799 */
2706 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2800 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2801 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2708 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2802 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2803 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2710 hw->fc = e1000_fc_tx_pause; 2804 hw->fc = E1000_FC_TX_PAUSE;
2711 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2805 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2712 } 2806 }
2713 /* For transmitting PAUSE frames ONLY. 2807 /* For transmitting PAUSE frames ONLY.
@@ -2715,14 +2809,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2715 * LOCAL DEVICE | LINK PARTNER 2809 * LOCAL DEVICE | LINK PARTNER
2716 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2717 *-------|---------|-------|---------|-------------------- 2811 *-------|---------|-------|---------|--------------------
2718 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 2812 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2719 * 2813 *
2720 */ 2814 */
2721 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2815 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2722 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2816 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2723 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2817 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2724 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2818 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2725 hw->fc = e1000_fc_rx_pause; 2819 hw->fc = E1000_FC_RX_PAUSE;
2726 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2820 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2727 } 2821 }
2728 /* Per the IEEE spec, at this point flow control should be 2822 /* Per the IEEE spec, at this point flow control should be
@@ -2745,13 +2839,13 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2745 * be asked to delay transmission of packets than asking 2839 * be asked to delay transmission of packets than asking
2746 * our link partner to pause transmission of frames. 2840 * our link partner to pause transmission of frames.
2747 */ 2841 */
2748 else if ((hw->original_fc == e1000_fc_none || 2842 else if ((hw->original_fc == E1000_FC_NONE ||
2749 hw->original_fc == e1000_fc_tx_pause) || 2843 hw->original_fc == E1000_FC_TX_PAUSE) ||
2750 hw->fc_strict_ieee) { 2844 hw->fc_strict_ieee) {
2751 hw->fc = e1000_fc_none; 2845 hw->fc = E1000_FC_NONE;
2752 DEBUGOUT("Flow Control = NONE.\n"); 2846 DEBUGOUT("Flow Control = NONE.\n");
2753 } else { 2847 } else {
2754 hw->fc = e1000_fc_rx_pause; 2848 hw->fc = E1000_FC_RX_PAUSE;
2755 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2849 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2756 } 2850 }
2757 2851
@@ -2766,7 +2860,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
2766 } 2860 }
2767 2861
2768 if (duplex == HALF_DUPLEX) 2862 if (duplex == HALF_DUPLEX)
2769 hw->fc = e1000_fc_none; 2863 hw->fc = E1000_FC_NONE;
2770 2864
2771 /* Now we call a subroutine to actually force the MAC 2865 /* Now we call a subroutine to actually force the MAC
2772 * controller to use the correct flow control settings. 2866 * controller to use the correct flow control settings.
@@ -3417,9 +3511,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3417 return ret_val; 3511 return ret_val;
3418} 3512}
3419 3513
3420int32_t 3514static int32_t
3421e1000_read_phy_reg_ex(struct e1000_hw *hw, 3515e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3422 uint32_t reg_addr,
3423 uint16_t *phy_data) 3516 uint16_t *phy_data)
3424{ 3517{
3425 uint32_t i; 3518 uint32_t i;
@@ -3499,8 +3592,7 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
3499* data - data to write to the PHY 3592* data - data to write to the PHY
3500******************************************************************************/ 3593******************************************************************************/
3501int32_t 3594int32_t
3502e1000_write_phy_reg(struct e1000_hw *hw, 3595e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3503 uint32_t reg_addr,
3504 uint16_t phy_data) 3596 uint16_t phy_data)
3505{ 3597{
3506 uint32_t ret_val; 3598 uint32_t ret_val;
@@ -3557,10 +3649,9 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3557 return ret_val; 3649 return ret_val;
3558} 3650}
3559 3651
3560int32_t 3652static int32_t
3561e1000_write_phy_reg_ex(struct e1000_hw *hw, 3653e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3562 uint32_t reg_addr, 3654 uint16_t phy_data)
3563 uint16_t phy_data)
3564{ 3655{
3565 uint32_t i; 3656 uint32_t i;
3566 uint32_t mdic = 0; 3657 uint32_t mdic = 0;
@@ -3711,7 +3802,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3711 swfw = E1000_SWFW_PHY0_SM; 3802 swfw = E1000_SWFW_PHY0_SM;
3712 } 3803 }
3713 if (e1000_swfw_sync_acquire(hw, swfw)) { 3804 if (e1000_swfw_sync_acquire(hw, swfw)) {
3714 e1000_release_software_semaphore(hw); 3805 DEBUGOUT("Unable to acquire swfw sync\n");
3715 return -E1000_ERR_SWFW_SYNC; 3806 return -E1000_ERR_SWFW_SYNC;
3716 } 3807 }
3717 /* Read the device control register and assert the E1000_CTRL_PHY_RST 3808 /* Read the device control register and assert the E1000_CTRL_PHY_RST
@@ -3734,6 +3825,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3734 3825
3735 if (hw->mac_type >= e1000_82571) 3826 if (hw->mac_type >= e1000_82571)
3736 mdelay(10); 3827 mdelay(10);
3828
3737 e1000_swfw_sync_release(hw, swfw); 3829 e1000_swfw_sync_release(hw, swfw);
3738 } else { 3830 } else {
3739 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3831 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3792,15 +3884,14 @@ e1000_phy_reset(struct e1000_hw *hw)
3792 if (ret_val) 3884 if (ret_val)
3793 return E1000_SUCCESS; 3885 return E1000_SUCCESS;
3794 3886
3795 switch (hw->mac_type) { 3887 switch (hw->phy_type) {
3796 case e1000_82541_rev_2: 3888 case e1000_phy_igp:
3797 case e1000_82571: 3889 case e1000_phy_igp_2:
3798 case e1000_82572: 3890 case e1000_phy_igp_3:
3799 case e1000_ich8lan: 3891 case e1000_phy_ife:
3800 ret_val = e1000_phy_hw_reset(hw); 3892 ret_val = e1000_phy_hw_reset(hw);
3801 if (ret_val) 3893 if (ret_val)
3802 return ret_val; 3894 return ret_val;
3803
3804 break; 3895 break;
3805 default: 3896 default:
3806 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3897 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3936,7 +4027,7 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3936* 4027*
3937* hw - Struct containing variables accessed by shared code 4028* hw - Struct containing variables accessed by shared code
3938******************************************************************************/ 4029******************************************************************************/
3939int32_t 4030static int32_t
3940e1000_detect_gig_phy(struct e1000_hw *hw) 4031e1000_detect_gig_phy(struct e1000_hw *hw)
3941{ 4032{
3942 int32_t phy_init_status, ret_val; 4033 int32_t phy_init_status, ret_val;
@@ -3945,6 +4036,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3945 4036
3946 DEBUGFUNC("e1000_detect_gig_phy"); 4037 DEBUGFUNC("e1000_detect_gig_phy");
3947 4038
4039 if (hw->phy_id != 0)
4040 return E1000_SUCCESS;
4041
3948 /* The 82571 firmware may still be configuring the PHY. In this 4042 /* The 82571 firmware may still be configuring the PHY. In this
3949 * case, we cannot access the PHY until the configuration is done. So 4043 * case, we cannot access the PHY until the configuration is done. So
3950 * we explicitly set the PHY values. */ 4044 * we explicitly set the PHY values. */
@@ -4061,7 +4155,8 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4061 struct e1000_phy_info *phy_info) 4155 struct e1000_phy_info *phy_info)
4062{ 4156{
4063 int32_t ret_val; 4157 int32_t ret_val;
4064 uint16_t phy_data, polarity, min_length, max_length, average; 4158 uint16_t phy_data, min_length, max_length, average;
4159 e1000_rev_polarity polarity;
4065 4160
4066 DEBUGFUNC("e1000_phy_igp_get_info"); 4161 DEBUGFUNC("e1000_phy_igp_get_info");
4067 4162
@@ -4086,8 +4181,8 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4086 if (ret_val) 4181 if (ret_val)
4087 return ret_val; 4182 return ret_val;
4088 4183
4089 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> 4184 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4090 IGP01E1000_PSSR_MDIX_SHIFT; 4185 IGP01E1000_PSSR_MDIX_SHIFT);
4091 4186
4092 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 4187 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4093 IGP01E1000_PSSR_SPEED_1000MBPS) { 4188 IGP01E1000_PSSR_SPEED_1000MBPS) {
@@ -4096,10 +4191,12 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
4096 if (ret_val) 4191 if (ret_val)
4097 return ret_val; 4192 return ret_val;
4098 4193
4099 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4194 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4100 SR_1000T_LOCAL_RX_STATUS_SHIFT; 4195 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4101 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> 4196 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4102 SR_1000T_REMOTE_RX_STATUS_SHIFT; 4197 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4198 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4199 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4103 4200
4104 /* Get cable length */ 4201 /* Get cable length */
4105 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 4202 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
@@ -4135,7 +4232,8 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4135 struct e1000_phy_info *phy_info) 4232 struct e1000_phy_info *phy_info)
4136{ 4233{
4137 int32_t ret_val; 4234 int32_t ret_val;
4138 uint16_t phy_data, polarity; 4235 uint16_t phy_data;
4236 e1000_rev_polarity polarity;
4139 4237
4140 DEBUGFUNC("e1000_phy_ife_get_info"); 4238 DEBUGFUNC("e1000_phy_ife_get_info");
4141 4239
@@ -4146,8 +4244,9 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4146 if (ret_val) 4244 if (ret_val)
4147 return ret_val; 4245 return ret_val;
4148 phy_info->polarity_correction = 4246 phy_info->polarity_correction =
4149 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> 4247 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4150 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT; 4248 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4249 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4151 4250
4152 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { 4251 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4153 ret_val = e1000_check_polarity(hw, &polarity); 4252 ret_val = e1000_check_polarity(hw, &polarity);
@@ -4155,8 +4254,9 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4155 return ret_val; 4254 return ret_val;
4156 } else { 4255 } else {
4157 /* Polarity is forced. */ 4256 /* Polarity is forced. */
4158 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >> 4257 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4159 IFE_PSC_FORCE_POLARITY_SHIFT; 4258 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4259 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4160 } 4260 }
4161 phy_info->cable_polarity = polarity; 4261 phy_info->cable_polarity = polarity;
4162 4262
@@ -4164,9 +4264,9 @@ e1000_phy_ife_get_info(struct e1000_hw *hw,
4164 if (ret_val) 4264 if (ret_val)
4165 return ret_val; 4265 return ret_val;
4166 4266
4167 phy_info->mdix_mode = 4267 phy_info->mdix_mode = (e1000_auto_x_mode)
4168 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> 4268 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4169 IFE_PMC_MDIX_MODE_SHIFT; 4269 IFE_PMC_MDIX_MODE_SHIFT);
4170 4270
4171 return E1000_SUCCESS; 4271 return E1000_SUCCESS;
4172} 4272}
@@ -4182,7 +4282,8 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4182 struct e1000_phy_info *phy_info) 4282 struct e1000_phy_info *phy_info)
4183{ 4283{
4184 int32_t ret_val; 4284 int32_t ret_val;
4185 uint16_t phy_data, polarity; 4285 uint16_t phy_data;
4286 e1000_rev_polarity polarity;
4186 4287
4187 DEBUGFUNC("e1000_phy_m88_get_info"); 4288 DEBUGFUNC("e1000_phy_m88_get_info");
4188 4289
@@ -4195,11 +4296,14 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4195 return ret_val; 4296 return ret_val;
4196 4297
4197 phy_info->extended_10bt_distance = 4298 phy_info->extended_10bt_distance =
4198 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 4299 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4199 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; 4300 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4301 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4302
4200 phy_info->polarity_correction = 4303 phy_info->polarity_correction =
4201 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 4304 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4202 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; 4305 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4306 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4203 4307
4204 /* Check polarity status */ 4308 /* Check polarity status */
4205 ret_val = e1000_check_polarity(hw, &polarity); 4309 ret_val = e1000_check_polarity(hw, &polarity);
@@ -4211,15 +4315,15 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4211 if (ret_val) 4315 if (ret_val)
4212 return ret_val; 4316 return ret_val;
4213 4317
4214 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> 4318 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4215 M88E1000_PSSR_MDIX_SHIFT; 4319 M88E1000_PSSR_MDIX_SHIFT);
4216 4320
4217 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 4321 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4218 /* Cable Length Estimation and Local/Remote Receiver Information 4322 /* Cable Length Estimation and Local/Remote Receiver Information
4219 * are only valid at 1000 Mbps. 4323 * are only valid at 1000 Mbps.
4220 */ 4324 */
4221 if (hw->phy_type != e1000_phy_gg82563) { 4325 if (hw->phy_type != e1000_phy_gg82563) {
4222 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4326 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4223 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 4327 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4224 } else { 4328 } else {
4225 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 4329 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
@@ -4227,18 +4331,20 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
4227 if (ret_val) 4331 if (ret_val)
4228 return ret_val; 4332 return ret_val;
4229 4333
4230 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 4334 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4231 } 4335 }
4232 4336
4233 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 4337 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4234 if (ret_val) 4338 if (ret_val)
4235 return ret_val; 4339 return ret_val;
4236 4340
4237 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> 4341 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4238 SR_1000T_LOCAL_RX_STATUS_SHIFT; 4342 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4343 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4344 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4345 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4346 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4239 4347
4240 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4241 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4242 } 4348 }
4243 4349
4244 return E1000_SUCCESS; 4350 return E1000_SUCCESS;
@@ -4441,7 +4547,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4441 eeprom->use_eewr = FALSE; 4547 eeprom->use_eewr = FALSE;
4442 break; 4548 break;
4443 case e1000_ich8lan: 4549 case e1000_ich8lan:
4444 { 4550 {
4445 int32_t i = 0; 4551 int32_t i = 0;
4446 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG); 4552 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4447 4553
@@ -4468,7 +4574,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4468 hw->flash_bank_size /= 2 * sizeof(uint16_t); 4574 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4469 4575
4470 break; 4576 break;
4471 } 4577 }
4472 default: 4578 default:
4473 break; 4579 break;
4474 } 4580 }
@@ -4800,7 +4906,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
4800 * 4906 *
4801 * hw - Struct containing variables accessed by shared code 4907 * hw - Struct containing variables accessed by shared code
4802 *****************************************************************************/ 4908 *****************************************************************************/
4803int32_t 4909static int32_t
4804e1000_spi_eeprom_ready(struct e1000_hw *hw) 4910e1000_spi_eeprom_ready(struct e1000_hw *hw)
4805{ 4911{
4806 uint16_t retry_count = 0; 4912 uint16_t retry_count = 0;
@@ -4854,44 +4960,43 @@ e1000_read_eeprom(struct e1000_hw *hw,
4854{ 4960{
4855 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4961 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4856 uint32_t i = 0; 4962 uint32_t i = 0;
4857 int32_t ret_val;
4858 4963
4859 DEBUGFUNC("e1000_read_eeprom"); 4964 DEBUGFUNC("e1000_read_eeprom");
4860 4965
4966 /* If eeprom is not yet detected, do so now */
4967 if (eeprom->word_size == 0)
4968 e1000_init_eeprom_params(hw);
4969
4861 /* A check for invalid values: offset too large, too many words, and not 4970 /* A check for invalid values: offset too large, too many words, and not
4862 * enough words. 4971 * enough words.
4863 */ 4972 */
4864 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4973 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4865 (words == 0)) { 4974 (words == 0)) {
4866 DEBUGOUT("\"words\" parameter out of bounds\n"); 4975 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
4867 return -E1000_ERR_EEPROM; 4976 return -E1000_ERR_EEPROM;
4868 } 4977 }
4869 4978
4870 /* FLASH reads without acquiring the semaphore are safe */ 4979 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4980 * directly. In this case, we need to acquire the EEPROM so that
4981 * FW or other port software does not interrupt.
4982 */
4871 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && 4983 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4872 hw->eeprom.use_eerd == FALSE) { 4984 hw->eeprom.use_eerd == FALSE) {
4873 switch (hw->mac_type) { 4985 /* Prepare the EEPROM for bit-bang reading */
4874 case e1000_80003es2lan: 4986 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4875 break; 4987 return -E1000_ERR_EEPROM;
4876 default:
4877 /* Prepare the EEPROM for reading */
4878 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4879 return -E1000_ERR_EEPROM;
4880 break;
4881 }
4882 } 4988 }
4883 4989
4884 if (eeprom->use_eerd == TRUE) { 4990 /* Eerd register EEPROM access requires no eeprom aquire/release */
4885 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); 4991 if (eeprom->use_eerd == TRUE)
4886 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || 4992 return e1000_read_eeprom_eerd(hw, offset, words, data);
4887 (hw->mac_type != e1000_82573))
4888 e1000_release_eeprom(hw);
4889 return ret_val;
4890 }
4891 4993
4994 /* ICH EEPROM access is done via the ICH flash controller */
4892 if (eeprom->type == e1000_eeprom_ich8) 4995 if (eeprom->type == e1000_eeprom_ich8)
4893 return e1000_read_eeprom_ich8(hw, offset, words, data); 4996 return e1000_read_eeprom_ich8(hw, offset, words, data);
4894 4997
4998 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
4999 * acquired the EEPROM at this point, so any returns should relase it */
4895 if (eeprom->type == e1000_eeprom_spi) { 5000 if (eeprom->type == e1000_eeprom_spi) {
4896 uint16_t word_in; 5001 uint16_t word_in;
4897 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 5002 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
@@ -5206,6 +5311,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
5206 5311
5207 DEBUGFUNC("e1000_write_eeprom"); 5312 DEBUGFUNC("e1000_write_eeprom");
5208 5313
5314 /* If eeprom is not yet detected, do so now */
5315 if (eeprom->word_size == 0)
5316 e1000_init_eeprom_params(hw);
5317
5209 /* A check for invalid values: offset too large, too many words, and not 5318 /* A check for invalid values: offset too large, too many words, and not
5210 * enough words. 5319 * enough words.
5211 */ 5320 */
@@ -5248,7 +5357,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
5248 * data - pointer to array of 8 bit words to be written to the EEPROM 5357 * data - pointer to array of 8 bit words to be written to the EEPROM
5249 * 5358 *
5250 *****************************************************************************/ 5359 *****************************************************************************/
5251int32_t 5360static int32_t
5252e1000_write_eeprom_spi(struct e1000_hw *hw, 5361e1000_write_eeprom_spi(struct e1000_hw *hw,
5253 uint16_t offset, 5362 uint16_t offset,
5254 uint16_t words, 5363 uint16_t words,
@@ -5314,7 +5423,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
5314 * data - pointer to array of 16 bit words to be written to the EEPROM 5423 * data - pointer to array of 16 bit words to be written to the EEPROM
5315 * 5424 *
5316 *****************************************************************************/ 5425 *****************************************************************************/
5317int32_t 5426static int32_t
5318e1000_write_eeprom_microwire(struct e1000_hw *hw, 5427e1000_write_eeprom_microwire(struct e1000_hw *hw,
5319 uint16_t offset, 5428 uint16_t offset,
5320 uint16_t words, 5429 uint16_t words,
@@ -5411,10 +5520,8 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5411 int32_t error = E1000_SUCCESS; 5520 int32_t error = E1000_SUCCESS;
5412 uint32_t old_bank_offset = 0; 5521 uint32_t old_bank_offset = 0;
5413 uint32_t new_bank_offset = 0; 5522 uint32_t new_bank_offset = 0;
5414 uint32_t sector_retries = 0;
5415 uint8_t low_byte = 0; 5523 uint8_t low_byte = 0;
5416 uint8_t high_byte = 0; 5524 uint8_t high_byte = 0;
5417 uint8_t temp_byte = 0;
5418 boolean_t sector_write_failed = FALSE; 5525 boolean_t sector_write_failed = FALSE;
5419 5526
5420 if (hw->mac_type == e1000_82573) { 5527 if (hw->mac_type == e1000_82573) {
@@ -5467,41 +5574,46 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5467 e1000_erase_ich8_4k_segment(hw, 0); 5574 e1000_erase_ich8_4k_segment(hw, 0);
5468 } 5575 }
5469 5576
5470 do { 5577 sector_write_failed = FALSE;
5471 sector_write_failed = FALSE; 5578 /* Loop for every byte in the shadow RAM,
5472 /* Loop for every byte in the shadow RAM, 5579 * which is in units of words. */
5473 * which is in units of words. */ 5580 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5474 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5581 /* Determine whether to write the value stored
5475 /* Determine whether to write the value stored 5582 * in the other NVM bank or a modified value stored
5476 * in the other NVM bank or a modified value stored 5583 * in the shadow RAM */
5477 * in the shadow RAM */ 5584 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5478 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 5585 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5479 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; 5586 udelay(100);
5480 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, 5587 error = e1000_verify_write_ich8_byte(hw,
5481 &temp_byte); 5588 (i << 1) + new_bank_offset, low_byte);
5482 udelay(100); 5589
5483 error = e1000_verify_write_ich8_byte(hw, 5590 if (error != E1000_SUCCESS)
5484 (i << 1) + new_bank_offset, 5591 sector_write_failed = TRUE;
5485 low_byte); 5592 else {
5486 if (error != E1000_SUCCESS)
5487 sector_write_failed = TRUE;
5488 high_byte = 5593 high_byte =
5489 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); 5594 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5490 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5491 &temp_byte);
5492 udelay(100);
5493 } else {
5494 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5495 &low_byte);
5496 udelay(100); 5595 udelay(100);
5497 error = e1000_verify_write_ich8_byte(hw, 5596 }
5498 (i << 1) + new_bank_offset, low_byte); 5597 } else {
5499 if (error != E1000_SUCCESS) 5598 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5500 sector_write_failed = TRUE; 5599 &low_byte);
5600 udelay(100);
5601 error = e1000_verify_write_ich8_byte(hw,
5602 (i << 1) + new_bank_offset, low_byte);
5603
5604 if (error != E1000_SUCCESS)
5605 sector_write_failed = TRUE;
5606 else {
5501 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, 5607 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5502 &high_byte); 5608 &high_byte);
5609 udelay(100);
5503 } 5610 }
5611 }
5504 5612
5613 /* If the write of the low byte was successful, go ahread and
5614 * write the high byte while checking to make sure that if it
5615 * is the signature byte, then it is handled properly */
5616 if (sector_write_failed == FALSE) {
5505 /* If the word is 0x13, then make sure the signature bits 5617 /* If the word is 0x13, then make sure the signature bits
5506 * (15:14) are 11b until the commit has completed. 5618 * (15:14) are 11b until the commit has completed.
5507 * This will allow us to write 10b which indicates the 5619 * This will allow us to write 10b which indicates the
@@ -5512,45 +5624,45 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5512 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte; 5624 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5513 5625
5514 error = e1000_verify_write_ich8_byte(hw, 5626 error = e1000_verify_write_ich8_byte(hw,
5515 (i << 1) + new_bank_offset + 1, high_byte); 5627 (i << 1) + new_bank_offset + 1, high_byte);
5516 if (error != E1000_SUCCESS) 5628 if (error != E1000_SUCCESS)
5517 sector_write_failed = TRUE; 5629 sector_write_failed = TRUE;
5518 5630
5519 if (sector_write_failed == FALSE) { 5631 } else {
5520 /* Clear the now not used entry in the cache */ 5632 /* If the write failed then break from the loop and
5521 hw->eeprom_shadow_ram[i].modified = FALSE; 5633 * return an error */
5522 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 5634 break;
5523 }
5524 } 5635 }
5636 }
5525 5637
5526 /* Don't bother writing the segment valid bits if sector 5638 /* Don't bother writing the segment valid bits if sector
5527 * programming failed. */ 5639 * programming failed. */
5528 if (sector_write_failed == FALSE) { 5640 if (sector_write_failed == FALSE) {
5529 /* Finally validate the new segment by setting bit 15:14 5641 /* Finally validate the new segment by setting bit 15:14
5530 * to 10b in word 0x13 , this can be done without an 5642 * to 10b in word 0x13 , this can be done without an
5531 * erase as well since these bits are 11 to start with 5643 * erase as well since these bits are 11 to start with
5532 * and we need to change bit 14 to 0b */ 5644 * and we need to change bit 14 to 0b */
5533 e1000_read_ich8_byte(hw, 5645 e1000_read_ich8_byte(hw,
5534 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5646 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5535 &high_byte); 5647 &high_byte);
5536 high_byte &= 0xBF; 5648 high_byte &= 0xBF;
5649 error = e1000_verify_write_ich8_byte(hw,
5650 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5651 /* And invalidate the previously valid segment by setting
5652 * its signature word (0x13) high_byte to 0b. This can be
5653 * done without an erase because flash erase sets all bits
5654 * to 1's. We can write 1's to 0's without an erase */
5655 if (error == E1000_SUCCESS) {
5537 error = e1000_verify_write_ich8_byte(hw, 5656 error = e1000_verify_write_ich8_byte(hw,
5538 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 5657 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5539 high_byte); 5658 }
5540 if (error != E1000_SUCCESS)
5541 sector_write_failed = TRUE;
5542 5659
5543 /* And invalidate the previously valid segment by setting 5660 /* Clear the now not used entry in the cache */
5544 * its signature word (0x13) high_byte to 0b. This can be 5661 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5545 * done without an erase because flash erase sets all bits 5662 hw->eeprom_shadow_ram[i].modified = FALSE;
5546 * to 1's. We can write 1's to 0's without an erase */ 5663 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5547 error = e1000_verify_write_ich8_byte(hw,
5548 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5549 0);
5550 if (error != E1000_SUCCESS)
5551 sector_write_failed = TRUE;
5552 } 5664 }
5553 } while (++sector_retries < 10 && sector_write_failed == TRUE); 5665 }
5554 } 5666 }
5555 5667
5556 return error; 5668 return error;
@@ -5640,99 +5752,6 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5640} 5752}
5641 5753
5642/****************************************************************************** 5754/******************************************************************************
5643 * Updates the MAC's list of multicast addresses.
5644 *
5645 * hw - Struct containing variables accessed by shared code
5646 * mc_addr_list - the list of new multicast addresses
5647 * mc_addr_count - number of addresses
5648 * pad - number of bytes between addresses in the list
5649 * rar_used_count - offset where to start adding mc addresses into the RAR's
5650 *
5651 * The given list replaces any existing list. Clears the last 15 receive
5652 * address registers and the multicast table. Uses receive address registers
5653 * for the first 15 multicast addresses, and hashes the rest into the
5654 * multicast table.
5655 *****************************************************************************/
5656#if 0
5657void
5658e1000_mc_addr_list_update(struct e1000_hw *hw,
5659 uint8_t *mc_addr_list,
5660 uint32_t mc_addr_count,
5661 uint32_t pad,
5662 uint32_t rar_used_count)
5663{
5664 uint32_t hash_value;
5665 uint32_t i;
5666 uint32_t num_rar_entry;
5667 uint32_t num_mta_entry;
5668
5669 DEBUGFUNC("e1000_mc_addr_list_update");
5670
5671 /* Set the new number of MC addresses that we are being requested to use. */
5672 hw->num_mc_addrs = mc_addr_count;
5673
5674 /* Clear RAR[1-15] */
5675 DEBUGOUT(" Clearing RAR[1-15]\n");
5676 num_rar_entry = E1000_RAR_ENTRIES;
5677 if (hw->mac_type == e1000_ich8lan)
5678 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5679 /* Reserve a spot for the Locally Administered Address to work around
5680 * an 82571 issue in which a reset on one port will reload the MAC on
5681 * the other port. */
5682 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5683 num_rar_entry -= 1;
5684
5685 for (i = rar_used_count; i < num_rar_entry; i++) {
5686 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5687 E1000_WRITE_FLUSH(hw);
5688 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5689 E1000_WRITE_FLUSH(hw);
5690 }
5691
5692 /* Clear the MTA */
5693 DEBUGOUT(" Clearing MTA\n");
5694 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5695 if (hw->mac_type == e1000_ich8lan)
5696 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5697 for (i = 0; i < num_mta_entry; i++) {
5698 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5699 E1000_WRITE_FLUSH(hw);
5700 }
5701
5702 /* Add the new addresses */
5703 for (i = 0; i < mc_addr_count; i++) {
5704 DEBUGOUT(" Adding the multicast addresses:\n");
5705 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5707 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5708 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5709 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5710 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5711 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5712
5713 hash_value = e1000_hash_mc_addr(hw,
5714 mc_addr_list +
5715 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5716
5717 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5718
5719 /* Place this multicast address in the RAR if there is room, *
5720 * else put it in the MTA
5721 */
5722 if (rar_used_count < num_rar_entry) {
5723 e1000_rar_set(hw,
5724 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5725 rar_used_count);
5726 rar_used_count++;
5727 } else {
5728 e1000_mta_set(hw, hash_value);
5729 }
5730 }
5731 DEBUGOUT("MC Update Complete\n");
5732}
5733#endif /* 0 */
5734
5735/******************************************************************************
5736 * Hashes an address to determine its location in the multicast table 5755 * Hashes an address to determine its location in the multicast table
5737 * 5756 *
5738 * hw - Struct containing variables accessed by shared code 5757 * hw - Struct containing variables accessed by shared code
@@ -6290,7 +6309,7 @@ e1000_led_off(struct e1000_hw *hw)
6290 * 6309 *
6291 * hw - Struct containing variables accessed by shared code 6310 * hw - Struct containing variables accessed by shared code
6292 *****************************************************************************/ 6311 *****************************************************************************/
6293void 6312static void
6294e1000_clear_hw_cntrs(struct e1000_hw *hw) 6313e1000_clear_hw_cntrs(struct e1000_hw *hw)
6295{ 6314{
6296 volatile uint32_t temp; 6315 volatile uint32_t temp;
@@ -6539,6 +6558,8 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
6539void 6558void
6540e1000_get_bus_info(struct e1000_hw *hw) 6559e1000_get_bus_info(struct e1000_hw *hw)
6541{ 6560{
6561 int32_t ret_val;
6562 uint16_t pci_ex_link_status;
6542 uint32_t status; 6563 uint32_t status;
6543 6564
6544 switch (hw->mac_type) { 6565 switch (hw->mac_type) {
@@ -6548,18 +6569,25 @@ e1000_get_bus_info(struct e1000_hw *hw)
6548 hw->bus_speed = e1000_bus_speed_unknown; 6569 hw->bus_speed = e1000_bus_speed_unknown;
6549 hw->bus_width = e1000_bus_width_unknown; 6570 hw->bus_width = e1000_bus_width_unknown;
6550 break; 6571 break;
6572 case e1000_82571:
6551 case e1000_82572: 6573 case e1000_82572:
6552 case e1000_82573: 6574 case e1000_82573:
6575 case e1000_80003es2lan:
6553 hw->bus_type = e1000_bus_type_pci_express; 6576 hw->bus_type = e1000_bus_type_pci_express;
6554 hw->bus_speed = e1000_bus_speed_2500; 6577 hw->bus_speed = e1000_bus_speed_2500;
6555 hw->bus_width = e1000_bus_width_pciex_1; 6578 ret_val = e1000_read_pcie_cap_reg(hw,
6579 PCI_EX_LINK_STATUS,
6580 &pci_ex_link_status);
6581 if (ret_val)
6582 hw->bus_width = e1000_bus_width_unknown;
6583 else
6584 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6585 PCI_EX_LINK_WIDTH_SHIFT;
6556 break; 6586 break;
6557 case e1000_82571:
6558 case e1000_ich8lan: 6587 case e1000_ich8lan:
6559 case e1000_80003es2lan:
6560 hw->bus_type = e1000_bus_type_pci_express; 6588 hw->bus_type = e1000_bus_type_pci_express;
6561 hw->bus_speed = e1000_bus_speed_2500; 6589 hw->bus_speed = e1000_bus_speed_2500;
6562 hw->bus_width = e1000_bus_width_pciex_4; 6590 hw->bus_width = e1000_bus_width_pciex_1;
6563 break; 6591 break;
6564 default: 6592 default:
6565 status = E1000_READ_REG(hw, STATUS); 6593 status = E1000_READ_REG(hw, STATUS);
@@ -6593,25 +6621,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
6593 break; 6621 break;
6594 } 6622 }
6595} 6623}
6596/******************************************************************************
6597 * Reads a value from one of the devices registers using port I/O (as opposed
6598 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6599 *
6600 * hw - Struct containing variables accessed by shared code
6601 * offset - offset to read from
6602 *****************************************************************************/
6603#if 0
6604uint32_t
6605e1000_read_reg_io(struct e1000_hw *hw,
6606 uint32_t offset)
6607{
6608 unsigned long io_addr = hw->io_base;
6609 unsigned long io_data = hw->io_base + 4;
6610
6611 e1000_io_write(hw, io_addr, offset);
6612 return e1000_io_read(hw, io_data);
6613}
6614#endif /* 0 */
6615 6624
6616/****************************************************************************** 6625/******************************************************************************
6617 * Writes a value to one of the devices registers using port I/O (as opposed to 6626 * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -6633,7 +6642,6 @@ e1000_write_reg_io(struct e1000_hw *hw,
6633 e1000_io_write(hw, io_data, value); 6642 e1000_io_write(hw, io_data, value);
6634} 6643}
6635 6644
6636
6637/****************************************************************************** 6645/******************************************************************************
6638 * Estimates the cable length. 6646 * Estimates the cable length.
6639 * 6647 *
@@ -6842,7 +6850,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
6842 *****************************************************************************/ 6850 *****************************************************************************/
6843static int32_t 6851static int32_t
6844e1000_check_polarity(struct e1000_hw *hw, 6852e1000_check_polarity(struct e1000_hw *hw,
6845 uint16_t *polarity) 6853 e1000_rev_polarity *polarity)
6846{ 6854{
6847 int32_t ret_val; 6855 int32_t ret_val;
6848 uint16_t phy_data; 6856 uint16_t phy_data;
@@ -6856,8 +6864,10 @@ e1000_check_polarity(struct e1000_hw *hw,
6856 &phy_data); 6864 &phy_data);
6857 if (ret_val) 6865 if (ret_val)
6858 return ret_val; 6866 return ret_val;
6859 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6867 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6860 M88E1000_PSSR_REV_POLARITY_SHIFT; 6868 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6869 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6870
6861 } else if (hw->phy_type == e1000_phy_igp || 6871 } else if (hw->phy_type == e1000_phy_igp ||
6862 hw->phy_type == e1000_phy_igp_3 || 6872 hw->phy_type == e1000_phy_igp_3 ||
6863 hw->phy_type == e1000_phy_igp_2) { 6873 hw->phy_type == e1000_phy_igp_2) {
@@ -6879,19 +6889,22 @@ e1000_check_polarity(struct e1000_hw *hw,
6879 return ret_val; 6889 return ret_val;
6880 6890
6881 /* Check the polarity bits */ 6891 /* Check the polarity bits */
6882 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; 6892 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6893 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6883 } else { 6894 } else {
6884 /* For 10 Mbps, read the polarity bit in the status register. (for 6895 /* For 10 Mbps, read the polarity bit in the status register. (for
6885 * 100 Mbps this bit is always 0) */ 6896 * 100 Mbps this bit is always 0) */
6886 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6897 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6898 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6887 } 6899 }
6888 } else if (hw->phy_type == e1000_phy_ife) { 6900 } else if (hw->phy_type == e1000_phy_ife) {
6889 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, 6901 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6890 &phy_data); 6902 &phy_data);
6891 if (ret_val) 6903 if (ret_val)
6892 return ret_val; 6904 return ret_val;
6893 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >> 6905 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6894 IFE_PESC_POLARITY_REVERSED_SHIFT; 6906 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6907 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6895 } 6908 }
6896 return E1000_SUCCESS; 6909 return E1000_SUCCESS;
6897} 6910}
@@ -7259,7 +7272,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
7259 } else if (hw->smart_speed == e1000_smart_speed_off) { 7272 } else if (hw->smart_speed == e1000_smart_speed_off) {
7260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7273 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7261 &phy_data); 7274 &phy_data);
7262 if (ret_val) 7275 if (ret_val)
7263 return ret_val; 7276 return ret_val;
7264 7277
7265 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7278 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
@@ -7369,7 +7382,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
7369 } else if (hw->smart_speed == e1000_smart_speed_off) { 7382 } else if (hw->smart_speed == e1000_smart_speed_off) {
7370 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 7383 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7371 &phy_data); 7384 &phy_data);
7372 if (ret_val) 7385 if (ret_val)
7373 return ret_val; 7386 return ret_val;
7374 7387
7375 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 7388 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
@@ -7475,7 +7488,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
7475 * 7488 *
7476 * returns: - E1000_SUCCESS . 7489 * returns: - E1000_SUCCESS .
7477 ****************************************************************************/ 7490 ****************************************************************************/
7478int32_t 7491static int32_t
7479e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) 7492e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7480{ 7493{
7481 uint8_t i; 7494 uint8_t i;
@@ -7686,7 +7699,7 @@ e1000_check_mng_mode(struct e1000_hw *hw)
7686 ****************************************************************************/ 7699 ****************************************************************************/
7687int32_t 7700int32_t
7688e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, 7701e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7689 uint16_t length) 7702 uint16_t length)
7690{ 7703{
7691 int32_t ret_val; 7704 int32_t ret_val;
7692 struct e1000_host_mng_command_header hdr; 7705 struct e1000_host_mng_command_header hdr;
@@ -7716,7 +7729,7 @@ e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7716 * 7729 *
7717 * returns - checksum of buffer contents. 7730 * returns - checksum of buffer contents.
7718 ****************************************************************************/ 7731 ****************************************************************************/
7719uint8_t 7732static uint8_t
7720e1000_calculate_mng_checksum(char *buffer, uint32_t length) 7733e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7721{ 7734{
7722 uint8_t sum = 0; 7735 uint8_t sum = 0;
@@ -7914,32 +7927,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7914 E1000_WRITE_REG(hw, CTRL, ctrl); 7927 E1000_WRITE_REG(hw, CTRL, ctrl);
7915} 7928}
7916 7929
7917/***************************************************************************
7918 *
7919 * Enables PCI-Express master access.
7920 *
7921 * hw: Struct containing variables accessed by shared code
7922 *
7923 * returns: - none.
7924 *
7925 ***************************************************************************/
7926#if 0
7927void
7928e1000_enable_pciex_master(struct e1000_hw *hw)
7929{
7930 uint32_t ctrl;
7931
7932 DEBUGFUNC("e1000_enable_pciex_master");
7933
7934 if (hw->bus_type != e1000_bus_type_pci_express)
7935 return;
7936
7937 ctrl = E1000_READ_REG(hw, CTRL);
7938 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7939 E1000_WRITE_REG(hw, CTRL, ctrl);
7940}
7941#endif /* 0 */
7942
7943/******************************************************************************* 7930/*******************************************************************************
7944 * 7931 *
7945 * Disables PCI-Express master access and verifies there are no pending requests 7932 * Disables PCI-Express master access and verifies there are no pending requests
@@ -8063,7 +8050,6 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
8063 msleep(1); 8050 msleep(1);
8064 timeout--; 8051 timeout--;
8065 } 8052 }
8066
8067 if (!timeout) { 8053 if (!timeout) {
8068 DEBUGOUT("MNG configuration cycle has not completed.\n"); 8054 DEBUGOUT("MNG configuration cycle has not completed.\n");
8069 return -E1000_ERR_RESET; 8055 return -E1000_ERR_RESET;
@@ -8172,8 +8158,9 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
8172 8158
8173 DEBUGFUNC("e1000_get_software_semaphore"); 8159 DEBUGFUNC("e1000_get_software_semaphore");
8174 8160
8175 if (hw->mac_type != e1000_80003es2lan) 8161 if (hw->mac_type != e1000_80003es2lan) {
8176 return E1000_SUCCESS; 8162 return E1000_SUCCESS;
8163 }
8177 8164
8178 while (timeout) { 8165 while (timeout) {
8179 swsm = E1000_READ_REG(hw, SWSM); 8166 swsm = E1000_READ_REG(hw, SWSM);
@@ -8206,8 +8193,9 @@ e1000_release_software_semaphore(struct e1000_hw *hw)
8206 8193
8207 DEBUGFUNC("e1000_release_software_semaphore"); 8194 DEBUGFUNC("e1000_release_software_semaphore");
8208 8195
8209 if (hw->mac_type != e1000_80003es2lan) 8196 if (hw->mac_type != e1000_80003es2lan) {
8210 return; 8197 return;
8198 }
8211 8199
8212 swsm = E1000_READ_REG(hw, SWSM); 8200 swsm = E1000_READ_REG(hw, SWSM);
8213 /* Release the SW semaphores.*/ 8201 /* Release the SW semaphores.*/
@@ -8241,7 +8229,7 @@ e1000_check_phy_reset_block(struct e1000_hw *hw)
8241 if (hw->mac_type > e1000_82547_rev_2) 8229 if (hw->mac_type > e1000_82547_rev_2)
8242 manc = E1000_READ_REG(hw, MANC); 8230 manc = E1000_READ_REG(hw, MANC);
8243 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8231 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8244 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8232 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8245} 8233}
8246 8234
8247static uint8_t 8235static uint8_t
@@ -8377,66 +8365,6 @@ e1000_release_software_flag(struct e1000_hw *hw)
8377 return; 8365 return;
8378} 8366}
8379 8367
8380/***************************************************************************
8381 *
8382 * Disable dynamic power down mode in ife PHY.
8383 * It can be used to workaround band-gap problem.
8384 *
8385 * hw: Struct containing variables accessed by shared code
8386 *
8387 ***************************************************************************/
8388#if 0
8389int32_t
8390e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8391{
8392 uint16_t phy_data;
8393 int32_t ret_val = E1000_SUCCESS;
8394
8395 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8396
8397 if (hw->phy_type == e1000_phy_ife) {
8398 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8399 if (ret_val)
8400 return ret_val;
8401
8402 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8403 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8404 }
8405
8406 return ret_val;
8407}
8408#endif /* 0 */
8409
8410/***************************************************************************
8411 *
8412 * Enable dynamic power down mode in ife PHY.
8413 * It can be used to workaround band-gap problem.
8414 *
8415 * hw: Struct containing variables accessed by shared code
8416 *
8417 ***************************************************************************/
8418#if 0
8419int32_t
8420e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8421{
8422 uint16_t phy_data;
8423 int32_t ret_val = E1000_SUCCESS;
8424
8425 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8426
8427 if (hw->phy_type == e1000_phy_ife) {
8428 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8429 if (ret_val)
8430 return ret_val;
8431
8432 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8433 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8434 }
8435
8436 return ret_val;
8437}
8438#endif /* 0 */
8439
8440/****************************************************************************** 8368/******************************************************************************
8441 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 8369 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8442 * register. 8370 * register.
@@ -8832,20 +8760,22 @@ static int32_t
8832e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) 8760e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8833{ 8761{
8834 int32_t error = E1000_SUCCESS; 8762 int32_t error = E1000_SUCCESS;
8835 int32_t program_retries; 8763 int32_t program_retries = 0;
8836 uint8_t temp_byte;
8837 8764
8838 e1000_write_ich8_byte(hw, index, byte); 8765 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8839 udelay(100);
8840 8766
8841 for (program_retries = 0; program_retries < 100; program_retries++) { 8767 error = e1000_write_ich8_byte(hw, index, byte);
8842 e1000_read_ich8_byte(hw, index, &temp_byte); 8768
8843 if (temp_byte == byte) 8769 if (error != E1000_SUCCESS) {
8844 break; 8770 for (program_retries = 0; program_retries < 100; program_retries++) {
8845 udelay(10); 8771 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8846 e1000_write_ich8_byte(hw, index, byte); 8772 error = e1000_write_ich8_byte(hw, index, byte);
8847 udelay(100); 8773 udelay(100);
8774 if (error == E1000_SUCCESS)
8775 break;
8776 }
8848 } 8777 }
8778
8849 if (program_retries == 100) 8779 if (program_retries == 100)
8850 error = E1000_ERR_EEPROM; 8780 error = E1000_ERR_EEPROM;
8851 8781
@@ -8886,39 +8816,27 @@ e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8886} 8816}
8887 8817
8888/****************************************************************************** 8818/******************************************************************************
8889 * Writes a word to the NVM using the ICH8 flash access registers. 8819 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8820 * based.
8890 * 8821 *
8891 * hw - pointer to e1000_hw structure 8822 * hw - pointer to e1000_hw structure
8892 * index - The starting byte index of the word to read. 8823 * bank - 0 for first bank, 1 for second bank
8893 * data - The word to write to the NVM.
8894 *****************************************************************************/
8895#if 0
8896int32_t
8897e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8898{
8899 int32_t status = E1000_SUCCESS;
8900 status = e1000_write_ich8_data(hw, index, 2, data);
8901 return status;
8902}
8903#endif /* 0 */
8904
8905/******************************************************************************
8906 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8907 * segment N is 4096 * N + flash_reg_addr.
8908 * 8824 *
8909 * hw - pointer to e1000_hw structure 8825 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8910 * segment - 0 for first segment, 1 for second segment, etc. 8826 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8827 * bank size may be 4, 8 or 64 KBytes
8911 *****************************************************************************/ 8828 *****************************************************************************/
8912static int32_t 8829int32_t
8913e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment) 8830e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8914{ 8831{
8915 union ich8_hws_flash_status hsfsts; 8832 union ich8_hws_flash_status hsfsts;
8916 union ich8_hws_flash_ctrl hsflctl; 8833 union ich8_hws_flash_ctrl hsflctl;
8917 uint32_t flash_linear_address; 8834 uint32_t flash_linear_address;
8918 int32_t count = 0; 8835 int32_t count = 0;
8919 int32_t error = E1000_ERR_EEPROM; 8836 int32_t error = E1000_ERR_EEPROM;
8920 int32_t iteration, seg_size; 8837 int32_t iteration;
8921 int32_t sector_size; 8838 int32_t sub_sector_size = 0;
8839 int32_t bank_size;
8922 int32_t j = 0; 8840 int32_t j = 0;
8923 int32_t error_flag = 0; 8841 int32_t error_flag = 0;
8924 8842
@@ -8927,22 +8845,27 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8927 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ 8845 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8928 /* 00: The Hw sector is 256 bytes, hence we need to erase 16 8846 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8929 * consecutive sectors. The start index for the nth Hw sector can be 8847 * consecutive sectors. The start index for the nth Hw sector can be
8930 * calculated as = segment * 4096 + n * 256 8848 * calculated as bank * 4096 + n * 256
8931 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 8849 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8932 * The start index for the nth Hw sector can be calculated 8850 * The start index for the nth Hw sector can be calculated
8933 * as = segment * 4096 8851 * as bank * 4096
8934 * 10: Error condition 8852 * 10: The HW sector is 8K bytes
8935 * 11: The Hw sector size is much bigger than the size asked to 8853 * 11: The Hw sector size is 64K bytes */
8936 * erase...error condition */
8937 if (hsfsts.hsf_status.berasesz == 0x0) { 8854 if (hsfsts.hsf_status.berasesz == 0x0) {
8938 /* Hw sector size 256 */ 8855 /* Hw sector size 256 */
8939 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256; 8856 sub_sector_size = ICH8_FLASH_SEG_SIZE_256;
8857 bank_size = ICH8_FLASH_SECTOR_SIZE;
8940 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256; 8858 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8941 } else if (hsfsts.hsf_status.berasesz == 0x1) { 8859 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8942 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K; 8860 bank_size = ICH8_FLASH_SEG_SIZE_4K;
8861 iteration = 1;
8862 } else if (hw->mac_type != e1000_ich8lan &&
8863 hsfsts.hsf_status.berasesz == 0x2) {
8864 /* 8K erase size invalid for ICH8 - added in for ICH9 */
8865 bank_size = ICH9_FLASH_SEG_SIZE_8K;
8943 iteration = 1; 8866 iteration = 1;
8944 } else if (hsfsts.hsf_status.berasesz == 0x3) { 8867 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8945 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K; 8868 bank_size = ICH8_FLASH_SEG_SIZE_64K;
8946 iteration = 1; 8869 iteration = 1;
8947 } else { 8870 } else {
8948 return error; 8871 return error;
@@ -8966,16 +8889,15 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8966 8889
8967 /* Write the last 24 bits of an index within the block into Flash 8890 /* Write the last 24 bits of an index within the block into Flash
8968 * Linear address field in Flash Address. This probably needs to 8891 * Linear address field in Flash Address. This probably needs to
8969 * be calculated here based off the on-chip segment size and the 8892 * be calculated here based off the on-chip erase sector size and
8970 * software segment size assumed (4K) */ 8893 * the software bank size (4, 8 or 64 KBytes) */
8971 /* TBD */ 8894 flash_linear_address = bank * bank_size + j * sub_sector_size;
8972 flash_linear_address = segment * sector_size + j * seg_size;
8973 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8974 flash_linear_address += hw->flash_base_addr; 8895 flash_linear_address += hw->flash_base_addr;
8896 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8975 8897
8976 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address); 8898 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8977 8899
8978 error = e1000_ich8_flash_cycle(hw, 1000000); 8900 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_ERASE_TIMEOUT);
8979 /* Check if FCERR is set to 1. If 1, clear it and try the whole 8901 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8980 * sequence a few more times else Done */ 8902 * sequence a few more times else Done */
8981 if (error == E1000_SUCCESS) { 8903 if (error == E1000_SUCCESS) {
@@ -8999,44 +8921,6 @@ e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8999 return error; 8921 return error;
9000} 8922}
9001 8923
9002/******************************************************************************
9003 *
9004 * Reverse duplex setting without breaking the link.
9005 *
9006 * hw: Struct containing variables accessed by shared code
9007 *
9008 *****************************************************************************/
9009#if 0
9010int32_t
9011e1000_duplex_reversal(struct e1000_hw *hw)
9012{
9013 int32_t ret_val;
9014 uint16_t phy_data;
9015
9016 if (hw->phy_type != e1000_phy_igp_3)
9017 return E1000_SUCCESS;
9018
9019 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9020 if (ret_val)
9021 return ret_val;
9022
9023 phy_data ^= MII_CR_FULL_DUPLEX;
9024
9025 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9026 if (ret_val)
9027 return ret_val;
9028
9029 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9030 if (ret_val)
9031 return ret_val;
9032
9033 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9034 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9035
9036 return ret_val;
9037}
9038#endif /* 0 */
9039
9040static int32_t 8924static int32_t
9041e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, 8925e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9042 uint32_t cnf_base_addr, uint32_t cnf_size) 8926 uint32_t cnf_base_addr, uint32_t cnf_size)
@@ -9071,6 +8955,14 @@ e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9071} 8955}
9072 8956
9073 8957
8958/******************************************************************************
8959 * This function initializes the PHY from the NVM on ICH8 platforms. This
8960 * is needed due to an issue where the NVM configuration is not properly
8961 * autoloaded after power transitions. Therefore, after each PHY reset, we
8962 * will load the configuration data out of the NVM manually.
8963 *
8964 * hw: Struct containing variables accessed by shared code
8965 *****************************************************************************/
9074static int32_t 8966static int32_t
9075e1000_init_lcd_from_nvm(struct e1000_hw *hw) 8967e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9076{ 8968{
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 12:57:55 -0500