e1000: Flush shadow RAM

Flush shadow RAM to save updates to ASF related bits for 82573 controllers.
These bits are past the first 63 words of NVM.

Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>
Signed-off-by: Ganesh Venkatesan <ganesh.venkatesan@intel.com>
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 7d627dd89a3d..8fc876da43b4 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -717,6 +717,7 @@ e1000_init_hw(struct e1000_hw *hw)
     default:
         break;
     case e1000_82571:
+    case e1000_82572:
         ctrl = E1000_READ_REG(hw, TXDCTL1);
         ctrl &= ~E1000_TXDCTL_WTHRESH;
         ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;