e1000: Whitespace cleanup, cosmetic changes

Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
author: Auke Kok <auke\\\-jan.h.kok@intel.com> 2006-08-28 17:56:16 -0400
committer: Auke Kok <juke-jan.h.kok@intel.com> 2006-08-28 17:56:16 -0400
commit: 8fc897b00a7d81ffaa24e18881c2d6b10698ab0b (patch)
tree: 3dac8c72398e8a23228b2a5edd5c926c2a58675d /drivers/net/e1000/e1000_hw.c
parent: 699a71238856b19091503c671bac8abb1e3f9a3a (diff)
1 files changed, 513 insertions, 511 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index f62d17848332..57749eb438e4 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -31,6 +31,7 @@
 * Shared functions for accessing and configuring the MAC
 */
 #include "e1000_hw.h"
 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
@@ -166,10 +167,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
 {
    DEBUGFUNC("e1000_set_phy_type");
-    if(hw->mac_type == e1000_undefined)
+    if (hw->mac_type == e1000_undefined)
        return -E1000_ERR_PHY_TYPE;
-    switch(hw->phy_id) {
+    switch (hw->phy_id) {
    case M88E1000_E_PHY_ID:
    case M88E1000_I_PHY_ID:
    case M88E1011_I_PHY_ID:
@@ -177,10 +178,10 @@ e1000_set_phy_type(struct e1000_hw *hw)
        hw->phy_type = e1000_phy_m88;
        break;
    case IGP01E1000_I_PHY_ID:
-        if(hw->mac_type == e1000_82541 ||
+        if (hw->mac_type == e1000_82541 ||
-           hw->mac_type == e1000_82541_rev_2 ||
+            hw->mac_type == e1000_82541_rev_2 ||
-           hw->mac_type == e1000_82547 ||
+            hw->mac_type == e1000_82547 ||
-           hw->mac_type == e1000_82547_rev_2) {
+            hw->mac_type == e1000_82547_rev_2) {
            hw->phy_type = e1000_phy_igp;
            break;
        }
@@ -207,6 +208,7 @@ e1000_set_phy_type(struct e1000_hw *hw)
    return E1000_SUCCESS;
 }
 /******************************************************************************
 * IGP phy init script - initializes the GbE PHY
 *
@@ -220,7 +222,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
    DEBUGFUNC("e1000_phy_init_script");
-    if(hw->phy_init_script) {
+    if (hw->phy_init_script) {
        msec_delay(20);
        /* Save off the current value of register 0x2F5B to be restored at
@@ -236,7 +238,7 @@ e1000_phy_init_script(struct e1000_hw *hw)
        msec_delay(5);
-        switch(hw->mac_type) {
+        switch (hw->mac_type) {
        case e1000_82541:
        case e1000_82547:
            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
@@ -273,22 +275,22 @@ e1000_phy_init_script(struct e1000_hw *hw)
        /* Now enable the transmitter */
        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-        if(hw->mac_type == e1000_82547) {
+        if (hw->mac_type == e1000_82547) {
            uint16_t fused, fine, coarse;
            /* Move to analog registers page */
            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
-            if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+            if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
-                if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+                if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
-                } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+                } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
@@ -418,7 +420,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
        return -E1000_ERR_MAC_TYPE;
    }
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_ich8lan:
        hw->swfwhw_semaphore_present = TRUE;
        hw->asf_firmware_present = TRUE;
@@ -456,7 +458,7 @@ e1000_set_media_type(struct e1000_hw *hw)
    DEBUGFUNC("e1000_set_media_type");
-    if(hw->mac_type != e1000_82543) {
+    if (hw->mac_type != e1000_82543) {
        /* tbi_compatibility is only valid on 82543 */
        hw->tbi_compatibility_en = FALSE;
    }
@@ -516,16 +518,16 @@ e1000_reset_hw(struct e1000_hw *hw)
    DEBUGFUNC("e1000_reset_hw");
    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-    if(hw->mac_type == e1000_82542_rev2_0) {
+    if (hw->mac_type == e1000_82542_rev2_0) {
        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
        e1000_pci_clear_mwi(hw);
    }
-    if(hw->bus_type == e1000_bus_type_pci_express) {
+    if (hw->bus_type == e1000_bus_type_pci_express) {
        /* Prevent the PCI-E bus from sticking if there is no TLP connection
         * on the last TLP read/write transaction when MAC is reset.
         */
-        if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
+        if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
            DEBUGOUT("PCI-E Master disable polling has failed.\n");
        }
    }
@@ -553,14 +555,14 @@ e1000_reset_hw(struct e1000_hw *hw)
    ctrl = E1000_READ_REG(hw, CTRL);
    /* Must reset the PHY before resetting the MAC */
-    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
        msec_delay(5);
    }
    /* Must acquire the MDIO ownership before MAC reset.
     * Ownership defaults to firmware after a reset. */
-    if(hw->mac_type == e1000_82573) {
+    if (hw->mac_type == e1000_82573) {
        timeout = 10;
        extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
@@ -570,14 +572,14 @@ e1000_reset_hw(struct e1000_hw *hw)
            E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
            extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
-            if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+            if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
                break;
            else
                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
            msec_delay(2);
            timeout--;
-        } while(timeout);
+        } while (timeout);
    }
    /* Workaround for ICH8 bit corruption issue in FIFO memory */
@@ -595,7 +597,7 @@ e1000_reset_hw(struct e1000_hw *hw)
     */
    DEBUGOUT("Issuing a global reset to MAC\n");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
        case e1000_82544:
        case e1000_82540:
        case e1000_82545:
@@ -634,7 +636,7 @@ e1000_reset_hw(struct e1000_hw *hw)
     * device.  Later controllers reload the EEPROM automatically, so just wait
     * for reload to complete.
     */
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
        case e1000_82542_rev2_0:
        case e1000_82542_rev2_1:
        case e1000_82543:
@@ -669,7 +671,7 @@ e1000_reset_hw(struct e1000_hw *hw)
        case e1000_ich8lan:
        case e1000_80003es2lan:
            ret_val = e1000_get_auto_rd_done(hw);
-            if(ret_val)
+            if (ret_val)
                /* We don't want to continue accessing MAC registers. */
                return ret_val;
            break;
@@ -680,13 +682,13 @@ e1000_reset_hw(struct e1000_hw *hw)
    }
    /* Disable HW ARPs on ASF enabled adapters */
-    if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
+    if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
        manc = E1000_READ_REG(hw, MANC);
        manc &= ~(E1000_MANC_ARP_EN);
        E1000_WRITE_REG(hw, MANC, manc);
    }
-    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
        e1000_phy_init_script(hw);
        /* Configure activity LED after PHY reset */
@@ -704,8 +706,8 @@ e1000_reset_hw(struct e1000_hw *hw)
    icr = E1000_READ_REG(hw, ICR);
    /* If MWI was previously enabled, reenable it. */
-    if(hw->mac_type == e1000_82542_rev2_0) {
+    if (hw->mac_type == e1000_82542_rev2_0) {
-        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+        if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
            e1000_pci_set_mwi(hw);
    }
@@ -758,7 +760,7 @@ e1000_init_hw(struct e1000_hw *hw)
    /* Initialize Identification LED */
    ret_val = e1000_id_led_init(hw);
-    if(ret_val) {
+    if (ret_val) {
        DEBUGOUT("Error Initializing Identification LED\n");
        return ret_val;
    }
@@ -776,7 +778,7 @@ e1000_init_hw(struct e1000_hw *hw)
    }
    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-    if(hw->mac_type == e1000_82542_rev2_0) {
+    if (hw->mac_type == e1000_82542_rev2_0) {
        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
        e1000_pci_clear_mwi(hw);
        E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
@@ -790,11 +792,11 @@ e1000_init_hw(struct e1000_hw *hw)
    e1000_init_rx_addrs(hw);
    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-    if(hw->mac_type == e1000_82542_rev2_0) {
+    if (hw->mac_type == e1000_82542_rev2_0) {
        E1000_WRITE_REG(hw, RCTL, 0);
        E1000_WRITE_FLUSH(hw);
        msec_delay(1);
-        if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+        if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
            e1000_pci_set_mwi(hw);
    }
@@ -803,7 +805,7 @@ e1000_init_hw(struct e1000_hw *hw)
    mta_size = E1000_MC_TBL_SIZE;
    if (hw->mac_type == e1000_ich8lan)
        mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
-    for(i = 0; i < mta_size; i++) {
+    for (i = 0; i < mta_size; i++) {
        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
        /* use write flush to prevent Memory Write Block (MWB) from
         * occuring when accessing our register space */
@@ -815,18 +817,18 @@ e1000_init_hw(struct e1000_hw *hw)
     * gives equal priority to transmits and receives.  Valid only on
     * 82542 and 82543 silicon.
     */
-    if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
+    if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
        ctrl = E1000_READ_REG(hw, CTRL);
        E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
    }
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82545_rev_3:
    case e1000_82546_rev_3:
        break;
    default:
        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-        if(hw->bus_type == e1000_bus_type_pcix) {
+        if (hw->bus_type == e1000_bus_type_pcix) {
            e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
            e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
                &pcix_stat_hi_word);
@@ -834,9 +836,9 @@ e1000_init_hw(struct e1000_hw *hw)
                PCIX_COMMAND_MMRBC_SHIFT;
            stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
                PCIX_STATUS_HI_MMRBC_SHIFT;
-            if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
+            if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
                stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
-            if(cmd_mmrbc > stat_mmrbc) {
+            if (cmd_mmrbc > stat_mmrbc) {
                pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
                pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
                e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
@@ -854,7 +856,7 @@ e1000_init_hw(struct e1000_hw *hw)
    ret_val = e1000_setup_link(hw);
    /* Set the transmit descriptor write-back policy */
-    if(hw->mac_type > e1000_82544) {
+    if (hw->mac_type > e1000_82544) {
        ctrl = E1000_READ_REG(hw, TXDCTL);
        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
        switch (hw->mac_type) {
@@ -905,14 +907,13 @@ e1000_init_hw(struct e1000_hw *hw)
    case e1000_ich8lan:
        ctrl = E1000_READ_REG(hw, TXDCTL1);
        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-        if(hw->mac_type >= e1000_82571)
+        if (hw->mac_type >= e1000_82571)
            ctrl |= E1000_TXDCTL_COUNT_DESC;
        E1000_WRITE_REG(hw, TXDCTL1, ctrl);
        break;
    }
    if (hw->mac_type == e1000_82573) {
        uint32_t gcr = E1000_READ_REG(hw, GCR);
        gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
@@ -956,10 +957,10 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
    DEBUGFUNC("e1000_adjust_serdes_amplitude");
-    if(hw->media_type != e1000_media_type_internal_serdes)
+    if (hw->media_type != e1000_media_type_internal_serdes)
        return E1000_SUCCESS;
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82545_rev_3:
    case e1000_82546_rev_3:
        break;
@@ -972,11 +973,11 @@ e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
        return ret_val;
    }
-    if(eeprom_data != EEPROM_RESERVED_WORD) {
+    if (eeprom_data != EEPROM_RESERVED_WORD) {
        /* Adjust SERDES output amplitude only. */
        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
@@ -1044,10 +1045,10 @@ e1000_setup_link(struct e1000_hw *hw)
     * in case we get disconnected and then reconnected into a different
     * hub or switch with different Flow Control capabilities.
     */
-    if(hw->mac_type == e1000_82542_rev2_0)
+    if (hw->mac_type == e1000_82542_rev2_0)
        hw->fc &= (~e1000_fc_tx_pause);
-    if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
+    if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
        hw->fc &= (~e1000_fc_rx_pause);
    hw->original_fc = hw->fc;
@@ -1062,12 +1063,12 @@ e1000_setup_link(struct e1000_hw *hw)
     * or e1000_phy_setup() is called.
     */
    if (hw->mac_type == e1000_82543) {
-                ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
-                                                                        1, &eeprom_data);
+                                    1, &eeprom_data);
-                if (ret_val) {
+        if (ret_val) {
-                        DEBUGOUT("EEPROM Read Error\n");
+            DEBUGOUT("EEPROM Read Error\n");
-                        return -E1000_ERR_EEPROM;
+            return -E1000_ERR_EEPROM;
-                }
+        }
        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
                    SWDPIO__EXT_SHIFT);
        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
@@ -1100,14 +1101,14 @@ e1000_setup_link(struct e1000_hw *hw)
     * ability to transmit pause frames in not enabled, then these
     * registers will be set to 0.
     */
-    if(!(hw->fc & e1000_fc_tx_pause)) {
+    if (!(hw->fc & e1000_fc_tx_pause)) {
        E1000_WRITE_REG(hw, FCRTL, 0);
        E1000_WRITE_REG(hw, FCRTH, 0);
    } else {
        /* We need to set up the Receive Threshold high and low water marks
         * as well as (optionally) enabling the transmission of XON frames.
         */
-        if(hw->fc_send_xon) {
+        if (hw->fc_send_xon) {
            E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
            E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
        } else {
@@ -1154,11 +1155,11 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
     * the EEPROM.
     */
    ctrl = E1000_READ_REG(hw, CTRL);
-    if(hw->media_type == e1000_media_type_fiber)
+    if (hw->media_type == e1000_media_type_fiber)
        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
    ret_val = e1000_adjust_serdes_amplitude(hw);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* Take the link out of reset */
@@ -1166,7 +1167,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
    /* Adjust VCO speed to improve BER performance */
    ret_val = e1000_set_vco_speed(hw);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    e1000_config_collision_dist(hw);
@@ -1237,15 +1238,15 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
     * less than 500 milliseconds even if the other end is doing it in SW).
     * For internal serdes, we just assume a signal is present, then poll.
     */
-    if(hw->media_type == e1000_media_type_internal_serdes ||
+    if (hw->media_type == e1000_media_type_internal_serdes ||
       (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
        DEBUGOUT("Looking for Link\n");
-        for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+        for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
            msec_delay(10);
            status = E1000_READ_REG(hw, STATUS);
-            if(status & E1000_STATUS_LU) break;
+            if (status & E1000_STATUS_LU) break;
        }
-        if(i == (LINK_UP_TIMEOUT / 10)) {
+        if (i == (LINK_UP_TIMEOUT / 10)) {
            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
            hw->autoneg_failed = 1;
            /* AutoNeg failed to achieve a link, so we'll call
@@ -1254,7 +1255,7 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
             * non-autonegotiating link partners.
             */
            ret_val = e1000_check_for_link(hw);
-            if(ret_val) {
+            if (ret_val) {
                DEBUGOUT("Error while checking for link\n");
                return ret_val;
            }
@@ -1288,7 +1289,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
     * the PHY speed and duplex configuration is. In addition, we need to
     * perform a hardware reset on the PHY to take it out of reset.
     */
-    if(hw->mac_type > e1000_82543) {
+    if (hw->mac_type > e1000_82543) {
        ctrl |= E1000_CTRL_SLU;
        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
        E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -1296,13 +1297,13 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
        E1000_WRITE_REG(hw, CTRL, ctrl);
        ret_val = e1000_phy_hw_reset(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
    /* Make sure we have a valid PHY */
    ret_val = e1000_detect_gig_phy(hw);
-    if(ret_val) {
+    if (ret_val) {
        DEBUGOUT("Error, did not detect valid phy.\n");
        return ret_val;
    }
@@ -1310,19 +1311,19 @@ e1000_copper_link_preconfig(struct e1000_hw *hw)
    /* Set PHY to class A mode (if necessary) */
    ret_val = e1000_set_phy_mode(hw);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
-    if((hw->mac_type == e1000_82545_rev_3) ||
+    if ((hw->mac_type == e1000_82545_rev_3) ||
       (hw->mac_type == e1000_82546_rev_3)) {
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
        phy_data |= 0x00000008;
        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
    }
-    if(hw->mac_type <= e1000_82543 ||
+    if (hw->mac_type <= e1000_82543 ||
-       hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
+        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
-       hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
+        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
        hw->phy_reset_disable = FALSE;
   return E1000_SUCCESS;
@@ -1352,7 +1353,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
        return ret_val;
    }
-    /* Wait 10ms for MAC to configure PHY from eeprom settings */
+    /* Wait 15ms for MAC to configure PHY from eeprom settings */
    msec_delay(15);
    if (hw->mac_type != e1000_ich8lan) {
    /* Configure activity LED after PHY reset */
@@ -1407,45 +1408,45 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
        }
    }
    ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* set auto-master slave resolution settings */
-    if(hw->autoneg) {
+    if (hw->autoneg) {
        e1000_ms_type phy_ms_setting = hw->master_slave;
-        if(hw->ffe_config_state == e1000_ffe_config_active)
+        if (hw->ffe_config_state == e1000_ffe_config_active)
            hw->ffe_config_state = e1000_ffe_config_enabled;
-        if(hw->dsp_config_state == e1000_dsp_config_activated)
+        if (hw->dsp_config_state == e1000_dsp_config_activated)
            hw->dsp_config_state = e1000_dsp_config_enabled;
        /* when autonegotiation advertisment is only 1000Mbps then we
          * should disable SmartSpeed and enable Auto MasterSlave
          * resolution as hardware default. */
-        if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+        if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
            /* Disable SmartSpeed */
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
+            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-            if(ret_val)
+                                         &phy_data);
+            if (ret_val)
                return ret_val;
            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw,
+            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                                  IGP01E1000_PHY_PORT_CONFIG,
+                                          phy_data);
-                                                  phy_data);
+            if (ret_val)
-            if(ret_val)
                return ret_val;
            /* Set auto Master/Slave resolution process */
            ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            phy_data &= ~CR_1000T_MS_ENABLE;
            ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        }
        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* load defaults for future use */
@@ -1469,7 +1470,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
            break;
        }
        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
@@ -1490,12 +1491,12 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
    DEBUGFUNC("e1000_copper_link_ggp_setup");
-    if(!hw->phy_reset_disable) {
+    if (!hw->phy_reset_disable) {
        /* Enable CRS on TX for half-duplex operation. */
        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -1504,7 +1505,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
                                      phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* Options:
@@ -1515,7 +1516,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
         *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
         */
        ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
@@ -1540,11 +1541,11 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
         *   1 - Enabled
         */
        phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
-        if(hw->disable_polarity_correction == 1)
+        if (hw->disable_polarity_correction == 1)
            phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
        ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* SW Reset the PHY so all changes take effect */
@@ -1600,9 +1601,9 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
                return ret_val;
            phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
            ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
                                          phy_data);
            if (ret_val)
                return ret_val;
        }
@@ -1637,12 +1638,12 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
    DEBUGFUNC("e1000_copper_link_mgp_setup");
-    if(hw->phy_reset_disable)
+    if (hw->phy_reset_disable)
        return E1000_SUCCESS;
    /* Enable CRS on TX. This must be set for half-duplex operation. */
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
@@ -1679,7 +1680,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
     *   1 - Enabled
     */
    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-    if(hw->disable_polarity_correction == 1)
+    if (hw->disable_polarity_correction == 1)
        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
    if (ret_val)
@@ -1719,7 +1720,7 @@ e1000_copper_link_mgp_setup(struct e1000_hw *hw)
    /* SW Reset the PHY so all changes take effect */
    ret_val = e1000_phy_reset(hw);
-    if(ret_val) {
+    if (ret_val) {
        DEBUGOUT("Error Resetting the PHY\n");
        return ret_val;
    }
@@ -1749,7 +1750,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
    /* If autoneg_advertised is zero, we assume it was not defaulted
     * by the calling code so we set to advertise full capability.
     */
-    if(hw->autoneg_advertised == 0)
+    if (hw->autoneg_advertised == 0)
        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
    /* IFE phy only supports 10/100 */
@@ -1758,7 +1759,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
    ret_val = e1000_phy_setup_autoneg(hw);
-    if(ret_val) {
+    if (ret_val) {
        DEBUGOUT("Error Setting up Auto-Negotiation\n");
        return ret_val;
    }
@@ -1768,20 +1769,20 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
     * the Auto Neg Restart bit in the PHY control register.
     */
    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* Does the user want to wait for Auto-Neg to complete here, or
     * check at a later time (for example, callback routine).
     */
-    if(hw->wait_autoneg_complete) {
+    if (hw->wait_autoneg_complete) {
        ret_val = e1000_wait_autoneg(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error while waiting for autoneg to complete\n");
            return ret_val;
        }
@@ -1792,7 +1793,6 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
    return E1000_SUCCESS;
 }
 /******************************************************************************
 * Config the MAC and the PHY after link is up.
 *   1) Set up the MAC to the current PHY speed/duplex
@@ -1811,25 +1811,25 @@ e1000_copper_link_postconfig(struct e1000_hw *hw)
    int32_t ret_val;
    DEBUGFUNC("e1000_copper_link_postconfig");
-    if(hw->mac_type >= e1000_82544) {
+    if (hw->mac_type >= e1000_82544) {
        e1000_config_collision_dist(hw);
    } else {
        ret_val = e1000_config_mac_to_phy(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error configuring MAC to PHY settings\n");
            return ret_val;
        }
    }
    ret_val = e1000_config_fc_after_link_up(hw);
-    if(ret_val) {
+    if (ret_val) {
        DEBUGOUT("Error Configuring Flow Control\n");
        return ret_val;
    }
    /* Config DSP to improve Giga link quality */
-    if(hw->phy_type == e1000_phy_igp) {
+    if (hw->phy_type == e1000_phy_igp) {
        ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error Configuring DSP after link up\n");
            return ret_val;
        }
@@ -1875,7 +1875,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
    /* Check if it is a valid PHY and set PHY mode if necessary. */
    ret_val = e1000_copper_link_preconfig(hw);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    switch (hw->mac_type) {
@@ -1896,30 +1896,30 @@ e1000_setup_copper_link(struct e1000_hw *hw)
        hw->phy_type == e1000_phy_igp_3 ||
        hw->phy_type == e1000_phy_igp_2) {
        ret_val = e1000_copper_link_igp_setup(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    } else if (hw->phy_type == e1000_phy_m88) {
        ret_val = e1000_copper_link_mgp_setup(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    } else if (hw->phy_type == e1000_phy_gg82563) {
        ret_val = e1000_copper_link_ggp_setup(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
-    if(hw->autoneg) {
+    if (hw->autoneg) {
        /* Setup autoneg and flow control advertisement
          * and perform autonegotiation */
        ret_val = e1000_copper_link_autoneg(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    } else {
        /* PHY will be set to 10H, 10F, 100H,or 100F
          * depending on value from forced_speed_duplex. */
        DEBUGOUT("Forcing speed and duplex\n");
        ret_val = e1000_phy_force_speed_duplex(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error Forcing Speed and Duplex\n");
            return ret_val;
        }
@@ -1928,18 +1928,18 @@ e1000_setup_copper_link(struct e1000_hw *hw)
    /* Check link status. Wait up to 100 microseconds for link to become
     * valid.
     */
-    for(i = 0; i < 10; i++) {
+    for (i = 0; i < 10; i++) {
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(phy_data & MII_SR_LINK_STATUS) {
+        if (phy_data & MII_SR_LINK_STATUS) {
            /* Config the MAC and PHY after link is up */
            ret_val = e1000_copper_link_postconfig(hw);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            DEBUGOUT("Valid link established!!!\n");
@@ -2041,7 +2041,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
    ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    if (hw->phy_type != e1000_phy_ife) {
@@ -2069,36 +2069,36 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
    /* Do we want to advertise 10 Mb Half Duplex? */
-    if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
+    if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
        DEBUGOUT("Advertise 10mb Half duplex\n");
        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
    }
    /* Do we want to advertise 10 Mb Full Duplex? */
-    if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
+    if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
        DEBUGOUT("Advertise 10mb Full duplex\n");
        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
    }
    /* Do we want to advertise 100 Mb Half Duplex? */
-    if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
+    if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
        DEBUGOUT("Advertise 100mb Half duplex\n");
        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
    }
    /* Do we want to advertise 100 Mb Full Duplex? */
-    if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
+    if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
        DEBUGOUT("Advertise 100mb Full duplex\n");
        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
    }
    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
-    if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
+    if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
    }
    /* Do we want to advertise 1000 Mb Full Duplex? */
-    if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
+    if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
        DEBUGOUT("Advertise 1000mb Full duplex\n");
        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
        if (hw->phy_type == e1000_phy_ife) {
@@ -2160,7 +2160,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
    }
    ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
@@ -2208,7 +2208,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
    /* Read the MII Control Register. */
    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* We need to disable autoneg in order to force link and duplex. */
@@ -2216,8 +2216,8 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
    /* Are we forcing Full or Half Duplex? */
-    if(hw->forced_speed_duplex == e1000_100_full ||
+    if (hw->forced_speed_duplex == e1000_100_full ||
-       hw->forced_speed_duplex == e1000_10_full) {
+        hw->forced_speed_duplex == e1000_10_full) {
        /* We want to force full duplex so we SET the full duplex bits in the
         * Device and MII Control Registers.
         */
@@ -2234,7 +2234,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
    }
    /* Are we forcing 100Mbps??? */
-    if(hw->forced_speed_duplex == e1000_100_full ||
+    if (hw->forced_speed_duplex == e1000_100_full ||
       hw->forced_speed_duplex == e1000_100_half) {
        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
        ctrl |= E1000_CTRL_SPD_100;
@@ -2257,7 +2257,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
    if ((hw->phy_type == e1000_phy_m88) ||
        (hw->phy_type == e1000_phy_gg82563)) {
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
@@ -2265,7 +2265,7 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
         */
        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
@@ -2289,20 +2289,20 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
         * forced whenever speed or duplex are forced.
         */
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
    /* Write back the modified PHY MII control register. */
    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    udelay(1);
@@ -2314,50 +2314,50 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
     * only if the user has set wait_autoneg_complete to 1, which is
     * the default.
     */
-    if(hw->wait_autoneg_complete) {
+    if (hw->wait_autoneg_complete) {
        /* We will wait for autoneg to complete. */
        DEBUGOUT("Waiting for forced speed/duplex link.\n");
        mii_status_reg = 0;
        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-        for(i = PHY_FORCE_TIME; i > 0; i--) {
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
            /* Read the MII Status Register and wait for Auto-Neg Complete bit
             * to be set.
             */
            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
-            if(mii_status_reg & MII_SR_LINK_STATUS) break;
+            if (mii_status_reg & MII_SR_LINK_STATUS) break;
            msec_delay(100);
        }
-        if((i == 0) &&
+        if ((i == 0) &&
           ((hw->phy_type == e1000_phy_m88) ||
            (hw->phy_type == e1000_phy_gg82563))) {
            /* We didn't get link.  Reset the DSP and wait again for link. */
            ret_val = e1000_phy_reset_dsp(hw);
-            if(ret_val) {
+            if (ret_val) {
                DEBUGOUT("Error Resetting PHY DSP\n");
                return ret_val;
            }
        }
        /* This loop will early-out if the link condition has been met.  */
-        for(i = PHY_FORCE_TIME; i > 0; i--) {
+        for (i = PHY_FORCE_TIME; i > 0; i--) {
-            if(mii_status_reg & MII_SR_LINK_STATUS) break;
+            if (mii_status_reg & MII_SR_LINK_STATUS) break;
            msec_delay(100);
            /* Read the MII Status Register and wait for Auto-Neg Complete bit
             * to be set.
             */
            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        }
    }
@@ -2368,32 +2368,31 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
         * defaults back to a 2.5MHz clock when the PHY is reset.
         */
        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data |= M88E1000_EPSCR_TX_CLK_25;
        ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* In addition, because of the s/w reset above, we need to enable CRS on
         * TX.  This must be set for both full and half duplex operation.
         */
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
+        if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-           (!hw->autoneg) &&
+            (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
-           (hw->forced_speed_duplex == e1000_10_full ||
+             hw->forced_speed_duplex == e1000_10_half)) {
-            hw->forced_speed_duplex == e1000_10_half)) {
            ret_val = e1000_polarity_reversal_workaround(hw);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        }
    } else if (hw->phy_type == e1000_phy_gg82563) {
@@ -2484,10 +2483,10 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
     * registers depending on negotiated values.
     */
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
-    if(phy_data & M88E1000_PSSR_DPLX)
+    if (phy_data & M88E1000_PSSR_DPLX)
        ctrl |= E1000_CTRL_FD;
    else
        ctrl &= ~E1000_CTRL_FD;
@@ -2497,9 +2496,9 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
    /* Set up speed in the Device Control register depending on
     * negotiated values.
     */
-    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
        ctrl |= E1000_CTRL_SPD_1000;
-    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
+    else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
        ctrl |= E1000_CTRL_SPD_100;
    /* Write the configured values back to the Device Control Reg. */
@@ -2567,7 +2566,7 @@ e1000_force_mac_fc(struct e1000_hw *hw)
    }
    /* Disable TX Flow Control for 82542 (rev 2.0) */
-    if(hw->mac_type == e1000_82542_rev2_0)
+    if (hw->mac_type == e1000_82542_rev2_0)
        ctrl &= (~E1000_CTRL_TFCE);
    E1000_WRITE_REG(hw, CTRL, ctrl);
@@ -2601,11 +2600,12 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
     * so we had to force link.  In this case, we need to force the
     * configuration of the MAC to match the "fc" parameter.
     */
-    if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
+    if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
-       ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
+        ((hw->media_type == e1000_media_type_internal_serdes) &&
-       ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
+         (hw->autoneg_failed)) ||
+        ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
        ret_val = e1000_force_mac_fc(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error forcing flow control settings\n");
            return ret_val;
        }
@@ -2616,19 +2616,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
     * has completed, and if so, how the PHY and link partner has
     * flow control configured.
     */
-    if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
+    if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
        /* Read the MII Status Register and check to see if AutoNeg
         * has completed.  We read this twice because this reg has
         * some "sticky" (latched) bits.
         */
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
+        if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
            /* The AutoNeg process has completed, so we now need to
             * read both the Auto Negotiation Advertisement Register
             * (Address 4) and the Auto_Negotiation Base Page Ability
@@ -2637,11 +2637,11 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             */
            ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
                                         &mii_nway_adv_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
                                         &mii_nway_lp_ability_reg);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            /* Two bits in the Auto Negotiation Advertisement Register
@@ -2678,15 +2678,15 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             *   1   |   DC    |   1   |   DC    | e1000_fc_full
             *
             */
-            if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+            if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-               (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
+                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
                /* Now we need to check if the user selected RX ONLY
                 * of pause frames.  In this case, we had to advertise
                 * FULL flow control because we could not advertise RX
                 * ONLY. Hence, we must now check to see if we need to
                 * turn OFF  the TRANSMISSION of PAUSE frames.
                 */
-                if(hw->original_fc == e1000_fc_full) {
+                if (hw->original_fc == e1000_fc_full) {
                    hw->fc = e1000_fc_full;
                    DEBUGOUT("Flow Control = FULL.\n");
                } else {
@@ -2702,10 +2702,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
             *
             */
-            else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+            else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
                hw->fc = e1000_fc_tx_pause;
                DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
            }
@@ -2717,10 +2717,10 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
             *
             */
-            else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+            else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                    (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                    !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                     !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                    (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
                hw->fc = e1000_fc_rx_pause;
                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
            }
@@ -2744,9 +2744,9 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             * be asked to delay transmission of packets than asking
             * our link partner to pause transmission of frames.
             */
-            else if((hw->original_fc == e1000_fc_none ||
+            else if ((hw->original_fc == e1000_fc_none ||
-                     hw->original_fc == e1000_fc_tx_pause) ||
+                      hw->original_fc == e1000_fc_tx_pause) ||
-                    hw->fc_strict_ieee) {
+                      hw->fc_strict_ieee) {
                hw->fc = e1000_fc_none;
                DEBUGOUT("Flow Control = NONE.\n");
            } else {
@@ -2759,19 +2759,19 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
             * enabled per IEEE 802.3 spec.
             */
            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-            if(ret_val) {
+            if (ret_val) {
                DEBUGOUT("Error getting link speed and duplex\n");
                return ret_val;
            }
-            if(duplex == HALF_DUPLEX)
+            if (duplex == HALF_DUPLEX)
                hw->fc = e1000_fc_none;
            /* Now we call a subroutine to actually force the MAC
             * controller to use the correct flow control settings.
             */
            ret_val = e1000_force_mac_fc(hw);
-            if(ret_val) {
+            if (ret_val) {
                DEBUGOUT("Error forcing flow control settings\n");
                return ret_val;
            }
@@ -2810,13 +2810,13 @@ e1000_check_for_link(struct e1000_hw *hw)
     * set when the optics detect a signal. On older adapters, it will be
     * cleared when there is a signal.  This applies to fiber media only.
     */
-    if((hw->media_type == e1000_media_type_fiber) ||
+    if ((hw->media_type == e1000_media_type_fiber) ||
-       (hw->media_type == e1000_media_type_internal_serdes)) {
+        (hw->media_type == e1000_media_type_internal_serdes)) {
        rxcw = E1000_READ_REG(hw, RXCW);
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-            if(status & E1000_STATUS_LU)
+            if (status & E1000_STATUS_LU)
                hw->get_link_status = FALSE;
        }
    }
@@ -2827,20 +2827,20 @@ e1000_check_for_link(struct e1000_hw *hw)
     * receive a Link Status Change interrupt or we have Rx Sequence
     * Errors.
     */
-    if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
+    if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
        /* First we want to see if the MII Status Register reports
         * link.  If so, then we want to get the current speed/duplex
         * of the PHY.
         * Read the register twice since the link bit is sticky.
         */
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(phy_data & MII_SR_LINK_STATUS) {
+        if (phy_data & MII_SR_LINK_STATUS) {
            hw->get_link_status = FALSE;
            /* Check if there was DownShift, must be checked immediately after
             * link-up */
@@ -2854,10 +2854,10 @@ e1000_check_for_link(struct e1000_hw *hw)
             * happen due to the execution of this workaround.
             */
-            if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
+            if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-               (!hw->autoneg) &&
+                (!hw->autoneg) &&
-               (hw->forced_speed_duplex == e1000_10_full ||
+                (hw->forced_speed_duplex == e1000_10_full ||
-                hw->forced_speed_duplex == e1000_10_half)) {
+                 hw->forced_speed_duplex == e1000_10_half)) {
                E1000_WRITE_REG(hw, IMC, 0xffffffff);
                ret_val = e1000_polarity_reversal_workaround(hw);
                icr = E1000_READ_REG(hw, ICR);
@@ -2874,7 +2874,7 @@ e1000_check_for_link(struct e1000_hw *hw)
        /* If we are forcing speed/duplex, then we simply return since
         * we have already determined whether we have link or not.
         */
-        if(!hw->autoneg) return -E1000_ERR_CONFIG;
+        if (!hw->autoneg) return -E1000_ERR_CONFIG;
        /* optimize the dsp settings for the igp phy */
        e1000_config_dsp_after_link_change(hw, TRUE);
@@ -2887,11 +2887,11 @@ e1000_check_for_link(struct e1000_hw *hw)
         * speed/duplex on the MAC to the current PHY speed/duplex
         * settings.
         */
-        if(hw->mac_type >= e1000_82544)
+        if (hw->mac_type >= e1000_82544)
            e1000_config_collision_dist(hw);
        else {
            ret_val = e1000_config_mac_to_phy(hw);
-            if(ret_val) {
+            if (ret_val) {
                DEBUGOUT("Error configuring MAC to PHY settings\n");
                return ret_val;
            }
@@ -2902,7 +2902,7 @@ e1000_check_for_link(struct e1000_hw *hw)
         * have had to re-autoneg with a different link partner.
         */
        ret_val = e1000_config_fc_after_link_up(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error configuring flow control\n");
            return ret_val;
        }
@@ -2914,7 +2914,7 @@ e1000_check_for_link(struct e1000_hw *hw)
         * at gigabit speed, then TBI compatibility is not needed.  If we are
         * at gigabit speed, we turn on TBI compatibility.
         */
-        if(hw->tbi_compatibility_en) {
+        if (hw->tbi_compatibility_en) {
            uint16_t speed, duplex;
            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
            if (ret_val) {
@@ -2925,7 +2925,7 @@ e1000_check_for_link(struct e1000_hw *hw)
                /* If link speed is not set to gigabit speed, we do not need
                 * to enable TBI compatibility.
                 */
-                if(hw->tbi_compatibility_on) {
+                if (hw->tbi_compatibility_on) {
                    /* If we previously were in the mode, turn it off. */
                    rctl = E1000_READ_REG(hw, RCTL);
                    rctl &= ~E1000_RCTL_SBP;
@@ -2938,7 +2938,7 @@ e1000_check_for_link(struct e1000_hw *hw)
                 * packets. Some frames have an additional byte on the end and
                 * will look like CRC errors to to the hardware.
                 */
-                if(!hw->tbi_compatibility_on) {
+                if (!hw->tbi_compatibility_on) {
                    hw->tbi_compatibility_on = TRUE;
                    rctl = E1000_READ_REG(hw, RCTL);
                    rctl |= E1000_RCTL_SBP;
@@ -2954,12 +2954,12 @@ e1000_check_for_link(struct e1000_hw *hw)
     * auto-negotiation time to complete, in case the cable was just plugged
     * in. The autoneg_failed flag does this.
     */
-    else if((((hw->media_type == e1000_media_type_fiber) &&
+    else if ((((hw->media_type == e1000_media_type_fiber) &&
              ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
-             (hw->media_type == e1000_media_type_internal_serdes)) &&
+              (hw->media_type == e1000_media_type_internal_serdes)) &&
-            (!(status & E1000_STATUS_LU)) &&
+              (!(status & E1000_STATUS_LU)) &&
-            (!(rxcw & E1000_RXCW_C))) {
+              (!(rxcw & E1000_RXCW_C))) {
-        if(hw->autoneg_failed == 0) {
+        if (hw->autoneg_failed == 0) {
            hw->autoneg_failed = 1;
            return 0;
        }
@@ -2975,7 +2975,7 @@ e1000_check_for_link(struct e1000_hw *hw)
        /* Configure Flow Control after forcing link up. */
        ret_val = e1000_config_fc_after_link_up(hw);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error configuring flow control\n");
            return ret_val;
        }
@@ -2985,9 +2985,9 @@ e1000_check_for_link(struct e1000_hw *hw)
     * Device Control register in an attempt to auto-negotiate with our link
     * partner.
     */
-    else if(((hw->media_type == e1000_media_type_fiber) ||
+    else if (((hw->media_type == e1000_media_type_fiber) ||
-             (hw->media_type == e1000_media_type_internal_serdes)) &&
+              (hw->media_type == e1000_media_type_internal_serdes)) &&
-            (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
+              (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
        DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
        E1000_WRITE_REG(hw, TXCW, hw->txcw);
        E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -2997,12 +2997,12 @@ e1000_check_for_link(struct e1000_hw *hw)
    /* If we force link for non-auto-negotiation switch, check link status
     * based on MAC synchronization for internal serdes media type.
     */
-    else if((hw->media_type == e1000_media_type_internal_serdes) &&
+    else if ((hw->media_type == e1000_media_type_internal_serdes) &&
-            !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
+             !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
        /* SYNCH bit and IV bit are sticky. */
        udelay(10);
-        if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
+        if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
-            if(!(rxcw & E1000_RXCW_IV)) {
+            if (!(rxcw & E1000_RXCW_IV)) {
                hw->serdes_link_down = FALSE;
                DEBUGOUT("SERDES: Link is up.\n");
            }
@@ -3011,8 +3011,8 @@ e1000_check_for_link(struct e1000_hw *hw)
            DEBUGOUT("SERDES: Link is down.\n");
        }
    }
-    if((hw->media_type == e1000_media_type_internal_serdes) &&
+    if ((hw->media_type == e1000_media_type_internal_serdes) &&
-       (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
+        (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
        hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
    }
    return E1000_SUCCESS;
@@ -3036,12 +3036,12 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
    DEBUGFUNC("e1000_get_speed_and_duplex");
-    if(hw->mac_type >= e1000_82543) {
+    if (hw->mac_type >= e1000_82543) {
        status = E1000_READ_REG(hw, STATUS);
-        if(status & E1000_STATUS_SPEED_1000) {
+        if (status & E1000_STATUS_SPEED_1000) {
            *speed = SPEED_1000;
            DEBUGOUT("1000 Mbs, ");
-        } else if(status & E1000_STATUS_SPEED_100) {
+        } else if (status & E1000_STATUS_SPEED_100) {
            *speed = SPEED_100;
            DEBUGOUT("100 Mbs, ");
        } else {
@@ -3049,7 +3049,7 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
            DEBUGOUT("10 Mbs, ");
        }
-        if(status & E1000_STATUS_FD) {
+        if (status & E1000_STATUS_FD) {
            *duplex = FULL_DUPLEX;
            DEBUGOUT("Full Duplex\n");
        } else {
@@ -3066,18 +3066,18 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
     * if it is operating at half duplex.  Here we set the duplex settings to
     * match the duplex in the link partner's capabilities.
     */
-    if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
+    if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+        if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
            *duplex = HALF_DUPLEX;
        else {
            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
-            if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
+            if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
                *duplex = HALF_DUPLEX;
        }
@@ -3118,17 +3118,17 @@ e1000_wait_autoneg(struct e1000_hw *hw)
    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-    for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+    for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
        /* Read the MII Status Register and wait for Auto-Neg
         * Complete bit to be set.
         */
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(phy_data & MII_SR_AUTONEG_COMPLETE) {
+        if (phy_data & MII_SR_AUTONEG_COMPLETE) {
            return E1000_SUCCESS;
        }
        msec_delay(100);
@@ -3201,14 +3201,16 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw,
    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-    while(mask) {
+    while (mask) {
        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
         * then raising and lowering the Management Data Clock. A "0" is
         * shifted out to the PHY by setting the MDIO bit to "0" and then
         * raising and lowering the clock.
         */
-        if(data & mask) ctrl |= E1000_CTRL_MDIO;
+        if (data & mask)
-        else ctrl &= ~E1000_CTRL_MDIO;
+            ctrl |= E1000_CTRL_MDIO;
+        else
+            ctrl &= ~E1000_CTRL_MDIO;
        E1000_WRITE_REG(hw, CTRL, ctrl);
        E1000_WRITE_FLUSH(hw);
@@ -3259,12 +3261,13 @@ e1000_shift_in_mdi_bits(struct e1000_hw *hw)
    e1000_raise_mdi_clk(hw, &ctrl);
    e1000_lower_mdi_clk(hw, &ctrl);
-    for(data = 0, i = 0; i < 16; i++) {
+    for (data = 0, i = 0; i < 16; i++) {
        data = data << 1;
        e1000_raise_mdi_clk(hw, &ctrl);
        ctrl = E1000_READ_REG(hw, CTRL);
        /* Check to see if we shifted in a "1". */
-        if(ctrl & E1000_CTRL_MDIO) data |= 1;
+        if (ctrl & E1000_CTRL_MDIO)
+            data |= 1;
        e1000_lower_mdi_clk(hw, &ctrl);
    }
@@ -3290,7 +3293,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
    if (!hw->swfw_sync_present)
        return e1000_get_hw_eeprom_semaphore(hw);
-    while(timeout) {
+    while (timeout) {
            if (e1000_get_hw_eeprom_semaphore(hw))
                return -E1000_ERR_SWFW_SYNC;
@@ -3379,7 +3382,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
                                         (uint16_t)reg_addr);
-        if(ret_val) {
+        if (ret_val) {
            e1000_swfw_sync_release(hw, swfw);
            return ret_val;
        }
@@ -3424,12 +3427,12 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
    DEBUGFUNC("e1000_read_phy_reg_ex");
-    if(reg_addr > MAX_PHY_REG_ADDRESS) {
+    if (reg_addr > MAX_PHY_REG_ADDRESS) {
        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
        return -E1000_ERR_PARAM;
    }
-    if(hw->mac_type > e1000_82543) {
+    if (hw->mac_type > e1000_82543) {
        /* Set up Op-code, Phy Address, and register address in the MDI
         * Control register.  The MAC will take care of interfacing with the
         * PHY to retrieve the desired data.
@@ -3441,16 +3444,16 @@ e1000_read_phy_reg_ex(struct e1000_hw *hw,
        E1000_WRITE_REG(hw, MDIC, mdic);
        /* Poll the ready bit to see if the MDI read completed */
-        for(i = 0; i < 64; i++) {
+        for (i = 0; i < 64; i++) {
            udelay(50);
            mdic = E1000_READ_REG(hw, MDIC);
-            if(mdic & E1000_MDIC_READY) break;
+            if (mdic & E1000_MDIC_READY) break;
        }
-        if(!(mdic & E1000_MDIC_READY)) {
+        if (!(mdic & E1000_MDIC_READY)) {
            DEBUGOUT("MDI Read did not complete\n");
            return -E1000_ERR_PHY;
        }
-        if(mdic & E1000_MDIC_ERROR) {
+        if (mdic & E1000_MDIC_ERROR) {
            DEBUGOUT("MDI Error\n");
            return -E1000_ERR_PHY;
        }
@@ -3519,7 +3522,7 @@ e1000_write_phy_reg(struct e1000_hw *hw,
       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
                                         (uint16_t)reg_addr);
-        if(ret_val) {
+        if (ret_val) {
            e1000_swfw_sync_release(hw, swfw);
            return ret_val;
        }
@@ -3564,12 +3567,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
    DEBUGFUNC("e1000_write_phy_reg_ex");
-    if(reg_addr > MAX_PHY_REG_ADDRESS) {
+    if (reg_addr > MAX_PHY_REG_ADDRESS) {
        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
        return -E1000_ERR_PARAM;
    }
-    if(hw->mac_type > e1000_82543) {
+    if (hw->mac_type > e1000_82543) {
        /* Set up Op-code, Phy Address, register address, and data intended
         * for the PHY register in the MDI Control register.  The MAC will take
         * care of interfacing with the PHY to send the desired data.
@@ -3582,12 +3585,12 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
        E1000_WRITE_REG(hw, MDIC, mdic);
        /* Poll the ready bit to see if the MDI read completed */
-        for(i = 0; i < 640; i++) {
+        for (i = 0; i < 641; i++) {
            udelay(5);
            mdic = E1000_READ_REG(hw, MDIC);
-            if(mdic & E1000_MDIC_READY) break;
+            if (mdic & E1000_MDIC_READY) break;
        }
-        if(!(mdic & E1000_MDIC_READY)) {
+        if (!(mdic & E1000_MDIC_READY)) {
            DEBUGOUT("MDI Write did not complete\n");
            return -E1000_ERR_PHY;
        }
@@ -3699,7 +3702,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
    DEBUGOUT("Resetting Phy...\n");
-    if(hw->mac_type > e1000_82543) {
+    if (hw->mac_type > e1000_82543) {
        if ((hw->mac_type == e1000_80003es2lan) &&
            (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
            swfw = E1000_SWFW_PHY1_SM;
@@ -3747,7 +3750,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
    }
    udelay(150);
-    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
        /* Configure activity LED after PHY reset */
        led_ctrl = E1000_READ_REG(hw, LEDCTL);
        led_ctrl &= IGP_ACTIVITY_LED_MASK;
@@ -3757,14 +3760,13 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
    /* Wait for FW to finish PHY configuration. */
    ret_val = e1000_get_phy_cfg_done(hw);
+    if (ret_val != E1000_SUCCESS)
+        return ret_val;
    e1000_release_software_semaphore(hw);
-        if ((hw->mac_type == e1000_ich8lan) &&
+    if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
-            (hw->phy_type == e1000_phy_igp_3)) {
+        ret_val = e1000_init_lcd_from_nvm(hw);
-            ret_val = e1000_init_lcd_from_nvm(hw);
-            if (ret_val)
-                return ret_val;
-        }
    return ret_val;
 }
@@ -3795,25 +3797,25 @@ e1000_phy_reset(struct e1000_hw *hw)
    case e1000_82572:
    case e1000_ich8lan:
        ret_val = e1000_phy_hw_reset(hw);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        break;
    default:
        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data |= MII_CR_RESET;
        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        udelay(1);
        break;
    }
-    if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
+    if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
        e1000_phy_init_script(hw);
    return E1000_SUCCESS;
@@ -3891,8 +3893,8 @@ e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
    if (hw->kmrn_lock_loss_workaround_disabled)
        return E1000_SUCCESS;
-    /* Make sure link is up before proceeding. If not just return.
+    /* Make sure link is up before proceeding.  If not just return.
-     * Attempting this while link is negotiating fouls up link
+     * Attempting this while link is negotiating fouled up link
     * stability */
    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
@@ -3969,34 +3971,34 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
    hw->phy_id = (uint32_t) (phy_id_high << 16);
    udelay(20);
    ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
    hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82543:
-        if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+        if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
        break;
    case e1000_82544:
-        if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+        if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
        break;
    case e1000_82540:
    case e1000_82545:
    case e1000_82545_rev_3:
    case e1000_82546:
    case e1000_82546_rev_3:
-        if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+        if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
        break;
    case e1000_82541:
    case e1000_82541_rev_2:
    case e1000_82547:
    case e1000_82547_rev_2:
-        if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
+        if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
        break;
    case e1000_82573:
-        if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
+        if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
        break;
    case e1000_80003es2lan:
        if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
@@ -4035,14 +4037,14 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
    do {
        if (hw->phy_type != e1000_phy_gg82563) {
            ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
-            if(ret_val) break;
+            if (ret_val) break;
        }
        ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
-        if(ret_val) break;
+        if (ret_val) break;
        ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
-        if(ret_val) break;
+        if (ret_val) break;
        ret_val = E1000_SUCCESS;
-    } while(0);
+    } while (0);
    return ret_val;
 }
@@ -4053,7 +4055,7 @@ e1000_phy_reset_dsp(struct e1000_hw *hw)
 * hw - Struct containing variables accessed by shared code
 * phy_info - PHY information structure
 ******************************************************************************/
-static int32_t
+int32_t
 e1000_phy_igp_get_info(struct e1000_hw *hw,
                       struct e1000_phy_info *phy_info)
 {
@@ -4074,23 +4076,23 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
    /* Check polarity status */
    ret_val = e1000_check_polarity(hw, &polarity);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_info->cable_polarity = polarity;
    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
                          IGP01E1000_PSSR_MDIX_SHIFT;
-    if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+    if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
       IGP01E1000_PSSR_SPEED_1000MBPS) {
        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4100,19 +4102,19 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
        /* Get cable length */
        ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* Translate to old method */
        average = (max_length + min_length) / 2;
-        if(average <= e1000_igp_cable_length_50)
+        if (average <= e1000_igp_cable_length_50)
            phy_info->cable_length = e1000_cable_length_50;
-        else if(average <= e1000_igp_cable_length_80)
+        else if (average <= e1000_igp_cable_length_80)
            phy_info->cable_length = e1000_cable_length_50_80;
-        else if(average <= e1000_igp_cable_length_110)
+        else if (average <= e1000_igp_cable_length_110)
            phy_info->cable_length = e1000_cable_length_80_110;
-        else if(average <= e1000_igp_cable_length_140)
+        else if (average <= e1000_igp_cable_length_140)
            phy_info->cable_length = e1000_cable_length_110_140;
        else
            phy_info->cable_length = e1000_cable_length_140;
@@ -4188,7 +4190,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_info->extended_10bt_distance =
@@ -4200,12 +4202,12 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
    /* Check polarity status */
    ret_val = e1000_check_polarity(hw, &polarity);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_info->cable_polarity = polarity;
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
@@ -4228,7 +4230,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
        }
        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
@@ -4265,20 +4267,20 @@ e1000_phy_get_info(struct e1000_hw *hw,
    phy_info->local_rx = e1000_1000t_rx_status_undefined;
    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
-    if(hw->media_type != e1000_media_type_copper) {
+    if (hw->media_type != e1000_media_type_copper) {
        DEBUGOUT("PHY info is only valid for copper media\n");
        return -E1000_ERR_CONFIG;
    }
    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
-    if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
+    if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
        DEBUGOUT("PHY info is only valid if link is up\n");
        return -E1000_ERR_CONFIG;
    }
@@ -4298,7 +4300,7 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
 {
    DEBUGFUNC("e1000_validate_mdi_settings");
-    if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
+    if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
        DEBUGOUT("Invalid MDI setting detected\n");
        hw->mdix = 1;
        return -E1000_ERR_CONFIG;
@@ -4345,7 +4347,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
        eeprom->type = e1000_eeprom_microwire;
        eeprom->opcode_bits = 3;
        eeprom->delay_usec = 50;
-        if(eecd & E1000_EECD_SIZE) {
+        if (eecd & E1000_EECD_SIZE) {
            eeprom->word_size = 256;
            eeprom->address_bits = 8;
        } else {
@@ -4413,7 +4415,7 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
        }
        eeprom->use_eerd = TRUE;
        eeprom->use_eewr = TRUE;
-        if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
+        if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
            eeprom->type = e1000_eeprom_flash;
            eeprom->word_size = 2048;
@@ -4474,17 +4476,17 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
        /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
         * 32KB (incremented by powers of 2).
         */
-        if(hw->mac_type <= e1000_82547_rev_2) {
+        if (hw->mac_type <= e1000_82547_rev_2) {
            /* Set to default value for initial eeprom read. */
            eeprom->word_size = 64;
            ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
            /* 256B eeprom size was not supported in earlier hardware, so we
             * bump eeprom_size up one to ensure that "1" (which maps to 256B)
             * is never the result used in the shifting logic below. */
-            if(eeprom_size)
+            if (eeprom_size)
                eeprom_size++;
        } else {
            eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
@@ -4569,7 +4571,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
         */
        eecd &= ~E1000_EECD_DI;
-        if(data & mask)
+        if (data & mask)
            eecd |= E1000_EECD_DI;
        E1000_WRITE_REG(hw, EECD, eecd);
@@ -4582,7 +4584,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw,
        mask = mask >> 1;
-    } while(mask);
+    } while (mask);
    /* We leave the "DI" bit set to "0" when we leave this routine. */
    eecd &= ~E1000_EECD_DI;
@@ -4614,14 +4616,14 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw,
    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
    data = 0;
-    for(i = 0; i < count; i++) {
+    for (i = 0; i < count; i++) {
        data = data << 1;
        e1000_raise_ee_clk(hw, &eecd);
        eecd = E1000_READ_REG(hw, EECD);
        eecd &= ~(E1000_EECD_DI);
-        if(eecd & E1000_EECD_DO)
+        if (eecd & E1000_EECD_DO)
            data |= 1;
        e1000_lower_ee_clk(hw, &eecd);
@@ -4652,17 +4654,17 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
    if (hw->mac_type != e1000_82573) {
        /* Request EEPROM Access */
-        if(hw->mac_type > e1000_82544) {
+        if (hw->mac_type > e1000_82544) {
            eecd |= E1000_EECD_REQ;
            E1000_WRITE_REG(hw, EECD, eecd);
            eecd = E1000_READ_REG(hw, EECD);
-            while((!(eecd & E1000_EECD_GNT)) &&
+            while ((!(eecd & E1000_EECD_GNT)) &&
                  (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
                i++;
                udelay(5);
                eecd = E1000_READ_REG(hw, EECD);
            }
-            if(!(eecd & E1000_EECD_GNT)) {
+            if (!(eecd & E1000_EECD_GNT)) {
                eecd &= ~E1000_EECD_REQ;
                E1000_WRITE_REG(hw, EECD, eecd);
                DEBUGOUT("Could not acquire EEPROM grant\n");
@@ -4705,7 +4707,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
    eecd = E1000_READ_REG(hw, EECD);
-    if(eeprom->type == e1000_eeprom_microwire) {
+    if (eeprom->type == e1000_eeprom_microwire) {
        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
        E1000_WRITE_REG(hw, EECD, eecd);
        E1000_WRITE_FLUSH(hw);
@@ -4728,7 +4730,7 @@ e1000_standby_eeprom(struct e1000_hw *hw)
        E1000_WRITE_REG(hw, EECD, eecd);
        E1000_WRITE_FLUSH(hw);
        udelay(eeprom->delay_usec);
-    } else if(eeprom->type == e1000_eeprom_spi) {
+    } else if (eeprom->type == e1000_eeprom_spi) {
        /* Toggle CS to flush commands */
        eecd |= E1000_EECD_CS;
        E1000_WRITE_REG(hw, EECD, eecd);
@@ -4762,7 +4764,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
        E1000_WRITE_REG(hw, EECD, eecd);
        udelay(hw->eeprom.delay_usec);
-    } else if(hw->eeprom.type == e1000_eeprom_microwire) {
+    } else if (hw->eeprom.type == e1000_eeprom_microwire) {
        /* cleanup eeprom */
        /* CS on Microwire is active-high */
@@ -4784,7 +4786,7 @@ e1000_release_eeprom(struct e1000_hw *hw)
    }
    /* Stop requesting EEPROM access */
-    if(hw->mac_type > e1000_82544) {
+    if (hw->mac_type > e1000_82544) {
        eecd &= ~E1000_EECD_REQ;
        E1000_WRITE_REG(hw, EECD, eecd);
    }
@@ -4822,12 +4824,12 @@ e1000_spi_eeprom_ready(struct e1000_hw *hw)
        retry_count += 5;
        e1000_standby_eeprom(hw);
-    } while(retry_count < EEPROM_MAX_RETRY_SPI);
+    } while (retry_count < EEPROM_MAX_RETRY_SPI);
    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
     * only 0-5mSec on 5V devices)
     */
-    if(retry_count >= EEPROM_MAX_RETRY_SPI) {
+    if (retry_count >= EEPROM_MAX_RETRY_SPI) {
        DEBUGOUT("SPI EEPROM Status error\n");
        return -E1000_ERR_EEPROM;
    }
@@ -4858,7 +4860,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
    /* A check for invalid values:  offset too large, too many words, and not
     * enough words.
     */
-    if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
+    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
       (words == 0)) {
        DEBUGOUT("\"words\" parameter out of bounds\n");
        return -E1000_ERR_EEPROM;
@@ -4866,7 +4868,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
    /* FLASH reads without acquiring the semaphore are safe */
    if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
-    hw->eeprom.use_eerd == FALSE) {
+        hw->eeprom.use_eerd == FALSE) {
        switch (hw->mac_type) {
        case e1000_80003es2lan:
            break;
@@ -4893,7 +4895,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
        uint16_t word_in;
        uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
-        if(e1000_spi_eeprom_ready(hw)) {
+        if (e1000_spi_eeprom_ready(hw)) {
            e1000_release_eeprom(hw);
            return -E1000_ERR_EEPROM;
        }
@@ -4901,7 +4903,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
        e1000_standby_eeprom(hw);
        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if((eeprom->address_bits == 8) && (offset >= 128))
+        if ((eeprom->address_bits == 8) && (offset >= 128))
            read_opcode |= EEPROM_A8_OPCODE_SPI;
        /* Send the READ command (opcode + addr)  */
@@ -4917,7 +4919,7 @@ e1000_read_eeprom(struct e1000_hw *hw,
            word_in = e1000_shift_in_ee_bits(hw, 16);
            data[i] = (word_in >> 8) | (word_in << 8);
        }
-    } else if(eeprom->type == e1000_eeprom_microwire) {
+    } else if (eeprom->type == e1000_eeprom_microwire) {
        for (i = 0; i < words; i++) {
            /* Send the READ command (opcode + addr)  */
            e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
@@ -4962,7 +4964,7 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw,
        E1000_WRITE_REG(hw, EERD, eerd);
        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
-        if(error) {
+        if (error) {
            break;
        }
        data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
@@ -4999,7 +5001,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
                         E1000_EEPROM_RW_REG_START;
        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
-        if(error) {
+        if (error) {
            break;
        }
@@ -5007,7 +5009,7 @@ e1000_write_eeprom_eewr(struct e1000_hw *hw,
        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
-        if(error) {
+        if (error) {
            break;
        }
    }
@@ -5028,13 +5030,13 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
    uint32_t i, reg = 0;
    int32_t done = E1000_ERR_EEPROM;
-    for(i = 0; i < attempts; i++) {
+    for (i = 0; i < attempts; i++) {
-        if(eerd == E1000_EEPROM_POLL_READ)
+        if (eerd == E1000_EEPROM_POLL_READ)
            reg = E1000_READ_REG(hw, EERD);
        else
            reg = E1000_READ_REG(hw, EEWR);
-        if(reg & E1000_EEPROM_RW_REG_DONE) {
+        if (reg & E1000_EEPROM_RW_REG_DONE) {
            done = E1000_SUCCESS;
            break;
        }
@@ -5066,7 +5068,7 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
        eecd = ((eecd >> 15) & 0x03);
        /* If both bits are set, device is Flash type */
-        if(eecd == 0x03) {
+        if (eecd == 0x03) {
            return FALSE;
        }
    }
@@ -5131,7 +5133,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
        checksum += eeprom_data;
    }
-    if(checksum == (uint16_t) EEPROM_SUM)
+    if (checksum == (uint16_t) EEPROM_SUM)
        return E1000_SUCCESS;
    else {
        DEBUGOUT("EEPROM Checksum Invalid\n");
@@ -5156,15 +5158,15 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
    DEBUGFUNC("e1000_update_eeprom_checksum");
-    for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
+    for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
-        if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
            DEBUGOUT("EEPROM Read Error\n");
            return -E1000_ERR_EEPROM;
        }
        checksum += eeprom_data;
    }
    checksum = (uint16_t) EEPROM_SUM - checksum;
-    if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
+    if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
        DEBUGOUT("EEPROM Write Error\n");
        return -E1000_ERR_EEPROM;
    } else if (hw->eeprom.type == e1000_eeprom_flash) {
@@ -5206,14 +5208,14 @@ e1000_write_eeprom(struct e1000_hw *hw,
    /* A check for invalid values:  offset too large, too many words, and not
     * enough words.
     */
-    if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
+    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
       (words == 0)) {
        DEBUGOUT("\"words\" parameter out of bounds\n");
        return -E1000_ERR_EEPROM;
    }
    /* 82573 writes only through eewr */
-    if(eeprom->use_eewr == TRUE)
+    if (eeprom->use_eewr == TRUE)
        return e1000_write_eeprom_eewr(hw, offset, words, data);
    if (eeprom->type == e1000_eeprom_ich8)
@@ -5223,7 +5225,7 @@ e1000_write_eeprom(struct e1000_hw *hw,
    if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
        return -E1000_ERR_EEPROM;
-    if(eeprom->type == e1000_eeprom_microwire) {
+    if (eeprom->type == e1000_eeprom_microwire) {
        status = e1000_write_eeprom_microwire(hw, offset, words, data);
    } else {
        status = e1000_write_eeprom_spi(hw, offset, words, data);
@@ -5259,7 +5261,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
    while (widx < words) {
        uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
-        if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
+        if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
        e1000_standby_eeprom(hw);
@@ -5270,7 +5272,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
        e1000_standby_eeprom(hw);
        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if((eeprom->address_bits == 8) && (offset >= 128))
+        if ((eeprom->address_bits == 8) && (offset >= 128))
            write_opcode |= EEPROM_A8_OPCODE_SPI;
        /* Send the Write command (8-bit opcode + addr) */
@@ -5292,7 +5294,7 @@ e1000_write_eeprom_spi(struct e1000_hw *hw,
             * operation, while the smaller eeproms are capable of an 8-byte
             * PAGE WRITE operation.  Break the inner loop to pass new address
             */
-            if((((offset + widx)*2) % eeprom->page_size) == 0) {
+            if ((((offset + widx)*2) % eeprom->page_size) == 0) {
                e1000_standby_eeprom(hw);
                break;
            }
@@ -5358,12 +5360,12 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
         * signal that the command has been completed by raising the DO signal.
         * If DO does not go high in 10 milliseconds, then error out.
         */
-        for(i = 0; i < 200; i++) {
+        for (i = 0; i < 200; i++) {
            eecd = E1000_READ_REG(hw, EECD);
-            if(eecd & E1000_EECD_DO) break;
+            if (eecd & E1000_EECD_DO) break;
            udelay(50);
        }
-        if(i == 200) {
+        if (i == 200) {
            DEBUGOUT("EEPROM Write did not complete\n");
            return -E1000_ERR_EEPROM;
        }
@@ -5569,7 +5571,7 @@ e1000_read_part_num(struct e1000_hw *hw,
    DEBUGFUNC("e1000_read_part_num");
    /* Get word 0 from EEPROM */
-    if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+    if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
        DEBUGOUT("EEPROM Read Error\n");
        return -E1000_ERR_EEPROM;
    }
@@ -5577,7 +5579,7 @@ e1000_read_part_num(struct e1000_hw *hw,
    *part_num = (uint32_t) (eeprom_data << 16);
    /* Get word 1 from EEPROM */
-    if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
+    if (e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
        DEBUGOUT("EEPROM Read Error\n");
        return -E1000_ERR_EEPROM;
    }
@@ -5601,9 +5603,9 @@ e1000_read_mac_addr(struct e1000_hw * hw)
    DEBUGFUNC("e1000_read_mac_addr");
-    for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+    for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
        offset = i >> 1;
-        if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+        if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
            DEBUGOUT("EEPROM Read Error\n");
            return -E1000_ERR_EEPROM;
        }
@@ -5618,12 +5620,12 @@ e1000_read_mac_addr(struct e1000_hw * hw)
    case e1000_82546_rev_3:
    case e1000_82571:
    case e1000_80003es2lan:
-        if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
+        if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
            hw->perm_mac_addr[5] ^= 0x01;
        break;
    }
-    for(i = 0; i < NODE_ADDRESS_SIZE; i++)
+    for (i = 0; i < NODE_ADDRESS_SIZE; i++)
        hw->mac_addr[i] = hw->perm_mac_addr[i];
    return E1000_SUCCESS;
 }
@@ -5662,7 +5664,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
    /* Zero out the other 15 receive addresses. */
    DEBUGOUT("Clearing RAR[1-15]\n");
-    for(i = 1; i < rar_num; i++) {
+    for (i = 1; i < rar_num; i++) {
        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
        E1000_WRITE_FLUSH(hw);
        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5713,7 +5715,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
    if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
        num_rar_entry -= 1;
-    for(i = rar_used_count; i < num_rar_entry; i++) {
+    for (i = rar_used_count; i < num_rar_entry; i++) {
        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
        E1000_WRITE_FLUSH(hw);
        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
@@ -5725,13 +5727,13 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
    num_mta_entry = E1000_NUM_MTA_REGISTERS;
    if (hw->mac_type == e1000_ich8lan)
        num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
-    for(i = 0; i < num_mta_entry; i++) {
+    for (i = 0; i < num_mta_entry; i++) {
        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
        E1000_WRITE_FLUSH(hw);
    }
    /* Add the new addresses */
-    for(i = 0; i < mc_addr_count; i++) {
+    for (i = 0; i < mc_addr_count; i++) {
        DEBUGOUT(" Adding the multicast addresses:\n");
        DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
                  mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
@@ -5863,7 +5865,7 @@ e1000_mta_set(struct e1000_hw *hw,
     * in the MTA, save off the previous entry before writing and
     * restore the old value after writing.
     */
-    if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
+    if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
        temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
        E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
        E1000_WRITE_FLUSH(hw);
@@ -6013,7 +6015,7 @@ e1000_id_led_init(struct e1000_hw * hw)
    DEBUGFUNC("e1000_id_led_init");
-    if(hw->mac_type < e1000_82540) {
+    if (hw->mac_type < e1000_82540) {
        /* Nothing to do */
        return E1000_SUCCESS;
    }
@@ -6023,7 +6025,7 @@ e1000_id_led_init(struct e1000_hw * hw)
    hw->ledctl_mode1 = hw->ledctl_default;
    hw->ledctl_mode2 = hw->ledctl_default;
-    if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
+    if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
        DEBUGOUT("EEPROM Read Error\n");
        return -E1000_ERR_EEPROM;
    }
@@ -6040,7 +6042,7 @@ e1000_id_led_init(struct e1000_hw * hw)
    }
    for (i = 0; i < 4; i++) {
        temp = (eeprom_data >> (i << 2)) & led_mask;
-        switch(temp) {
+        switch (temp) {
        case ID_LED_ON1_DEF2:
        case ID_LED_ON1_ON2:
        case ID_LED_ON1_OFF2:
@@ -6057,7 +6059,7 @@ e1000_id_led_init(struct e1000_hw * hw)
            /* Do nothing */
            break;
        }
-        switch(temp) {
+        switch (temp) {
        case ID_LED_DEF1_ON2:
        case ID_LED_ON1_ON2:
        case ID_LED_OFF1_ON2:
@@ -6091,7 +6093,7 @@ e1000_setup_led(struct e1000_hw *hw)
    DEBUGFUNC("e1000_setup_led");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82542_rev2_0:
    case e1000_82542_rev2_1:
    case e1000_82543:
@@ -6105,16 +6107,16 @@ e1000_setup_led(struct e1000_hw *hw)
        /* Turn off PHY Smart Power Down (if enabled) */
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
                                     &hw->phy_spd_default);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
                                      (uint16_t)(hw->phy_spd_default &
                                      ~IGP01E1000_GMII_SPD));
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* Fall Through */
    default:
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            ledctl = E1000_READ_REG(hw, LEDCTL);
            /* Save current LEDCTL settings */
            hw->ledctl_default = ledctl;
@@ -6125,7 +6127,7 @@ e1000_setup_led(struct e1000_hw *hw)
            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
                       E1000_LEDCTL_LED0_MODE_SHIFT);
            E1000_WRITE_REG(hw, LEDCTL, ledctl);
-        } else if(hw->media_type == e1000_media_type_copper)
+        } else if (hw->media_type == e1000_media_type_copper)
            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
        break;
    }
@@ -6133,6 +6135,7 @@ e1000_setup_led(struct e1000_hw *hw)
    return E1000_SUCCESS;
 }
 /******************************************************************************
 * Used on 82571 and later Si that has LED blink bits.
 * Callers must use their own timer and should have already called
@@ -6183,7 +6186,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
    DEBUGFUNC("e1000_cleanup_led");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82542_rev2_0:
    case e1000_82542_rev2_1:
    case e1000_82543:
@@ -6197,7 +6200,7 @@ e1000_cleanup_led(struct e1000_hw *hw)
        /* Turn on PHY Smart Power Down (if previously enabled) */
        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
                                      hw->phy_spd_default);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* Fall Through */
    default:
@@ -6225,7 +6228,7 @@ e1000_led_on(struct e1000_hw *hw)
    DEBUGFUNC("e1000_led_on");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82542_rev2_0:
    case e1000_82542_rev2_1:
    case e1000_82543:
@@ -6234,7 +6237,7 @@ e1000_led_on(struct e1000_hw *hw)
        ctrl |= E1000_CTRL_SWDPIO0;
        break;
    case e1000_82544:
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            /* Set SW Defineable Pin 0 to turn on the LED */
            ctrl |= E1000_CTRL_SWDPIN0;
            ctrl |= E1000_CTRL_SWDPIO0;
@@ -6245,7 +6248,7 @@ e1000_led_on(struct e1000_hw *hw)
        }
        break;
    default:
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            /* Clear SW Defineable Pin 0 to turn on the LED */
            ctrl &= ~E1000_CTRL_SWDPIN0;
            ctrl |= E1000_CTRL_SWDPIO0;
@@ -6276,7 +6279,7 @@ e1000_led_off(struct e1000_hw *hw)
    DEBUGFUNC("e1000_led_off");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82542_rev2_0:
    case e1000_82542_rev2_1:
    case e1000_82543:
@@ -6285,7 +6288,7 @@ e1000_led_off(struct e1000_hw *hw)
        ctrl |= E1000_CTRL_SWDPIO0;
        break;
    case e1000_82544:
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            /* Clear SW Defineable Pin 0 to turn off the LED */
            ctrl &= ~E1000_CTRL_SWDPIN0;
            ctrl |= E1000_CTRL_SWDPIO0;
@@ -6296,7 +6299,7 @@ e1000_led_off(struct e1000_hw *hw)
        }
        break;
    default:
-        if(hw->media_type == e1000_media_type_fiber) {
+        if (hw->media_type == e1000_media_type_fiber) {
            /* Set SW Defineable Pin 0 to turn off the LED */
            ctrl |= E1000_CTRL_SWDPIN0;
            ctrl |= E1000_CTRL_SWDPIO0;
@@ -6320,7 +6323,7 @@ e1000_led_off(struct e1000_hw *hw)
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
-static void
+void
 e1000_clear_hw_cntrs(struct e1000_hw *hw)
 {
    volatile uint32_t temp;
@@ -6383,7 +6386,7 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
    temp = E1000_READ_REG(hw, MPTC);
    temp = E1000_READ_REG(hw, BPTC);
-    if(hw->mac_type < e1000_82543) return;
+    if (hw->mac_type < e1000_82543) return;
    temp = E1000_READ_REG(hw, ALGNERRC);
    temp = E1000_READ_REG(hw, RXERRC);
@@ -6392,13 +6395,13 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
    temp = E1000_READ_REG(hw, TSCTC);
    temp = E1000_READ_REG(hw, TSCTFC);
-    if(hw->mac_type <= e1000_82544) return;
+    if (hw->mac_type <= e1000_82544) return;
    temp = E1000_READ_REG(hw, MGTPRC);
    temp = E1000_READ_REG(hw, MGTPDC);
    temp = E1000_READ_REG(hw, MGTPTC);
-    if(hw->mac_type <= e1000_82547_rev_2) return;
+    if (hw->mac_type <= e1000_82547_rev_2) return;
    temp = E1000_READ_REG(hw, IAC);
    temp = E1000_READ_REG(hw, ICRXOC);
@@ -6429,8 +6432,8 @@ e1000_reset_adaptive(struct e1000_hw *hw)
 {
    DEBUGFUNC("e1000_reset_adaptive");
-    if(hw->adaptive_ifs) {
+    if (hw->adaptive_ifs) {
-        if(!hw->ifs_params_forced) {
+        if (!hw->ifs_params_forced) {
            hw->current_ifs_val = 0;
            hw->ifs_min_val = IFS_MIN;
            hw->ifs_max_val = IFS_MAX;
@@ -6457,12 +6460,12 @@ e1000_update_adaptive(struct e1000_hw *hw)
 {
    DEBUGFUNC("e1000_update_adaptive");
-    if(hw->adaptive_ifs) {
+    if (hw->adaptive_ifs) {
-        if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
+        if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
-            if(hw->tx_packet_delta > MIN_NUM_XMITS) {
+            if (hw->tx_packet_delta > MIN_NUM_XMITS) {
                hw->in_ifs_mode = TRUE;
-                if(hw->current_ifs_val < hw->ifs_max_val) {
+                if (hw->current_ifs_val < hw->ifs_max_val) {
-                    if(hw->current_ifs_val == 0)
+                    if (hw->current_ifs_val == 0)
                        hw->current_ifs_val = hw->ifs_min_val;
                    else
                        hw->current_ifs_val += hw->ifs_step_size;
@@ -6470,7 +6473,7 @@ e1000_update_adaptive(struct e1000_hw *hw)
                }
            }
        } else {
-            if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
+            if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
                hw->current_ifs_val = 0;
                hw->in_ifs_mode = FALSE;
                E1000_WRITE_REG(hw, AIT, 0);
@@ -6517,46 +6520,46 @@ e1000_tbi_adjust_stats(struct e1000_hw *hw,
     * This could be simplified if all environments supported
     * 64-bit integers.
     */
-    if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
+    if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
        stats->gorch++;
    /* Is this a broadcast or multicast?  Check broadcast first,
     * since the test for a multicast frame will test positive on
     * a broadcast frame.
     */
-    if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
+    if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
        /* Broadcast packet */
        stats->bprc++;
-    else if(*mac_addr & 0x01)
+    else if (*mac_addr & 0x01)
        /* Multicast packet */
        stats->mprc++;
-    if(frame_len == hw->max_frame_size) {
+    if (frame_len == hw->max_frame_size) {
        /* In this case, the hardware has overcounted the number of
         * oversize frames.
         */
-        if(stats->roc > 0)
+        if (stats->roc > 0)
            stats->roc--;
    }
    /* Adjust the bin counters when the extra byte put the frame in the
     * wrong bin. Remember that the frame_len was adjusted above.
     */
-    if(frame_len == 64) {
+    if (frame_len == 64) {
        stats->prc64++;
        stats->prc127--;
-    } else if(frame_len == 127) {
+    } else if (frame_len == 127) {
        stats->prc127++;
        stats->prc255--;
-    } else if(frame_len == 255) {
+    } else if (frame_len == 255) {
        stats->prc255++;
        stats->prc511--;
-    } else if(frame_len == 511) {
+    } else if (frame_len == 511) {
        stats->prc511++;
        stats->prc1023--;
-    } else if(frame_len == 1023) {
+    } else if (frame_len == 1023) {
        stats->prc1023++;
        stats->prc1522--;
-    } else if(frame_len == 1522) {
+    } else if (frame_len == 1522) {
        stats->prc1522++;
    }
 }
@@ -6596,10 +6599,10 @@ e1000_get_bus_info(struct e1000_hw *hw)
        hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
                       e1000_bus_type_pcix : e1000_bus_type_pci;
-        if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
+        if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
            hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
                            e1000_bus_speed_66 : e1000_bus_speed_120;
-        } else if(hw->bus_type == e1000_bus_type_pci) {
+        } else if (hw->bus_type == e1000_bus_type_pci) {
            hw->bus_speed = (status & E1000_STATUS_PCI66) ?
                            e1000_bus_speed_66 : e1000_bus_speed_33;
        } else {
@@ -6694,11 +6697,11 @@ e1000_get_cable_length(struct e1000_hw *hw,
    *min_length = *max_length = 0;
    /* Use old method for Phy older than IGP */
-    if(hw->phy_type == e1000_phy_m88) {
+    if (hw->phy_type == e1000_phy_m88) {
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
                       M88E1000_PSSR_CABLE_LENGTH_SHIFT;
@@ -6757,7 +6760,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
            return -E1000_ERR_PHY;
            break;
        }
-    } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
+    } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
        uint16_t cur_agc_value;
        uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
        uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
@@ -6766,10 +6769,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
                                                          IGP01E1000_PHY_AGC_C,
                                                          IGP01E1000_PHY_AGC_D};
        /* Read the AGC registers for all channels */
-        for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+        for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
@@ -6819,7 +6822,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
            if (ret_val)
                return ret_val;
-            /* Getting bits 15:9, which represent the combination of course and
+            /* Getting bits 15:9, which represent the combination of course and
             * fine gain values.  The result is a number that can be put into
             * the lookup table to obtain the approximate cable length. */
            cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
@@ -6884,7 +6887,7 @@ e1000_check_polarity(struct e1000_hw *hw,
        /* return the Polarity bit in the Status register. */
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
                    M88E1000_PSSR_REV_POLARITY_SHIFT;
@@ -6894,18 +6897,18 @@ e1000_check_polarity(struct e1000_hw *hw,
        /* Read the Status register to check the speed */
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
         * find the polarity status */
-        if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+        if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
           IGP01E1000_PSSR_SPEED_1000MBPS) {
            /* Read the GIG initialization PCS register (0x00B4) */
            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
                                         &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            /* Check the polarity bits */
@@ -6954,7 +6957,7 @@ e1000_check_downshift(struct e1000_hw *hw)
        hw->phy_type == e1000_phy_igp_2) {
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
@@ -6962,7 +6965,7 @@ e1000_check_downshift(struct e1000_hw *hw)
               (hw->phy_type == e1000_phy_gg82563)) {
        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
                                     &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
@@ -7002,42 +7005,42 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
    DEBUGFUNC("e1000_config_dsp_after_link_change");
-    if(hw->phy_type != e1000_phy_igp)
+    if (hw->phy_type != e1000_phy_igp)
        return E1000_SUCCESS;
-    if(link_up) {
+    if (link_up) {
        ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-        if(ret_val) {
+        if (ret_val) {
            DEBUGOUT("Error getting link speed and duplex\n");
            return ret_val;
        }
-        if(speed == SPEED_1000) {
+        if (speed == SPEED_1000) {
            ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
            if (ret_val)
                return ret_val;
-            if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
+            if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
                min_length >= e1000_igp_cable_length_50) {
-                for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
                    ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
                                                 &phy_data);
-                    if(ret_val)
+                    if (ret_val)
                        return ret_val;
                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
                    ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
                                                  phy_data);
-                    if(ret_val)
+                    if (ret_val)
                        return ret_val;
                }
                hw->dsp_config_state = e1000_dsp_config_activated;
            }
-            if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
+            if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
               (min_length < e1000_igp_cable_length_50)) {
                uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
@@ -7046,70 +7049,70 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
                /* clear previous idle error counts */
                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
                                             &phy_data);
-                if(ret_val)
+                if (ret_val)
                    return ret_val;
-                for(i = 0; i < ffe_idle_err_timeout; i++) {
+                for (i = 0; i < ffe_idle_err_timeout; i++) {
                    udelay(1000);
                    ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
                                                 &phy_data);
-                    if(ret_val)
+                    if (ret_val)
                        return ret_val;
                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
-                    if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
+                    if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
                        hw->ffe_config_state = e1000_ffe_config_active;
                        ret_val = e1000_write_phy_reg(hw,
                                    IGP01E1000_PHY_DSP_FFE,
                                    IGP01E1000_PHY_DSP_FFE_CM_CP);
-                        if(ret_val)
+                        if (ret_val)
                            return ret_val;
                        break;
                    }
-                    if(idle_errs)
+                    if (idle_errs)
                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
                }
            }
        }
    } else {
-        if(hw->dsp_config_state == e1000_dsp_config_activated) {
+        if (hw->dsp_config_state == e1000_dsp_config_activated) {
            /* Save off the current value of register 0x2F5B to be restored at
             * the end of the routines. */
            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            /* Disable the PHY transmitter */
            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            msec_delay_irq(20);
            ret_val = e1000_write_phy_reg(hw, 0x0000,
                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
-            for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+            for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
                ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
-                if(ret_val)
+                if (ret_val)
                    return ret_val;
                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
                ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
-                if(ret_val)
+                if (ret_val)
                    return ret_val;
            }
            ret_val = e1000_write_phy_reg(hw, 0x0000,
                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            msec_delay_irq(20);
@@ -7117,40 +7120,40 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
            /* Now enable the transmitter */
            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            hw->dsp_config_state = e1000_dsp_config_enabled;
        }
-        if(hw->ffe_config_state == e1000_ffe_config_active) {
+        if (hw->ffe_config_state == e1000_ffe_config_active) {
            /* Save off the current value of register 0x2F5B to be restored at
             * the end of the routines. */
            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            /* Disable the PHY transmitter */
            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            msec_delay_irq(20);
            ret_val = e1000_write_phy_reg(hw, 0x0000,
                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_write_phy_reg(hw, 0x0000,
                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            msec_delay_irq(20);
@@ -7158,7 +7161,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
            /* Now enable the transmitter */
            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            hw->ffe_config_state = e1000_ffe_config_enabled;
@@ -7183,20 +7186,20 @@ e1000_set_phy_mode(struct e1000_hw *hw)
    DEBUGFUNC("e1000_set_phy_mode");
-    if((hw->mac_type == e1000_82545_rev_3) &&
+    if ((hw->mac_type == e1000_82545_rev_3) &&
-       (hw->media_type == e1000_media_type_copper)) {
+        (hw->media_type == e1000_media_type_copper)) {
        ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
-        if(ret_val) {
+        if (ret_val) {
            return ret_val;
        }
-        if((eeprom_data != EEPROM_RESERVED_WORD) &&
+        if ((eeprom_data != EEPROM_RESERVED_WORD) &&
-           (eeprom_data & EEPROM_PHY_CLASS_A)) {
+            (eeprom_data & EEPROM_PHY_CLASS_A)) {
            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            hw->phy_reset_disable = FALSE;
@@ -7247,16 +7250,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
        phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
    } else {
        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
-    if(!active) {
+    if (!active) {
-        if(hw->mac_type == e1000_82541_rev_2 ||
+        if (hw->mac_type == e1000_82541_rev_2 ||
-           hw->mac_type == e1000_82547_rev_2) {
+            hw->mac_type == e1000_82547_rev_2) {
            phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        } else {
            if (hw->mac_type == e1000_ich8lan) {
@@ -7278,13 +7281,13 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
        if (hw->smart_speed == e1000_smart_speed_on) {
            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                         &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                          phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        } else if (hw->smart_speed == e1000_smart_speed_off) {
            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7295,19 +7298,19 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                          phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        }
-    } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
+    } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
-              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
+               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
-              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
+               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
-        if(hw->mac_type == e1000_82541_rev_2 ||
+        if (hw->mac_type == e1000_82541_rev_2 ||
            hw->mac_type == e1000_82547_rev_2) {
            phy_data |= IGP01E1000_GMII_FLEX_SPD;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        } else {
            if (hw->mac_type == e1000_ich8lan) {
@@ -7324,12 +7327,12 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
        /* When LPLU is enabled we should disable SmartSpeed */
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
@@ -7359,14 +7362,14 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
    uint16_t phy_data;
    DEBUGFUNC("e1000_set_d0_lplu_state");
-    if(hw->mac_type <= e1000_82547_rev_2)
+    if (hw->mac_type <= e1000_82547_rev_2)
        return E1000_SUCCESS;
    if (hw->mac_type == e1000_ich8lan) {
        phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
    } else {
        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
@@ -7388,13 +7391,13 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
        if (hw->smart_speed == e1000_smart_speed_on) {
            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                         &phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                          phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        } else if (hw->smart_speed == e1000_smart_speed_off) {
            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
@@ -7405,7 +7408,7 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
                                          phy_data);
-            if(ret_val)
+            if (ret_val)
                return ret_val;
        }
@@ -7424,12 +7427,12 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
        /* When LPLU is enabled we should disable SmartSpeed */
        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
    }
@@ -7450,7 +7453,7 @@ e1000_set_vco_speed(struct e1000_hw *hw)
    DEBUGFUNC("e1000_set_vco_speed");
-    switch(hw->mac_type) {
+    switch (hw->mac_type) {
    case e1000_82545_rev_3:
    case e1000_82546_rev_3:
       break;
@@ -7461,39 +7464,39 @@ e1000_set_vco_speed(struct e1000_hw *hw)
    /* Set PHY register 30, page 5, bit 8 to 0 */
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* Set PHY register 30, page 4, bit 11 to 1 */
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    return E1000_SUCCESS;
@@ -7572,7 +7575,7 @@ e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
 {
    uint8_t *tmp;
    uint8_t *bufptr = buffer;
-    uint32_t data;
+    uint32_t data = 0;
    uint16_t remaining, i, j, prev_bytes;
    /* sum = only sum of the data and it is not checksum */
@@ -7652,7 +7655,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
    buffer = (uint8_t *) hdr;
    i = length;
-    while(i--)
+    while (i--)
        sum += buffer[i];
    hdr->checksum = 0 - sum;
@@ -7675,8 +7678,7 @@ e1000_mng_write_cmd_header(struct e1000_hw * hw,
 * returns  - E1000_SUCCESS for success.
 ****************************************************************************/
 static int32_t
-e1000_mng_write_commit(
+e1000_mng_write_commit(struct e1000_hw * hw)
-    struct e1000_hw * hw)
 {
    uint32_t hicr;
@@ -7848,31 +7850,31 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
    /* Disable the transmitter on the PHY */
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* This loop will early-out if the NO link condition has been met. */
-    for(i = PHY_FORCE_TIME; i > 0; i--) {
+    for (i = PHY_FORCE_TIME; i > 0; i--) {
        /* Read the MII Status Register and wait for Link Status bit
         * to be clear.
         */
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
+        if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
        msec_delay_irq(100);
    }
@@ -7882,40 +7884,40 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
    /* Now we will re-enable th transmitter on the PHY */
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    msec_delay_irq(50);
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    msec_delay_irq(50);
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    msec_delay_irq(50);
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if(ret_val)
+    if (ret_val)
        return ret_val;
    /* This loop will early-out if the link condition has been met. */
-    for(i = PHY_FORCE_TIME; i > 0; i--) {
+    for (i = PHY_FORCE_TIME; i > 0; i--) {
        /* Read the MII Status Register and wait for Link Status bit
         * to be set.
         */
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if(ret_val)
+        if (ret_val)
            return ret_val;
-        if(mii_status_reg & MII_SR_LINK_STATUS) break;
+        if (mii_status_reg & MII_SR_LINK_STATUS) break;
        msec_delay_irq(100);
    }
    return E1000_SUCCESS;
@@ -7994,15 +7996,15 @@ e1000_disable_pciex_master(struct e1000_hw *hw)
    e1000_set_pci_express_master_disable(hw);
-    while(timeout) {
+    while (timeout) {
-        if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
+        if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
            break;
        else
            udelay(100);
        timeout--;
    }
-    if(!timeout) {
+    if (!timeout) {
        DEBUGOUT("Master requests are pending.\n");
        return -E1000_ERR_MASTER_REQUESTS_PENDING;
    }
@@ -8043,7 +8045,7 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
            timeout--;
        }
-        if(!timeout) {
+        if (!timeout) {
            DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
            return -E1000_ERR_RESET;
        }
@@ -8124,7 +8126,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
    DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
-    if(!hw->eeprom_semaphore_present)
+    if (!hw->eeprom_semaphore_present)
        return E1000_SUCCESS;
    if (hw->mac_type == e1000_80003es2lan) {
@@ -8135,20 +8137,20 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
    /* Get the FW semaphore. */
    timeout = hw->eeprom.word_size + 1;
-    while(timeout) {
+    while (timeout) {
        swsm = E1000_READ_REG(hw, SWSM);
        swsm |= E1000_SWSM_SWESMBI;
        E1000_WRITE_REG(hw, SWSM, swsm);
        /* if we managed to set the bit we got the semaphore. */
        swsm = E1000_READ_REG(hw, SWSM);
-        if(swsm & E1000_SWSM_SWESMBI)
+        if (swsm & E1000_SWSM_SWESMBI)
            break;
        udelay(50);
        timeout--;
    }
-    if(!timeout) {
+    if (!timeout) {
        /* Release semaphores */
        e1000_put_hw_eeprom_semaphore(hw);
        DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
@@ -8173,7 +8175,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
    DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
-    if(!hw->eeprom_semaphore_present)
+    if (!hw->eeprom_semaphore_present)
        return;
    swsm = E1000_READ_REG(hw, SWSM);
@@ -8206,16 +8208,16 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
    if (hw->mac_type != e1000_80003es2lan)
        return E1000_SUCCESS;
-    while(timeout) {
+    while (timeout) {
        swsm = E1000_READ_REG(hw, SWSM);
        /* If SMBI bit cleared, it is now set and we hold the semaphore */
-        if(!(swsm & E1000_SWSM_SMBI))
+        if (!(swsm & E1000_SWSM_SMBI))
            break;
        msec_delay_irq(1);
        timeout--;
    }
-    if(!timeout) {
+    if (!timeout) {
        DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
        return -E1000_ERR_RESET;
    }
@@ -8291,7 +8293,7 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
    case e1000_82573:
    case e1000_80003es2lan:
        fwsm = E1000_READ_REG(hw, FWSM);
-        if((fwsm & E1000_FWSM_MODE_MASK) != 0)
+        if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
            return TRUE;
        break;
    case e1000_ich8lan:
author	Auke Kok <auke\\\-jan.h.kok@intel.com>	2006-08-28 17:56:16 -0400
committer	Auke Kok <juke-jan.h.kok@intel.com>	2006-08-28 17:56:16 -0400
commit	8fc897b00a7d81ffaa24e18881c2d6b10698ab0b (patch)
tree	3dac8c72398e8a23228b2a5edd5c926c2a58675d /drivers/net/e1000/e1000_hw.c
parent	699a71238856b19091503c671bac8abb1e3f9a3a (diff)