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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/e1000/e1000_hw.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c5405
1 files changed, 5405 insertions, 0 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
new file mode 100644
index 000000000000..786a9b935659
--- /dev/null
+++ b/drivers/net/e1000/e1000_hw.c
@@ -0,0 +1,5405 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33#include "e1000_hw.h"
34
35static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36static void e1000_phy_init_script(struct e1000_hw *hw);
37static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
45 uint16_t count);
46static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
52 uint16_t *data);
53static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
57 uint16_t count);
58static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
59 uint16_t phy_data);
60static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
61 uint16_t *phy_data);
62static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70
71/* IGP cable length table */
72static const
73uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
74 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
75 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
76 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
77 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
78 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
79 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82
83
84/******************************************************************************
85 * Set the phy type member in the hw struct.
86 *
87 * hw - Struct containing variables accessed by shared code
88 *****************************************************************************/
89int32_t
90e1000_set_phy_type(struct e1000_hw *hw)
91{
92 DEBUGFUNC("e1000_set_phy_type");
93
94 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88;
99 break;
100 case IGP01E1000_I_PHY_ID:
101 if(hw->mac_type == e1000_82541 ||
102 hw->mac_type == e1000_82541_rev_2 ||
103 hw->mac_type == e1000_82547 ||
104 hw->mac_type == e1000_82547_rev_2) {
105 hw->phy_type = e1000_phy_igp;
106 break;
107 }
108 /* Fall Through */
109 default:
110 /* Should never have loaded on this device */
111 hw->phy_type = e1000_phy_undefined;
112 return -E1000_ERR_PHY_TYPE;
113 }
114
115 return E1000_SUCCESS;
116}
117
118/******************************************************************************
119 * IGP phy init script - initializes the GbE PHY
120 *
121 * hw - Struct containing variables accessed by shared code
122 *****************************************************************************/
123static void
124e1000_phy_init_script(struct e1000_hw *hw)
125{
126 uint32_t ret_val;
127 uint16_t phy_saved_data;
128
129 DEBUGFUNC("e1000_phy_init_script");
130
131
132 if(hw->phy_init_script) {
133 msec_delay(20);
134
135 /* Save off the current value of register 0x2F5B to be restored at
136 * the end of this routine. */
137 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
138
139 /* Disabled the PHY transmitter */
140 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
141
142 msec_delay(20);
143
144 e1000_write_phy_reg(hw,0x0000,0x0140);
145
146 msec_delay(5);
147
148 switch(hw->mac_type) {
149 case e1000_82541:
150 case e1000_82547:
151 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
152
153 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
154
155 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
156
157 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
158
159 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
160
161 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
162
163 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
164
165 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
166
167 e1000_write_phy_reg(hw, 0x2010, 0x0008);
168 break;
169
170 case e1000_82541_rev_2:
171 case e1000_82547_rev_2:
172 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
173 break;
174 default:
175 break;
176 }
177
178 e1000_write_phy_reg(hw, 0x0000, 0x3300);
179
180 msec_delay(20);
181
182 /* Now enable the transmitter */
183 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
184
185 if(hw->mac_type == e1000_82547) {
186 uint16_t fused, fine, coarse;
187
188 /* Move to analog registers page */
189 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
190
191 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
192 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
193
194 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
195 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
196
197 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
198 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
199 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
200 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202
203 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
204 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
205 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
206
207 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
208 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
209 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
210 }
211 }
212 }
213}
214
215/******************************************************************************
216 * Set the mac type member in the hw struct.
217 *
218 * hw - Struct containing variables accessed by shared code
219 *****************************************************************************/
220int32_t
221e1000_set_mac_type(struct e1000_hw *hw)
222{
223 DEBUGFUNC("e1000_set_mac_type");
224
225 switch (hw->device_id) {
226 case E1000_DEV_ID_82542:
227 switch (hw->revision_id) {
228 case E1000_82542_2_0_REV_ID:
229 hw->mac_type = e1000_82542_rev2_0;
230 break;
231 case E1000_82542_2_1_REV_ID:
232 hw->mac_type = e1000_82542_rev2_1;
233 break;
234 default:
235 /* Invalid 82542 revision ID */
236 return -E1000_ERR_MAC_TYPE;
237 }
238 break;
239 case E1000_DEV_ID_82543GC_FIBER:
240 case E1000_DEV_ID_82543GC_COPPER:
241 hw->mac_type = e1000_82543;
242 break;
243 case E1000_DEV_ID_82544EI_COPPER:
244 case E1000_DEV_ID_82544EI_FIBER:
245 case E1000_DEV_ID_82544GC_COPPER:
246 case E1000_DEV_ID_82544GC_LOM:
247 hw->mac_type = e1000_82544;
248 break;
249 case E1000_DEV_ID_82540EM:
250 case E1000_DEV_ID_82540EM_LOM:
251 case E1000_DEV_ID_82540EP:
252 case E1000_DEV_ID_82540EP_LOM:
253 case E1000_DEV_ID_82540EP_LP:
254 hw->mac_type = e1000_82540;
255 break;
256 case E1000_DEV_ID_82545EM_COPPER:
257 case E1000_DEV_ID_82545EM_FIBER:
258 hw->mac_type = e1000_82545;
259 break;
260 case E1000_DEV_ID_82545GM_COPPER:
261 case E1000_DEV_ID_82545GM_FIBER:
262 case E1000_DEV_ID_82545GM_SERDES:
263 hw->mac_type = e1000_82545_rev_3;
264 break;
265 case E1000_DEV_ID_82546EB_COPPER:
266 case E1000_DEV_ID_82546EB_FIBER:
267 case E1000_DEV_ID_82546EB_QUAD_COPPER:
268 hw->mac_type = e1000_82546;
269 break;
270 case E1000_DEV_ID_82546GB_COPPER:
271 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE:
274 hw->mac_type = e1000_82546_rev_3;
275 break;
276 case E1000_DEV_ID_82541EI:
277 case E1000_DEV_ID_82541EI_MOBILE:
278 hw->mac_type = e1000_82541;
279 break;
280 case E1000_DEV_ID_82541ER:
281 case E1000_DEV_ID_82541GI:
282 case E1000_DEV_ID_82541GI_LF:
283 case E1000_DEV_ID_82541GI_MOBILE:
284 hw->mac_type = e1000_82541_rev_2;
285 break;
286 case E1000_DEV_ID_82547EI:
287 hw->mac_type = e1000_82547;
288 break;
289 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2;
291 break;
292 default:
293 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE;
295 }
296
297 switch(hw->mac_type) {
298 case e1000_82541:
299 case e1000_82547:
300 case e1000_82541_rev_2:
301 case e1000_82547_rev_2:
302 hw->asf_firmware_present = TRUE;
303 break;
304 default:
305 break;
306 }
307
308 return E1000_SUCCESS;
309}
310
311/*****************************************************************************
312 * Set media type and TBI compatibility.
313 *
314 * hw - Struct containing variables accessed by shared code
315 * **************************************************************************/
316void
317e1000_set_media_type(struct e1000_hw *hw)
318{
319 uint32_t status;
320
321 DEBUGFUNC("e1000_set_media_type");
322
323 if(hw->mac_type != e1000_82543) {
324 /* tbi_compatibility is only valid on 82543 */
325 hw->tbi_compatibility_en = FALSE;
326 }
327
328 switch (hw->device_id) {
329 case E1000_DEV_ID_82545GM_SERDES:
330 case E1000_DEV_ID_82546GB_SERDES:
331 hw->media_type = e1000_media_type_internal_serdes;
332 break;
333 default:
334 if(hw->mac_type >= e1000_82543) {
335 status = E1000_READ_REG(hw, STATUS);
336 if(status & E1000_STATUS_TBIMODE) {
337 hw->media_type = e1000_media_type_fiber;
338 /* tbi_compatibility not valid on fiber */
339 hw->tbi_compatibility_en = FALSE;
340 } else {
341 hw->media_type = e1000_media_type_copper;
342 }
343 } else {
344 /* This is an 82542 (fiber only) */
345 hw->media_type = e1000_media_type_fiber;
346 }
347 }
348}
349
350/******************************************************************************
351 * Reset the transmit and receive units; mask and clear all interrupts.
352 *
353 * hw - Struct containing variables accessed by shared code
354 *****************************************************************************/
355int32_t
356e1000_reset_hw(struct e1000_hw *hw)
357{
358 uint32_t ctrl;
359 uint32_t ctrl_ext;
360 uint32_t icr;
361 uint32_t manc;
362 uint32_t led_ctrl;
363
364 DEBUGFUNC("e1000_reset_hw");
365
366 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
367 if(hw->mac_type == e1000_82542_rev2_0) {
368 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
369 e1000_pci_clear_mwi(hw);
370 }
371
372 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff);
375
376 /* Disable the Transmit and Receive units. Then delay to allow
377 * any pending transactions to complete before we hit the MAC with
378 * the global reset.
379 */
380 E1000_WRITE_REG(hw, RCTL, 0);
381 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
382 E1000_WRITE_FLUSH(hw);
383
384 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
385 hw->tbi_compatibility_on = FALSE;
386
387 /* Delay to allow any outstanding PCI transactions to complete before
388 * resetting the device
389 */
390 msec_delay(10);
391
392 ctrl = E1000_READ_REG(hw, CTRL);
393
394 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5);
398 }
399
400 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self-
403 * clearing, and should clear within a microsecond.
404 */
405 DEBUGOUT("Issuing a global reset to MAC\n");
406
407 switch(hw->mac_type) {
408 case e1000_82544:
409 case e1000_82540:
410 case e1000_82545:
411 case e1000_82546:
412 case e1000_82541:
413 case e1000_82541_rev_2:
414 /* These controllers can't ack the 64-bit write when issuing the
415 * reset, so use IO-mapping as a workaround to issue the reset */
416 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
417 break;
418 case e1000_82545_rev_3:
419 case e1000_82546_rev_3:
420 /* Reset is performed on a shadow of the control register */
421 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
422 break;
423 default:
424 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
425 break;
426 }
427
428 /* After MAC reset, force reload of EEPROM to restore power-on settings to
429 * device. Later controllers reload the EEPROM automatically, so just wait
430 * for reload to complete.
431 */
432 switch(hw->mac_type) {
433 case e1000_82542_rev2_0:
434 case e1000_82542_rev2_1:
435 case e1000_82543:
436 case e1000_82544:
437 /* Wait for reset to complete */
438 udelay(10);
439 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
440 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
441 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
442 E1000_WRITE_FLUSH(hw);
443 /* Wait for EEPROM reload */
444 msec_delay(2);
445 break;
446 case e1000_82541:
447 case e1000_82541_rev_2:
448 case e1000_82547:
449 case e1000_82547_rev_2:
450 /* Wait for EEPROM reload */
451 msec_delay(20);
452 break;
453 default:
454 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5);
456 break;
457 }
458
459 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) {
461 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc);
464 }
465
466 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
467 e1000_phy_init_script(hw);
468
469 /* Configure activity LED after PHY reset */
470 led_ctrl = E1000_READ_REG(hw, LEDCTL);
471 led_ctrl &= IGP_ACTIVITY_LED_MASK;
472 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
473 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
474 }
475
476 /* Clear interrupt mask to stop board from generating interrupts */
477 DEBUGOUT("Masking off all interrupts\n");
478 E1000_WRITE_REG(hw, IMC, 0xffffffff);
479
480 /* Clear any pending interrupt events. */
481 icr = E1000_READ_REG(hw, ICR);
482
483 /* If MWI was previously enabled, reenable it. */
484 if(hw->mac_type == e1000_82542_rev2_0) {
485 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
486 e1000_pci_set_mwi(hw);
487 }
488
489 return E1000_SUCCESS;
490}
491
492/******************************************************************************
493 * Performs basic configuration of the adapter.
494 *
495 * hw - Struct containing variables accessed by shared code
496 *
497 * Assumes that the controller has previously been reset and is in a
498 * post-reset uninitialized state. Initializes the receive address registers,
499 * multicast table, and VLAN filter table. Calls routines to setup link
500 * configuration and flow control settings. Clears all on-chip counters. Leaves
501 * the transmit and receive units disabled and uninitialized.
502 *****************************************************************************/
503int32_t
504e1000_init_hw(struct e1000_hw *hw)
505{
506 uint32_t ctrl;
507 uint32_t i;
508 int32_t ret_val;
509 uint16_t pcix_cmd_word;
510 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc;
513 DEBUGFUNC("e1000_init_hw");
514
515 /* Initialize Identification LED */
516 ret_val = e1000_id_led_init(hw);
517 if(ret_val) {
518 DEBUGOUT("Error Initializing Identification LED\n");
519 return ret_val;
520 }
521
522 /* Set the media type and TBI compatibility */
523 e1000_set_media_type(hw);
524
525 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0);
528
529 e1000_clear_vfta(hw);
530
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
532 if(hw->mac_type == e1000_82542_rev2_0) {
533 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
534 e1000_pci_clear_mwi(hw);
535 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
536 E1000_WRITE_FLUSH(hw);
537 msec_delay(5);
538 }
539
540 /* Setup the receive address. This involves initializing all of the Receive
541 * Address Registers (RARs 0 - 15).
542 */
543 e1000_init_rx_addrs(hw);
544
545 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
546 if(hw->mac_type == e1000_82542_rev2_0) {
547 E1000_WRITE_REG(hw, RCTL, 0);
548 E1000_WRITE_FLUSH(hw);
549 msec_delay(1);
550 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
551 e1000_pci_set_mwi(hw);
552 }
553
554 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558
559 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives.
562 */
563 if(hw->dma_fairness) {
564 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 }
567
568 switch(hw->mac_type) {
569 case e1000_82545_rev_3:
570 case e1000_82546_rev_3:
571 break;
572 default:
573 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
574 if(hw->bus_type == e1000_bus_type_pcix) {
575 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
576 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
577 &pcix_stat_hi_word);
578 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
579 PCIX_COMMAND_MMRBC_SHIFT;
580 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
581 PCIX_STATUS_HI_MMRBC_SHIFT;
582 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
583 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
584 if(cmd_mmrbc > stat_mmrbc) {
585 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
586 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
587 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
588 &pcix_cmd_word);
589 }
590 }
591 break;
592 }
593
594 /* Call a subroutine to configure the link and setup flow control. */
595 ret_val = e1000_setup_link(hw);
596
597 /* Set the transmit descriptor write-back policy */
598 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
601 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 }
603
604 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there
607 * is no link.
608 */
609 e1000_clear_hw_cntrs(hw);
610
611 return ret_val;
612}
613
614/******************************************************************************
615 * Adjust SERDES output amplitude based on EEPROM setting.
616 *
617 * hw - Struct containing variables accessed by shared code.
618 *****************************************************************************/
619static int32_t
620e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
621{
622 uint16_t eeprom_data;
623 int32_t ret_val;
624
625 DEBUGFUNC("e1000_adjust_serdes_amplitude");
626
627 if(hw->media_type != e1000_media_type_internal_serdes)
628 return E1000_SUCCESS;
629
630 switch(hw->mac_type) {
631 case e1000_82545_rev_3:
632 case e1000_82546_rev_3:
633 break;
634 default:
635 return E1000_SUCCESS;
636 }
637
638 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
639 if (ret_val) {
640 return ret_val;
641 }
642
643 if(eeprom_data != EEPROM_RESERVED_WORD) {
644 /* Adjust SERDES output amplitude only. */
645 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
646 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
647 if(ret_val)
648 return ret_val;
649 }
650
651 return E1000_SUCCESS;
652}
653
654/******************************************************************************
655 * Configures flow control and link settings.
656 *
657 * hw - Struct containing variables accessed by shared code
658 *
659 * Determines which flow control settings to use. Calls the apropriate media-
660 * specific link configuration function. Configures the flow control settings.
661 * Assuming the adapter has a valid link partner, a valid link should be
662 * established. Assumes the hardware has previously been reset and the
663 * transmitter and receiver are not enabled.
664 *****************************************************************************/
665int32_t
666e1000_setup_link(struct e1000_hw *hw)
667{
668 uint32_t ctrl_ext;
669 int32_t ret_val;
670 uint16_t eeprom_data;
671
672 DEBUGFUNC("e1000_setup_link");
673
674 /* Read and store word 0x0F of the EEPROM. This word contains bits
675 * that determine the hardware's default PAUSE (flow control) mode,
676 * a bit that determines whether the HW defaults to enabling or
677 * disabling auto-negotiation, and the direction of the
678 * SW defined pins. If there is no SW over-ride of the flow
679 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM.
681 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
683 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM;
685 }
686
687 if(hw->fc == e1000_fc_default) {
688 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
689 hw->fc = e1000_fc_none;
690 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
691 EEPROM_WORD0F_ASM_DIR)
692 hw->fc = e1000_fc_tx_pause;
693 else
694 hw->fc = e1000_fc_full;
695 }
696
697 /* We want to save off the original Flow Control configuration just
698 * in case we get disconnected and then reconnected into a different
699 * hub or switch with different Flow Control capabilities.
700 */
701 if(hw->mac_type == e1000_82542_rev2_0)
702 hw->fc &= (~e1000_fc_tx_pause);
703
704 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
705 hw->fc &= (~e1000_fc_rx_pause);
706
707 hw->original_fc = hw->fc;
708
709 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
710
711 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
712 * polarity value for the SW controlled pins, and setup the
713 * Extended Device Control reg with that info.
714 * This is needed because one of the SW controlled pins is used for
715 * signal detection. So this should be done before e1000_setup_pcs_link()
716 * or e1000_phy_setup() is called.
717 */
718 if(hw->mac_type == e1000_82543) {
719 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
720 SWDPIO__EXT_SHIFT);
721 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
722 }
723
724 /* Call the necessary subroutine to configure the link. */
725 ret_val = (hw->media_type == e1000_media_type_copper) ?
726 e1000_setup_copper_link(hw) :
727 e1000_setup_fiber_serdes_link(hw);
728
729 /* Initialize the flow control address, type, and PAUSE timer
730 * registers to their default values. This is done even if flow
731 * control is disabled, because it does not hurt anything to
732 * initialize these registers.
733 */
734 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
735
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740
741 /* Set the flow control receive threshold registers. Normally,
742 * these registers will be set to a default threshold that may be
743 * adjusted later by the driver's runtime code. However, if the
744 * ability to transmit pause frames in not enabled, then these
745 * registers will be set to 0.
746 */
747 if(!(hw->fc & e1000_fc_tx_pause)) {
748 E1000_WRITE_REG(hw, FCRTL, 0);
749 E1000_WRITE_REG(hw, FCRTH, 0);
750 } else {
751 /* We need to set up the Receive Threshold high and low water marks
752 * as well as (optionally) enabling the transmission of XON frames.
753 */
754 if(hw->fc_send_xon) {
755 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
756 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
757 } else {
758 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
759 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
760 }
761 }
762 return ret_val;
763}
764
765/******************************************************************************
766 * Sets up link for a fiber based or serdes based adapter
767 *
768 * hw - Struct containing variables accessed by shared code
769 *
770 * Manipulates Physical Coding Sublayer functions in order to configure
771 * link. Assumes the hardware has been previously reset and the transmitter
772 * and receiver are not enabled.
773 *****************************************************************************/
774static int32_t
775e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
776{
777 uint32_t ctrl;
778 uint32_t status;
779 uint32_t txcw = 0;
780 uint32_t i;
781 uint32_t signal = 0;
782 int32_t ret_val;
783
784 DEBUGFUNC("e1000_setup_fiber_serdes_link");
785
786 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
787 * set when the optics detect a signal. On older adapters, it will be
788 * cleared when there is a signal. This applies to fiber media only.
789 * If we're on serdes media, adjust the output amplitude to value set in
790 * the EEPROM.
791 */
792 ctrl = E1000_READ_REG(hw, CTRL);
793 if(hw->media_type == e1000_media_type_fiber)
794 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
795
796 ret_val = e1000_adjust_serdes_amplitude(hw);
797 if(ret_val)
798 return ret_val;
799
800 /* Take the link out of reset */
801 ctrl &= ~(E1000_CTRL_LRST);
802
803 /* Adjust VCO speed to improve BER performance */
804 ret_val = e1000_set_vco_speed(hw);
805 if(ret_val)
806 return ret_val;
807
808 e1000_config_collision_dist(hw);
809
810 /* Check for a software override of the flow control settings, and setup
811 * the device accordingly. If auto-negotiation is enabled, then software
812 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
813 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
814 * auto-negotiation is disabled, then software will have to manually
815 * configure the two flow control enable bits in the CTRL register.
816 *
817 * The possible values of the "fc" parameter are:
818 * 0: Flow control is completely disabled
819 * 1: Rx flow control is enabled (we can receive pause frames, but
820 * not send pause frames).
821 * 2: Tx flow control is enabled (we can send pause frames but we do
822 * not support receiving pause frames).
823 * 3: Both Rx and TX flow control (symmetric) are enabled.
824 */
825 switch (hw->fc) {
826 case e1000_fc_none:
827 /* Flow control is completely disabled by a software over-ride. */
828 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
829 break;
830 case e1000_fc_rx_pause:
831 /* RX Flow control is enabled and TX Flow control is disabled by a
832 * software over-ride. Since there really isn't a way to advertise
833 * that we are capable of RX Pause ONLY, we will advertise that we
834 * support both symmetric and asymmetric RX PAUSE. Later, we will
835 * disable the adapter's ability to send PAUSE frames.
836 */
837 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
838 break;
839 case e1000_fc_tx_pause:
840 /* TX Flow control is enabled, and RX Flow control is disabled, by a
841 * software over-ride.
842 */
843 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
844 break;
845 case e1000_fc_full:
846 /* Flow control (both RX and TX) is enabled by a software over-ride. */
847 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
848 break;
849 default:
850 DEBUGOUT("Flow control param set incorrectly\n");
851 return -E1000_ERR_CONFIG;
852 break;
853 }
854
855 /* Since auto-negotiation is enabled, take the link out of reset (the link
856 * will be in reset, because we previously reset the chip). This will
857 * restart auto-negotiation. If auto-neogtiation is successful then the
858 * link-up status bit will be set and the flow control enable bits (RFCE
859 * and TFCE) will be set according to their negotiated value.
860 */
861 DEBUGOUT("Auto-negotiation enabled\n");
862
863 E1000_WRITE_REG(hw, TXCW, txcw);
864 E1000_WRITE_REG(hw, CTRL, ctrl);
865 E1000_WRITE_FLUSH(hw);
866
867 hw->txcw = txcw;
868 msec_delay(1);
869
870 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
871 * indication in the Device Status Register. Time-out if a link isn't
872 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
873 * less than 500 milliseconds even if the other end is doing it in SW).
874 * For internal serdes, we just assume a signal is present, then poll.
875 */
876 if(hw->media_type == e1000_media_type_internal_serdes ||
877 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
878 DEBUGOUT("Looking for Link\n");
879 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
880 msec_delay(10);
881 status = E1000_READ_REG(hw, STATUS);
882 if(status & E1000_STATUS_LU) break;
883 }
884 if(i == (LINK_UP_TIMEOUT / 10)) {
885 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
886 hw->autoneg_failed = 1;
887 /* AutoNeg failed to achieve a link, so we'll call
888 * e1000_check_for_link. This routine will force the link up if
889 * we detect a signal. This will allow us to communicate with
890 * non-autonegotiating link partners.
891 */
892 ret_val = e1000_check_for_link(hw);
893 if(ret_val) {
894 DEBUGOUT("Error while checking for link\n");
895 return ret_val;
896 }
897 hw->autoneg_failed = 0;
898 } else {
899 hw->autoneg_failed = 0;
900 DEBUGOUT("Valid Link Found\n");
901 }
902 } else {
903 DEBUGOUT("No Signal Detected\n");
904 }
905 return E1000_SUCCESS;
906}
907
908/******************************************************************************
909* Detects which PHY is present and the speed and duplex
910*
911* hw - Struct containing variables accessed by shared code
912******************************************************************************/
913static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw)
915{
916 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data;
921
922 DEBUGFUNC("e1000_setup_copper_link");
923
924 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what
926 * the PHY speed and duplex configuration is. In addition, we need to
927 * perform a hardware reset on the PHY to take it out of reset.
928 */
929 if(hw->mac_type > e1000_82543) {
930 ctrl |= E1000_CTRL_SLU;
931 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
932 E1000_WRITE_REG(hw, CTRL, ctrl);
933 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw);
937 }
938
939 /* Make sure we have a valid PHY */
940 ret_val = e1000_detect_gig_phy(hw);
941 if(ret_val) {
942 DEBUGOUT("Error, did not detect valid phy.\n");
943 return ret_val;
944 }
945 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
946
947 /* Set PHY to class A mode (if necessary) */
948 ret_val = e1000_set_phy_mode(hw);
949 if(ret_val)
950 return ret_val;
951
952 if((hw->mac_type == e1000_82545_rev_3) ||
953 (hw->mac_type == e1000_82546_rev_3)) {
954 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
955 phy_data |= 0x00000008;
956 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
957 }
958
959 if(hw->mac_type <= e1000_82543 ||
960 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE;
963
964 if(!hw->phy_reset_disable) {
965 if (hw->phy_type == e1000_phy_igp) {
966
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */
974 msec_delay(15);
975
976 /* Configure activity LED after PHY reset */
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981
982 /* disable lplu d3 during driver init */
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
984 if(ret_val) {
985 DEBUGOUT("Error Disabling LPLU D3\n");
986 return ret_val;
987 }
988
989 /* Configure mdi-mdix settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
996 hw->dsp_config_state = e1000_dsp_config_disabled;
997 /* Force MDI for earlier revs of the IGP PHY */
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
999 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1000 hw->mdix = 1;
1001
1002 } else {
1003 hw->dsp_config_state = e1000_dsp_config_enabled;
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1005
1006 switch (hw->mdix) {
1007 case 1:
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023
1024 /* set auto-master slave resolution settings */
1025 if(hw->autoneg) {
1026 e1000_ms_type phy_ms_setting = hw->master_slave;
1027
1028 if(hw->ffe_config_state == e1000_ffe_config_active)
1029 hw->ffe_config_state = e1000_ffe_config_enabled;
1030
1031 if(hw->dsp_config_state == e1000_dsp_config_activated)
1032 hw->dsp_config_state = e1000_dsp_config_enabled;
1033
1034 /* when autonegotiation advertisment is only 1000Mbps then we
1035 * should disable SmartSpeed and enable Auto MasterSlave
1036 * resolution as hardware default. */
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1038 /* Disable SmartSpeed */
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1040 &phy_data);
1041 if(ret_val)
1042 return ret_val;
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1044 ret_val = e1000_write_phy_reg(hw,
1045 IGP01E1000_PHY_PORT_CONFIG,
1046 phy_data);
1047 if(ret_val)
1048 return ret_val;
1049 /* Set auto Master/Slave resolution process */
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1060 if(ret_val)
1061 return ret_val;
1062
1063 /* load defaults for future use */
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1065 ((phy_data & CR_1000T_MS_VALUE) ?
1066 e1000_ms_force_master :
1067 e1000_ms_force_slave) :
1068 e1000_ms_auto;
1069
1070 switch (phy_ms_setting) {
1071 case e1000_ms_force_master:
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1073 break;
1074 case e1000_ms_force_slave:
1075 phy_data |= CR_1000T_MS_ENABLE;
1076 phy_data &= ~(CR_1000T_MS_VALUE);
1077 break;
1078 case e1000_ms_auto:
1079 phy_data &= ~CR_1000T_MS_ENABLE;
1080 default:
1081 break;
1082 }
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1084 if(ret_val)
1085 return ret_val;
1086 }
1087 } else {
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val)
1092 return ret_val;
1093
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1095
1096 /* Options:
1097 * MDI/MDI-X = 0 (default)
1098 * 0 - Auto for all speeds
1099 * 1 - MDI mode
1100 * 2 - MDI-X mode
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104
1105 switch (hw->mdix) {
1106 case 1:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1108 break;
1109 case 2:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1111 break;
1112 case 3:
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1114 break;
1115 case 0:
1116 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1118 break;
1119 }
1120
1121 /* Options:
1122 * disable_polarity_correction = 0 (default)
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1144
1145 if (hw->phy_revision < M88E1011_I_REV_4) {
1146 /* Configure Master and Slave downshift values */
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1152 phy_data);
1153 if(ret_val)
1154 return ret_val;
1155 }
1156
1157 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val;
1162 }
1163 }
1164
1165 /* Options:
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173
1174 /* Is autoneg enabled? This is enabled by default or by software
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1193 ret_val = e1000_phy_setup_autoneg(hw);
1194 if(ret_val) {
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1196 return ret_val;
1197 }
1198 DEBUGOUT("Restarting Auto-Neg\n");
1199
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1201 * the Auto Neg Restart bit in the PHY control register.
1202 */
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1204 if(ret_val)
1205 return ret_val;
1206
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1209 if(ret_val)
1210 return ret_val;
1211
1212 /* Does the user want to wait for Auto-Neg to complete here, or
1213 * check at a later time (for example, callback routine).
1214 */
1215 if(hw->wait_autoneg_complete) {
1216 ret_val = e1000_wait_autoneg(hw);
1217 if(ret_val) {
1218 DEBUGOUT("Error while waiting for autoneg to complete\n");
1219 return ret_val;
1220 }
1221 }
1222 hw->get_link_status = TRUE;
1223 } else {
1224 DEBUGOUT("Forcing speed and duplex\n");
1225 ret_val = e1000_phy_force_speed_duplex(hw);
1226 if(ret_val) {
1227 DEBUGOUT("Error Forcing Speed and Duplex\n");
1228 return ret_val;
1229 }
1230 }
1231 } /* !hw->phy_reset_disable */
1232
1233 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid.
1235 */
1236 for(i = 0; i < 10; i++) {
1237 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1238 if(ret_val)
1239 return ret_val;
1240 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1241 if(ret_val)
1242 return ret_val;
1243
1244 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process:
1246 * 1) Set up the MAC to the current PHY speed/duplex
1247 * if we are on 82543. If we
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val;
1266 }
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS;
1278 }
1279 udelay(10);
1280 }
1281
1282 DEBUGOUT("Unable to establish link!!!\n");
1283 return E1000_SUCCESS;
1284}
1285
1286/******************************************************************************
1287* Configures PHY autoneg and flow control advertisement settings
1288*
1289* hw - Struct containing variables accessed by shared code
1290******************************************************************************/
1291int32_t
1292e1000_phy_setup_autoneg(struct e1000_hw *hw)
1293{
1294 int32_t ret_val;
1295 uint16_t mii_autoneg_adv_reg;
1296 uint16_t mii_1000t_ctrl_reg;
1297
1298 DEBUGFUNC("e1000_phy_setup_autoneg");
1299
1300 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1301 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1302 if(ret_val)
1303 return ret_val;
1304
1305 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val)
1308 return ret_val;
1309
1310 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for
1312 * autoneg_advertised software override. Since we can advertise
1313 * a plethora of combinations, we need to check each bit
1314 * individually.
1315 */
1316
1317 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1318 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1319 * the 1000Base-T Control Register (Address 9).
1320 */
1321 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1322 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1323
1324 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1325
1326 /* Do we want to advertise 10 Mb Half Duplex? */
1327 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1328 DEBUGOUT("Advertise 10mb Half duplex\n");
1329 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1330 }
1331
1332 /* Do we want to advertise 10 Mb Full Duplex? */
1333 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1334 DEBUGOUT("Advertise 10mb Full duplex\n");
1335 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1336 }
1337
1338 /* Do we want to advertise 100 Mb Half Duplex? */
1339 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1340 DEBUGOUT("Advertise 100mb Half duplex\n");
1341 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1342 }
1343
1344 /* Do we want to advertise 100 Mb Full Duplex? */
1345 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1346 DEBUGOUT("Advertise 100mb Full duplex\n");
1347 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1348 }
1349
1350 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1351 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1352 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1353 }
1354
1355 /* Do we want to advertise 1000 Mb Full Duplex? */
1356 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1357 DEBUGOUT("Advertise 1000mb Full duplex\n");
1358 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1359 }
1360
1361 /* Check for a software override of the flow control settings, and
1362 * setup the PHY advertisement registers accordingly. If
1363 * auto-negotiation is enabled, then software will have to set the
1364 * "PAUSE" bits to the correct value in the Auto-Negotiation
1365 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1366 *
1367 * The possible values of the "fc" parameter are:
1368 * 0: Flow control is completely disabled
1369 * 1: Rx flow control is enabled (we can receive pause frames
1370 * but not send pause frames).
1371 * 2: Tx flow control is enabled (we can send pause frames
1372 * but we do not support receiving pause frames).
1373 * 3: Both Rx and TX flow control (symmetric) are enabled.
1374 * other: No software override. The flow control configuration
1375 * in the EEPROM is used.
1376 */
1377 switch (hw->fc) {
1378 case e1000_fc_none: /* 0 */
1379 /* Flow control (RX & TX) is completely disabled by a
1380 * software over-ride.
1381 */
1382 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1383 break;
1384 case e1000_fc_rx_pause: /* 1 */
1385 /* RX Flow control is enabled, and TX Flow control is
1386 * disabled, by a software over-ride.
1387 */
1388 /* Since there really isn't a way to advertise that we are
1389 * capable of RX Pause ONLY, we will advertise that we
1390 * support both symmetric and asymmetric RX PAUSE. Later
1391 * (in e1000_config_fc_after_link_up) we will disable the
1392 *hw's ability to send PAUSE frames.
1393 */
1394 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1395 break;
1396 case e1000_fc_tx_pause: /* 2 */
1397 /* TX Flow control is enabled, and RX Flow control is
1398 * disabled, by a software over-ride.
1399 */
1400 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1401 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1402 break;
1403 case e1000_fc_full: /* 3 */
1404 /* Flow control (both RX and TX) is enabled by a software
1405 * over-ride.
1406 */
1407 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1408 break;
1409 default:
1410 DEBUGOUT("Flow control param set incorrectly\n");
1411 return -E1000_ERR_CONFIG;
1412 }
1413
1414 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1415 if(ret_val)
1416 return ret_val;
1417
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val)
1422 return ret_val;
1423
1424 return E1000_SUCCESS;
1425}
1426
1427/******************************************************************************
1428* Force PHY speed and duplex settings to hw->forced_speed_duplex
1429*
1430* hw - Struct containing variables accessed by shared code
1431******************************************************************************/
1432static int32_t
1433e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1434{
1435 uint32_t ctrl;
1436 int32_t ret_val;
1437 uint16_t mii_ctrl_reg;
1438 uint16_t mii_status_reg;
1439 uint16_t phy_data;
1440 uint16_t i;
1441
1442 DEBUGFUNC("e1000_phy_force_speed_duplex");
1443
1444 /* Turn off Flow control if we are forcing speed and duplex. */
1445 hw->fc = e1000_fc_none;
1446
1447 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1448
1449 /* Read the Device Control Register. */
1450 ctrl = E1000_READ_REG(hw, CTRL);
1451
1452 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1453 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1454 ctrl &= ~(DEVICE_SPEED_MASK);
1455
1456 /* Clear the Auto Speed Detect Enable bit. */
1457 ctrl &= ~E1000_CTRL_ASDE;
1458
1459 /* Read the MII Control Register. */
1460 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1461 if(ret_val)
1462 return ret_val;
1463
1464 /* We need to disable autoneg in order to force link and duplex. */
1465
1466 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1467
1468 /* Are we forcing Full or Half Duplex? */
1469 if(hw->forced_speed_duplex == e1000_100_full ||
1470 hw->forced_speed_duplex == e1000_10_full) {
1471 /* We want to force full duplex so we SET the full duplex bits in the
1472 * Device and MII Control Registers.
1473 */
1474 ctrl |= E1000_CTRL_FD;
1475 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1476 DEBUGOUT("Full Duplex\n");
1477 } else {
1478 /* We want to force half duplex so we CLEAR the full duplex bits in
1479 * the Device and MII Control Registers.
1480 */
1481 ctrl &= ~E1000_CTRL_FD;
1482 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1483 DEBUGOUT("Half Duplex\n");
1484 }
1485
1486 /* Are we forcing 100Mbps??? */
1487 if(hw->forced_speed_duplex == e1000_100_full ||
1488 hw->forced_speed_duplex == e1000_100_half) {
1489 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1490 ctrl |= E1000_CTRL_SPD_100;
1491 mii_ctrl_reg |= MII_CR_SPEED_100;
1492 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1493 DEBUGOUT("Forcing 100mb ");
1494 } else {
1495 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1496 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1497 mii_ctrl_reg |= MII_CR_SPEED_10;
1498 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1499 DEBUGOUT("Forcing 10mb ");
1500 }
1501
1502 e1000_config_collision_dist(hw);
1503
1504 /* Write the configured values back to the Device Control Reg. */
1505 E1000_WRITE_REG(hw, CTRL, ctrl);
1506
1507 if (hw->phy_type == e1000_phy_m88) {
1508 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1509 if(ret_val)
1510 return ret_val;
1511
1512 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1513 * forced whenever speed are duplex are forced.
1514 */
1515 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1516 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1517 if(ret_val)
1518 return ret_val;
1519
1520 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1521
1522 /* Need to reset the PHY or these changes will be ignored */
1523 mii_ctrl_reg |= MII_CR_RESET;
1524 } else {
1525 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1526 * forced whenever speed or duplex are forced.
1527 */
1528 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1529 if(ret_val)
1530 return ret_val;
1531
1532 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1533 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1534
1535 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1536 if(ret_val)
1537 return ret_val;
1538 }
1539
1540 /* Write back the modified PHY MII control register. */
1541 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1542 if(ret_val)
1543 return ret_val;
1544
1545 udelay(1);
1546
1547 /* The wait_autoneg_complete flag may be a little misleading here.
1548 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1549 * But we do want to delay for a period while forcing only so we
1550 * don't generate false No Link messages. So we will wait here
1551 * only if the user has set wait_autoneg_complete to 1, which is
1552 * the default.
1553 */
1554 if(hw->wait_autoneg_complete) {
1555 /* We will wait for autoneg to complete. */
1556 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1557 mii_status_reg = 0;
1558
1559 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1560 for(i = PHY_FORCE_TIME; i > 0; i--) {
1561 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1562 * to be set.
1563 */
1564 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1565 if(ret_val)
1566 return ret_val;
1567
1568 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1569 if(ret_val)
1570 return ret_val;
1571
1572 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1573 msec_delay(100);
1574 }
1575 if((i == 0) &&
1576 (hw->phy_type == e1000_phy_m88)) {
1577 /* We didn't get link. Reset the DSP and wait again for link. */
1578 ret_val = e1000_phy_reset_dsp(hw);
1579 if(ret_val) {
1580 DEBUGOUT("Error Resetting PHY DSP\n");
1581 return ret_val;
1582 }
1583 }
1584 /* This loop will early-out if the link condition has been met. */
1585 for(i = PHY_FORCE_TIME; i > 0; i--) {
1586 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1587 msec_delay(100);
1588 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1589 * to be set.
1590 */
1591 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1592 if(ret_val)
1593 return ret_val;
1594
1595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1596 if(ret_val)
1597 return ret_val;
1598 }
1599 }
1600
1601 if (hw->phy_type == e1000_phy_m88) {
1602 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1603 * Extended PHY Specific Control Register to 25MHz clock. This value
1604 * defaults back to a 2.5MHz clock when the PHY is reset.
1605 */
1606 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1607 if(ret_val)
1608 return ret_val;
1609
1610 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1611 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1612 if(ret_val)
1613 return ret_val;
1614
1615 /* In addition, because of the s/w reset above, we need to enable CRS on
1616 * TX. This must be set for both full and half duplex operation.
1617 */
1618 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1619 if(ret_val)
1620 return ret_val;
1621
1622 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1623 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1624 if(ret_val)
1625 return ret_val;
1626
1627 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
1628 (!hw->autoneg) &&
1629 (hw->forced_speed_duplex == e1000_10_full ||
1630 hw->forced_speed_duplex == e1000_10_half)) {
1631 ret_val = e1000_polarity_reversal_workaround(hw);
1632 if(ret_val)
1633 return ret_val;
1634 }
1635 }
1636 return E1000_SUCCESS;
1637}
1638
1639/******************************************************************************
1640* Sets the collision distance in the Transmit Control register
1641*
1642* hw - Struct containing variables accessed by shared code
1643*
1644* Link should have been established previously. Reads the speed and duplex
1645* information from the Device Status register.
1646******************************************************************************/
1647void
1648e1000_config_collision_dist(struct e1000_hw *hw)
1649{
1650 uint32_t tctl;
1651
1652 DEBUGFUNC("e1000_config_collision_dist");
1653
1654 tctl = E1000_READ_REG(hw, TCTL);
1655
1656 tctl &= ~E1000_TCTL_COLD;
1657 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1658
1659 E1000_WRITE_REG(hw, TCTL, tctl);
1660 E1000_WRITE_FLUSH(hw);
1661}
1662
1663/******************************************************************************
1664* Sets MAC speed and duplex settings to reflect the those in the PHY
1665*
1666* hw - Struct containing variables accessed by shared code
1667* mii_reg - data to write to the MII control register
1668*
1669* The contents of the PHY register containing the needed information need to
1670* be passed in.
1671******************************************************************************/
1672static int32_t
1673e1000_config_mac_to_phy(struct e1000_hw *hw)
1674{
1675 uint32_t ctrl;
1676 int32_t ret_val;
1677 uint16_t phy_data;
1678
1679 DEBUGFUNC("e1000_config_mac_to_phy");
1680
1681 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex.
1683 */
1684 ctrl = E1000_READ_REG(hw, CTRL);
1685 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1686 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1687
1688 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values.
1690 */
1691 if (hw->phy_type == e1000_phy_igp) {
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1693 &phy_data);
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701
1702 /* Set up speed in the Device Control register depending on
1703 * negotiated values.
1704 */
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1718 else ctrl &= ~E1000_CTRL_FD;
1719
1720 e1000_config_collision_dist(hw);
1721
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS;
1733}
1734
1735/******************************************************************************
1736 * Forces the MAC's flow control settings.
1737 *
1738 * hw - Struct containing variables accessed by shared code
1739 *
1740 * Sets the TFCE and RFCE bits in the device control register to reflect
1741 * the adapter settings. TFCE and RFCE need to be explicitly set by
1742 * software when a Copper PHY is used because autonegotiation is managed
1743 * by the PHY rather than the MAC. Software must also configure these
1744 * bits when link is forced on a fiber connection.
1745 *****************************************************************************/
1746int32_t
1747e1000_force_mac_fc(struct e1000_hw *hw)
1748{
1749 uint32_t ctrl;
1750
1751 DEBUGFUNC("e1000_force_mac_fc");
1752
1753 /* Get the current configuration of the Device Control Register */
1754 ctrl = E1000_READ_REG(hw, CTRL);
1755
1756 /* Because we didn't get link via the internal auto-negotiation
1757 * mechanism (we either forced link or we got link via PHY
1758 * auto-neg), we have to manually enable/disable transmit an
1759 * receive flow control.
1760 *
1761 * The "Case" statement below enables/disable flow control
1762 * according to the "hw->fc" parameter.
1763 *
1764 * The possible values of the "fc" parameter are:
1765 * 0: Flow control is completely disabled
1766 * 1: Rx flow control is enabled (we can receive pause
1767 * frames but not send pause frames).
1768 * 2: Tx flow control is enabled (we can send pause frames
1769 * frames but we do not receive pause frames).
1770 * 3: Both Rx and TX flow control (symmetric) is enabled.
1771 * other: No other values should be possible at this point.
1772 */
1773
1774 switch (hw->fc) {
1775 case e1000_fc_none:
1776 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1777 break;
1778 case e1000_fc_rx_pause:
1779 ctrl &= (~E1000_CTRL_TFCE);
1780 ctrl |= E1000_CTRL_RFCE;
1781 break;
1782 case e1000_fc_tx_pause:
1783 ctrl &= (~E1000_CTRL_RFCE);
1784 ctrl |= E1000_CTRL_TFCE;
1785 break;
1786 case e1000_fc_full:
1787 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1788 break;
1789 default:
1790 DEBUGOUT("Flow control param set incorrectly\n");
1791 return -E1000_ERR_CONFIG;
1792 }
1793
1794 /* Disable TX Flow Control for 82542 (rev 2.0) */
1795 if(hw->mac_type == e1000_82542_rev2_0)
1796 ctrl &= (~E1000_CTRL_TFCE);
1797
1798 E1000_WRITE_REG(hw, CTRL, ctrl);
1799 return E1000_SUCCESS;
1800}
1801
1802/******************************************************************************
1803 * Configures flow control settings after link is established
1804 *
1805 * hw - Struct containing variables accessed by shared code
1806 *
1807 * Should be called immediately after a valid link has been established.
1808 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1809 * and autonegotiation is enabled, the MAC flow control settings will be set
1810 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1811 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1812 *****************************************************************************/
1813int32_t
1814e1000_config_fc_after_link_up(struct e1000_hw *hw)
1815{
1816 int32_t ret_val;
1817 uint16_t mii_status_reg;
1818 uint16_t mii_nway_adv_reg;
1819 uint16_t mii_nway_lp_ability_reg;
1820 uint16_t speed;
1821 uint16_t duplex;
1822
1823 DEBUGFUNC("e1000_config_fc_after_link_up");
1824
1825 /* Check for the case where we have fiber media and auto-neg failed
1826 * so we had to force link. In this case, we need to force the
1827 * configuration of the MAC to match the "fc" parameter.
1828 */
1829 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1830 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1831 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1832 ret_val = e1000_force_mac_fc(hw);
1833 if(ret_val) {
1834 DEBUGOUT("Error forcing flow control settings\n");
1835 return ret_val;
1836 }
1837 }
1838
1839 /* Check for the case where we have copper media and auto-neg is
1840 * enabled. In this case, we need to check and see if Auto-Neg
1841 * has completed, and if so, how the PHY and link partner has
1842 * flow control configured.
1843 */
1844 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1845 /* Read the MII Status Register and check to see if AutoNeg
1846 * has completed. We read this twice because this reg has
1847 * some "sticky" (latched) bits.
1848 */
1849 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1850 if(ret_val)
1851 return ret_val;
1852 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1853 if(ret_val)
1854 return ret_val;
1855
1856 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1857 /* The AutoNeg process has completed, so we now need to
1858 * read both the Auto Negotiation Advertisement Register
1859 * (Address 4) and the Auto_Negotiation Base Page Ability
1860 * Register (Address 5) to determine how flow control was
1861 * negotiated.
1862 */
1863 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1864 &mii_nway_adv_reg);
1865 if(ret_val)
1866 return ret_val;
1867 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1868 &mii_nway_lp_ability_reg);
1869 if(ret_val)
1870 return ret_val;
1871
1872 /* Two bits in the Auto Negotiation Advertisement Register
1873 * (Address 4) and two bits in the Auto Negotiation Base
1874 * Page Ability Register (Address 5) determine flow control
1875 * for both the PHY and the link partner. The following
1876 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1877 * 1999, describes these PAUSE resolution bits and how flow
1878 * control is determined based upon these settings.
1879 * NOTE: DC = Don't Care
1880 *
1881 * LOCAL DEVICE | LINK PARTNER
1882 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1883 *-------|---------|-------|---------|--------------------
1884 * 0 | 0 | DC | DC | e1000_fc_none
1885 * 0 | 1 | 0 | DC | e1000_fc_none
1886 * 0 | 1 | 1 | 0 | e1000_fc_none
1887 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1888 * 1 | 0 | 0 | DC | e1000_fc_none
1889 * 1 | DC | 1 | DC | e1000_fc_full
1890 * 1 | 1 | 0 | 0 | e1000_fc_none
1891 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1892 *
1893 */
1894 /* Are both PAUSE bits set to 1? If so, this implies
1895 * Symmetric Flow Control is enabled at both ends. The
1896 * ASM_DIR bits are irrelevant per the spec.
1897 *
1898 * For Symmetric Flow Control:
1899 *
1900 * LOCAL DEVICE | LINK PARTNER
1901 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1902 *-------|---------|-------|---------|--------------------
1903 * 1 | DC | 1 | DC | e1000_fc_full
1904 *
1905 */
1906 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1907 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1908 /* Now we need to check if the user selected RX ONLY
1909 * of pause frames. In this case, we had to advertise
1910 * FULL flow control because we could not advertise RX
1911 * ONLY. Hence, we must now check to see if we need to
1912 * turn OFF the TRANSMISSION of PAUSE frames.
1913 */
1914 if(hw->original_fc == e1000_fc_full) {
1915 hw->fc = e1000_fc_full;
1916 DEBUGOUT("Flow Control = FULL.\r\n");
1917 } else {
1918 hw->fc = e1000_fc_rx_pause;
1919 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1920 }
1921 }
1922 /* For receiving PAUSE frames ONLY.
1923 *
1924 * LOCAL DEVICE | LINK PARTNER
1925 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1926 *-------|---------|-------|---------|--------------------
1927 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1928 *
1929 */
1930 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1931 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1932 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1933 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1934 hw->fc = e1000_fc_tx_pause;
1935 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1936 }
1937 /* For transmitting PAUSE frames ONLY.
1938 *
1939 * LOCAL DEVICE | LINK PARTNER
1940 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1941 *-------|---------|-------|---------|--------------------
1942 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1943 *
1944 */
1945 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1946 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1947 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1948 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1949 hw->fc = e1000_fc_rx_pause;
1950 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1951 }
1952 /* Per the IEEE spec, at this point flow control should be
1953 * disabled. However, we want to consider that we could
1954 * be connected to a legacy switch that doesn't advertise
1955 * desired flow control, but can be forced on the link
1956 * partner. So if we advertised no flow control, that is
1957 * what we will resolve to. If we advertised some kind of
1958 * receive capability (Rx Pause Only or Full Flow Control)
1959 * and the link partner advertised none, we will configure
1960 * ourselves to enable Rx Flow Control only. We can do
1961 * this safely for two reasons: If the link partner really
1962 * didn't want flow control enabled, and we enable Rx, no
1963 * harm done since we won't be receiving any PAUSE frames
1964 * anyway. If the intent on the link partner was to have
1965 * flow control enabled, then by us enabling RX only, we
1966 * can at least receive pause frames and process them.
1967 * This is a good idea because in most cases, since we are
1968 * predominantly a server NIC, more times than not we will
1969 * be asked to delay transmission of packets than asking
1970 * our link partner to pause transmission of frames.
1971 */
1972 else if((hw->original_fc == e1000_fc_none ||
1973 hw->original_fc == e1000_fc_tx_pause) ||
1974 hw->fc_strict_ieee) {
1975 hw->fc = e1000_fc_none;
1976 DEBUGOUT("Flow Control = NONE.\r\n");
1977 } else {
1978 hw->fc = e1000_fc_rx_pause;
1979 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1980 }
1981
1982 /* Now we need to do one last check... If we auto-
1983 * negotiated to HALF DUPLEX, flow control should not be
1984 * enabled per IEEE 802.3 spec.
1985 */
1986 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1987 if(ret_val) {
1988 DEBUGOUT("Error getting link speed and duplex\n");
1989 return ret_val;
1990 }
1991
1992 if(duplex == HALF_DUPLEX)
1993 hw->fc = e1000_fc_none;
1994
1995 /* Now we call a subroutine to actually force the MAC
1996 * controller to use the correct flow control settings.
1997 */
1998 ret_val = e1000_force_mac_fc(hw);
1999 if(ret_val) {
2000 DEBUGOUT("Error forcing flow control settings\n");
2001 return ret_val;
2002 }
2003 } else {
2004 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2005 }
2006 }
2007 return E1000_SUCCESS;
2008}
2009
2010/******************************************************************************
2011 * Checks to see if the link status of the hardware has changed.
2012 *
2013 * hw - Struct containing variables accessed by shared code
2014 *
2015 * Called by any function that needs to check the link status of the adapter.
2016 *****************************************************************************/
2017int32_t
2018e1000_check_for_link(struct e1000_hw *hw)
2019{
2020 uint32_t rxcw = 0;
2021 uint32_t ctrl;
2022 uint32_t status;
2023 uint32_t rctl;
2024 uint32_t icr;
2025 uint32_t signal = 0;
2026 int32_t ret_val;
2027 uint16_t phy_data;
2028
2029 DEBUGFUNC("e1000_check_for_link");
2030
2031 ctrl = E1000_READ_REG(hw, CTRL);
2032 status = E1000_READ_REG(hw, STATUS);
2033
2034 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2035 * set when the optics detect a signal. On older adapters, it will be
2036 * cleared when there is a signal. This applies to fiber media only.
2037 */
2038 if((hw->media_type == e1000_media_type_fiber) ||
2039 (hw->media_type == e1000_media_type_internal_serdes)) {
2040 rxcw = E1000_READ_REG(hw, RXCW);
2041
2042 if(hw->media_type == e1000_media_type_fiber) {
2043 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2044 if(status & E1000_STATUS_LU)
2045 hw->get_link_status = FALSE;
2046 }
2047 }
2048
2049 /* If we have a copper PHY then we only want to go out to the PHY
2050 * registers to see if Auto-Neg has completed and/or if our link
2051 * status has changed. The get_link_status flag will be set if we
2052 * receive a Link Status Change interrupt or we have Rx Sequence
2053 * Errors.
2054 */
2055 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2056 /* First we want to see if the MII Status Register reports
2057 * link. If so, then we want to get the current speed/duplex
2058 * of the PHY.
2059 * Read the register twice since the link bit is sticky.
2060 */
2061 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2062 if(ret_val)
2063 return ret_val;
2064 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2065 if(ret_val)
2066 return ret_val;
2067
2068 if(phy_data & MII_SR_LINK_STATUS) {
2069 hw->get_link_status = FALSE;
2070 /* Check if there was DownShift, must be checked immediately after
2071 * link-up */
2072 e1000_check_downshift(hw);
2073
2074 /* If we are on 82544 or 82543 silicon and speed/duplex
2075 * are forced to 10H or 10F, then we will implement the polarity
2076 * reversal workaround. We disable interrupts first, and upon
2077 * returning, place the devices interrupt state to its previous
2078 * value except for the link status change interrupt which will
2079 * happen due to the execution of this workaround.
2080 */
2081
2082 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2083 (!hw->autoneg) &&
2084 (hw->forced_speed_duplex == e1000_10_full ||
2085 hw->forced_speed_duplex == e1000_10_half)) {
2086 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2087 ret_val = e1000_polarity_reversal_workaround(hw);
2088 icr = E1000_READ_REG(hw, ICR);
2089 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2090 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2091 }
2092
2093 } else {
2094 /* No link detected */
2095 e1000_config_dsp_after_link_change(hw, FALSE);
2096 return 0;
2097 }
2098
2099 /* If we are forcing speed/duplex, then we simply return since
2100 * we have already determined whether we have link or not.
2101 */
2102 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2103
2104 /* optimize the dsp settings for the igp phy */
2105 e1000_config_dsp_after_link_change(hw, TRUE);
2106
2107 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2108 * have Si on board that is 82544 or newer, Auto
2109 * Speed Detection takes care of MAC speed/duplex
2110 * configuration. So we only need to configure Collision
2111 * Distance in the MAC. Otherwise, we need to force
2112 * speed/duplex on the MAC to the current PHY speed/duplex
2113 * settings.
2114 */
2115 if(hw->mac_type >= e1000_82544)
2116 e1000_config_collision_dist(hw);
2117 else {
2118 ret_val = e1000_config_mac_to_phy(hw);
2119 if(ret_val) {
2120 DEBUGOUT("Error configuring MAC to PHY settings\n");
2121 return ret_val;
2122 }
2123 }
2124
2125 /* Configure Flow Control now that Auto-Neg has completed. First, we
2126 * need to restore the desired flow control settings because we may
2127 * have had to re-autoneg with a different link partner.
2128 */
2129 ret_val = e1000_config_fc_after_link_up(hw);
2130 if(ret_val) {
2131 DEBUGOUT("Error configuring flow control\n");
2132 return ret_val;
2133 }
2134
2135 /* At this point we know that we are on copper and we have
2136 * auto-negotiated link. These are conditions for checking the link
2137 * partner capability register. We use the link speed to determine if
2138 * TBI compatibility needs to be turned on or off. If the link is not
2139 * at gigabit speed, then TBI compatibility is not needed. If we are
2140 * at gigabit speed, we turn on TBI compatibility.
2141 */
2142 if(hw->tbi_compatibility_en) {
2143 uint16_t speed, duplex;
2144 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2145 if(speed != SPEED_1000) {
2146 /* If link speed is not set to gigabit speed, we do not need
2147 * to enable TBI compatibility.
2148 */
2149 if(hw->tbi_compatibility_on) {
2150 /* If we previously were in the mode, turn it off. */
2151 rctl = E1000_READ_REG(hw, RCTL);
2152 rctl &= ~E1000_RCTL_SBP;
2153 E1000_WRITE_REG(hw, RCTL, rctl);
2154 hw->tbi_compatibility_on = FALSE;
2155 }
2156 } else {
2157 /* If TBI compatibility is was previously off, turn it on. For
2158 * compatibility with a TBI link partner, we will store bad
2159 * packets. Some frames have an additional byte on the end and
2160 * will look like CRC errors to to the hardware.
2161 */
2162 if(!hw->tbi_compatibility_on) {
2163 hw->tbi_compatibility_on = TRUE;
2164 rctl = E1000_READ_REG(hw, RCTL);
2165 rctl |= E1000_RCTL_SBP;
2166 E1000_WRITE_REG(hw, RCTL, rctl);
2167 }
2168 }
2169 }
2170 }
2171 /* If we don't have link (auto-negotiation failed or link partner cannot
2172 * auto-negotiate), the cable is plugged in (we have signal), and our
2173 * link partner is not trying to auto-negotiate with us (we are receiving
2174 * idles or data), we need to force link up. We also need to give
2175 * auto-negotiation time to complete, in case the cable was just plugged
2176 * in. The autoneg_failed flag does this.
2177 */
2178 else if((((hw->media_type == e1000_media_type_fiber) &&
2179 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2180 (hw->media_type == e1000_media_type_internal_serdes)) &&
2181 (!(status & E1000_STATUS_LU)) &&
2182 (!(rxcw & E1000_RXCW_C))) {
2183 if(hw->autoneg_failed == 0) {
2184 hw->autoneg_failed = 1;
2185 return 0;
2186 }
2187 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2188
2189 /* Disable auto-negotiation in the TXCW register */
2190 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2191
2192 /* Force link-up and also force full-duplex. */
2193 ctrl = E1000_READ_REG(hw, CTRL);
2194 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2195 E1000_WRITE_REG(hw, CTRL, ctrl);
2196
2197 /* Configure Flow Control after forcing link up. */
2198 ret_val = e1000_config_fc_after_link_up(hw);
2199 if(ret_val) {
2200 DEBUGOUT("Error configuring flow control\n");
2201 return ret_val;
2202 }
2203 }
2204 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2205 * auto-negotiation in the TXCW register and disable forced link in the
2206 * Device Control register in an attempt to auto-negotiate with our link
2207 * partner.
2208 */
2209 else if(((hw->media_type == e1000_media_type_fiber) ||
2210 (hw->media_type == e1000_media_type_internal_serdes)) &&
2211 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2212 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2213 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2214 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2215
2216 hw->serdes_link_down = FALSE;
2217 }
2218 /* If we force link for non-auto-negotiation switch, check link status
2219 * based on MAC synchronization for internal serdes media type.
2220 */
2221 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2222 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2223 /* SYNCH bit and IV bit are sticky. */
2224 udelay(10);
2225 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2226 if(!(rxcw & E1000_RXCW_IV)) {
2227 hw->serdes_link_down = FALSE;
2228 DEBUGOUT("SERDES: Link is up.\n");
2229 }
2230 } else {
2231 hw->serdes_link_down = TRUE;
2232 DEBUGOUT("SERDES: Link is down.\n");
2233 }
2234 }
2235 if((hw->media_type == e1000_media_type_internal_serdes) &&
2236 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2237 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2238 }
2239 return E1000_SUCCESS;
2240}
2241
2242/******************************************************************************
2243 * Detects the current speed and duplex settings of the hardware.
2244 *
2245 * hw - Struct containing variables accessed by shared code
2246 * speed - Speed of the connection
2247 * duplex - Duplex setting of the connection
2248 *****************************************************************************/
2249int32_t
2250e1000_get_speed_and_duplex(struct e1000_hw *hw,
2251 uint16_t *speed,
2252 uint16_t *duplex)
2253{
2254 uint32_t status;
2255 int32_t ret_val;
2256 uint16_t phy_data;
2257
2258 DEBUGFUNC("e1000_get_speed_and_duplex");
2259
2260 if(hw->mac_type >= e1000_82543) {
2261 status = E1000_READ_REG(hw, STATUS);
2262 if(status & E1000_STATUS_SPEED_1000) {
2263 *speed = SPEED_1000;
2264 DEBUGOUT("1000 Mbs, ");
2265 } else if(status & E1000_STATUS_SPEED_100) {
2266 *speed = SPEED_100;
2267 DEBUGOUT("100 Mbs, ");
2268 } else {
2269 *speed = SPEED_10;
2270 DEBUGOUT("10 Mbs, ");
2271 }
2272
2273 if(status & E1000_STATUS_FD) {
2274 *duplex = FULL_DUPLEX;
2275 DEBUGOUT("Full Duplex\r\n");
2276 } else {
2277 *duplex = HALF_DUPLEX;
2278 DEBUGOUT(" Half Duplex\r\n");
2279 }
2280 } else {
2281 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2282 *speed = SPEED_1000;
2283 *duplex = FULL_DUPLEX;
2284 }
2285
2286 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2287 * if it is operating at half duplex. Here we set the duplex settings to
2288 * match the duplex in the link partner's capabilities.
2289 */
2290 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2291 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2292 if(ret_val)
2293 return ret_val;
2294
2295 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2296 *duplex = HALF_DUPLEX;
2297 else {
2298 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2299 if(ret_val)
2300 return ret_val;
2301 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2302 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2303 *duplex = HALF_DUPLEX;
2304 }
2305 }
2306
2307 return E1000_SUCCESS;
2308}
2309
2310/******************************************************************************
2311* Blocks until autoneg completes or times out (~4.5 seconds)
2312*
2313* hw - Struct containing variables accessed by shared code
2314******************************************************************************/
2315int32_t
2316e1000_wait_autoneg(struct e1000_hw *hw)
2317{
2318 int32_t ret_val;
2319 uint16_t i;
2320 uint16_t phy_data;
2321
2322 DEBUGFUNC("e1000_wait_autoneg");
2323 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2324
2325 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2326 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2327 /* Read the MII Status Register and wait for Auto-Neg
2328 * Complete bit to be set.
2329 */
2330 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2331 if(ret_val)
2332 return ret_val;
2333 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2334 if(ret_val)
2335 return ret_val;
2336 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2337 return E1000_SUCCESS;
2338 }
2339 msec_delay(100);
2340 }
2341 return E1000_SUCCESS;
2342}
2343
2344/******************************************************************************
2345* Raises the Management Data Clock
2346*
2347* hw - Struct containing variables accessed by shared code
2348* ctrl - Device control register's current value
2349******************************************************************************/
2350static void
2351e1000_raise_mdi_clk(struct e1000_hw *hw,
2352 uint32_t *ctrl)
2353{
2354 /* Raise the clock input to the Management Data Clock (by setting the MDC
2355 * bit), and then delay 10 microseconds.
2356 */
2357 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2358 E1000_WRITE_FLUSH(hw);
2359 udelay(10);
2360}
2361
2362/******************************************************************************
2363* Lowers the Management Data Clock
2364*
2365* hw - Struct containing variables accessed by shared code
2366* ctrl - Device control register's current value
2367******************************************************************************/
2368static void
2369e1000_lower_mdi_clk(struct e1000_hw *hw,
2370 uint32_t *ctrl)
2371{
2372 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2373 * bit), and then delay 10 microseconds.
2374 */
2375 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2376 E1000_WRITE_FLUSH(hw);
2377 udelay(10);
2378}
2379
2380/******************************************************************************
2381* Shifts data bits out to the PHY
2382*
2383* hw - Struct containing variables accessed by shared code
2384* data - Data to send out to the PHY
2385* count - Number of bits to shift out
2386*
2387* Bits are shifted out in MSB to LSB order.
2388******************************************************************************/
2389static void
2390e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2391 uint32_t data,
2392 uint16_t count)
2393{
2394 uint32_t ctrl;
2395 uint32_t mask;
2396
2397 /* We need to shift "count" number of bits out to the PHY. So, the value
2398 * in the "data" parameter will be shifted out to the PHY one bit at a
2399 * time. In order to do this, "data" must be broken down into bits.
2400 */
2401 mask = 0x01;
2402 mask <<= (count - 1);
2403
2404 ctrl = E1000_READ_REG(hw, CTRL);
2405
2406 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2407 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2408
2409 while(mask) {
2410 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2411 * then raising and lowering the Management Data Clock. A "0" is
2412 * shifted out to the PHY by setting the MDIO bit to "0" and then
2413 * raising and lowering the clock.
2414 */
2415 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2416 else ctrl &= ~E1000_CTRL_MDIO;
2417
2418 E1000_WRITE_REG(hw, CTRL, ctrl);
2419 E1000_WRITE_FLUSH(hw);
2420
2421 udelay(10);
2422
2423 e1000_raise_mdi_clk(hw, &ctrl);
2424 e1000_lower_mdi_clk(hw, &ctrl);
2425
2426 mask = mask >> 1;
2427 }
2428}
2429
2430/******************************************************************************
2431* Shifts data bits in from the PHY
2432*
2433* hw - Struct containing variables accessed by shared code
2434*
2435* Bits are shifted in in MSB to LSB order.
2436******************************************************************************/
2437static uint16_t
2438e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2439{
2440 uint32_t ctrl;
2441 uint16_t data = 0;
2442 uint8_t i;
2443
2444 /* In order to read a register from the PHY, we need to shift in a total
2445 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2446 * to avoid contention on the MDIO pin when a read operation is performed.
2447 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2448 * by raising the input to the Management Data Clock (setting the MDC bit),
2449 * and then reading the value of the MDIO bit.
2450 */
2451 ctrl = E1000_READ_REG(hw, CTRL);
2452
2453 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2454 ctrl &= ~E1000_CTRL_MDIO_DIR;
2455 ctrl &= ~E1000_CTRL_MDIO;
2456
2457 E1000_WRITE_REG(hw, CTRL, ctrl);
2458 E1000_WRITE_FLUSH(hw);
2459
2460 /* Raise and Lower the clock before reading in the data. This accounts for
2461 * the turnaround bits. The first clock occurred when we clocked out the
2462 * last bit of the Register Address.
2463 */
2464 e1000_raise_mdi_clk(hw, &ctrl);
2465 e1000_lower_mdi_clk(hw, &ctrl);
2466
2467 for(data = 0, i = 0; i < 16; i++) {
2468 data = data << 1;
2469 e1000_raise_mdi_clk(hw, &ctrl);
2470 ctrl = E1000_READ_REG(hw, CTRL);
2471 /* Check to see if we shifted in a "1". */
2472 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2473 e1000_lower_mdi_clk(hw, &ctrl);
2474 }
2475
2476 e1000_raise_mdi_clk(hw, &ctrl);
2477 e1000_lower_mdi_clk(hw, &ctrl);
2478
2479 return data;
2480}
2481
2482/*****************************************************************************
2483* Reads the value from a PHY register, if the value is on a specific non zero
2484* page, sets the page first.
2485* hw - Struct containing variables accessed by shared code
2486* reg_addr - address of the PHY register to read
2487******************************************************************************/
2488int32_t
2489e1000_read_phy_reg(struct e1000_hw *hw,
2490 uint32_t reg_addr,
2491 uint16_t *phy_data)
2492{
2493 uint32_t ret_val;
2494
2495 DEBUGFUNC("e1000_read_phy_reg");
2496
2497
2498 if(hw->phy_type == e1000_phy_igp &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr);
2502 if(ret_val) {
2503 return ret_val;
2504 }
2505 }
2506
2507 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2508 phy_data);
2509
2510 return ret_val;
2511}
2512
2513int32_t
2514e1000_read_phy_reg_ex(struct e1000_hw *hw,
2515 uint32_t reg_addr,
2516 uint16_t *phy_data)
2517{
2518 uint32_t i;
2519 uint32_t mdic = 0;
2520 const uint32_t phy_addr = 1;
2521
2522 DEBUGFUNC("e1000_read_phy_reg_ex");
2523
2524 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2525 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2526 return -E1000_ERR_PARAM;
2527 }
2528
2529 if(hw->mac_type > e1000_82543) {
2530 /* Set up Op-code, Phy Address, and register address in the MDI
2531 * Control register. The MAC will take care of interfacing with the
2532 * PHY to retrieve the desired data.
2533 */
2534 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2535 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2536 (E1000_MDIC_OP_READ));
2537
2538 E1000_WRITE_REG(hw, MDIC, mdic);
2539
2540 /* Poll the ready bit to see if the MDI read completed */
2541 for(i = 0; i < 64; i++) {
2542 udelay(50);
2543 mdic = E1000_READ_REG(hw, MDIC);
2544 if(mdic & E1000_MDIC_READY) break;
2545 }
2546 if(!(mdic & E1000_MDIC_READY)) {
2547 DEBUGOUT("MDI Read did not complete\n");
2548 return -E1000_ERR_PHY;
2549 }
2550 if(mdic & E1000_MDIC_ERROR) {
2551 DEBUGOUT("MDI Error\n");
2552 return -E1000_ERR_PHY;
2553 }
2554 *phy_data = (uint16_t) mdic;
2555 } else {
2556 /* We must first send a preamble through the MDIO pin to signal the
2557 * beginning of an MII instruction. This is done by sending 32
2558 * consecutive "1" bits.
2559 */
2560 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2561
2562 /* Now combine the next few fields that are required for a read
2563 * operation. We use this method instead of calling the
2564 * e1000_shift_out_mdi_bits routine five different times. The format of
2565 * a MII read instruction consists of a shift out of 14 bits and is
2566 * defined as follows:
2567 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2568 * followed by a shift in of 18 bits. This first two bits shifted in
2569 * are TurnAround bits used to avoid contention on the MDIO pin when a
2570 * READ operation is performed. These two bits are thrown away
2571 * followed by a shift in of 16 bits which contains the desired data.
2572 */
2573 mdic = ((reg_addr) | (phy_addr << 5) |
2574 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2575
2576 e1000_shift_out_mdi_bits(hw, mdic, 14);
2577
2578 /* Now that we've shifted out the read command to the MII, we need to
2579 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2580 * register address.
2581 */
2582 *phy_data = e1000_shift_in_mdi_bits(hw);
2583 }
2584 return E1000_SUCCESS;
2585}
2586
2587/******************************************************************************
2588* Writes a value to a PHY register
2589*
2590* hw - Struct containing variables accessed by shared code
2591* reg_addr - address of the PHY register to write
2592* data - data to write to the PHY
2593******************************************************************************/
2594int32_t
2595e1000_write_phy_reg(struct e1000_hw *hw,
2596 uint32_t reg_addr,
2597 uint16_t phy_data)
2598{
2599 uint32_t ret_val;
2600
2601 DEBUGFUNC("e1000_write_phy_reg");
2602
2603
2604 if(hw->phy_type == e1000_phy_igp &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr);
2608 if(ret_val) {
2609 return ret_val;
2610 }
2611 }
2612
2613 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2614 phy_data);
2615
2616 return ret_val;
2617}
2618
2619int32_t
2620e1000_write_phy_reg_ex(struct e1000_hw *hw,
2621 uint32_t reg_addr,
2622 uint16_t phy_data)
2623{
2624 uint32_t i;
2625 uint32_t mdic = 0;
2626 const uint32_t phy_addr = 1;
2627
2628 DEBUGFUNC("e1000_write_phy_reg_ex");
2629
2630 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2631 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2632 return -E1000_ERR_PARAM;
2633 }
2634
2635 if(hw->mac_type > e1000_82543) {
2636 /* Set up Op-code, Phy Address, register address, and data intended
2637 * for the PHY register in the MDI Control register. The MAC will take
2638 * care of interfacing with the PHY to send the desired data.
2639 */
2640 mdic = (((uint32_t) phy_data) |
2641 (reg_addr << E1000_MDIC_REG_SHIFT) |
2642 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2643 (E1000_MDIC_OP_WRITE));
2644
2645 E1000_WRITE_REG(hw, MDIC, mdic);
2646
2647 /* Poll the ready bit to see if the MDI read completed */
2648 for(i = 0; i < 640; i++) {
2649 udelay(5);
2650 mdic = E1000_READ_REG(hw, MDIC);
2651 if(mdic & E1000_MDIC_READY) break;
2652 }
2653 if(!(mdic & E1000_MDIC_READY)) {
2654 DEBUGOUT("MDI Write did not complete\n");
2655 return -E1000_ERR_PHY;
2656 }
2657 } else {
2658 /* We'll need to use the SW defined pins to shift the write command
2659 * out to the PHY. We first send a preamble to the PHY to signal the
2660 * beginning of the MII instruction. This is done by sending 32
2661 * consecutive "1" bits.
2662 */
2663 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2664
2665 /* Now combine the remaining required fields that will indicate a
2666 * write operation. We use this method instead of calling the
2667 * e1000_shift_out_mdi_bits routine for each field in the command. The
2668 * format of a MII write instruction is as follows:
2669 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2670 */
2671 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2672 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2673 mdic <<= 16;
2674 mdic |= (uint32_t) phy_data;
2675
2676 e1000_shift_out_mdi_bits(hw, mdic, 32);
2677 }
2678
2679 return E1000_SUCCESS;
2680}
2681
2682/******************************************************************************
2683* Returns the PHY to the power-on reset state
2684*
2685* hw - Struct containing variables accessed by shared code
2686******************************************************************************/
2687void
2688e1000_phy_hw_reset(struct e1000_hw *hw)
2689{
2690 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl;
2692
2693 DEBUGFUNC("e1000_phy_hw_reset");
2694
2695 DEBUGOUT("Resetting Phy...\n");
2696
2697 if(hw->mac_type > e1000_82543) {
2698 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2699 * bit. Then, take it out of reset.
2700 */
2701 ctrl = E1000_READ_REG(hw, CTRL);
2702 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2703 E1000_WRITE_FLUSH(hw);
2704 msec_delay(10);
2705 E1000_WRITE_REG(hw, CTRL, ctrl);
2706 E1000_WRITE_FLUSH(hw);
2707 } else {
2708 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2709 * bit to put the PHY into reset. Then, take it out of reset.
2710 */
2711 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2712 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2713 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2714 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2715 E1000_WRITE_FLUSH(hw);
2716 msec_delay(10);
2717 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2718 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2719 E1000_WRITE_FLUSH(hw);
2720 }
2721 udelay(150);
2722
2723 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2724 /* Configure activity LED after PHY reset */
2725 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2726 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 }
2730}
2731
2732/******************************************************************************
2733* Resets the PHY
2734*
2735* hw - Struct containing variables accessed by shared code
2736*
2737* Sets bit 15 of the MII Control regiser
2738******************************************************************************/
2739int32_t
2740e1000_phy_reset(struct e1000_hw *hw)
2741{
2742 int32_t ret_val;
2743 uint16_t phy_data;
2744
2745 DEBUGFUNC("e1000_phy_reset");
2746
2747 if(hw->mac_type != e1000_82541_rev_2) {
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val)
2750 return ret_val;
2751
2752 phy_data |= MII_CR_RESET;
2753 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2754 if(ret_val)
2755 return ret_val;
2756
2757 udelay(1);
2758 } else e1000_phy_hw_reset(hw);
2759
2760 if(hw->phy_type == e1000_phy_igp)
2761 e1000_phy_init_script(hw);
2762
2763 return E1000_SUCCESS;
2764}
2765
2766/******************************************************************************
2767* Probes the expected PHY address for known PHY IDs
2768*
2769* hw - Struct containing variables accessed by shared code
2770******************************************************************************/
2771int32_t
2772e1000_detect_gig_phy(struct e1000_hw *hw)
2773{
2774 int32_t phy_init_status, ret_val;
2775 uint16_t phy_id_high, phy_id_low;
2776 boolean_t match = FALSE;
2777
2778 DEBUGFUNC("e1000_detect_gig_phy");
2779
2780 /* Read the PHY ID Registers to identify which PHY is onboard. */
2781 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2782 if(ret_val)
2783 return ret_val;
2784
2785 hw->phy_id = (uint32_t) (phy_id_high << 16);
2786 udelay(20);
2787 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2788 if(ret_val)
2789 return ret_val;
2790
2791 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2792 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2793
2794 switch(hw->mac_type) {
2795 case e1000_82543:
2796 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2797 break;
2798 case e1000_82544:
2799 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2800 break;
2801 case e1000_82540:
2802 case e1000_82545:
2803 case e1000_82545_rev_3:
2804 case e1000_82546:
2805 case e1000_82546_rev_3:
2806 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2807 break;
2808 case e1000_82541:
2809 case e1000_82541_rev_2:
2810 case e1000_82547:
2811 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break;
2814 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG;
2817 }
2818 phy_init_status = e1000_set_phy_type(hw);
2819
2820 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2821 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2822 return E1000_SUCCESS;
2823 }
2824 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2825 return -E1000_ERR_PHY;
2826}
2827
2828/******************************************************************************
2829* Resets the PHY's DSP
2830*
2831* hw - Struct containing variables accessed by shared code
2832******************************************************************************/
2833static int32_t
2834e1000_phy_reset_dsp(struct e1000_hw *hw)
2835{
2836 int32_t ret_val;
2837 DEBUGFUNC("e1000_phy_reset_dsp");
2838
2839 do {
2840 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2841 if(ret_val) break;
2842 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2843 if(ret_val) break;
2844 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2845 if(ret_val) break;
2846 ret_val = E1000_SUCCESS;
2847 } while(0);
2848
2849 return ret_val;
2850}
2851
2852/******************************************************************************
2853* Get PHY information from various PHY registers for igp PHY only.
2854*
2855* hw - Struct containing variables accessed by shared code
2856* phy_info - PHY information structure
2857******************************************************************************/
2858int32_t
2859e1000_phy_igp_get_info(struct e1000_hw *hw,
2860 struct e1000_phy_info *phy_info)
2861{
2862 int32_t ret_val;
2863 uint16_t phy_data, polarity, min_length, max_length, average;
2864
2865 DEBUGFUNC("e1000_phy_igp_get_info");
2866
2867 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded;
2870
2871 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
2873
2874 /* IGP01E1000 always correct polarity reversal */
2875 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
2876
2877 /* Check polarity status */
2878 ret_val = e1000_check_polarity(hw, &polarity);
2879 if(ret_val)
2880 return ret_val;
2881
2882 phy_info->cable_polarity = polarity;
2883
2884 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2885 if(ret_val)
2886 return ret_val;
2887
2888 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2889 IGP01E1000_PSSR_MDIX_SHIFT;
2890
2891 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2892 IGP01E1000_PSSR_SPEED_1000MBPS) {
2893 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2894 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2895 if(ret_val)
2896 return ret_val;
2897
2898 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2899 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2900 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2901 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2902
2903 /* Get cable length */
2904 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2905 if(ret_val)
2906 return ret_val;
2907
2908 /* transalte to old method */
2909 average = (max_length + min_length) / 2;
2910
2911 if(average <= e1000_igp_cable_length_50)
2912 phy_info->cable_length = e1000_cable_length_50;
2913 else if(average <= e1000_igp_cable_length_80)
2914 phy_info->cable_length = e1000_cable_length_50_80;
2915 else if(average <= e1000_igp_cable_length_110)
2916 phy_info->cable_length = e1000_cable_length_80_110;
2917 else if(average <= e1000_igp_cable_length_140)
2918 phy_info->cable_length = e1000_cable_length_110_140;
2919 else
2920 phy_info->cable_length = e1000_cable_length_140;
2921 }
2922
2923 return E1000_SUCCESS;
2924}
2925
2926/******************************************************************************
2927* Get PHY information from various PHY registers fot m88 PHY only.
2928*
2929* hw - Struct containing variables accessed by shared code
2930* phy_info - PHY information structure
2931******************************************************************************/
2932int32_t
2933e1000_phy_m88_get_info(struct e1000_hw *hw,
2934 struct e1000_phy_info *phy_info)
2935{
2936 int32_t ret_val;
2937 uint16_t phy_data, polarity;
2938
2939 DEBUGFUNC("e1000_phy_m88_get_info");
2940
2941 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded;
2944
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val)
2947 return ret_val;
2948
2949 phy_info->extended_10bt_distance =
2950 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2951 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2952 phy_info->polarity_correction =
2953 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2954 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2955
2956 /* Check polarity status */
2957 ret_val = e1000_check_polarity(hw, &polarity);
2958 if(ret_val)
2959 return ret_val;
2960 phy_info->cable_polarity = polarity;
2961
2962 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2963 if(ret_val)
2964 return ret_val;
2965
2966 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2967 M88E1000_PSSR_MDIX_SHIFT;
2968
2969 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2970 /* Cable Length Estimation and Local/Remote Receiver Information
2971 * are only valid at 1000 Mbps.
2972 */
2973 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2974 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2975
2976 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2977 if(ret_val)
2978 return ret_val;
2979
2980 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2981 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2982
2983 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2984 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2985 }
2986
2987 return E1000_SUCCESS;
2988}
2989
2990/******************************************************************************
2991* Get PHY information from various PHY registers
2992*
2993* hw - Struct containing variables accessed by shared code
2994* phy_info - PHY information structure
2995******************************************************************************/
2996int32_t
2997e1000_phy_get_info(struct e1000_hw *hw,
2998 struct e1000_phy_info *phy_info)
2999{
3000 int32_t ret_val;
3001 uint16_t phy_data;
3002
3003 DEBUGFUNC("e1000_phy_get_info");
3004
3005 phy_info->cable_length = e1000_cable_length_undefined;
3006 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3007 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3008 phy_info->downshift = e1000_downshift_undefined;
3009 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3010 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3011 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3012 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3013
3014 if(hw->media_type != e1000_media_type_copper) {
3015 DEBUGOUT("PHY info is only valid for copper media\n");
3016 return -E1000_ERR_CONFIG;
3017 }
3018
3019 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3020 if(ret_val)
3021 return ret_val;
3022
3023 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3024 if(ret_val)
3025 return ret_val;
3026
3027 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3028 DEBUGOUT("PHY info is only valid if link is up\n");
3029 return -E1000_ERR_CONFIG;
3030 }
3031
3032 if(hw->phy_type == e1000_phy_igp)
3033 return e1000_phy_igp_get_info(hw, phy_info);
3034 else
3035 return e1000_phy_m88_get_info(hw, phy_info);
3036}
3037
3038int32_t
3039e1000_validate_mdi_setting(struct e1000_hw *hw)
3040{
3041 DEBUGFUNC("e1000_validate_mdi_settings");
3042
3043 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3044 DEBUGOUT("Invalid MDI setting detected\n");
3045 hw->mdix = 1;
3046 return -E1000_ERR_CONFIG;
3047 }
3048 return E1000_SUCCESS;
3049}
3050
3051
3052/******************************************************************************
3053 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3054 * is configured.
3055 *
3056 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/
3058void
3059e1000_init_eeprom_params(struct e1000_hw *hw)
3060{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD);
3063 uint16_t eeprom_size;
3064
3065 DEBUGFUNC("e1000_init_eeprom_params");
3066
3067 switch (hw->mac_type) {
3068 case e1000_82542_rev2_0:
3069 case e1000_82542_rev2_1:
3070 case e1000_82543:
3071 case e1000_82544:
3072 eeprom->type = e1000_eeprom_microwire;
3073 eeprom->word_size = 64;
3074 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50;
3077 break;
3078 case e1000_82540:
3079 case e1000_82545:
3080 case e1000_82545_rev_3:
3081 case e1000_82546:
3082 case e1000_82546_rev_3:
3083 eeprom->type = e1000_eeprom_microwire;
3084 eeprom->opcode_bits = 3;
3085 eeprom->delay_usec = 50;
3086 if(eecd & E1000_EECD_SIZE) {
3087 eeprom->word_size = 256;
3088 eeprom->address_bits = 8;
3089 } else {
3090 eeprom->word_size = 64;
3091 eeprom->address_bits = 6;
3092 }
3093 break;
3094 case e1000_82541:
3095 case e1000_82541_rev_2:
3096 case e1000_82547:
3097 case e1000_82547_rev_2:
3098 if (eecd & E1000_EECD_TYPE) {
3099 eeprom->type = e1000_eeprom_spi;
3100 eeprom->opcode_bits = 8;
3101 eeprom->delay_usec = 1;
3102 if (eecd & E1000_EECD_ADDR_BITS) {
3103 eeprom->page_size = 32;
3104 eeprom->address_bits = 16;
3105 } else {
3106 eeprom->page_size = 8;
3107 eeprom->address_bits = 8;
3108 }
3109 } else {
3110 eeprom->type = e1000_eeprom_microwire;
3111 eeprom->opcode_bits = 3;
3112 eeprom->delay_usec = 50;
3113 if (eecd & E1000_EECD_ADDR_BITS) {
3114 eeprom->word_size = 256;
3115 eeprom->address_bits = 8;
3116 } else {
3117 eeprom->word_size = 64;
3118 eeprom->address_bits = 6;
3119 }
3120 }
3121 break;
3122 default:
3123 break;
3124 }
3125
3126 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64;
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3129 eeprom_size &= EEPROM_SIZE_MASK;
3130
3131 switch (eeprom_size) {
3132 case EEPROM_SIZE_16KB:
3133 eeprom->word_size = 8192;
3134 break;
3135 case EEPROM_SIZE_8KB:
3136 eeprom->word_size = 4096;
3137 break;
3138 case EEPROM_SIZE_4KB:
3139 eeprom->word_size = 2048;
3140 break;
3141 case EEPROM_SIZE_2KB:
3142 eeprom->word_size = 1024;
3143 break;
3144 case EEPROM_SIZE_1KB:
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 }
3156 }
3157}
3158
3159/******************************************************************************
3160 * Raises the EEPROM's clock input.
3161 *
3162 * hw - Struct containing variables accessed by shared code
3163 * eecd - EECD's current value
3164 *****************************************************************************/
3165static void
3166e1000_raise_ee_clk(struct e1000_hw *hw,
3167 uint32_t *eecd)
3168{
3169 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3170 * wait <delay> microseconds.
3171 */
3172 *eecd = *eecd | E1000_EECD_SK;
3173 E1000_WRITE_REG(hw, EECD, *eecd);
3174 E1000_WRITE_FLUSH(hw);
3175 udelay(hw->eeprom.delay_usec);
3176}
3177
3178/******************************************************************************
3179 * Lowers the EEPROM's clock input.
3180 *
3181 * hw - Struct containing variables accessed by shared code
3182 * eecd - EECD's current value
3183 *****************************************************************************/
3184static void
3185e1000_lower_ee_clk(struct e1000_hw *hw,
3186 uint32_t *eecd)
3187{
3188 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3189 * wait 50 microseconds.
3190 */
3191 *eecd = *eecd & ~E1000_EECD_SK;
3192 E1000_WRITE_REG(hw, EECD, *eecd);
3193 E1000_WRITE_FLUSH(hw);
3194 udelay(hw->eeprom.delay_usec);
3195}
3196
3197/******************************************************************************
3198 * Shift data bits out to the EEPROM.
3199 *
3200 * hw - Struct containing variables accessed by shared code
3201 * data - data to send to the EEPROM
3202 * count - number of bits to shift out
3203 *****************************************************************************/
3204static void
3205e1000_shift_out_ee_bits(struct e1000_hw *hw,
3206 uint16_t data,
3207 uint16_t count)
3208{
3209 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3210 uint32_t eecd;
3211 uint32_t mask;
3212
3213 /* We need to shift "count" bits out to the EEPROM. So, value in the
3214 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3215 * In order to do this, "data" must be broken down into bits.
3216 */
3217 mask = 0x01 << (count - 1);
3218 eecd = E1000_READ_REG(hw, EECD);
3219 if (eeprom->type == e1000_eeprom_microwire) {
3220 eecd &= ~E1000_EECD_DO;
3221 } else if (eeprom->type == e1000_eeprom_spi) {
3222 eecd |= E1000_EECD_DO;
3223 }
3224 do {
3225 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3226 * and then raising and then lowering the clock (the SK bit controls
3227 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3228 * by setting "DI" to "0" and then raising and then lowering the clock.
3229 */
3230 eecd &= ~E1000_EECD_DI;
3231
3232 if(data & mask)
3233 eecd |= E1000_EECD_DI;
3234
3235 E1000_WRITE_REG(hw, EECD, eecd);
3236 E1000_WRITE_FLUSH(hw);
3237
3238 udelay(eeprom->delay_usec);
3239
3240 e1000_raise_ee_clk(hw, &eecd);
3241 e1000_lower_ee_clk(hw, &eecd);
3242
3243 mask = mask >> 1;
3244
3245 } while(mask);
3246
3247 /* We leave the "DI" bit set to "0" when we leave this routine. */
3248 eecd &= ~E1000_EECD_DI;
3249 E1000_WRITE_REG(hw, EECD, eecd);
3250}
3251
3252/******************************************************************************
3253 * Shift data bits in from the EEPROM
3254 *
3255 * hw - Struct containing variables accessed by shared code
3256 *****************************************************************************/
3257static uint16_t
3258e1000_shift_in_ee_bits(struct e1000_hw *hw,
3259 uint16_t count)
3260{
3261 uint32_t eecd;
3262 uint32_t i;
3263 uint16_t data;
3264
3265 /* In order to read a register from the EEPROM, we need to shift 'count'
3266 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3267 * input to the EEPROM (setting the SK bit), and then reading the value of
3268 * the "DO" bit. During this "shifting in" process the "DI" bit should
3269 * always be clear.
3270 */
3271
3272 eecd = E1000_READ_REG(hw, EECD);
3273
3274 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3275 data = 0;
3276
3277 for(i = 0; i < count; i++) {
3278 data = data << 1;
3279 e1000_raise_ee_clk(hw, &eecd);
3280
3281 eecd = E1000_READ_REG(hw, EECD);
3282
3283 eecd &= ~(E1000_EECD_DI);
3284 if(eecd & E1000_EECD_DO)
3285 data |= 1;
3286
3287 e1000_lower_ee_clk(hw, &eecd);
3288 }
3289
3290 return data;
3291}
3292
3293/******************************************************************************
3294 * Prepares EEPROM for access
3295 *
3296 * hw - Struct containing variables accessed by shared code
3297 *
3298 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3299 * function should be called before issuing a command to the EEPROM.
3300 *****************************************************************************/
3301static int32_t
3302e1000_acquire_eeprom(struct e1000_hw *hw)
3303{
3304 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3305 uint32_t eecd, i=0;
3306
3307 DEBUGFUNC("e1000_acquire_eeprom");
3308
3309 eecd = E1000_READ_REG(hw, EECD);
3310
3311 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ;
3314 E1000_WRITE_REG(hw, EECD, eecd);
3315 eecd = E1000_READ_REG(hw, EECD);
3316 while((!(eecd & E1000_EECD_GNT)) &&
3317 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3318 i++;
3319 udelay(5);
3320 eecd = E1000_READ_REG(hw, EECD);
3321 }
3322 if(!(eecd & E1000_EECD_GNT)) {
3323 eecd &= ~E1000_EECD_REQ;
3324 E1000_WRITE_REG(hw, EECD, eecd);
3325 DEBUGOUT("Could not acquire EEPROM grant\n");
3326 return -E1000_ERR_EEPROM;
3327 }
3328 }
3329
3330 /* Setup EEPROM for Read/Write */
3331
3332 if (eeprom->type == e1000_eeprom_microwire) {
3333 /* Clear SK and DI */
3334 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3335 E1000_WRITE_REG(hw, EECD, eecd);
3336
3337 /* Set CS */
3338 eecd |= E1000_EECD_CS;
3339 E1000_WRITE_REG(hw, EECD, eecd);
3340 } else if (eeprom->type == e1000_eeprom_spi) {
3341 /* Clear SK and CS */
3342 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3343 E1000_WRITE_REG(hw, EECD, eecd);
3344 udelay(1);
3345 }
3346
3347 return E1000_SUCCESS;
3348}
3349
3350/******************************************************************************
3351 * Returns EEPROM to a "standby" state
3352 *
3353 * hw - Struct containing variables accessed by shared code
3354 *****************************************************************************/
3355static void
3356e1000_standby_eeprom(struct e1000_hw *hw)
3357{
3358 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3359 uint32_t eecd;
3360
3361 eecd = E1000_READ_REG(hw, EECD);
3362
3363 if(eeprom->type == e1000_eeprom_microwire) {
3364 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3365 E1000_WRITE_REG(hw, EECD, eecd);
3366 E1000_WRITE_FLUSH(hw);
3367 udelay(eeprom->delay_usec);
3368
3369 /* Clock high */
3370 eecd |= E1000_EECD_SK;
3371 E1000_WRITE_REG(hw, EECD, eecd);
3372 E1000_WRITE_FLUSH(hw);
3373 udelay(eeprom->delay_usec);
3374
3375 /* Select EEPROM */
3376 eecd |= E1000_EECD_CS;
3377 E1000_WRITE_REG(hw, EECD, eecd);
3378 E1000_WRITE_FLUSH(hw);
3379 udelay(eeprom->delay_usec);
3380
3381 /* Clock low */
3382 eecd &= ~E1000_EECD_SK;
3383 E1000_WRITE_REG(hw, EECD, eecd);
3384 E1000_WRITE_FLUSH(hw);
3385 udelay(eeprom->delay_usec);
3386 } else if(eeprom->type == e1000_eeprom_spi) {
3387 /* Toggle CS to flush commands */
3388 eecd |= E1000_EECD_CS;
3389 E1000_WRITE_REG(hw, EECD, eecd);
3390 E1000_WRITE_FLUSH(hw);
3391 udelay(eeprom->delay_usec);
3392 eecd &= ~E1000_EECD_CS;
3393 E1000_WRITE_REG(hw, EECD, eecd);
3394 E1000_WRITE_FLUSH(hw);
3395 udelay(eeprom->delay_usec);
3396 }
3397}
3398
3399/******************************************************************************
3400 * Terminates a command by inverting the EEPROM's chip select pin
3401 *
3402 * hw - Struct containing variables accessed by shared code
3403 *****************************************************************************/
3404static void
3405e1000_release_eeprom(struct e1000_hw *hw)
3406{
3407 uint32_t eecd;
3408
3409 DEBUGFUNC("e1000_release_eeprom");
3410
3411 eecd = E1000_READ_REG(hw, EECD);
3412
3413 if (hw->eeprom.type == e1000_eeprom_spi) {
3414 eecd |= E1000_EECD_CS; /* Pull CS high */
3415 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3416
3417 E1000_WRITE_REG(hw, EECD, eecd);
3418
3419 udelay(hw->eeprom.delay_usec);
3420 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3421 /* cleanup eeprom */
3422
3423 /* CS on Microwire is active-high */
3424 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3425
3426 E1000_WRITE_REG(hw, EECD, eecd);
3427
3428 /* Rising edge of clock */
3429 eecd |= E1000_EECD_SK;
3430 E1000_WRITE_REG(hw, EECD, eecd);
3431 E1000_WRITE_FLUSH(hw);
3432 udelay(hw->eeprom.delay_usec);
3433
3434 /* Falling edge of clock */
3435 eecd &= ~E1000_EECD_SK;
3436 E1000_WRITE_REG(hw, EECD, eecd);
3437 E1000_WRITE_FLUSH(hw);
3438 udelay(hw->eeprom.delay_usec);
3439 }
3440
3441 /* Stop requesting EEPROM access */
3442 if(hw->mac_type > e1000_82544) {
3443 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd);
3445 }
3446}
3447
3448/******************************************************************************
3449 * Reads a 16 bit word from the EEPROM.
3450 *
3451 * hw - Struct containing variables accessed by shared code
3452 *****************************************************************************/
3453int32_t
3454e1000_spi_eeprom_ready(struct e1000_hw *hw)
3455{
3456 uint16_t retry_count = 0;
3457 uint8_t spi_stat_reg;
3458
3459 DEBUGFUNC("e1000_spi_eeprom_ready");
3460
3461 /* Read "Status Register" repeatedly until the LSB is cleared. The
3462 * EEPROM will signal that the command has been completed by clearing
3463 * bit 0 of the internal status register. If it's not cleared within
3464 * 5 milliseconds, then error out.
3465 */
3466 retry_count = 0;
3467 do {
3468 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3469 hw->eeprom.opcode_bits);
3470 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3471 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3472 break;
3473
3474 udelay(5);
3475 retry_count += 5;
3476
3477 e1000_standby_eeprom(hw);
3478 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3479
3480 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3481 * only 0-5mSec on 5V devices)
3482 */
3483 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3484 DEBUGOUT("SPI EEPROM Status error\n");
3485 return -E1000_ERR_EEPROM;
3486 }
3487
3488 return E1000_SUCCESS;
3489}
3490
3491/******************************************************************************
3492 * Reads a 16 bit word from the EEPROM.
3493 *
3494 * hw - Struct containing variables accessed by shared code
3495 * offset - offset of word in the EEPROM to read
3496 * data - word read from the EEPROM
3497 * words - number of words to read
3498 *****************************************************************************/
3499int32_t
3500e1000_read_eeprom(struct e1000_hw *hw,
3501 uint16_t offset,
3502 uint16_t words,
3503 uint16_t *data)
3504{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0;
3507
3508 DEBUGFUNC("e1000_read_eeprom");
3509 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words.
3511 */
3512 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3513 (words == 0)) {
3514 DEBUGOUT("\"words\" parameter out of bounds\n");
3515 return -E1000_ERR_EEPROM;
3516 }
3517
3518 /* Prepare the EEPROM for reading */
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3520 return -E1000_ERR_EEPROM;
3521
3522 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in;
3524 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3525
3526 if(e1000_spi_eeprom_ready(hw)) {
3527 e1000_release_eeprom(hw);
3528 return -E1000_ERR_EEPROM;
3529 }
3530
3531 e1000_standby_eeprom(hw);
3532
3533 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3534 if((eeprom->address_bits == 8) && (offset >= 128))
3535 read_opcode |= EEPROM_A8_OPCODE_SPI;
3536
3537 /* Send the READ command (opcode + addr) */
3538 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3539 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3540
3541 /* Read the data. The address of the eeprom internally increments with
3542 * each byte (spi) being read, saving on the overhead of eeprom setup
3543 * and tear-down. The address counter will roll over if reading beyond
3544 * the size of the eeprom, thus allowing the entire memory to be read
3545 * starting from any offset. */
3546 for (i = 0; i < words; i++) {
3547 word_in = e1000_shift_in_ee_bits(hw, 16);
3548 data[i] = (word_in >> 8) | (word_in << 8);
3549 }
3550 } else if(eeprom->type == e1000_eeprom_microwire) {
3551 for (i = 0; i < words; i++) {
3552 /* Send the READ command (opcode + addr) */
3553 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3554 eeprom->opcode_bits);
3555 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3556 eeprom->address_bits);
3557
3558 /* Read the data. For microwire, each word requires the overhead
3559 * of eeprom setup and tear-down. */
3560 data[i] = e1000_shift_in_ee_bits(hw, 16);
3561 e1000_standby_eeprom(hw);
3562 }
3563 }
3564
3565 /* End this read operation */
3566 e1000_release_eeprom(hw);
3567
3568 return E1000_SUCCESS;
3569}
3570
3571/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum
3573 *
3574 * hw - Struct containing variables accessed by shared code
3575 *
3576 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3577 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3578 * valid.
3579 *****************************************************************************/
3580int32_t
3581e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3582{
3583 uint16_t checksum = 0;
3584 uint16_t i, eeprom_data;
3585
3586 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n");
3591 return -E1000_ERR_EEPROM;
3592 }
3593 checksum += eeprom_data;
3594 }
3595
3596 if(checksum == (uint16_t) EEPROM_SUM)
3597 return E1000_SUCCESS;
3598 else {
3599 DEBUGOUT("EEPROM Checksum Invalid\n");
3600 return -E1000_ERR_EEPROM;
3601 }
3602}
3603
3604/******************************************************************************
3605 * Calculates the EEPROM checksum and writes it to the EEPROM
3606 *
3607 * hw - Struct containing variables accessed by shared code
3608 *
3609 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3610 * Writes the difference to word offset 63 of the EEPROM.
3611 *****************************************************************************/
3612int32_t
3613e1000_update_eeprom_checksum(struct e1000_hw *hw)
3614{
3615 uint16_t checksum = 0;
3616 uint16_t i, eeprom_data;
3617
3618 DEBUGFUNC("e1000_update_eeprom_checksum");
3619
3620 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3621 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3622 DEBUGOUT("EEPROM Read Error\n");
3623 return -E1000_ERR_EEPROM;
3624 }
3625 checksum += eeprom_data;
3626 }
3627 checksum = (uint16_t) EEPROM_SUM - checksum;
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM;
3631 }
3632 return E1000_SUCCESS;
3633}
3634
3635/******************************************************************************
3636 * Parent function for writing words to the different EEPROM types.
3637 *
3638 * hw - Struct containing variables accessed by shared code
3639 * offset - offset within the EEPROM to be written to
3640 * words - number of words to write
3641 * data - 16 bit word to be written to the EEPROM
3642 *
3643 * If e1000_update_eeprom_checksum is not called after this function, the
3644 * EEPROM will most likely contain an invalid checksum.
3645 *****************************************************************************/
3646int32_t
3647e1000_write_eeprom(struct e1000_hw *hw,
3648 uint16_t offset,
3649 uint16_t words,
3650 uint16_t *data)
3651{
3652 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3653 int32_t status = 0;
3654
3655 DEBUGFUNC("e1000_write_eeprom");
3656
3657 /* A check for invalid values: offset too large, too many words, and not
3658 * enough words.
3659 */
3660 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3661 (words == 0)) {
3662 DEBUGOUT("\"words\" parameter out of bounds\n");
3663 return -E1000_ERR_EEPROM;
3664 }
3665
3666 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM;
3669
3670 if(eeprom->type == e1000_eeprom_microwire) {
3671 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3672 } else {
3673 status = e1000_write_eeprom_spi(hw, offset, words, data);
3674 msec_delay(10);
3675 }
3676
3677 /* Done with writing */
3678 e1000_release_eeprom(hw);
3679
3680 return status;
3681}
3682
3683/******************************************************************************
3684 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3685 *
3686 * hw - Struct containing variables accessed by shared code
3687 * offset - offset within the EEPROM to be written to
3688 * words - number of words to write
3689 * data - pointer to array of 8 bit words to be written to the EEPROM
3690 *
3691 *****************************************************************************/
3692int32_t
3693e1000_write_eeprom_spi(struct e1000_hw *hw,
3694 uint16_t offset,
3695 uint16_t words,
3696 uint16_t *data)
3697{
3698 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3699 uint16_t widx = 0;
3700
3701 DEBUGFUNC("e1000_write_eeprom_spi");
3702
3703 while (widx < words) {
3704 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3705
3706 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3707
3708 e1000_standby_eeprom(hw);
3709
3710 /* Send the WRITE ENABLE command (8 bit opcode ) */
3711 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3712 eeprom->opcode_bits);
3713
3714 e1000_standby_eeprom(hw);
3715
3716 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3717 if((eeprom->address_bits == 8) && (offset >= 128))
3718 write_opcode |= EEPROM_A8_OPCODE_SPI;
3719
3720 /* Send the Write command (8-bit opcode + addr) */
3721 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3722
3723 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3724 eeprom->address_bits);
3725
3726 /* Send the data */
3727
3728 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3729 while (widx < words) {
3730 uint16_t word_out = data[widx];
3731 word_out = (word_out >> 8) | (word_out << 8);
3732 e1000_shift_out_ee_bits(hw, word_out, 16);
3733 widx++;
3734
3735 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3736 * operation, while the smaller eeproms are capable of an 8-byte
3737 * PAGE WRITE operation. Break the inner loop to pass new address
3738 */
3739 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3740 e1000_standby_eeprom(hw);
3741 break;
3742 }
3743 }
3744 }
3745
3746 return E1000_SUCCESS;
3747}
3748
3749/******************************************************************************
3750 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3751 *
3752 * hw - Struct containing variables accessed by shared code
3753 * offset - offset within the EEPROM to be written to
3754 * words - number of words to write
3755 * data - pointer to array of 16 bit words to be written to the EEPROM
3756 *
3757 *****************************************************************************/
3758int32_t
3759e1000_write_eeprom_microwire(struct e1000_hw *hw,
3760 uint16_t offset,
3761 uint16_t words,
3762 uint16_t *data)
3763{
3764 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3765 uint32_t eecd;
3766 uint16_t words_written = 0;
3767 uint16_t i = 0;
3768
3769 DEBUGFUNC("e1000_write_eeprom_microwire");
3770
3771 /* Send the write enable command to the EEPROM (3-bit opcode plus
3772 * 6/8-bit dummy address beginning with 11). It's less work to include
3773 * the 11 of the dummy address as part of the opcode than it is to shift
3774 * it over the correct number of bits for the address. This puts the
3775 * EEPROM into write/erase mode.
3776 */
3777 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3778 (uint16_t)(eeprom->opcode_bits + 2));
3779
3780 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3781
3782 /* Prepare the EEPROM */
3783 e1000_standby_eeprom(hw);
3784
3785 while (words_written < words) {
3786 /* Send the Write command (3-bit opcode + addr) */
3787 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3788 eeprom->opcode_bits);
3789
3790 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3791 eeprom->address_bits);
3792
3793 /* Send the data */
3794 e1000_shift_out_ee_bits(hw, data[words_written], 16);
3795
3796 /* Toggle the CS line. This in effect tells the EEPROM to execute
3797 * the previous command.
3798 */
3799 e1000_standby_eeprom(hw);
3800
3801 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3802 * signal that the command has been completed by raising the DO signal.
3803 * If DO does not go high in 10 milliseconds, then error out.
3804 */
3805 for(i = 0; i < 200; i++) {
3806 eecd = E1000_READ_REG(hw, EECD);
3807 if(eecd & E1000_EECD_DO) break;
3808 udelay(50);
3809 }
3810 if(i == 200) {
3811 DEBUGOUT("EEPROM Write did not complete\n");
3812 return -E1000_ERR_EEPROM;
3813 }
3814
3815 /* Recover from write */
3816 e1000_standby_eeprom(hw);
3817
3818 words_written++;
3819 }
3820
3821 /* Send the write disable command to the EEPROM (3-bit opcode plus
3822 * 6/8-bit dummy address beginning with 10). It's less work to include
3823 * the 10 of the dummy address as part of the opcode than it is to shift
3824 * it over the correct number of bits for the address. This takes the
3825 * EEPROM out of write/erase mode.
3826 */
3827 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3828 (uint16_t)(eeprom->opcode_bits + 2));
3829
3830 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3831
3832 return E1000_SUCCESS;
3833}
3834
3835/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM
3837 *
3838 * hw - Struct containing variables accessed by shared code
3839 * part_num - Adapter's part number
3840 *****************************************************************************/
3841int32_t
3842e1000_read_part_num(struct e1000_hw *hw,
3843 uint32_t *part_num)
3844{
3845 uint16_t offset = EEPROM_PBA_BYTE_1;
3846 uint16_t eeprom_data;
3847
3848 DEBUGFUNC("e1000_read_part_num");
3849
3850 /* Get word 0 from EEPROM */
3851 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3852 DEBUGOUT("EEPROM Read Error\n");
3853 return -E1000_ERR_EEPROM;
3854 }
3855 /* Save word 0 in upper half of part_num */
3856 *part_num = (uint32_t) (eeprom_data << 16);
3857
3858 /* Get word 1 from EEPROM */
3859 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3860 DEBUGOUT("EEPROM Read Error\n");
3861 return -E1000_ERR_EEPROM;
3862 }
3863 /* Save word 1 in lower half of part_num */
3864 *part_num |= eeprom_data;
3865
3866 return E1000_SUCCESS;
3867}
3868
3869/******************************************************************************
3870 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3871 * second function of dual function devices
3872 *
3873 * hw - Struct containing variables accessed by shared code
3874 *****************************************************************************/
3875int32_t
3876e1000_read_mac_addr(struct e1000_hw * hw)
3877{
3878 uint16_t offset;
3879 uint16_t eeprom_data, i;
3880
3881 DEBUGFUNC("e1000_read_mac_addr");
3882
3883 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3884 offset = i >> 1;
3885 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3886 DEBUGOUT("EEPROM Read Error\n");
3887 return -E1000_ERR_EEPROM;
3888 }
3889 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3890 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3891 }
3892 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3893 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3894 hw->perm_mac_addr[5] ^= 0x01;
3895
3896 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3897 hw->mac_addr[i] = hw->perm_mac_addr[i];
3898 return E1000_SUCCESS;
3899}
3900
3901/******************************************************************************
3902 * Initializes receive address filters.
3903 *
3904 * hw - Struct containing variables accessed by shared code
3905 *
3906 * Places the MAC address in receive address register 0 and clears the rest
3907 * of the receive addresss registers. Clears the multicast table. Assumes
3908 * the receiver is in reset when the routine is called.
3909 *****************************************************************************/
3910void
3911e1000_init_rx_addrs(struct e1000_hw *hw)
3912{
3913 uint32_t i;
3914
3915 DEBUGFUNC("e1000_init_rx_addrs");
3916
3917 /* Setup the receive address. */
3918 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3919
3920 e1000_rar_set(hw, hw->mac_addr, 0);
3921
3922 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 }
3928}
3929
3930/******************************************************************************
3931 * Updates the MAC's list of multicast addresses.
3932 *
3933 * hw - Struct containing variables accessed by shared code
3934 * mc_addr_list - the list of new multicast addresses
3935 * mc_addr_count - number of addresses
3936 * pad - number of bytes between addresses in the list
3937 * rar_used_count - offset where to start adding mc addresses into the RAR's
3938 *
3939 * The given list replaces any existing list. Clears the last 15 receive
3940 * address registers and the multicast table. Uses receive address registers
3941 * for the first 15 multicast addresses, and hashes the rest into the
3942 * multicast table.
3943 *****************************************************************************/
3944void
3945e1000_mc_addr_list_update(struct e1000_hw *hw,
3946 uint8_t *mc_addr_list,
3947 uint32_t mc_addr_count,
3948 uint32_t pad,
3949 uint32_t rar_used_count)
3950{
3951 uint32_t hash_value;
3952 uint32_t i;
3953
3954 DEBUGFUNC("e1000_mc_addr_list_update");
3955
3956 /* Set the new number of MC addresses that we are being requested to use. */
3957 hw->num_mc_addrs = mc_addr_count;
3958
3959 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 }
3965
3966 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 }
3971
3972 /* Add the new addresses */
3973 for(i = 0; i < mc_addr_count; i++) {
3974 DEBUGOUT(" Adding the multicast addresses:\n");
3975 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3976 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3977 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3978 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3979 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3980 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3981 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3982
3983 hash_value = e1000_hash_mc_addr(hw,
3984 mc_addr_list +
3985 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3986
3987 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3988
3989 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA
3991 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) {
3993 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count);
3996 rar_used_count++;
3997 } else {
3998 e1000_mta_set(hw, hash_value);
3999 }
4000 }
4001 DEBUGOUT("MC Update Complete\n");
4002}
4003
4004/******************************************************************************
4005 * Hashes an address to determine its location in the multicast table
4006 *
4007 * hw - Struct containing variables accessed by shared code
4008 * mc_addr - the multicast address to hash
4009 *****************************************************************************/
4010uint32_t
4011e1000_hash_mc_addr(struct e1000_hw *hw,
4012 uint8_t *mc_addr)
4013{
4014 uint32_t hash_value = 0;
4015
4016 /* The portion of the address that is used for the hash table is
4017 * determined by the mc_filter_type setting.
4018 */
4019 switch (hw->mc_filter_type) {
4020 /* [0] [1] [2] [3] [4] [5]
4021 * 01 AA 00 12 34 56
4022 * LSB MSB
4023 */
4024 case 0:
4025 /* [47:36] i.e. 0x563 for above example address */
4026 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
4027 break;
4028 case 1:
4029 /* [46:35] i.e. 0xAC6 for above example address */
4030 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
4031 break;
4032 case 2:
4033 /* [45:34] i.e. 0x5D8 for above example address */
4034 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
4035 break;
4036 case 3:
4037 /* [43:32] i.e. 0x634 for above example address */
4038 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
4039 break;
4040 }
4041
4042 hash_value &= 0xFFF;
4043 return hash_value;
4044}
4045
4046/******************************************************************************
4047 * Sets the bit in the multicast table corresponding to the hash value.
4048 *
4049 * hw - Struct containing variables accessed by shared code
4050 * hash_value - Multicast address hash value
4051 *****************************************************************************/
4052void
4053e1000_mta_set(struct e1000_hw *hw,
4054 uint32_t hash_value)
4055{
4056 uint32_t hash_bit, hash_reg;
4057 uint32_t mta;
4058 uint32_t temp;
4059
4060 /* The MTA is a register array of 128 32-bit registers.
4061 * It is treated like an array of 4096 bits. We want to set
4062 * bit BitArray[hash_value]. So we figure out what register
4063 * the bit is in, read it, OR in the new bit, then write
4064 * back the new value. The register is determined by the
4065 * upper 7 bits of the hash value and the bit within that
4066 * register are determined by the lower 5 bits of the value.
4067 */
4068 hash_reg = (hash_value >> 5) & 0x7F;
4069 hash_bit = hash_value & 0x1F;
4070
4071 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4072
4073 mta |= (1 << hash_bit);
4074
4075 /* If we are on an 82544 and we are trying to write an odd offset
4076 * in the MTA, save off the previous entry before writing and
4077 * restore the old value after writing.
4078 */
4079 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4080 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4081 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4082 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4083 } else {
4084 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4085 }
4086}
4087
4088/******************************************************************************
4089 * Puts an ethernet address into a receive address register.
4090 *
4091 * hw - Struct containing variables accessed by shared code
4092 * addr - Address to put into receive address register
4093 * index - Receive address register to write
4094 *****************************************************************************/
4095void
4096e1000_rar_set(struct e1000_hw *hw,
4097 uint8_t *addr,
4098 uint32_t index)
4099{
4100 uint32_t rar_low, rar_high;
4101
4102 /* HW expects these in little endian so we reverse the byte order
4103 * from network order (big endian) to little endian
4104 */
4105 rar_low = ((uint32_t) addr[0] |
4106 ((uint32_t) addr[1] << 8) |
4107 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4108
4109 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4110
4111 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4112 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4113}
4114
4115/******************************************************************************
4116 * Writes a value to the specified offset in the VLAN filter table.
4117 *
4118 * hw - Struct containing variables accessed by shared code
4119 * offset - Offset in VLAN filer table to write
4120 * value - Value to write into VLAN filter table
4121 *****************************************************************************/
4122void
4123e1000_write_vfta(struct e1000_hw *hw,
4124 uint32_t offset,
4125 uint32_t value)
4126{
4127 uint32_t temp;
4128
4129 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4130 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4131 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4132 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4133 } else {
4134 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4135 }
4136}
4137
4138/******************************************************************************
4139 * Clears the VLAN filer table
4140 *
4141 * hw - Struct containing variables accessed by shared code
4142 *****************************************************************************/
4143void
4144e1000_clear_vfta(struct e1000_hw *hw)
4145{
4146 uint32_t offset;
4147
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4150}
4151
4152static int32_t
4153e1000_id_led_init(struct e1000_hw * hw)
4154{
4155 uint32_t ledctl;
4156 const uint32_t ledctl_mask = 0x000000FF;
4157 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4158 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4159 uint16_t eeprom_data, i, temp;
4160 const uint16_t led_mask = 0x0F;
4161
4162 DEBUGFUNC("e1000_id_led_init");
4163
4164 if(hw->mac_type < e1000_82540) {
4165 /* Nothing to do */
4166 return E1000_SUCCESS;
4167 }
4168
4169 ledctl = E1000_READ_REG(hw, LEDCTL);
4170 hw->ledctl_default = ledctl;
4171 hw->ledctl_mode1 = hw->ledctl_default;
4172 hw->ledctl_mode2 = hw->ledctl_default;
4173
4174 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4175 DEBUGOUT("EEPROM Read Error\n");
4176 return -E1000_ERR_EEPROM;
4177 }
4178 if((eeprom_data== ID_LED_RESERVED_0000) ||
4179 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4180 for(i = 0; i < 4; i++) {
4181 temp = (eeprom_data >> (i << 2)) & led_mask;
4182 switch(temp) {
4183 case ID_LED_ON1_DEF2:
4184 case ID_LED_ON1_ON2:
4185 case ID_LED_ON1_OFF2:
4186 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4187 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4188 break;
4189 case ID_LED_OFF1_DEF2:
4190 case ID_LED_OFF1_ON2:
4191 case ID_LED_OFF1_OFF2:
4192 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4193 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4194 break;
4195 default:
4196 /* Do nothing */
4197 break;
4198 }
4199 switch(temp) {
4200 case ID_LED_DEF1_ON2:
4201 case ID_LED_ON1_ON2:
4202 case ID_LED_OFF1_ON2:
4203 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4204 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4205 break;
4206 case ID_LED_DEF1_OFF2:
4207 case ID_LED_ON1_OFF2:
4208 case ID_LED_OFF1_OFF2:
4209 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4210 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4211 break;
4212 default:
4213 /* Do nothing */
4214 break;
4215 }
4216 }
4217 return E1000_SUCCESS;
4218}
4219
4220/******************************************************************************
4221 * Prepares SW controlable LED for use and saves the current state of the LED.
4222 *
4223 * hw - Struct containing variables accessed by shared code
4224 *****************************************************************************/
4225int32_t
4226e1000_setup_led(struct e1000_hw *hw)
4227{
4228 uint32_t ledctl;
4229 int32_t ret_val = E1000_SUCCESS;
4230
4231 DEBUGFUNC("e1000_setup_led");
4232
4233 switch(hw->mac_type) {
4234 case e1000_82542_rev2_0:
4235 case e1000_82542_rev2_1:
4236 case e1000_82543:
4237 case e1000_82544:
4238 /* No setup necessary */
4239 break;
4240 case e1000_82541:
4241 case e1000_82547:
4242 case e1000_82541_rev_2:
4243 case e1000_82547_rev_2:
4244 /* Turn off PHY Smart Power Down (if enabled) */
4245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4246 &hw->phy_spd_default);
4247 if(ret_val)
4248 return ret_val;
4249 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4250 (uint16_t)(hw->phy_spd_default &
4251 ~IGP01E1000_GMII_SPD));
4252 if(ret_val)
4253 return ret_val;
4254 /* Fall Through */
4255 default:
4256 if(hw->media_type == e1000_media_type_fiber) {
4257 ledctl = E1000_READ_REG(hw, LEDCTL);
4258 /* Save current LEDCTL settings */
4259 hw->ledctl_default = ledctl;
4260 /* Turn off LED0 */
4261 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4262 E1000_LEDCTL_LED0_BLINK |
4263 E1000_LEDCTL_LED0_MODE_MASK);
4264 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4265 E1000_LEDCTL_LED0_MODE_SHIFT);
4266 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4267 } else if(hw->media_type == e1000_media_type_copper)
4268 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4269 break;
4270 }
4271
4272 return E1000_SUCCESS;
4273}
4274
4275/******************************************************************************
4276 * Restores the saved state of the SW controlable LED.
4277 *
4278 * hw - Struct containing variables accessed by shared code
4279 *****************************************************************************/
4280int32_t
4281e1000_cleanup_led(struct e1000_hw *hw)
4282{
4283 int32_t ret_val = E1000_SUCCESS;
4284
4285 DEBUGFUNC("e1000_cleanup_led");
4286
4287 switch(hw->mac_type) {
4288 case e1000_82542_rev2_0:
4289 case e1000_82542_rev2_1:
4290 case e1000_82543:
4291 case e1000_82544:
4292 /* No cleanup necessary */
4293 break;
4294 case e1000_82541:
4295 case e1000_82547:
4296 case e1000_82541_rev_2:
4297 case e1000_82547_rev_2:
4298 /* Turn on PHY Smart Power Down (if previously enabled) */
4299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4300 hw->phy_spd_default);
4301 if(ret_val)
4302 return ret_val;
4303 /* Fall Through */
4304 default:
4305 /* Restore LEDCTL settings */
4306 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4307 break;
4308 }
4309
4310 return E1000_SUCCESS;
4311}
4312
4313/******************************************************************************
4314 * Turns on the software controllable LED
4315 *
4316 * hw - Struct containing variables accessed by shared code
4317 *****************************************************************************/
4318int32_t
4319e1000_led_on(struct e1000_hw *hw)
4320{
4321 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4322
4323 DEBUGFUNC("e1000_led_on");
4324
4325 switch(hw->mac_type) {
4326 case e1000_82542_rev2_0:
4327 case e1000_82542_rev2_1:
4328 case e1000_82543:
4329 /* Set SW Defineable Pin 0 to turn on the LED */
4330 ctrl |= E1000_CTRL_SWDPIN0;
4331 ctrl |= E1000_CTRL_SWDPIO0;
4332 break;
4333 case e1000_82544:
4334 if(hw->media_type == e1000_media_type_fiber) {
4335 /* Set SW Defineable Pin 0 to turn on the LED */
4336 ctrl |= E1000_CTRL_SWDPIN0;
4337 ctrl |= E1000_CTRL_SWDPIO0;
4338 } else {
4339 /* Clear SW Defineable Pin 0 to turn on the LED */
4340 ctrl &= ~E1000_CTRL_SWDPIN0;
4341 ctrl |= E1000_CTRL_SWDPIO0;
4342 }
4343 break;
4344 default:
4345 if(hw->media_type == e1000_media_type_fiber) {
4346 /* Clear SW Defineable Pin 0 to turn on the LED */
4347 ctrl &= ~E1000_CTRL_SWDPIN0;
4348 ctrl |= E1000_CTRL_SWDPIO0;
4349 } else if(hw->media_type == e1000_media_type_copper) {
4350 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4351 return E1000_SUCCESS;
4352 }
4353 break;
4354 }
4355
4356 E1000_WRITE_REG(hw, CTRL, ctrl);
4357
4358 return E1000_SUCCESS;
4359}
4360
4361/******************************************************************************
4362 * Turns off the software controllable LED
4363 *
4364 * hw - Struct containing variables accessed by shared code
4365 *****************************************************************************/
4366int32_t
4367e1000_led_off(struct e1000_hw *hw)
4368{
4369 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4370
4371 DEBUGFUNC("e1000_led_off");
4372
4373 switch(hw->mac_type) {
4374 case e1000_82542_rev2_0:
4375 case e1000_82542_rev2_1:
4376 case e1000_82543:
4377 /* Clear SW Defineable Pin 0 to turn off the LED */
4378 ctrl &= ~E1000_CTRL_SWDPIN0;
4379 ctrl |= E1000_CTRL_SWDPIO0;
4380 break;
4381 case e1000_82544:
4382 if(hw->media_type == e1000_media_type_fiber) {
4383 /* Clear SW Defineable Pin 0 to turn off the LED */
4384 ctrl &= ~E1000_CTRL_SWDPIN0;
4385 ctrl |= E1000_CTRL_SWDPIO0;
4386 } else {
4387 /* Set SW Defineable Pin 0 to turn off the LED */
4388 ctrl |= E1000_CTRL_SWDPIN0;
4389 ctrl |= E1000_CTRL_SWDPIO0;
4390 }
4391 break;
4392 default:
4393 if(hw->media_type == e1000_media_type_fiber) {
4394 /* Set SW Defineable Pin 0 to turn off the LED */
4395 ctrl |= E1000_CTRL_SWDPIN0;
4396 ctrl |= E1000_CTRL_SWDPIO0;
4397 } else if(hw->media_type == e1000_media_type_copper) {
4398 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4399 return E1000_SUCCESS;
4400 }
4401 break;
4402 }
4403
4404 E1000_WRITE_REG(hw, CTRL, ctrl);
4405
4406 return E1000_SUCCESS;
4407}
4408
4409/******************************************************************************
4410 * Clears all hardware statistics counters.
4411 *
4412 * hw - Struct containing variables accessed by shared code
4413 *****************************************************************************/
4414void
4415e1000_clear_hw_cntrs(struct e1000_hw *hw)
4416{
4417 volatile uint32_t temp;
4418
4419 temp = E1000_READ_REG(hw, CRCERRS);
4420 temp = E1000_READ_REG(hw, SYMERRS);
4421 temp = E1000_READ_REG(hw, MPC);
4422 temp = E1000_READ_REG(hw, SCC);
4423 temp = E1000_READ_REG(hw, ECOL);
4424 temp = E1000_READ_REG(hw, MCC);
4425 temp = E1000_READ_REG(hw, LATECOL);
4426 temp = E1000_READ_REG(hw, COLC);
4427 temp = E1000_READ_REG(hw, DC);
4428 temp = E1000_READ_REG(hw, SEC);
4429 temp = E1000_READ_REG(hw, RLEC);
4430 temp = E1000_READ_REG(hw, XONRXC);
4431 temp = E1000_READ_REG(hw, XONTXC);
4432 temp = E1000_READ_REG(hw, XOFFRXC);
4433 temp = E1000_READ_REG(hw, XOFFTXC);
4434 temp = E1000_READ_REG(hw, FCRUC);
4435 temp = E1000_READ_REG(hw, PRC64);
4436 temp = E1000_READ_REG(hw, PRC127);
4437 temp = E1000_READ_REG(hw, PRC255);
4438 temp = E1000_READ_REG(hw, PRC511);
4439 temp = E1000_READ_REG(hw, PRC1023);
4440 temp = E1000_READ_REG(hw, PRC1522);
4441 temp = E1000_READ_REG(hw, GPRC);
4442 temp = E1000_READ_REG(hw, BPRC);
4443 temp = E1000_READ_REG(hw, MPRC);
4444 temp = E1000_READ_REG(hw, GPTC);
4445 temp = E1000_READ_REG(hw, GORCL);
4446 temp = E1000_READ_REG(hw, GORCH);
4447 temp = E1000_READ_REG(hw, GOTCL);
4448 temp = E1000_READ_REG(hw, GOTCH);
4449 temp = E1000_READ_REG(hw, RNBC);
4450 temp = E1000_READ_REG(hw, RUC);
4451 temp = E1000_READ_REG(hw, RFC);
4452 temp = E1000_READ_REG(hw, ROC);
4453 temp = E1000_READ_REG(hw, RJC);
4454 temp = E1000_READ_REG(hw, TORL);
4455 temp = E1000_READ_REG(hw, TORH);
4456 temp = E1000_READ_REG(hw, TOTL);
4457 temp = E1000_READ_REG(hw, TOTH);
4458 temp = E1000_READ_REG(hw, TPR);
4459 temp = E1000_READ_REG(hw, TPT);
4460 temp = E1000_READ_REG(hw, PTC64);
4461 temp = E1000_READ_REG(hw, PTC127);
4462 temp = E1000_READ_REG(hw, PTC255);
4463 temp = E1000_READ_REG(hw, PTC511);
4464 temp = E1000_READ_REG(hw, PTC1023);
4465 temp = E1000_READ_REG(hw, PTC1522);
4466 temp = E1000_READ_REG(hw, MPTC);
4467 temp = E1000_READ_REG(hw, BPTC);
4468
4469 if(hw->mac_type < e1000_82543) return;
4470
4471 temp = E1000_READ_REG(hw, ALGNERRC);
4472 temp = E1000_READ_REG(hw, RXERRC);
4473 temp = E1000_READ_REG(hw, TNCRS);
4474 temp = E1000_READ_REG(hw, CEXTERR);
4475 temp = E1000_READ_REG(hw, TSCTC);
4476 temp = E1000_READ_REG(hw, TSCTFC);
4477
4478 if(hw->mac_type <= e1000_82544) return;
4479
4480 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC);
4483}
4484
4485/******************************************************************************
4486 * Resets Adaptive IFS to its default state.
4487 *
4488 * hw - Struct containing variables accessed by shared code
4489 *
4490 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4491 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4492 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4493 * before calling this function.
4494 *****************************************************************************/
4495void
4496e1000_reset_adaptive(struct e1000_hw *hw)
4497{
4498 DEBUGFUNC("e1000_reset_adaptive");
4499
4500 if(hw->adaptive_ifs) {
4501 if(!hw->ifs_params_forced) {
4502 hw->current_ifs_val = 0;
4503 hw->ifs_min_val = IFS_MIN;
4504 hw->ifs_max_val = IFS_MAX;
4505 hw->ifs_step_size = IFS_STEP;
4506 hw->ifs_ratio = IFS_RATIO;
4507 }
4508 hw->in_ifs_mode = FALSE;
4509 E1000_WRITE_REG(hw, AIT, 0);
4510 } else {
4511 DEBUGOUT("Not in Adaptive IFS mode!\n");
4512 }
4513}
4514
4515/******************************************************************************
4516 * Called during the callback/watchdog routine to update IFS value based on
4517 * the ratio of transmits to collisions.
4518 *
4519 * hw - Struct containing variables accessed by shared code
4520 * tx_packets - Number of transmits since last callback
4521 * total_collisions - Number of collisions since last callback
4522 *****************************************************************************/
4523void
4524e1000_update_adaptive(struct e1000_hw *hw)
4525{
4526 DEBUGFUNC("e1000_update_adaptive");
4527
4528 if(hw->adaptive_ifs) {
4529 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4530 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4531 hw->in_ifs_mode = TRUE;
4532 if(hw->current_ifs_val < hw->ifs_max_val) {
4533 if(hw->current_ifs_val == 0)
4534 hw->current_ifs_val = hw->ifs_min_val;
4535 else
4536 hw->current_ifs_val += hw->ifs_step_size;
4537 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4538 }
4539 }
4540 } else {
4541 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4542 hw->current_ifs_val = 0;
4543 hw->in_ifs_mode = FALSE;
4544 E1000_WRITE_REG(hw, AIT, 0);
4545 }
4546 }
4547 } else {
4548 DEBUGOUT("Not in Adaptive IFS mode!\n");
4549 }
4550}
4551
4552/******************************************************************************
4553 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4554 *
4555 * hw - Struct containing variables accessed by shared code
4556 * frame_len - The length of the frame in question
4557 * mac_addr - The Ethernet destination address of the frame in question
4558 *****************************************************************************/
4559void
4560e1000_tbi_adjust_stats(struct e1000_hw *hw,
4561 struct e1000_hw_stats *stats,
4562 uint32_t frame_len,
4563 uint8_t *mac_addr)
4564{
4565 uint64_t carry_bit;
4566
4567 /* First adjust the frame length. */
4568 frame_len--;
4569 /* We need to adjust the statistics counters, since the hardware
4570 * counters overcount this packet as a CRC error and undercount
4571 * the packet as a good packet
4572 */
4573 /* This packet should not be counted as a CRC error. */
4574 stats->crcerrs--;
4575 /* This packet does count as a Good Packet Received. */
4576 stats->gprc++;
4577
4578 /* Adjust the Good Octets received counters */
4579 carry_bit = 0x80000000 & stats->gorcl;
4580 stats->gorcl += frame_len;
4581 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4582 * Received Count) was one before the addition,
4583 * AND it is zero after, then we lost the carry out,
4584 * need to add one to Gorch (Good Octets Received Count High).
4585 * This could be simplified if all environments supported
4586 * 64-bit integers.
4587 */
4588 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4589 stats->gorch++;
4590 /* Is this a broadcast or multicast? Check broadcast first,
4591 * since the test for a multicast frame will test positive on
4592 * a broadcast frame.
4593 */
4594 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4595 /* Broadcast packet */
4596 stats->bprc++;
4597 else if(*mac_addr & 0x01)
4598 /* Multicast packet */
4599 stats->mprc++;
4600
4601 if(frame_len == hw->max_frame_size) {
4602 /* In this case, the hardware has overcounted the number of
4603 * oversize frames.
4604 */
4605 if(stats->roc > 0)
4606 stats->roc--;
4607 }
4608
4609 /* Adjust the bin counters when the extra byte put the frame in the
4610 * wrong bin. Remember that the frame_len was adjusted above.
4611 */
4612 if(frame_len == 64) {
4613 stats->prc64++;
4614 stats->prc127--;
4615 } else if(frame_len == 127) {
4616 stats->prc127++;
4617 stats->prc255--;
4618 } else if(frame_len == 255) {
4619 stats->prc255++;
4620 stats->prc511--;
4621 } else if(frame_len == 511) {
4622 stats->prc511++;
4623 stats->prc1023--;
4624 } else if(frame_len == 1023) {
4625 stats->prc1023++;
4626 stats->prc1522--;
4627 } else if(frame_len == 1522) {
4628 stats->prc1522++;
4629 }
4630}
4631
4632/******************************************************************************
4633 * Gets the current PCI bus type, speed, and width of the hardware
4634 *
4635 * hw - Struct containing variables accessed by shared code
4636 *****************************************************************************/
4637void
4638e1000_get_bus_info(struct e1000_hw *hw)
4639{
4640 uint32_t status;
4641
4642 switch (hw->mac_type) {
4643 case e1000_82542_rev2_0:
4644 case e1000_82542_rev2_1:
4645 hw->bus_type = e1000_bus_type_unknown;
4646 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown;
4648 break;
4649 default:
4650 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4652 e1000_bus_type_pcix : e1000_bus_type_pci;
4653
4654 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4655 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4656 e1000_bus_speed_66 : e1000_bus_speed_120;
4657 } else if(hw->bus_type == e1000_bus_type_pci) {
4658 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4659 e1000_bus_speed_66 : e1000_bus_speed_33;
4660 } else {
4661 switch (status & E1000_STATUS_PCIX_SPEED) {
4662 case E1000_STATUS_PCIX_SPEED_66:
4663 hw->bus_speed = e1000_bus_speed_66;
4664 break;
4665 case E1000_STATUS_PCIX_SPEED_100:
4666 hw->bus_speed = e1000_bus_speed_100;
4667 break;
4668 case E1000_STATUS_PCIX_SPEED_133:
4669 hw->bus_speed = e1000_bus_speed_133;
4670 break;
4671 default:
4672 hw->bus_speed = e1000_bus_speed_reserved;
4673 break;
4674 }
4675 }
4676 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4677 e1000_bus_width_64 : e1000_bus_width_32;
4678 break;
4679 }
4680}
4681/******************************************************************************
4682 * Reads a value from one of the devices registers using port I/O (as opposed
4683 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4684 *
4685 * hw - Struct containing variables accessed by shared code
4686 * offset - offset to read from
4687 *****************************************************************************/
4688uint32_t
4689e1000_read_reg_io(struct e1000_hw *hw,
4690 uint32_t offset)
4691{
4692 unsigned long io_addr = hw->io_base;
4693 unsigned long io_data = hw->io_base + 4;
4694
4695 e1000_io_write(hw, io_addr, offset);
4696 return e1000_io_read(hw, io_data);
4697}
4698
4699/******************************************************************************
4700 * Writes a value to one of the devices registers using port I/O (as opposed to
4701 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4702 *
4703 * hw - Struct containing variables accessed by shared code
4704 * offset - offset to write to
4705 * value - value to write
4706 *****************************************************************************/
4707void
4708e1000_write_reg_io(struct e1000_hw *hw,
4709 uint32_t offset,
4710 uint32_t value)
4711{
4712 unsigned long io_addr = hw->io_base;
4713 unsigned long io_data = hw->io_base + 4;
4714
4715 e1000_io_write(hw, io_addr, offset);
4716 e1000_io_write(hw, io_data, value);
4717}
4718
4719
4720/******************************************************************************
4721 * Estimates the cable length.
4722 *
4723 * hw - Struct containing variables accessed by shared code
4724 * min_length - The estimated minimum length
4725 * max_length - The estimated maximum length
4726 *
4727 * returns: - E1000_ERR_XXX
4728 * E1000_SUCCESS
4729 *
4730 * This function always returns a ranged length (minimum & maximum).
4731 * So for M88 phy's, this function interprets the one value returned from the
4732 * register to the minimum and maximum range.
4733 * For IGP phy's, the function calculates the range by the AGC registers.
4734 *****************************************************************************/
4735int32_t
4736e1000_get_cable_length(struct e1000_hw *hw,
4737 uint16_t *min_length,
4738 uint16_t *max_length)
4739{
4740 int32_t ret_val;
4741 uint16_t agc_value = 0;
4742 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4743 uint16_t i, phy_data;
4744 uint16_t cable_length;
4745
4746 DEBUGFUNC("e1000_get_cable_length");
4747
4748 *min_length = *max_length = 0;
4749
4750 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) {
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data);
4754 if(ret_val)
4755 return ret_val;
4756 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4757 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4758
4759 /* Convert the enum value to ranged values */
4760 switch (cable_length) {
4761 case e1000_cable_length_50:
4762 *min_length = 0;
4763 *max_length = e1000_igp_cable_length_50;
4764 break;
4765 case e1000_cable_length_50_80:
4766 *min_length = e1000_igp_cable_length_50;
4767 *max_length = e1000_igp_cable_length_80;
4768 break;
4769 case e1000_cable_length_80_110:
4770 *min_length = e1000_igp_cable_length_80;
4771 *max_length = e1000_igp_cable_length_110;
4772 break;
4773 case e1000_cable_length_110_140:
4774 *min_length = e1000_igp_cable_length_110;
4775 *max_length = e1000_igp_cable_length_140;
4776 break;
4777 case e1000_cable_length_140:
4778 *min_length = e1000_igp_cable_length_140;
4779 *max_length = e1000_igp_cable_length_170;
4780 break;
4781 default:
4782 return -E1000_ERR_PHY;
4783 break;
4784 }
4785 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4786 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4787 {IGP01E1000_PHY_AGC_A,
4788 IGP01E1000_PHY_AGC_B,
4789 IGP01E1000_PHY_AGC_C,
4790 IGP01E1000_PHY_AGC_D};
4791 /* Read the AGC registers for all channels */
4792 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4793
4794 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4795 if(ret_val)
4796 return ret_val;
4797
4798 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4799
4800 /* Array bound check. */
4801 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4802 (cur_agc == 0))
4803 return -E1000_ERR_PHY;
4804
4805 agc_value += cur_agc;
4806
4807 /* Update minimal AGC value. */
4808 if(min_agc > cur_agc)
4809 min_agc = cur_agc;
4810 }
4811
4812 /* Remove the minimal AGC result for length < 50m */
4813 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4814 agc_value -= min_agc;
4815
4816 /* Get the average length of the remaining 3 channels */
4817 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4818 } else {
4819 /* Get the average length of all the 4 channels. */
4820 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4821 }
4822
4823 /* Set the range of the calculated length. */
4824 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4825 IGP01E1000_AGC_RANGE) > 0) ?
4826 (e1000_igp_cable_length_table[agc_value] -
4827 IGP01E1000_AGC_RANGE) : 0;
4828 *max_length = e1000_igp_cable_length_table[agc_value] +
4829 IGP01E1000_AGC_RANGE;
4830 }
4831
4832 return E1000_SUCCESS;
4833}
4834
4835/******************************************************************************
4836 * Check the cable polarity
4837 *
4838 * hw - Struct containing variables accessed by shared code
4839 * polarity - output parameter : 0 - Polarity is not reversed
4840 * 1 - Polarity is reversed.
4841 *
4842 * returns: - E1000_ERR_XXX
4843 * E1000_SUCCESS
4844 *
4845 * For phy's older then IGP, this function simply reads the polarity bit in the
4846 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4847 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4848 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4849 * IGP01E1000_PHY_PCS_INIT_REG.
4850 *****************************************************************************/
4851int32_t
4852e1000_check_polarity(struct e1000_hw *hw,
4853 uint16_t *polarity)
4854{
4855 int32_t ret_val;
4856 uint16_t phy_data;
4857
4858 DEBUGFUNC("e1000_check_polarity");
4859
4860 if(hw->phy_type == e1000_phy_m88) {
4861 /* return the Polarity bit in the Status register. */
4862 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4863 &phy_data);
4864 if(ret_val)
4865 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) {
4869 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data);
4872 if(ret_val)
4873 return ret_val;
4874
4875 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4876 * find the polarity status */
4877 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4878 IGP01E1000_PSSR_SPEED_1000MBPS) {
4879
4880 /* Read the GIG initialization PCS register (0x00B4) */
4881 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4882 &phy_data);
4883 if(ret_val)
4884 return ret_val;
4885
4886 /* Check the polarity bits */
4887 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4888 } else {
4889 /* For 10 Mbps, read the polarity bit in the status register. (for
4890 * 100 Mbps this bit is always 0) */
4891 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4892 }
4893 }
4894 return E1000_SUCCESS;
4895}
4896
4897/******************************************************************************
4898 * Check if Downshift occured
4899 *
4900 * hw - Struct containing variables accessed by shared code
4901 * downshift - output parameter : 0 - No Downshift ocured.
4902 * 1 - Downshift ocured.
4903 *
4904 * returns: - E1000_ERR_XXX
4905 * E1000_SUCCESS
4906 *
4907 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4908 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4909 * Link Health register. In IGP this bit is latched high, so the driver must
4910 * read it immediately after link is established.
4911 *****************************************************************************/
4912int32_t
4913e1000_check_downshift(struct e1000_hw *hw)
4914{
4915 int32_t ret_val;
4916 uint16_t phy_data;
4917
4918 DEBUGFUNC("e1000_check_downshift");
4919
4920 if(hw->phy_type == e1000_phy_igp) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data);
4923 if(ret_val)
4924 return ret_val;
4925
4926 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4927 } else if(hw->phy_type == e1000_phy_m88) {
4928 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4929 &phy_data);
4930 if(ret_val)
4931 return ret_val;
4932
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 }
4936 return E1000_SUCCESS;
4937}
4938
4939/*****************************************************************************
4940 *
4941 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4942 * gigabit link is achieved to improve link quality.
4943 *
4944 * hw: Struct containing variables accessed by shared code
4945 *
4946 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4947 * E1000_SUCCESS at any other case.
4948 *
4949 ****************************************************************************/
4950
4951int32_t
4952e1000_config_dsp_after_link_change(struct e1000_hw *hw,
4953 boolean_t link_up)
4954{
4955 int32_t ret_val;
4956 uint16_t phy_data, phy_saved_data, speed, duplex, i;
4957 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4958 {IGP01E1000_PHY_AGC_PARAM_A,
4959 IGP01E1000_PHY_AGC_PARAM_B,
4960 IGP01E1000_PHY_AGC_PARAM_C,
4961 IGP01E1000_PHY_AGC_PARAM_D};
4962 uint16_t min_length, max_length;
4963
4964 DEBUGFUNC("e1000_config_dsp_after_link_change");
4965
4966 if(hw->phy_type != e1000_phy_igp)
4967 return E1000_SUCCESS;
4968
4969 if(link_up) {
4970 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
4971 if(ret_val) {
4972 DEBUGOUT("Error getting link speed and duplex\n");
4973 return ret_val;
4974 }
4975
4976 if(speed == SPEED_1000) {
4977
4978 e1000_get_cable_length(hw, &min_length, &max_length);
4979
4980 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
4981 min_length >= e1000_igp_cable_length_50) {
4982
4983 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4984 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4985 &phy_data);
4986 if(ret_val)
4987 return ret_val;
4988
4989 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4990
4991 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
4992 phy_data);
4993 if(ret_val)
4994 return ret_val;
4995 }
4996 hw->dsp_config_state = e1000_dsp_config_activated;
4997 }
4998
4999 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
5000 (min_length < e1000_igp_cable_length_50)) {
5001
5002 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5003 uint32_t idle_errs = 0;
5004
5005 /* clear previous idle error counts */
5006 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5007 &phy_data);
5008 if(ret_val)
5009 return ret_val;
5010
5011 for(i = 0; i < ffe_idle_err_timeout; i++) {
5012 udelay(1000);
5013 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5014 &phy_data);
5015 if(ret_val)
5016 return ret_val;
5017
5018 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5019 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5020 hw->ffe_config_state = e1000_ffe_config_active;
5021
5022 ret_val = e1000_write_phy_reg(hw,
5023 IGP01E1000_PHY_DSP_FFE,
5024 IGP01E1000_PHY_DSP_FFE_CM_CP);
5025 if(ret_val)
5026 return ret_val;
5027 break;
5028 }
5029
5030 if(idle_errs)
5031 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5032 }
5033 }
5034 }
5035 } else {
5036 if(hw->dsp_config_state == e1000_dsp_config_activated) {
5037 /* Save off the current value of register 0x2F5B to be restored at
5038 * the end of the routines. */
5039 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5040
5041 if(ret_val)
5042 return ret_val;
5043
5044 /* Disable the PHY transmitter */
5045 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5046
5047 if(ret_val)
5048 return ret_val;
5049
5050 msec_delay(20);
5051
5052 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA);
5054 if(ret_val)
5055 return ret_val;
5056 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5057 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
5058 if(ret_val)
5059 return ret_val;
5060
5061 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5062 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5063
5064 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
5065 if(ret_val)
5066 return ret_val;
5067 }
5068
5069 ret_val = e1000_write_phy_reg(hw, 0x0000,
5070 IGP01E1000_IEEE_RESTART_AUTONEG);
5071 if(ret_val)
5072 return ret_val;
5073
5074 msec_delay(20);
5075
5076 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5078
5079 if(ret_val)
5080 return ret_val;
5081
5082 hw->dsp_config_state = e1000_dsp_config_enabled;
5083 }
5084
5085 if(hw->ffe_config_state == e1000_ffe_config_active) {
5086 /* Save off the current value of register 0x2F5B to be restored at
5087 * the end of the routines. */
5088 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5089
5090 if(ret_val)
5091 return ret_val;
5092
5093 /* Disable the PHY transmitter */
5094 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5095
5096 if(ret_val)
5097 return ret_val;
5098
5099 msec_delay(20);
5100
5101 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA);
5103 if(ret_val)
5104 return ret_val;
5105 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5106 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5107 if(ret_val)
5108 return ret_val;
5109
5110 ret_val = e1000_write_phy_reg(hw, 0x0000,
5111 IGP01E1000_IEEE_RESTART_AUTONEG);
5112 if(ret_val)
5113 return ret_val;
5114
5115 msec_delay(20);
5116
5117 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5119
5120 if(ret_val)
5121 return ret_val;
5122
5123 hw->ffe_config_state = e1000_ffe_config_enabled;
5124 }
5125 }
5126 return E1000_SUCCESS;
5127}
5128
5129/*****************************************************************************
5130 * Set PHY to class A mode
5131 * Assumes the following operations will follow to enable the new class mode.
5132 * 1. Do a PHY soft reset
5133 * 2. Restart auto-negotiation or force link.
5134 *
5135 * hw - Struct containing variables accessed by shared code
5136 ****************************************************************************/
5137static int32_t
5138e1000_set_phy_mode(struct e1000_hw *hw)
5139{
5140 int32_t ret_val;
5141 uint16_t eeprom_data;
5142
5143 DEBUGFUNC("e1000_set_phy_mode");
5144
5145 if((hw->mac_type == e1000_82545_rev_3) &&
5146 (hw->media_type == e1000_media_type_copper)) {
5147 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5148 if(ret_val) {
5149 return ret_val;
5150 }
5151
5152 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5153 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5154 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5155 if(ret_val)
5156 return ret_val;
5157 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5158 if(ret_val)
5159 return ret_val;
5160
5161 hw->phy_reset_disable = FALSE;
5162 }
5163 }
5164
5165 return E1000_SUCCESS;
5166}
5167
5168/*****************************************************************************
5169 *
5170 * This function sets the lplu state according to the active flag. When
5171 * activating lplu this function also disables smart speed and vise versa.
5172 * lplu will not be activated unless the device autonegotiation advertisment
5173 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5174 * hw: Struct containing variables accessed by shared code
5175 * active - true to enable lplu false to disable lplu.
5176 *
5177 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5178 * E1000_SUCCESS at any other case.
5179 *
5180 ****************************************************************************/
5181
5182int32_t
5183e1000_set_d3_lplu_state(struct e1000_hw *hw,
5184 boolean_t active)
5185{
5186 int32_t ret_val;
5187 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state");
5189
5190 if(!((hw->mac_type == e1000_82541_rev_2) ||
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS;
5193
5194 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5198 if(ret_val)
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val)
5205 return ret_val;
5206
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During
5209 * driver activity we should enable SmartSpeed, so performance is
5210 * maintained. */
5211 if (hw->smart_speed == e1000_smart_speed_on) {
5212 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5213 &phy_data);
5214 if(ret_val)
5215 return ret_val;
5216
5217 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5218 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5219 phy_data);
5220 if(ret_val)
5221 return ret_val;
5222 } else if (hw->smart_speed == e1000_smart_speed_off) {
5223 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5224 &phy_data);
5225 if (ret_val)
5226 return ret_val;
5227
5228 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5229 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5230 phy_data);
5231 if(ret_val)
5232 return ret_val;
5233 }
5234
5235 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5241 if(ret_val)
5242 return ret_val;
5243
5244 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val)
5247 return ret_val;
5248
5249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5251 if(ret_val)
5252 return ret_val;
5253
5254 }
5255 return E1000_SUCCESS;
5256}
5257
5258/******************************************************************************
5259 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5260 *
5261 * hw - Struct containing variables accessed by shared code
5262 *****************************************************************************/
5263static int32_t
5264e1000_set_vco_speed(struct e1000_hw *hw)
5265{
5266 int32_t ret_val;
5267 uint16_t default_page = 0;
5268 uint16_t phy_data;
5269
5270 DEBUGFUNC("e1000_set_vco_speed");
5271
5272 switch(hw->mac_type) {
5273 case e1000_82545_rev_3:
5274 case e1000_82546_rev_3:
5275 break;
5276 default:
5277 return E1000_SUCCESS;
5278 }
5279
5280 /* Set PHY register 30, page 5, bit 8 to 0 */
5281
5282 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5283 if(ret_val)
5284 return ret_val;
5285
5286 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5287 if(ret_val)
5288 return ret_val;
5289
5290 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5291 if(ret_val)
5292 return ret_val;
5293
5294 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5295 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5296 if(ret_val)
5297 return ret_val;
5298
5299 /* Set PHY register 30, page 4, bit 11 to 1 */
5300
5301 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5302 if(ret_val)
5303 return ret_val;
5304
5305 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5306 if(ret_val)
5307 return ret_val;
5308
5309 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5310 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5311 if(ret_val)
5312 return ret_val;
5313
5314 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5315 if(ret_val)
5316 return ret_val;
5317
5318 return E1000_SUCCESS;
5319}
5320
5321static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{
5324 int32_t ret_val;
5325 uint16_t mii_status_reg;
5326 uint16_t i;
5327
5328 /* Polarity reversal workaround for forced 10F/10H links. */
5329
5330 /* Disable the transmitter on the PHY */
5331
5332 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5333 if(ret_val)
5334 return ret_val;
5335 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5336 if(ret_val)
5337 return ret_val;
5338
5339 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5340 if(ret_val)
5341 return ret_val;
5342
5343 /* This loop will early-out if the NO link condition has been met. */
5344 for(i = PHY_FORCE_TIME; i > 0; i--) {
5345 /* Read the MII Status Register and wait for Link Status bit
5346 * to be clear.
5347 */
5348
5349 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5350 if(ret_val)
5351 return ret_val;
5352
5353 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5354 if(ret_val)
5355 return ret_val;
5356
5357 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
5358 msec_delay_irq(100);
5359 }
5360
5361 /* Recommended delay time after link has been lost */
5362 msec_delay_irq(1000);
5363
5364 /* Now we will re-enable th transmitter on the PHY */
5365
5366 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5367 if(ret_val)
5368 return ret_val;
5369 msec_delay_irq(50);
5370 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5371 if(ret_val)
5372 return ret_val;
5373 msec_delay_irq(50);
5374 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5375 if(ret_val)
5376 return ret_val;
5377 msec_delay_irq(50);
5378 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5379 if(ret_val)
5380 return ret_val;
5381
5382 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5383 if(ret_val)
5384 return ret_val;
5385
5386 /* This loop will early-out if the link condition has been met. */
5387 for(i = PHY_FORCE_TIME; i > 0; i--) {
5388 /* Read the MII Status Register and wait for Link Status bit
5389 * to be set.
5390 */
5391
5392 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5393 if(ret_val)
5394 return ret_val;
5395
5396 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5397 if(ret_val)
5398 return ret_val;
5399
5400 if(mii_status_reg & MII_SR_LINK_STATUS) break;
5401 msec_delay_irq(100);
5402 }
5403 return E1000_SUCCESS;
5404}
5405
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 07:35:56 -0500