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authorJoe Perches <joe@perches.com>2008-07-11 18:17:08 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-22 19:38:47 -0400
commit1dc329180fe22ff8651e0ef550ba17ca1cc7bf22 (patch)
tree720ae356d0b4997baa2a0389e896fc6d2930a2bf /drivers/net/e1000/e1000_hw.c
parent6479884509e6cd30c6708fbf05fafc0d1fc85f7a (diff)
e1000: Use hw, er32, and ew32
Use struct e1000_hw *hw = adapter->hw; where necessary Change macros E1000_READ_REG and E1000_WRITE_REG to er32 and ew32 Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/e1000/e1000_hw.c')
-rw-r--r--drivers/net/e1000/e1000_hw.c762
1 files changed, 381 insertions, 381 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index d6c272ae437f..5d3c2bd7b612 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -520,7 +520,7 @@ void e1000_set_media_type(struct e1000_hw *hw)
520 hw->media_type = e1000_media_type_copper; 520 hw->media_type = e1000_media_type_copper;
521 break; 521 break;
522 default: 522 default:
523 status = E1000_READ_REG(hw, STATUS); 523 status = er32(STATUS);
524 if (status & E1000_STATUS_TBIMODE) { 524 if (status & E1000_STATUS_TBIMODE) {
525 hw->media_type = e1000_media_type_fiber; 525 hw->media_type = e1000_media_type_fiber;
526 /* tbi_compatibility not valid on fiber */ 526 /* tbi_compatibility not valid on fiber */
@@ -568,15 +568,15 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
568 568
569 /* Clear interrupt mask to stop board from generating interrupts */ 569 /* Clear interrupt mask to stop board from generating interrupts */
570 DEBUGOUT("Masking off all interrupts\n"); 570 DEBUGOUT("Masking off all interrupts\n");
571 E1000_WRITE_REG(hw, IMC, 0xffffffff); 571 ew32(IMC, 0xffffffff);
572 572
573 /* Disable the Transmit and Receive units. Then delay to allow 573 /* Disable the Transmit and Receive units. Then delay to allow
574 * any pending transactions to complete before we hit the MAC with 574 * any pending transactions to complete before we hit the MAC with
575 * the global reset. 575 * the global reset.
576 */ 576 */
577 E1000_WRITE_REG(hw, RCTL, 0); 577 ew32(RCTL, 0);
578 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 578 ew32(TCTL, E1000_TCTL_PSP);
579 E1000_WRITE_FLUSH(hw); 579 E1000_WRITE_FLUSH();
580 580
581 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 581 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
582 hw->tbi_compatibility_on = false; 582 hw->tbi_compatibility_on = false;
@@ -586,11 +586,11 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
586 */ 586 */
587 msleep(10); 587 msleep(10);
588 588
589 ctrl = E1000_READ_REG(hw, CTRL); 589 ctrl = er32(CTRL);
590 590
591 /* Must reset the PHY before resetting the MAC */ 591 /* Must reset the PHY before resetting the MAC */
592 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 592 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
593 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 593 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
594 msleep(5); 594 msleep(5);
595 } 595 }
596 596
@@ -599,12 +599,12 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
599 if (hw->mac_type == e1000_82573) { 599 if (hw->mac_type == e1000_82573) {
600 timeout = 10; 600 timeout = 10;
601 601
602 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 602 extcnf_ctrl = er32(EXTCNF_CTRL);
603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
604 604
605 do { 605 do {
606 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 606 ew32(EXTCNF_CTRL, extcnf_ctrl);
607 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 607 extcnf_ctrl = er32(EXTCNF_CTRL);
608 608
609 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 609 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
610 break; 610 break;
@@ -619,9 +619,9 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
619 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 619 /* Workaround for ICH8 bit corruption issue in FIFO memory */
620 if (hw->mac_type == e1000_ich8lan) { 620 if (hw->mac_type == e1000_ich8lan) {
621 /* Set Tx and Rx buffer allocation to 8k apiece. */ 621 /* Set Tx and Rx buffer allocation to 8k apiece. */
622 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 622 ew32(PBA, E1000_PBA_8K);
623 /* Set Packet Buffer Size to 16k. */ 623 /* Set Packet Buffer Size to 16k. */
624 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 624 ew32(PBS, E1000_PBS_16K);
625 } 625 }
626 626
627 /* Issue a global reset to the MAC. This will reset the chip's 627 /* Issue a global reset to the MAC. This will reset the chip's
@@ -645,7 +645,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
645 case e1000_82545_rev_3: 645 case e1000_82545_rev_3:
646 case e1000_82546_rev_3: 646 case e1000_82546_rev_3:
647 /* Reset is performed on a shadow of the control register */ 647 /* Reset is performed on a shadow of the control register */
648 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 648 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
649 break; 649 break;
650 case e1000_ich8lan: 650 case e1000_ich8lan:
651 if (!hw->phy_reset_disable && 651 if (!hw->phy_reset_disable &&
@@ -658,11 +658,11 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
658 } 658 }
659 659
660 e1000_get_software_flag(hw); 660 e1000_get_software_flag(hw);
661 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 661 ew32(CTRL, (ctrl | E1000_CTRL_RST));
662 msleep(5); 662 msleep(5);
663 break; 663 break;
664 default: 664 default:
665 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 665 ew32(CTRL, (ctrl | E1000_CTRL_RST));
666 break; 666 break;
667 } 667 }
668 668
@@ -677,10 +677,10 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
677 case e1000_82544: 677 case e1000_82544:
678 /* Wait for reset to complete */ 678 /* Wait for reset to complete */
679 udelay(10); 679 udelay(10);
680 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 680 ctrl_ext = er32(CTRL_EXT);
681 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 681 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
682 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 682 ew32(CTRL_EXT, ctrl_ext);
683 E1000_WRITE_FLUSH(hw); 683 E1000_WRITE_FLUSH();
684 /* Wait for EEPROM reload */ 684 /* Wait for EEPROM reload */
685 msleep(2); 685 msleep(2);
686 break; 686 break;
@@ -694,10 +694,10 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
694 case e1000_82573: 694 case e1000_82573:
695 if (!e1000_is_onboard_nvm_eeprom(hw)) { 695 if (!e1000_is_onboard_nvm_eeprom(hw)) {
696 udelay(10); 696 udelay(10);
697 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 697 ctrl_ext = er32(CTRL_EXT);
698 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 698 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
699 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 699 ew32(CTRL_EXT, ctrl_ext);
700 E1000_WRITE_FLUSH(hw); 700 E1000_WRITE_FLUSH();
701 } 701 }
702 /* fall through */ 702 /* fall through */
703 default: 703 default:
@@ -710,27 +710,27 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
710 710
711 /* Disable HW ARPs on ASF enabled adapters */ 711 /* Disable HW ARPs on ASF enabled adapters */
712 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { 712 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
713 manc = E1000_READ_REG(hw, MANC); 713 manc = er32(MANC);
714 manc &= ~(E1000_MANC_ARP_EN); 714 manc &= ~(E1000_MANC_ARP_EN);
715 E1000_WRITE_REG(hw, MANC, manc); 715 ew32(MANC, manc);
716 } 716 }
717 717
718 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 718 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
719 e1000_phy_init_script(hw); 719 e1000_phy_init_script(hw);
720 720
721 /* Configure activity LED after PHY reset */ 721 /* Configure activity LED after PHY reset */
722 led_ctrl = E1000_READ_REG(hw, LEDCTL); 722 led_ctrl = er32(LEDCTL);
723 led_ctrl &= IGP_ACTIVITY_LED_MASK; 723 led_ctrl &= IGP_ACTIVITY_LED_MASK;
724 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 724 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
725 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 725 ew32(LEDCTL, led_ctrl);
726 } 726 }
727 727
728 /* Clear interrupt mask to stop board from generating interrupts */ 728 /* Clear interrupt mask to stop board from generating interrupts */
729 DEBUGOUT("Masking off all interrupts\n"); 729 DEBUGOUT("Masking off all interrupts\n");
730 E1000_WRITE_REG(hw, IMC, 0xffffffff); 730 ew32(IMC, 0xffffffff);
731 731
732 /* Clear any pending interrupt events. */ 732 /* Clear any pending interrupt events. */
733 icr = E1000_READ_REG(hw, ICR); 733 icr = er32(ICR);
734 734
735 /* If MWI was previously enabled, reenable it. */ 735 /* If MWI was previously enabled, reenable it. */
736 if (hw->mac_type == e1000_82542_rev2_0) { 736 if (hw->mac_type == e1000_82542_rev2_0) {
@@ -739,9 +739,9 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
739 } 739 }
740 740
741 if (hw->mac_type == e1000_ich8lan) { 741 if (hw->mac_type == e1000_ich8lan) {
742 u32 kab = E1000_READ_REG(hw, KABGTXD); 742 u32 kab = er32(KABGTXD);
743 kab |= E1000_KABGTXD_BGSQLBIAS; 743 kab |= E1000_KABGTXD_BGSQLBIAS;
744 E1000_WRITE_REG(hw, KABGTXD, kab); 744 ew32(KABGTXD, kab);
745 } 745 }
746 746
747 return E1000_SUCCESS; 747 return E1000_SUCCESS;
@@ -766,22 +766,22 @@ static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
766 u32 reg_txdctl, reg_txdctl1; 766 u32 reg_txdctl, reg_txdctl1;
767 767
768 /* link autonegotiation/sync workarounds */ 768 /* link autonegotiation/sync workarounds */
769 reg_tarc0 = E1000_READ_REG(hw, TARC0); 769 reg_tarc0 = er32(TARC0);
770 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); 770 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
771 771
772 /* Enable not-done TX descriptor counting */ 772 /* Enable not-done TX descriptor counting */
773 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 773 reg_txdctl = er32(TXDCTL);
774 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; 774 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
775 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 775 ew32(TXDCTL, reg_txdctl);
776 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 776 reg_txdctl1 = er32(TXDCTL1);
777 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; 777 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
778 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 778 ew32(TXDCTL1, reg_txdctl1);
779 779
780 switch (hw->mac_type) { 780 switch (hw->mac_type) {
781 case e1000_82571: 781 case e1000_82571:
782 case e1000_82572: 782 case e1000_82572:
783 /* Clear PHY TX compatible mode bits */ 783 /* Clear PHY TX compatible mode bits */
784 reg_tarc1 = E1000_READ_REG(hw, TARC1); 784 reg_tarc1 = er32(TARC1);
785 reg_tarc1 &= ~((1 << 30)|(1 << 29)); 785 reg_tarc1 &= ~((1 << 30)|(1 << 29));
786 786
787 /* link autonegotiation/sync workarounds */ 787 /* link autonegotiation/sync workarounds */
@@ -791,25 +791,25 @@ static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
791 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); 791 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
792 792
793 /* Multiple read bit is reversed polarity */ 793 /* Multiple read bit is reversed polarity */
794 reg_tctl = E1000_READ_REG(hw, TCTL); 794 reg_tctl = er32(TCTL);
795 if (reg_tctl & E1000_TCTL_MULR) 795 if (reg_tctl & E1000_TCTL_MULR)
796 reg_tarc1 &= ~(1 << 28); 796 reg_tarc1 &= ~(1 << 28);
797 else 797 else
798 reg_tarc1 |= (1 << 28); 798 reg_tarc1 |= (1 << 28);
799 799
800 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 800 ew32(TARC1, reg_tarc1);
801 break; 801 break;
802 case e1000_82573: 802 case e1000_82573:
803 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 803 reg_ctrl_ext = er32(CTRL_EXT);
804 reg_ctrl_ext &= ~(1 << 23); 804 reg_ctrl_ext &= ~(1 << 23);
805 reg_ctrl_ext |= (1 << 22); 805 reg_ctrl_ext |= (1 << 22);
806 806
807 /* TX byte count fix */ 807 /* TX byte count fix */
808 reg_ctrl = E1000_READ_REG(hw, CTRL); 808 reg_ctrl = er32(CTRL);
809 reg_ctrl &= ~(1 << 29); 809 reg_ctrl &= ~(1 << 29);
810 810
811 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 811 ew32(CTRL_EXT, reg_ctrl_ext);
812 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 812 ew32(CTRL, reg_ctrl);
813 break; 813 break;
814 case e1000_80003es2lan: 814 case e1000_80003es2lan:
815 /* improve small packet performace for fiber/serdes */ 815 /* improve small packet performace for fiber/serdes */
@@ -819,14 +819,14 @@ static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
819 } 819 }
820 820
821 /* Multiple read bit is reversed polarity */ 821 /* Multiple read bit is reversed polarity */
822 reg_tctl = E1000_READ_REG(hw, TCTL); 822 reg_tctl = er32(TCTL);
823 reg_tarc1 = E1000_READ_REG(hw, TARC1); 823 reg_tarc1 = er32(TARC1);
824 if (reg_tctl & E1000_TCTL_MULR) 824 if (reg_tctl & E1000_TCTL_MULR)
825 reg_tarc1 &= ~(1 << 28); 825 reg_tarc1 &= ~(1 << 28);
826 else 826 else
827 reg_tarc1 |= (1 << 28); 827 reg_tarc1 |= (1 << 28);
828 828
829 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 829 ew32(TARC1, reg_tarc1);
830 break; 830 break;
831 case e1000_ich8lan: 831 case e1000_ich8lan:
832 /* Reduce concurrent DMA requests to 3 from 4 */ 832 /* Reduce concurrent DMA requests to 3 from 4 */
@@ -835,16 +835,16 @@ static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
835 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) 835 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
836 reg_tarc0 |= ((1 << 29)|(1 << 28)); 836 reg_tarc0 |= ((1 << 29)|(1 << 28));
837 837
838 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 838 reg_ctrl_ext = er32(CTRL_EXT);
839 reg_ctrl_ext |= (1 << 22); 839 reg_ctrl_ext |= (1 << 22);
840 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 840 ew32(CTRL_EXT, reg_ctrl_ext);
841 841
842 /* workaround TX hang with TSO=on */ 842 /* workaround TX hang with TSO=on */
843 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); 843 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
844 844
845 /* Multiple read bit is reversed polarity */ 845 /* Multiple read bit is reversed polarity */
846 reg_tctl = E1000_READ_REG(hw, TCTL); 846 reg_tctl = er32(TCTL);
847 reg_tarc1 = E1000_READ_REG(hw, TARC1); 847 reg_tarc1 = er32(TARC1);
848 if (reg_tctl & E1000_TCTL_MULR) 848 if (reg_tctl & E1000_TCTL_MULR)
849 reg_tarc1 &= ~(1 << 28); 849 reg_tarc1 &= ~(1 << 28);
850 else 850 else
@@ -853,13 +853,13 @@ static void e1000_initialize_hardware_bits(struct e1000_hw *hw)
853 /* workaround TX hang with TSO=on */ 853 /* workaround TX hang with TSO=on */
854 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); 854 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
855 855
856 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 856 ew32(TARC1, reg_tarc1);
857 break; 857 break;
858 default: 858 default:
859 break; 859 break;
860 } 860 }
861 861
862 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 862 ew32(TARC0, reg_tarc0);
863 } 863 }
864} 864}
865 865
@@ -890,9 +890,9 @@ s32 e1000_init_hw(struct e1000_hw *hw)
890 ((hw->revision_id < 3) || 890 ((hw->revision_id < 3) ||
891 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && 891 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
892 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { 892 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
893 reg_data = E1000_READ_REG(hw, STATUS); 893 reg_data = er32(STATUS);
894 reg_data &= ~0x80000000; 894 reg_data &= ~0x80000000;
895 E1000_WRITE_REG(hw, STATUS, reg_data); 895 ew32(STATUS, reg_data);
896 } 896 }
897 897
898 /* Initialize Identification LED */ 898 /* Initialize Identification LED */
@@ -913,7 +913,7 @@ s32 e1000_init_hw(struct e1000_hw *hw)
913 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ 913 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
914 if (hw->mac_type != e1000_ich8lan) { 914 if (hw->mac_type != e1000_ich8lan) {
915 if (hw->mac_type < e1000_82545_rev_3) 915 if (hw->mac_type < e1000_82545_rev_3)
916 E1000_WRITE_REG(hw, VET, 0); 916 ew32(VET, 0);
917 e1000_clear_vfta(hw); 917 e1000_clear_vfta(hw);
918 } 918 }
919 919
@@ -921,8 +921,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)
921 if (hw->mac_type == e1000_82542_rev2_0) { 921 if (hw->mac_type == e1000_82542_rev2_0) {
922 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 922 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
923 e1000_pci_clear_mwi(hw); 923 e1000_pci_clear_mwi(hw);
924 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 924 ew32(RCTL, E1000_RCTL_RST);
925 E1000_WRITE_FLUSH(hw); 925 E1000_WRITE_FLUSH();
926 msleep(5); 926 msleep(5);
927 } 927 }
928 928
@@ -933,8 +933,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)
933 933
934 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 934 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
935 if (hw->mac_type == e1000_82542_rev2_0) { 935 if (hw->mac_type == e1000_82542_rev2_0) {
936 E1000_WRITE_REG(hw, RCTL, 0); 936 ew32(RCTL, 0);
937 E1000_WRITE_FLUSH(hw); 937 E1000_WRITE_FLUSH();
938 msleep(1); 938 msleep(1);
939 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 939 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
940 e1000_pci_set_mwi(hw); 940 e1000_pci_set_mwi(hw);
@@ -949,7 +949,7 @@ s32 e1000_init_hw(struct e1000_hw *hw)
949 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 949 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
950 /* use write flush to prevent Memory Write Block (MWB) from 950 /* use write flush to prevent Memory Write Block (MWB) from
951 * occuring when accessing our register space */ 951 * occuring when accessing our register space */
952 E1000_WRITE_FLUSH(hw); 952 E1000_WRITE_FLUSH();
953 } 953 }
954 954
955 /* Set the PCI priority bit correctly in the CTRL register. This 955 /* Set the PCI priority bit correctly in the CTRL register. This
@@ -958,8 +958,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)
958 * 82542 and 82543 silicon. 958 * 82542 and 82543 silicon.
959 */ 959 */
960 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 960 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
961 ctrl = E1000_READ_REG(hw, CTRL); 961 ctrl = er32(CTRL);
962 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 962 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
963 } 963 }
964 964
965 switch (hw->mac_type) { 965 switch (hw->mac_type) {
@@ -982,9 +982,9 @@ s32 e1000_init_hw(struct e1000_hw *hw)
982 982
983 /* Set the transmit descriptor write-back policy */ 983 /* Set the transmit descriptor write-back policy */
984 if (hw->mac_type > e1000_82544) { 984 if (hw->mac_type > e1000_82544) {
985 ctrl = E1000_READ_REG(hw, TXDCTL); 985 ctrl = er32(TXDCTL);
986 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 986 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
987 E1000_WRITE_REG(hw, TXDCTL, ctrl); 987 ew32(TXDCTL, ctrl);
988 } 988 }
989 989
990 if (hw->mac_type == e1000_82573) { 990 if (hw->mac_type == e1000_82573) {
@@ -996,21 +996,21 @@ s32 e1000_init_hw(struct e1000_hw *hw)
996 break; 996 break;
997 case e1000_80003es2lan: 997 case e1000_80003es2lan:
998 /* Enable retransmit on late collisions */ 998 /* Enable retransmit on late collisions */
999 reg_data = E1000_READ_REG(hw, TCTL); 999 reg_data = er32(TCTL);
1000 reg_data |= E1000_TCTL_RTLC; 1000 reg_data |= E1000_TCTL_RTLC;
1001 E1000_WRITE_REG(hw, TCTL, reg_data); 1001 ew32(TCTL, reg_data);
1002 1002
1003 /* Configure Gigabit Carry Extend Padding */ 1003 /* Configure Gigabit Carry Extend Padding */
1004 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1004 reg_data = er32(TCTL_EXT);
1005 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1005 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1006 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1006 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1007 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1007 ew32(TCTL_EXT, reg_data);
1008 1008
1009 /* Configure Transmit Inter-Packet Gap */ 1009 /* Configure Transmit Inter-Packet Gap */
1010 reg_data = E1000_READ_REG(hw, TIPG); 1010 reg_data = er32(TIPG);
1011 reg_data &= ~E1000_TIPG_IPGT_MASK; 1011 reg_data &= ~E1000_TIPG_IPGT_MASK;
1012 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1012 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1013 E1000_WRITE_REG(hw, TIPG, reg_data); 1013 ew32(TIPG, reg_data);
1014 1014
1015 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1015 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1016 reg_data &= ~0x00100000; 1016 reg_data &= ~0x00100000;
@@ -1019,17 +1019,17 @@ s32 e1000_init_hw(struct e1000_hw *hw)
1019 case e1000_82571: 1019 case e1000_82571:
1020 case e1000_82572: 1020 case e1000_82572:
1021 case e1000_ich8lan: 1021 case e1000_ich8lan:
1022 ctrl = E1000_READ_REG(hw, TXDCTL1); 1022 ctrl = er32(TXDCTL1);
1023 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 1023 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1024 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1024 ew32(TXDCTL1, ctrl);
1025 break; 1025 break;
1026 } 1026 }
1027 1027
1028 1028
1029 if (hw->mac_type == e1000_82573) { 1029 if (hw->mac_type == e1000_82573) {
1030 u32 gcr = E1000_READ_REG(hw, GCR); 1030 u32 gcr = er32(GCR);
1031 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1031 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1032 E1000_WRITE_REG(hw, GCR, gcr); 1032 ew32(GCR, gcr);
1033 } 1033 }
1034 1034
1035 /* Clear all of the statistics registers (clear on read). It is 1035 /* Clear all of the statistics registers (clear on read). It is
@@ -1046,11 +1046,11 @@ s32 e1000_init_hw(struct e1000_hw *hw)
1046 1046
1047 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1047 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1048 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1048 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1049 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1049 ctrl_ext = er32(CTRL_EXT);
1050 /* Relaxed ordering must be disabled to avoid a parity 1050 /* Relaxed ordering must be disabled to avoid a parity
1051 * error crash in a PCI slot. */ 1051 * error crash in a PCI slot. */
1052 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1052 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1053 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1053 ew32(CTRL_EXT, ctrl_ext);
1054 } 1054 }
1055 1055
1056 return ret_val; 1056 return ret_val;
@@ -1181,7 +1181,7 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1181 } 1181 }
1182 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1182 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1183 SWDPIO__EXT_SHIFT); 1183 SWDPIO__EXT_SHIFT);
1184 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1184 ew32(CTRL_EXT, ctrl_ext);
1185 } 1185 }
1186 1186
1187 /* Call the necessary subroutine to configure the link. */ 1187 /* Call the necessary subroutine to configure the link. */
@@ -1198,12 +1198,12 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1198 1198
1199 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ 1199 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1200 if (hw->mac_type != e1000_ich8lan) { 1200 if (hw->mac_type != e1000_ich8lan) {
1201 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1201 ew32(FCT, FLOW_CONTROL_TYPE);
1202 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1202 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1203 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1203 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
1204 } 1204 }
1205 1205
1206 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1206 ew32(FCTTV, hw->fc_pause_time);
1207 1207
1208 /* Set the flow control receive threshold registers. Normally, 1208 /* Set the flow control receive threshold registers. Normally,
1209 * these registers will be set to a default threshold that may be 1209 * these registers will be set to a default threshold that may be
@@ -1212,18 +1212,18 @@ s32 e1000_setup_link(struct e1000_hw *hw)
1212 * registers will be set to 0. 1212 * registers will be set to 0.
1213 */ 1213 */
1214 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1214 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1215 E1000_WRITE_REG(hw, FCRTL, 0); 1215 ew32(FCRTL, 0);
1216 E1000_WRITE_REG(hw, FCRTH, 0); 1216 ew32(FCRTH, 0);
1217 } else { 1217 } else {
1218 /* We need to set up the Receive Threshold high and low water marks 1218 /* We need to set up the Receive Threshold high and low water marks
1219 * as well as (optionally) enabling the transmission of XON frames. 1219 * as well as (optionally) enabling the transmission of XON frames.
1220 */ 1220 */
1221 if (hw->fc_send_xon) { 1221 if (hw->fc_send_xon) {
1222 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 1222 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1223 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1223 ew32(FCRTH, hw->fc_high_water);
1224 } else { 1224 } else {
1225 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1225 ew32(FCRTL, hw->fc_low_water);
1226 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1226 ew32(FCRTH, hw->fc_high_water);
1227 } 1227 }
1228 } 1228 }
1229 return ret_val; 1229 return ret_val;
@@ -1255,7 +1255,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1255 * loopback mode is disabled during initialization. 1255 * loopback mode is disabled during initialization.
1256 */ 1256 */
1257 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) 1257 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1258 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1258 ew32(SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1259 1259
1260 /* On adapters with a MAC newer than 82544, SWDP 1 will be 1260 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1261 * set when the optics detect a signal. On older adapters, it will be 1261 * set when the optics detect a signal. On older adapters, it will be
@@ -1263,7 +1263,7 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1263 * If we're on serdes media, adjust the output amplitude to value 1263 * If we're on serdes media, adjust the output amplitude to value
1264 * set in the EEPROM. 1264 * set in the EEPROM.
1265 */ 1265 */
1266 ctrl = E1000_READ_REG(hw, CTRL); 1266 ctrl = er32(CTRL);
1267 if (hw->media_type == e1000_media_type_fiber) 1267 if (hw->media_type == e1000_media_type_fiber)
1268 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 1268 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1269 1269
@@ -1334,9 +1334,9 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1334 */ 1334 */
1335 DEBUGOUT("Auto-negotiation enabled\n"); 1335 DEBUGOUT("Auto-negotiation enabled\n");
1336 1336
1337 E1000_WRITE_REG(hw, TXCW, txcw); 1337 ew32(TXCW, txcw);
1338 E1000_WRITE_REG(hw, CTRL, ctrl); 1338 ew32(CTRL, ctrl);
1339 E1000_WRITE_FLUSH(hw); 1339 E1000_WRITE_FLUSH();
1340 1340
1341 hw->txcw = txcw; 1341 hw->txcw = txcw;
1342 msleep(1); 1342 msleep(1);
@@ -1348,11 +1348,11 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1348 * For internal serdes, we just assume a signal is present, then poll. 1348 * For internal serdes, we just assume a signal is present, then poll.
1349 */ 1349 */
1350 if (hw->media_type == e1000_media_type_internal_serdes || 1350 if (hw->media_type == e1000_media_type_internal_serdes ||
1351 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1351 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1352 DEBUGOUT("Looking for Link\n"); 1352 DEBUGOUT("Looking for Link\n");
1353 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1353 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1354 msleep(10); 1354 msleep(10);
1355 status = E1000_READ_REG(hw, STATUS); 1355 status = er32(STATUS);
1356 if (status & E1000_STATUS_LU) break; 1356 if (status & E1000_STATUS_LU) break;
1357 } 1357 }
1358 if (i == (LINK_UP_TIMEOUT / 10)) { 1358 if (i == (LINK_UP_TIMEOUT / 10)) {
@@ -1392,7 +1392,7 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1392 1392
1393 DEBUGFUNC("e1000_copper_link_preconfig"); 1393 DEBUGFUNC("e1000_copper_link_preconfig");
1394 1394
1395 ctrl = E1000_READ_REG(hw, CTRL); 1395 ctrl = er32(CTRL);
1396 /* With 82543, we need to force speed and duplex on the MAC equal to what 1396 /* With 82543, we need to force speed and duplex on the MAC equal to what
1397 * the PHY speed and duplex configuration is. In addition, we need to 1397 * the PHY speed and duplex configuration is. In addition, we need to
1398 * perform a hardware reset on the PHY to take it out of reset. 1398 * perform a hardware reset on the PHY to take it out of reset.
@@ -1400,10 +1400,10 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1400 if (hw->mac_type > e1000_82543) { 1400 if (hw->mac_type > e1000_82543) {
1401 ctrl |= E1000_CTRL_SLU; 1401 ctrl |= E1000_CTRL_SLU;
1402 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1402 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1403 E1000_WRITE_REG(hw, CTRL, ctrl); 1403 ew32(CTRL, ctrl);
1404 } else { 1404 } else {
1405 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1405 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1406 E1000_WRITE_REG(hw, CTRL, ctrl); 1406 ew32(CTRL, ctrl);
1407 ret_val = e1000_phy_hw_reset(hw); 1407 ret_val = e1000_phy_hw_reset(hw);
1408 if (ret_val) 1408 if (ret_val)
1409 return ret_val; 1409 return ret_val;
@@ -1464,10 +1464,10 @@ static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1464 msleep(15); 1464 msleep(15);
1465 if (hw->mac_type != e1000_ich8lan) { 1465 if (hw->mac_type != e1000_ich8lan) {
1466 /* Configure activity LED after PHY reset */ 1466 /* Configure activity LED after PHY reset */
1467 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1467 led_ctrl = er32(LEDCTL);
1468 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1468 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1469 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1469 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1470 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1470 ew32(LEDCTL, led_ctrl);
1471 } 1471 }
1472 1472
1473 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1473 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
@@ -1680,9 +1680,9 @@ static s32 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1680 if (ret_val) 1680 if (ret_val)
1681 return ret_val; 1681 return ret_val;
1682 1682
1683 reg_data = E1000_READ_REG(hw, CTRL_EXT); 1683 reg_data = er32(CTRL_EXT);
1684 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1684 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1685 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 1685 ew32(CTRL_EXT, reg_data);
1686 1686
1687 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1687 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1688 &phy_data); 1688 &phy_data);
@@ -2074,10 +2074,10 @@ static s32 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, u16 duplex)
2074 return ret_val; 2074 return ret_val;
2075 2075
2076 /* Configure Transmit Inter-Packet Gap */ 2076 /* Configure Transmit Inter-Packet Gap */
2077 tipg = E1000_READ_REG(hw, TIPG); 2077 tipg = er32(TIPG);
2078 tipg &= ~E1000_TIPG_IPGT_MASK; 2078 tipg &= ~E1000_TIPG_IPGT_MASK;
2079 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2079 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2080 E1000_WRITE_REG(hw, TIPG, tipg); 2080 ew32(TIPG, tipg);
2081 2081
2082 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 2082 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2083 2083
@@ -2109,10 +2109,10 @@ static s32 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2109 return ret_val; 2109 return ret_val;
2110 2110
2111 /* Configure Transmit Inter-Packet Gap */ 2111 /* Configure Transmit Inter-Packet Gap */
2112 tipg = E1000_READ_REG(hw, TIPG); 2112 tipg = er32(TIPG);
2113 tipg &= ~E1000_TIPG_IPGT_MASK; 2113 tipg &= ~E1000_TIPG_IPGT_MASK;
2114 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2114 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2115 E1000_WRITE_REG(hw, TIPG, tipg); 2115 ew32(TIPG, tipg);
2116 2116
2117 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data); 2117 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2118 2118
@@ -2295,7 +2295,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2295 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2295 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2296 2296
2297 /* Read the Device Control Register. */ 2297 /* Read the Device Control Register. */
2298 ctrl = E1000_READ_REG(hw, CTRL); 2298 ctrl = er32(CTRL);
2299 2299
2300 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2300 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2301 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2301 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
@@ -2350,7 +2350,7 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2350 e1000_config_collision_dist(hw); 2350 e1000_config_collision_dist(hw);
2351 2351
2352 /* Write the configured values back to the Device Control Reg. */ 2352 /* Write the configured values back to the Device Control Reg. */
2353 E1000_WRITE_REG(hw, CTRL, ctrl); 2353 ew32(CTRL, ctrl);
2354 2354
2355 if ((hw->phy_type == e1000_phy_m88) || 2355 if ((hw->phy_type == e1000_phy_m88) ||
2356 (hw->phy_type == e1000_phy_gg82563)) { 2356 (hw->phy_type == e1000_phy_gg82563)) {
@@ -2539,13 +2539,13 @@ void e1000_config_collision_dist(struct e1000_hw *hw)
2539 else 2539 else
2540 coll_dist = E1000_COLLISION_DISTANCE; 2540 coll_dist = E1000_COLLISION_DISTANCE;
2541 2541
2542 tctl = E1000_READ_REG(hw, TCTL); 2542 tctl = er32(TCTL);
2543 2543
2544 tctl &= ~E1000_TCTL_COLD; 2544 tctl &= ~E1000_TCTL_COLD;
2545 tctl |= coll_dist << E1000_COLD_SHIFT; 2545 tctl |= coll_dist << E1000_COLD_SHIFT;
2546 2546
2547 E1000_WRITE_REG(hw, TCTL, tctl); 2547 ew32(TCTL, tctl);
2548 E1000_WRITE_FLUSH(hw); 2548 E1000_WRITE_FLUSH();
2549} 2549}
2550 2550
2551/****************************************************************************** 2551/******************************************************************************
@@ -2573,7 +2573,7 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2573 /* Read the Device Control Register and set the bits to Force Speed 2573 /* Read the Device Control Register and set the bits to Force Speed
2574 * and Duplex. 2574 * and Duplex.
2575 */ 2575 */
2576 ctrl = E1000_READ_REG(hw, CTRL); 2576 ctrl = er32(CTRL);
2577 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2577 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2578 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 2578 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2579 2579
@@ -2600,7 +2600,7 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
2600 ctrl |= E1000_CTRL_SPD_100; 2600 ctrl |= E1000_CTRL_SPD_100;
2601 2601
2602 /* Write the configured values back to the Device Control Reg. */ 2602 /* Write the configured values back to the Device Control Reg. */
2603 E1000_WRITE_REG(hw, CTRL, ctrl); 2603 ew32(CTRL, ctrl);
2604 return E1000_SUCCESS; 2604 return E1000_SUCCESS;
2605} 2605}
2606 2606
@@ -2622,7 +2622,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw)
2622 DEBUGFUNC("e1000_force_mac_fc"); 2622 DEBUGFUNC("e1000_force_mac_fc");
2623 2623
2624 /* Get the current configuration of the Device Control Register */ 2624 /* Get the current configuration of the Device Control Register */
2625 ctrl = E1000_READ_REG(hw, CTRL); 2625 ctrl = er32(CTRL);
2626 2626
2627 /* Because we didn't get link via the internal auto-negotiation 2627 /* Because we didn't get link via the internal auto-negotiation
2628 * mechanism (we either forced link or we got link via PHY 2628 * mechanism (we either forced link or we got link via PHY
@@ -2666,7 +2666,7 @@ s32 e1000_force_mac_fc(struct e1000_hw *hw)
2666 if (hw->mac_type == e1000_82542_rev2_0) 2666 if (hw->mac_type == e1000_82542_rev2_0)
2667 ctrl &= (~E1000_CTRL_TFCE); 2667 ctrl &= (~E1000_CTRL_TFCE);
2668 2668
2669 E1000_WRITE_REG(hw, CTRL, ctrl); 2669 ew32(CTRL, ctrl);
2670 return E1000_SUCCESS; 2670 return E1000_SUCCESS;
2671} 2671}
2672 2672
@@ -2898,8 +2898,8 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2898 2898
2899 DEBUGFUNC("e1000_check_for_link"); 2899 DEBUGFUNC("e1000_check_for_link");
2900 2900
2901 ctrl = E1000_READ_REG(hw, CTRL); 2901 ctrl = er32(CTRL);
2902 status = E1000_READ_REG(hw, STATUS); 2902 status = er32(STATUS);
2903 2903
2904 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2904 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2905 * set when the optics detect a signal. On older adapters, it will be 2905 * set when the optics detect a signal. On older adapters, it will be
@@ -2907,7 +2907,7 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2907 */ 2907 */
2908 if ((hw->media_type == e1000_media_type_fiber) || 2908 if ((hw->media_type == e1000_media_type_fiber) ||
2909 (hw->media_type == e1000_media_type_internal_serdes)) { 2909 (hw->media_type == e1000_media_type_internal_serdes)) {
2910 rxcw = E1000_READ_REG(hw, RXCW); 2910 rxcw = er32(RXCW);
2911 2911
2912 if (hw->media_type == e1000_media_type_fiber) { 2912 if (hw->media_type == e1000_media_type_fiber) {
2913 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2913 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
@@ -2953,11 +2953,11 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
2953 (!hw->autoneg) && 2953 (!hw->autoneg) &&
2954 (hw->forced_speed_duplex == e1000_10_full || 2954 (hw->forced_speed_duplex == e1000_10_full ||
2955 hw->forced_speed_duplex == e1000_10_half)) { 2955 hw->forced_speed_duplex == e1000_10_half)) {
2956 E1000_WRITE_REG(hw, IMC, 0xffffffff); 2956 ew32(IMC, 0xffffffff);
2957 ret_val = e1000_polarity_reversal_workaround(hw); 2957 ret_val = e1000_polarity_reversal_workaround(hw);
2958 icr = E1000_READ_REG(hw, ICR); 2958 icr = er32(ICR);
2959 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); 2959 ew32(ICS, (icr & ~E1000_ICS_LSC));
2960 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 2960 ew32(IMS, IMS_ENABLE_MASK);
2961 } 2961 }
2962 2962
2963 } else { 2963 } else {
@@ -3022,9 +3022,9 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3022 */ 3022 */
3023 if (hw->tbi_compatibility_on) { 3023 if (hw->tbi_compatibility_on) {
3024 /* If we previously were in the mode, turn it off. */ 3024 /* If we previously were in the mode, turn it off. */
3025 rctl = E1000_READ_REG(hw, RCTL); 3025 rctl = er32(RCTL);
3026 rctl &= ~E1000_RCTL_SBP; 3026 rctl &= ~E1000_RCTL_SBP;
3027 E1000_WRITE_REG(hw, RCTL, rctl); 3027 ew32(RCTL, rctl);
3028 hw->tbi_compatibility_on = false; 3028 hw->tbi_compatibility_on = false;
3029 } 3029 }
3030 } else { 3030 } else {
@@ -3035,9 +3035,9 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3035 */ 3035 */
3036 if (!hw->tbi_compatibility_on) { 3036 if (!hw->tbi_compatibility_on) {
3037 hw->tbi_compatibility_on = true; 3037 hw->tbi_compatibility_on = true;
3038 rctl = E1000_READ_REG(hw, RCTL); 3038 rctl = er32(RCTL);
3039 rctl |= E1000_RCTL_SBP; 3039 rctl |= E1000_RCTL_SBP;
3040 E1000_WRITE_REG(hw, RCTL, rctl); 3040 ew32(RCTL, rctl);
3041 } 3041 }
3042 } 3042 }
3043 } 3043 }
@@ -3061,12 +3061,12 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3061 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3061 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3062 3062
3063 /* Disable auto-negotiation in the TXCW register */ 3063 /* Disable auto-negotiation in the TXCW register */
3064 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3064 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3065 3065
3066 /* Force link-up and also force full-duplex. */ 3066 /* Force link-up and also force full-duplex. */
3067 ctrl = E1000_READ_REG(hw, CTRL); 3067 ctrl = er32(CTRL);
3068 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3068 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3069 E1000_WRITE_REG(hw, CTRL, ctrl); 3069 ew32(CTRL, ctrl);
3070 3070
3071 /* Configure Flow Control after forcing link up. */ 3071 /* Configure Flow Control after forcing link up. */
3072 ret_val = e1000_config_fc_after_link_up(hw); 3072 ret_val = e1000_config_fc_after_link_up(hw);
@@ -3084,8 +3084,8 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3084 (hw->media_type == e1000_media_type_internal_serdes)) && 3084 (hw->media_type == e1000_media_type_internal_serdes)) &&
3085 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3085 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3086 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3086 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3087 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3087 ew32(TXCW, hw->txcw);
3088 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3088 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
3089 3089
3090 hw->serdes_link_down = false; 3090 hw->serdes_link_down = false;
3091 } 3091 }
@@ -3093,10 +3093,10 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3093 * based on MAC synchronization for internal serdes media type. 3093 * based on MAC synchronization for internal serdes media type.
3094 */ 3094 */
3095 else if ((hw->media_type == e1000_media_type_internal_serdes) && 3095 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3096 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3096 !(E1000_TXCW_ANE & er32(TXCW))) {
3097 /* SYNCH bit and IV bit are sticky. */ 3097 /* SYNCH bit and IV bit are sticky. */
3098 udelay(10); 3098 udelay(10);
3099 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3099 if (E1000_RXCW_SYNCH & er32(RXCW)) {
3100 if (!(rxcw & E1000_RXCW_IV)) { 3100 if (!(rxcw & E1000_RXCW_IV)) {
3101 hw->serdes_link_down = false; 3101 hw->serdes_link_down = false;
3102 DEBUGOUT("SERDES: Link is up.\n"); 3102 DEBUGOUT("SERDES: Link is up.\n");
@@ -3107,8 +3107,8 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
3107 } 3107 }
3108 } 3108 }
3109 if ((hw->media_type == e1000_media_type_internal_serdes) && 3109 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3110 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3110 (E1000_TXCW_ANE & er32(TXCW))) {
3111 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); 3111 hw->serdes_link_down = !(E1000_STATUS_LU & er32(STATUS));
3112 } 3112 }
3113 return E1000_SUCCESS; 3113 return E1000_SUCCESS;
3114} 3114}
@@ -3129,7 +3129,7 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
3129 DEBUGFUNC("e1000_get_speed_and_duplex"); 3129 DEBUGFUNC("e1000_get_speed_and_duplex");
3130 3130
3131 if (hw->mac_type >= e1000_82543) { 3131 if (hw->mac_type >= e1000_82543) {
3132 status = E1000_READ_REG(hw, STATUS); 3132 status = er32(STATUS);
3133 if (status & E1000_STATUS_SPEED_1000) { 3133 if (status & E1000_STATUS_SPEED_1000) {
3134 *speed = SPEED_1000; 3134 *speed = SPEED_1000;
3135 DEBUGOUT("1000 Mbs, "); 3135 DEBUGOUT("1000 Mbs, ");
@@ -3238,8 +3238,8 @@ static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3238 /* Raise the clock input to the Management Data Clock (by setting the MDC 3238 /* Raise the clock input to the Management Data Clock (by setting the MDC
3239 * bit), and then delay 10 microseconds. 3239 * bit), and then delay 10 microseconds.
3240 */ 3240 */
3241 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 3241 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
3242 E1000_WRITE_FLUSH(hw); 3242 E1000_WRITE_FLUSH();
3243 udelay(10); 3243 udelay(10);
3244} 3244}
3245 3245
@@ -3254,8 +3254,8 @@ static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
3254 /* Lower the clock input to the Management Data Clock (by clearing the MDC 3254 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3255 * bit), and then delay 10 microseconds. 3255 * bit), and then delay 10 microseconds.
3256 */ 3256 */
3257 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 3257 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
3258 E1000_WRITE_FLUSH(hw); 3258 E1000_WRITE_FLUSH();
3259 udelay(10); 3259 udelay(10);
3260} 3260}
3261 3261
@@ -3280,7 +3280,7 @@ static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3280 mask = 0x01; 3280 mask = 0x01;
3281 mask <<= (count - 1); 3281 mask <<= (count - 1);
3282 3282
3283 ctrl = E1000_READ_REG(hw, CTRL); 3283 ctrl = er32(CTRL);
3284 3284
3285 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 3285 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3286 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 3286 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
@@ -3296,8 +3296,8 @@ static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
3296 else 3296 else
3297 ctrl &= ~E1000_CTRL_MDIO; 3297 ctrl &= ~E1000_CTRL_MDIO;
3298 3298
3299 E1000_WRITE_REG(hw, CTRL, ctrl); 3299 ew32(CTRL, ctrl);
3300 E1000_WRITE_FLUSH(hw); 3300 E1000_WRITE_FLUSH();
3301 3301
3302 udelay(10); 3302 udelay(10);
3303 3303
@@ -3328,14 +3328,14 @@ static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3328 * by raising the input to the Management Data Clock (setting the MDC bit), 3328 * by raising the input to the Management Data Clock (setting the MDC bit),
3329 * and then reading the value of the MDIO bit. 3329 * and then reading the value of the MDIO bit.
3330 */ 3330 */
3331 ctrl = E1000_READ_REG(hw, CTRL); 3331 ctrl = er32(CTRL);
3332 3332
3333 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 3333 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3334 ctrl &= ~E1000_CTRL_MDIO_DIR; 3334 ctrl &= ~E1000_CTRL_MDIO_DIR;
3335 ctrl &= ~E1000_CTRL_MDIO; 3335 ctrl &= ~E1000_CTRL_MDIO;
3336 3336
3337 E1000_WRITE_REG(hw, CTRL, ctrl); 3337 ew32(CTRL, ctrl);
3338 E1000_WRITE_FLUSH(hw); 3338 E1000_WRITE_FLUSH();
3339 3339
3340 /* Raise and Lower the clock before reading in the data. This accounts for 3340 /* Raise and Lower the clock before reading in the data. This accounts for
3341 * the turnaround bits. The first clock occurred when we clocked out the 3341 * the turnaround bits. The first clock occurred when we clocked out the
@@ -3347,7 +3347,7 @@ static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3347 for (data = 0, i = 0; i < 16; i++) { 3347 for (data = 0, i = 0; i < 16; i++) {
3348 data = data << 1; 3348 data = data << 1;
3349 e1000_raise_mdi_clk(hw, &ctrl); 3349 e1000_raise_mdi_clk(hw, &ctrl);
3350 ctrl = E1000_READ_REG(hw, CTRL); 3350 ctrl = er32(CTRL);
3351 /* Check to see if we shifted in a "1". */ 3351 /* Check to see if we shifted in a "1". */
3352 if (ctrl & E1000_CTRL_MDIO) 3352 if (ctrl & E1000_CTRL_MDIO)
3353 data |= 1; 3353 data |= 1;
@@ -3379,7 +3379,7 @@ static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3379 if (e1000_get_hw_eeprom_semaphore(hw)) 3379 if (e1000_get_hw_eeprom_semaphore(hw))
3380 return -E1000_ERR_SWFW_SYNC; 3380 return -E1000_ERR_SWFW_SYNC;
3381 3381
3382 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3382 swfw_sync = er32(SW_FW_SYNC);
3383 if (!(swfw_sync & (fwmask | swmask))) { 3383 if (!(swfw_sync & (fwmask | swmask))) {
3384 break; 3384 break;
3385 } 3385 }
@@ -3397,7 +3397,7 @@ static s32 e1000_swfw_sync_acquire(struct e1000_hw *hw, u16 mask)
3397 } 3397 }
3398 3398
3399 swfw_sync |= swmask; 3399 swfw_sync |= swmask;
3400 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3400 ew32(SW_FW_SYNC, swfw_sync);
3401 3401
3402 e1000_put_hw_eeprom_semaphore(hw); 3402 e1000_put_hw_eeprom_semaphore(hw);
3403 return E1000_SUCCESS; 3403 return E1000_SUCCESS;
@@ -3425,9 +3425,9 @@ static void e1000_swfw_sync_release(struct e1000_hw *hw, u16 mask)
3425 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 3425 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3426 /* empty */ 3426 /* empty */
3427 3427
3428 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 3428 swfw_sync = er32(SW_FW_SYNC);
3429 swfw_sync &= ~swmask; 3429 swfw_sync &= ~swmask;
3430 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 3430 ew32(SW_FW_SYNC, swfw_sync);
3431 3431
3432 e1000_put_hw_eeprom_semaphore(hw); 3432 e1000_put_hw_eeprom_semaphore(hw);
3433} 3433}
@@ -3446,7 +3446,7 @@ s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
3446 DEBUGFUNC("e1000_read_phy_reg"); 3446 DEBUGFUNC("e1000_read_phy_reg");
3447 3447
3448 if ((hw->mac_type == e1000_80003es2lan) && 3448 if ((hw->mac_type == e1000_80003es2lan) &&
3449 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3449 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3450 swfw = E1000_SWFW_PHY1_SM; 3450 swfw = E1000_SWFW_PHY1_SM;
3451 } else { 3451 } else {
3452 swfw = E1000_SWFW_PHY0_SM; 3452 swfw = E1000_SWFW_PHY0_SM;
@@ -3517,12 +3517,12 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3517 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3517 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3518 (E1000_MDIC_OP_READ)); 3518 (E1000_MDIC_OP_READ));
3519 3519
3520 E1000_WRITE_REG(hw, MDIC, mdic); 3520 ew32(MDIC, mdic);
3521 3521
3522 /* Poll the ready bit to see if the MDI read completed */ 3522 /* Poll the ready bit to see if the MDI read completed */
3523 for (i = 0; i < 64; i++) { 3523 for (i = 0; i < 64; i++) {
3524 udelay(50); 3524 udelay(50);
3525 mdic = E1000_READ_REG(hw, MDIC); 3525 mdic = er32(MDIC);
3526 if (mdic & E1000_MDIC_READY) break; 3526 if (mdic & E1000_MDIC_READY) break;
3527 } 3527 }
3528 if (!(mdic & E1000_MDIC_READY)) { 3528 if (!(mdic & E1000_MDIC_READY)) {
@@ -3581,7 +3581,7 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
3581 DEBUGFUNC("e1000_write_phy_reg"); 3581 DEBUGFUNC("e1000_write_phy_reg");
3582 3582
3583 if ((hw->mac_type == e1000_80003es2lan) && 3583 if ((hw->mac_type == e1000_80003es2lan) &&
3584 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3584 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3585 swfw = E1000_SWFW_PHY1_SM; 3585 swfw = E1000_SWFW_PHY1_SM;
3586 } else { 3586 } else {
3587 swfw = E1000_SWFW_PHY0_SM; 3587 swfw = E1000_SWFW_PHY0_SM;
@@ -3653,12 +3653,12 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
3653 (phy_addr << E1000_MDIC_PHY_SHIFT) | 3653 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3654 (E1000_MDIC_OP_WRITE)); 3654 (E1000_MDIC_OP_WRITE));
3655 3655
3656 E1000_WRITE_REG(hw, MDIC, mdic); 3656 ew32(MDIC, mdic);
3657 3657
3658 /* Poll the ready bit to see if the MDI read completed */ 3658 /* Poll the ready bit to see if the MDI read completed */
3659 for (i = 0; i < 641; i++) { 3659 for (i = 0; i < 641; i++) {
3660 udelay(5); 3660 udelay(5);
3661 mdic = E1000_READ_REG(hw, MDIC); 3661 mdic = er32(MDIC);
3662 if (mdic & E1000_MDIC_READY) break; 3662 if (mdic & E1000_MDIC_READY) break;
3663 } 3663 }
3664 if (!(mdic & E1000_MDIC_READY)) { 3664 if (!(mdic & E1000_MDIC_READY)) {
@@ -3697,7 +3697,7 @@ static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3697 DEBUGFUNC("e1000_read_kmrn_reg"); 3697 DEBUGFUNC("e1000_read_kmrn_reg");
3698 3698
3699 if ((hw->mac_type == e1000_80003es2lan) && 3699 if ((hw->mac_type == e1000_80003es2lan) &&
3700 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3700 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3701 swfw = E1000_SWFW_PHY1_SM; 3701 swfw = E1000_SWFW_PHY1_SM;
3702 } else { 3702 } else {
3703 swfw = E1000_SWFW_PHY0_SM; 3703 swfw = E1000_SWFW_PHY0_SM;
@@ -3709,11 +3709,11 @@ static s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 *data)
3709 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3709 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3710 E1000_KUMCTRLSTA_OFFSET) | 3710 E1000_KUMCTRLSTA_OFFSET) |
3711 E1000_KUMCTRLSTA_REN; 3711 E1000_KUMCTRLSTA_REN;
3712 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3712 ew32(KUMCTRLSTA, reg_val);
3713 udelay(2); 3713 udelay(2);
3714 3714
3715 /* Read the data returned */ 3715 /* Read the data returned */
3716 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 3716 reg_val = er32(KUMCTRLSTA);
3717 *data = (u16)reg_val; 3717 *data = (u16)reg_val;
3718 3718
3719 e1000_swfw_sync_release(hw, swfw); 3719 e1000_swfw_sync_release(hw, swfw);
@@ -3727,7 +3727,7 @@ static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3727 DEBUGFUNC("e1000_write_kmrn_reg"); 3727 DEBUGFUNC("e1000_write_kmrn_reg");
3728 3728
3729 if ((hw->mac_type == e1000_80003es2lan) && 3729 if ((hw->mac_type == e1000_80003es2lan) &&
3730 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3730 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3731 swfw = E1000_SWFW_PHY1_SM; 3731 swfw = E1000_SWFW_PHY1_SM;
3732 } else { 3732 } else {
3733 swfw = E1000_SWFW_PHY0_SM; 3733 swfw = E1000_SWFW_PHY0_SM;
@@ -3737,7 +3737,7 @@ static s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 reg_addr, u16 data)
3737 3737
3738 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 3738 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3739 E1000_KUMCTRLSTA_OFFSET) | data; 3739 E1000_KUMCTRLSTA_OFFSET) | data;
3740 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 3740 ew32(KUMCTRLSTA, reg_val);
3741 udelay(2); 3741 udelay(2);
3742 3742
3743 e1000_swfw_sync_release(hw, swfw); 3743 e1000_swfw_sync_release(hw, swfw);
@@ -3768,7 +3768,7 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3768 3768
3769 if (hw->mac_type > e1000_82543) { 3769 if (hw->mac_type > e1000_82543) {
3770 if ((hw->mac_type == e1000_80003es2lan) && 3770 if ((hw->mac_type == e1000_80003es2lan) &&
3771 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 3771 (er32(STATUS) & E1000_STATUS_FUNC_1)) {
3772 swfw = E1000_SWFW_PHY1_SM; 3772 swfw = E1000_SWFW_PHY1_SM;
3773 } else { 3773 } else {
3774 swfw = E1000_SWFW_PHY0_SM; 3774 swfw = E1000_SWFW_PHY0_SM;
@@ -3783,17 +3783,17 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3783 * and deassert. For e1000_82571 hardware and later, we instead delay 3783 * and deassert. For e1000_82571 hardware and later, we instead delay
3784 * for 50us between and 10ms after the deassertion. 3784 * for 50us between and 10ms after the deassertion.
3785 */ 3785 */
3786 ctrl = E1000_READ_REG(hw, CTRL); 3786 ctrl = er32(CTRL);
3787 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 3787 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3788 E1000_WRITE_FLUSH(hw); 3788 E1000_WRITE_FLUSH();
3789 3789
3790 if (hw->mac_type < e1000_82571) 3790 if (hw->mac_type < e1000_82571)
3791 msleep(10); 3791 msleep(10);
3792 else 3792 else
3793 udelay(100); 3793 udelay(100);
3794 3794
3795 E1000_WRITE_REG(hw, CTRL, ctrl); 3795 ew32(CTRL, ctrl);
3796 E1000_WRITE_FLUSH(hw); 3796 E1000_WRITE_FLUSH();
3797 3797
3798 if (hw->mac_type >= e1000_82571) 3798 if (hw->mac_type >= e1000_82571)
3799 mdelay(10); 3799 mdelay(10);
@@ -3803,24 +3803,24 @@ s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3803 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3803 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3804 * bit to put the PHY into reset. Then, take it out of reset. 3804 * bit to put the PHY into reset. Then, take it out of reset.
3805 */ 3805 */
3806 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3806 ctrl_ext = er32(CTRL_EXT);
3807 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 3807 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3808 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 3808 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3809 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3809 ew32(CTRL_EXT, ctrl_ext);
3810 E1000_WRITE_FLUSH(hw); 3810 E1000_WRITE_FLUSH();
3811 msleep(10); 3811 msleep(10);
3812 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 3812 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3813 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3813 ew32(CTRL_EXT, ctrl_ext);
3814 E1000_WRITE_FLUSH(hw); 3814 E1000_WRITE_FLUSH();
3815 } 3815 }
3816 udelay(150); 3816 udelay(150);
3817 3817
3818 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 3818 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3819 /* Configure activity LED after PHY reset */ 3819 /* Configure activity LED after PHY reset */
3820 led_ctrl = E1000_READ_REG(hw, LEDCTL); 3820 led_ctrl = er32(LEDCTL);
3821 led_ctrl &= IGP_ACTIVITY_LED_MASK; 3821 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3822 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 3822 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3823 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 3823 ew32(LEDCTL, led_ctrl);
3824 } 3824 }
3825 3825
3826 /* Wait for FW to finish PHY configuration. */ 3826 /* Wait for FW to finish PHY configuration. */
@@ -3906,8 +3906,8 @@ void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3906 3906
3907 do { 3907 do {
3908 /* Disable link */ 3908 /* Disable link */
3909 reg = E1000_READ_REG(hw, PHY_CTRL); 3909 reg = er32(PHY_CTRL);
3910 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3910 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3911 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3911 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3912 3912
3913 /* Write VR power-down enable - bits 9:8 should be 10b */ 3913 /* Write VR power-down enable - bits 9:8 should be 10b */
@@ -3922,8 +3922,8 @@ void e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3922 break; 3922 break;
3923 3923
3924 /* Issue PHY reset and repeat at most one more time */ 3924 /* Issue PHY reset and repeat at most one more time */
3925 reg = E1000_READ_REG(hw, CTRL); 3925 reg = er32(CTRL);
3926 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); 3926 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3927 retry++; 3927 retry++;
3928 } while (retry); 3928 } while (retry);
3929 3929
@@ -3981,8 +3981,8 @@ static s32 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3981 mdelay(5); 3981 mdelay(5);
3982 } 3982 }
3983 /* Disable GigE link negotiation */ 3983 /* Disable GigE link negotiation */
3984 reg = E1000_READ_REG(hw, PHY_CTRL); 3984 reg = er32(PHY_CTRL);
3985 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | 3985 ew32(PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3986 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3986 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3987 3987
3988 /* unable to acquire PCS lock */ 3988 /* unable to acquire PCS lock */
@@ -4388,7 +4388,7 @@ s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
4388s32 e1000_init_eeprom_params(struct e1000_hw *hw) 4388s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4389{ 4389{
4390 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4390 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4391 u32 eecd = E1000_READ_REG(hw, EECD); 4391 u32 eecd = er32(EECD);
4392 s32 ret_val = E1000_SUCCESS; 4392 s32 ret_val = E1000_SUCCESS;
4393 u16 eeprom_size; 4393 u16 eeprom_size;
4394 4394
@@ -4490,7 +4490,7 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw)
4490 /* Ensure that the Autonomous FLASH update bit is cleared due to 4490 /* Ensure that the Autonomous FLASH update bit is cleared due to
4491 * Flash update issue on parts which use a FLASH for NVM. */ 4491 * Flash update issue on parts which use a FLASH for NVM. */
4492 eecd &= ~E1000_EECD_AUPDEN; 4492 eecd &= ~E1000_EECD_AUPDEN;
4493 E1000_WRITE_REG(hw, EECD, eecd); 4493 ew32(EECD, eecd);
4494 } 4494 }
4495 break; 4495 break;
4496 case e1000_80003es2lan: 4496 case e1000_80003es2lan:
@@ -4580,8 +4580,8 @@ static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
4580 * wait <delay> microseconds. 4580 * wait <delay> microseconds.
4581 */ 4581 */
4582 *eecd = *eecd | E1000_EECD_SK; 4582 *eecd = *eecd | E1000_EECD_SK;
4583 E1000_WRITE_REG(hw, EECD, *eecd); 4583 ew32(EECD, *eecd);
4584 E1000_WRITE_FLUSH(hw); 4584 E1000_WRITE_FLUSH();
4585 udelay(hw->eeprom.delay_usec); 4585 udelay(hw->eeprom.delay_usec);
4586} 4586}
4587 4587
@@ -4597,8 +4597,8 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
4597 * wait 50 microseconds. 4597 * wait 50 microseconds.
4598 */ 4598 */
4599 *eecd = *eecd & ~E1000_EECD_SK; 4599 *eecd = *eecd & ~E1000_EECD_SK;
4600 E1000_WRITE_REG(hw, EECD, *eecd); 4600 ew32(EECD, *eecd);
4601 E1000_WRITE_FLUSH(hw); 4601 E1000_WRITE_FLUSH();
4602 udelay(hw->eeprom.delay_usec); 4602 udelay(hw->eeprom.delay_usec);
4603} 4603}
4604 4604
@@ -4620,7 +4620,7 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4620 * In order to do this, "data" must be broken down into bits. 4620 * In order to do this, "data" must be broken down into bits.
4621 */ 4621 */
4622 mask = 0x01 << (count - 1); 4622 mask = 0x01 << (count - 1);
4623 eecd = E1000_READ_REG(hw, EECD); 4623 eecd = er32(EECD);
4624 if (eeprom->type == e1000_eeprom_microwire) { 4624 if (eeprom->type == e1000_eeprom_microwire) {
4625 eecd &= ~E1000_EECD_DO; 4625 eecd &= ~E1000_EECD_DO;
4626 } else if (eeprom->type == e1000_eeprom_spi) { 4626 } else if (eeprom->type == e1000_eeprom_spi) {
@@ -4637,8 +4637,8 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4637 if (data & mask) 4637 if (data & mask)
4638 eecd |= E1000_EECD_DI; 4638 eecd |= E1000_EECD_DI;
4639 4639
4640 E1000_WRITE_REG(hw, EECD, eecd); 4640 ew32(EECD, eecd);
4641 E1000_WRITE_FLUSH(hw); 4641 E1000_WRITE_FLUSH();
4642 4642
4643 udelay(eeprom->delay_usec); 4643 udelay(eeprom->delay_usec);
4644 4644
@@ -4651,7 +4651,7 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
4651 4651
4652 /* We leave the "DI" bit set to "0" when we leave this routine. */ 4652 /* We leave the "DI" bit set to "0" when we leave this routine. */
4653 eecd &= ~E1000_EECD_DI; 4653 eecd &= ~E1000_EECD_DI;
4654 E1000_WRITE_REG(hw, EECD, eecd); 4654 ew32(EECD, eecd);
4655} 4655}
4656 4656
4657/****************************************************************************** 4657/******************************************************************************
@@ -4672,7 +4672,7 @@ static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4672 * always be clear. 4672 * always be clear.
4673 */ 4673 */
4674 4674
4675 eecd = E1000_READ_REG(hw, EECD); 4675 eecd = er32(EECD);
4676 4676
4677 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 4677 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4678 data = 0; 4678 data = 0;
@@ -4681,7 +4681,7 @@ static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
4681 data = data << 1; 4681 data = data << 1;
4682 e1000_raise_ee_clk(hw, &eecd); 4682 e1000_raise_ee_clk(hw, &eecd);
4683 4683
4684 eecd = E1000_READ_REG(hw, EECD); 4684 eecd = er32(EECD);
4685 4685
4686 eecd &= ~(E1000_EECD_DI); 4686 eecd &= ~(E1000_EECD_DI);
4687 if (eecd & E1000_EECD_DO) 4687 if (eecd & E1000_EECD_DO)
@@ -4710,23 +4710,23 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4710 4710
4711 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 4711 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4712 return -E1000_ERR_SWFW_SYNC; 4712 return -E1000_ERR_SWFW_SYNC;
4713 eecd = E1000_READ_REG(hw, EECD); 4713 eecd = er32(EECD);
4714 4714
4715 if (hw->mac_type != e1000_82573) { 4715 if (hw->mac_type != e1000_82573) {
4716 /* Request EEPROM Access */ 4716 /* Request EEPROM Access */
4717 if (hw->mac_type > e1000_82544) { 4717 if (hw->mac_type > e1000_82544) {
4718 eecd |= E1000_EECD_REQ; 4718 eecd |= E1000_EECD_REQ;
4719 E1000_WRITE_REG(hw, EECD, eecd); 4719 ew32(EECD, eecd);
4720 eecd = E1000_READ_REG(hw, EECD); 4720 eecd = er32(EECD);
4721 while ((!(eecd & E1000_EECD_GNT)) && 4721 while ((!(eecd & E1000_EECD_GNT)) &&
4722 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 4722 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4723 i++; 4723 i++;
4724 udelay(5); 4724 udelay(5);
4725 eecd = E1000_READ_REG(hw, EECD); 4725 eecd = er32(EECD);
4726 } 4726 }
4727 if (!(eecd & E1000_EECD_GNT)) { 4727 if (!(eecd & E1000_EECD_GNT)) {
4728 eecd &= ~E1000_EECD_REQ; 4728 eecd &= ~E1000_EECD_REQ;
4729 E1000_WRITE_REG(hw, EECD, eecd); 4729 ew32(EECD, eecd);
4730 DEBUGOUT("Could not acquire EEPROM grant\n"); 4730 DEBUGOUT("Could not acquire EEPROM grant\n");
4731 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4731 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4732 return -E1000_ERR_EEPROM; 4732 return -E1000_ERR_EEPROM;
@@ -4739,15 +4739,15 @@ static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
4739 if (eeprom->type == e1000_eeprom_microwire) { 4739 if (eeprom->type == e1000_eeprom_microwire) {
4740 /* Clear SK and DI */ 4740 /* Clear SK and DI */
4741 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 4741 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4742 E1000_WRITE_REG(hw, EECD, eecd); 4742 ew32(EECD, eecd);
4743 4743
4744 /* Set CS */ 4744 /* Set CS */
4745 eecd |= E1000_EECD_CS; 4745 eecd |= E1000_EECD_CS;
4746 E1000_WRITE_REG(hw, EECD, eecd); 4746 ew32(EECD, eecd);
4747 } else if (eeprom->type == e1000_eeprom_spi) { 4747 } else if (eeprom->type == e1000_eeprom_spi) {
4748 /* Clear SK and CS */ 4748 /* Clear SK and CS */
4749 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4749 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4750 E1000_WRITE_REG(hw, EECD, eecd); 4750 ew32(EECD, eecd);
4751 udelay(1); 4751 udelay(1);
4752 } 4752 }
4753 4753
@@ -4764,40 +4764,40 @@ static void e1000_standby_eeprom(struct e1000_hw *hw)
4764 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4764 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4765 u32 eecd; 4765 u32 eecd;
4766 4766
4767 eecd = E1000_READ_REG(hw, EECD); 4767 eecd = er32(EECD);
4768 4768
4769 if (eeprom->type == e1000_eeprom_microwire) { 4769 if (eeprom->type == e1000_eeprom_microwire) {
4770 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 4770 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4771 E1000_WRITE_REG(hw, EECD, eecd); 4771 ew32(EECD, eecd);
4772 E1000_WRITE_FLUSH(hw); 4772 E1000_WRITE_FLUSH();
4773 udelay(eeprom->delay_usec); 4773 udelay(eeprom->delay_usec);
4774 4774
4775 /* Clock high */ 4775 /* Clock high */
4776 eecd |= E1000_EECD_SK; 4776 eecd |= E1000_EECD_SK;
4777 E1000_WRITE_REG(hw, EECD, eecd); 4777 ew32(EECD, eecd);
4778 E1000_WRITE_FLUSH(hw); 4778 E1000_WRITE_FLUSH();
4779 udelay(eeprom->delay_usec); 4779 udelay(eeprom->delay_usec);
4780 4780
4781 /* Select EEPROM */ 4781 /* Select EEPROM */
4782 eecd |= E1000_EECD_CS; 4782 eecd |= E1000_EECD_CS;
4783 E1000_WRITE_REG(hw, EECD, eecd); 4783 ew32(EECD, eecd);
4784 E1000_WRITE_FLUSH(hw); 4784 E1000_WRITE_FLUSH();
4785 udelay(eeprom->delay_usec); 4785 udelay(eeprom->delay_usec);
4786 4786
4787 /* Clock low */ 4787 /* Clock low */
4788 eecd &= ~E1000_EECD_SK; 4788 eecd &= ~E1000_EECD_SK;
4789 E1000_WRITE_REG(hw, EECD, eecd); 4789 ew32(EECD, eecd);
4790 E1000_WRITE_FLUSH(hw); 4790 E1000_WRITE_FLUSH();
4791 udelay(eeprom->delay_usec); 4791 udelay(eeprom->delay_usec);
4792 } else if (eeprom->type == e1000_eeprom_spi) { 4792 } else if (eeprom->type == e1000_eeprom_spi) {
4793 /* Toggle CS to flush commands */ 4793 /* Toggle CS to flush commands */
4794 eecd |= E1000_EECD_CS; 4794 eecd |= E1000_EECD_CS;
4795 E1000_WRITE_REG(hw, EECD, eecd); 4795 ew32(EECD, eecd);
4796 E1000_WRITE_FLUSH(hw); 4796 E1000_WRITE_FLUSH();
4797 udelay(eeprom->delay_usec); 4797 udelay(eeprom->delay_usec);
4798 eecd &= ~E1000_EECD_CS; 4798 eecd &= ~E1000_EECD_CS;
4799 E1000_WRITE_REG(hw, EECD, eecd); 4799 ew32(EECD, eecd);
4800 E1000_WRITE_FLUSH(hw); 4800 E1000_WRITE_FLUSH();
4801 udelay(eeprom->delay_usec); 4801 udelay(eeprom->delay_usec);
4802 } 4802 }
4803} 4803}
@@ -4813,13 +4813,13 @@ static void e1000_release_eeprom(struct e1000_hw *hw)
4813 4813
4814 DEBUGFUNC("e1000_release_eeprom"); 4814 DEBUGFUNC("e1000_release_eeprom");
4815 4815
4816 eecd = E1000_READ_REG(hw, EECD); 4816 eecd = er32(EECD);
4817 4817
4818 if (hw->eeprom.type == e1000_eeprom_spi) { 4818 if (hw->eeprom.type == e1000_eeprom_spi) {
4819 eecd |= E1000_EECD_CS; /* Pull CS high */ 4819 eecd |= E1000_EECD_CS; /* Pull CS high */
4820 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 4820 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4821 4821
4822 E1000_WRITE_REG(hw, EECD, eecd); 4822 ew32(EECD, eecd);
4823 4823
4824 udelay(hw->eeprom.delay_usec); 4824 udelay(hw->eeprom.delay_usec);
4825 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 4825 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
@@ -4828,25 +4828,25 @@ static void e1000_release_eeprom(struct e1000_hw *hw)
4828 /* CS on Microwire is active-high */ 4828 /* CS on Microwire is active-high */
4829 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 4829 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4830 4830
4831 E1000_WRITE_REG(hw, EECD, eecd); 4831 ew32(EECD, eecd);
4832 4832
4833 /* Rising edge of clock */ 4833 /* Rising edge of clock */
4834 eecd |= E1000_EECD_SK; 4834 eecd |= E1000_EECD_SK;
4835 E1000_WRITE_REG(hw, EECD, eecd); 4835 ew32(EECD, eecd);
4836 E1000_WRITE_FLUSH(hw); 4836 E1000_WRITE_FLUSH();
4837 udelay(hw->eeprom.delay_usec); 4837 udelay(hw->eeprom.delay_usec);
4838 4838
4839 /* Falling edge of clock */ 4839 /* Falling edge of clock */
4840 eecd &= ~E1000_EECD_SK; 4840 eecd &= ~E1000_EECD_SK;
4841 E1000_WRITE_REG(hw, EECD, eecd); 4841 ew32(EECD, eecd);
4842 E1000_WRITE_FLUSH(hw); 4842 E1000_WRITE_FLUSH();
4843 udelay(hw->eeprom.delay_usec); 4843 udelay(hw->eeprom.delay_usec);
4844 } 4844 }
4845 4845
4846 /* Stop requesting EEPROM access */ 4846 /* Stop requesting EEPROM access */
4847 if (hw->mac_type > e1000_82544) { 4847 if (hw->mac_type > e1000_82544) {
4848 eecd &= ~E1000_EECD_REQ; 4848 eecd &= ~E1000_EECD_REQ;
4849 E1000_WRITE_REG(hw, EECD, eecd); 4849 ew32(EECD, eecd);
4850 } 4850 }
4851 4851
4852 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 4852 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
@@ -5009,13 +5009,13 @@ static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
5009 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 5009 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5010 E1000_EEPROM_RW_REG_START; 5010 E1000_EEPROM_RW_REG_START;
5011 5011
5012 E1000_WRITE_REG(hw, EERD, eerd); 5012 ew32(EERD, eerd);
5013 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 5013 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5014 5014
5015 if (error) { 5015 if (error) {
5016 break; 5016 break;
5017 } 5017 }
5018 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); 5018 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
5019 5019
5020 } 5020 }
5021 5021
@@ -5050,7 +5050,7 @@ static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
5050 break; 5050 break;
5051 } 5051 }
5052 5052
5053 E1000_WRITE_REG(hw, EEWR, register_value); 5053 ew32(EEWR, register_value);
5054 5054
5055 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 5055 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5056 5056
@@ -5076,9 +5076,9 @@ static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5076 5076
5077 for (i = 0; i < attempts; i++) { 5077 for (i = 0; i < attempts; i++) {
5078 if (eerd == E1000_EEPROM_POLL_READ) 5078 if (eerd == E1000_EEPROM_POLL_READ)
5079 reg = E1000_READ_REG(hw, EERD); 5079 reg = er32(EERD);
5080 else 5080 else
5081 reg = E1000_READ_REG(hw, EEWR); 5081 reg = er32(EEWR);
5082 5082
5083 if (reg & E1000_EEPROM_RW_REG_DONE) { 5083 if (reg & E1000_EEPROM_RW_REG_DONE) {
5084 done = E1000_SUCCESS; 5084 done = E1000_SUCCESS;
@@ -5105,7 +5105,7 @@ static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5105 return false; 5105 return false;
5106 5106
5107 if (hw->mac_type == e1000_82573) { 5107 if (hw->mac_type == e1000_82573) {
5108 eecd = E1000_READ_REG(hw, EECD); 5108 eecd = er32(EECD);
5109 5109
5110 /* Isolate bits 15 & 16 */ 5110 /* Isolate bits 15 & 16 */
5111 eecd = ((eecd >> 15) & 0x03); 5111 eecd = ((eecd >> 15) & 0x03);
@@ -5215,9 +5215,9 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5215 e1000_commit_shadow_ram(hw); 5215 e1000_commit_shadow_ram(hw);
5216 /* Reload the EEPROM, or else modifications will not appear 5216 /* Reload the EEPROM, or else modifications will not appear
5217 * until after next adapter reset. */ 5217 * until after next adapter reset. */
5218 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5218 ctrl_ext = er32(CTRL_EXT);
5219 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 5219 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5220 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5220 ew32(CTRL_EXT, ctrl_ext);
5221 msleep(10); 5221 msleep(10);
5222 } 5222 }
5223 return E1000_SUCCESS; 5223 return E1000_SUCCESS;
@@ -5395,7 +5395,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
5395 * If DO does not go high in 10 milliseconds, then error out. 5395 * If DO does not go high in 10 milliseconds, then error out.
5396 */ 5396 */
5397 for (i = 0; i < 200; i++) { 5397 for (i = 0; i < 200; i++) {
5398 eecd = E1000_READ_REG(hw, EECD); 5398 eecd = er32(EECD);
5399 if (eecd & E1000_EECD_DO) break; 5399 if (eecd & E1000_EECD_DO) break;
5400 udelay(50); 5400 udelay(50);
5401 } 5401 }
@@ -5449,9 +5449,9 @@ static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5449 5449
5450 if (hw->mac_type == e1000_82573) { 5450 if (hw->mac_type == e1000_82573) {
5451 /* The flop register will be used to determine if flash type is STM */ 5451 /* The flop register will be used to determine if flash type is STM */
5452 flop = E1000_READ_REG(hw, FLOP); 5452 flop = er32(FLOP);
5453 for (i=0; i < attempts; i++) { 5453 for (i=0; i < attempts; i++) {
5454 eecd = E1000_READ_REG(hw, EECD); 5454 eecd = er32(EECD);
5455 if ((eecd & E1000_EECD_FLUPD) == 0) { 5455 if ((eecd & E1000_EECD_FLUPD) == 0) {
5456 break; 5456 break;
5457 } 5457 }
@@ -5464,14 +5464,14 @@ static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5464 5464
5465 /* If STM opcode located in bits 15:8 of flop, reset firmware */ 5465 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5466 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 5466 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5467 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 5467 ew32(HICR, E1000_HICR_FW_RESET);
5468 } 5468 }
5469 5469
5470 /* Perform the flash update */ 5470 /* Perform the flash update */
5471 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 5471 ew32(EECD, eecd | E1000_EECD_FLUPD);
5472 5472
5473 for (i=0; i < attempts; i++) { 5473 for (i=0; i < attempts; i++) {
5474 eecd = E1000_READ_REG(hw, EECD); 5474 eecd = er32(EECD);
5475 if ((eecd & E1000_EECD_FLUPD) == 0) { 5475 if ((eecd & E1000_EECD_FLUPD) == 0) {
5476 break; 5476 break;
5477 } 5477 }
@@ -5487,7 +5487,7 @@ static s32 e1000_commit_shadow_ram(struct e1000_hw *hw)
5487 /* We're writing to the opposite bank so if we're on bank 1, 5487 /* We're writing to the opposite bank so if we're on bank 1,
5488 * write to bank 0 etc. We also need to erase the segment that 5488 * write to bank 0 etc. We also need to erase the segment that
5489 * is going to be written */ 5489 * is going to be written */
5490 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 5490 if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
5491 new_bank_offset = hw->flash_bank_size * 2; 5491 new_bank_offset = hw->flash_bank_size * 2;
5492 old_bank_offset = 0; 5492 old_bank_offset = 0;
5493 e1000_erase_ich8_4k_segment(hw, 1); 5493 e1000_erase_ich8_4k_segment(hw, 1);
@@ -5621,7 +5621,7 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)
5621 case e1000_82546_rev_3: 5621 case e1000_82546_rev_3:
5622 case e1000_82571: 5622 case e1000_82571:
5623 case e1000_80003es2lan: 5623 case e1000_80003es2lan:
5624 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 5624 if (er32(STATUS) & E1000_STATUS_FUNC_1)
5625 hw->perm_mac_addr[5] ^= 0x01; 5625 hw->perm_mac_addr[5] ^= 0x01;
5626 break; 5626 break;
5627 } 5627 }
@@ -5666,9 +5666,9 @@ static void e1000_init_rx_addrs(struct e1000_hw *hw)
5666 DEBUGOUT("Clearing RAR[1-15]\n"); 5666 DEBUGOUT("Clearing RAR[1-15]\n");
5667 for (i = 1; i < rar_num; i++) { 5667 for (i = 1; i < rar_num; i++) {
5668 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 5668 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5669 E1000_WRITE_FLUSH(hw); 5669 E1000_WRITE_FLUSH();
5670 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 5670 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5671 E1000_WRITE_FLUSH(hw); 5671 E1000_WRITE_FLUSH();
5672 } 5672 }
5673} 5673}
5674 5674
@@ -5772,12 +5772,12 @@ void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
5772 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { 5772 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5773 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 5773 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5774 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5774 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5775 E1000_WRITE_FLUSH(hw); 5775 E1000_WRITE_FLUSH();
5776 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 5776 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5777 E1000_WRITE_FLUSH(hw); 5777 E1000_WRITE_FLUSH();
5778 } else { 5778 } else {
5779 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 5779 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5780 E1000_WRITE_FLUSH(hw); 5780 E1000_WRITE_FLUSH();
5781 } 5781 }
5782} 5782}
5783 5783
@@ -5831,9 +5831,9 @@ void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
5831 } 5831 }
5832 5832
5833 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 5833 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5834 E1000_WRITE_FLUSH(hw); 5834 E1000_WRITE_FLUSH();
5835 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 5835 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5836 E1000_WRITE_FLUSH(hw); 5836 E1000_WRITE_FLUSH();
5837} 5837}
5838 5838
5839/****************************************************************************** 5839/******************************************************************************
@@ -5853,12 +5853,12 @@ void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
5853 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5853 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5854 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5854 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5855 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5855 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5856 E1000_WRITE_FLUSH(hw); 5856 E1000_WRITE_FLUSH();
5857 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 5857 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5858 E1000_WRITE_FLUSH(hw); 5858 E1000_WRITE_FLUSH();
5859 } else { 5859 } else {
5860 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5860 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5861 E1000_WRITE_FLUSH(hw); 5861 E1000_WRITE_FLUSH();
5862 } 5862 }
5863} 5863}
5864 5864
@@ -5896,7 +5896,7 @@ static void e1000_clear_vfta(struct e1000_hw *hw)
5896 * manageability unit */ 5896 * manageability unit */
5897 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 5897 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5898 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 5898 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5899 E1000_WRITE_FLUSH(hw); 5899 E1000_WRITE_FLUSH();
5900 } 5900 }
5901} 5901}
5902 5902
@@ -5916,7 +5916,7 @@ static s32 e1000_id_led_init(struct e1000_hw *hw)
5916 return E1000_SUCCESS; 5916 return E1000_SUCCESS;
5917 } 5917 }
5918 5918
5919 ledctl = E1000_READ_REG(hw, LEDCTL); 5919 ledctl = er32(LEDCTL);
5920 hw->ledctl_default = ledctl; 5920 hw->ledctl_default = ledctl;
5921 hw->ledctl_mode1 = hw->ledctl_default; 5921 hw->ledctl_mode1 = hw->ledctl_default;
5922 hw->ledctl_mode2 = hw->ledctl_default; 5922 hw->ledctl_mode2 = hw->ledctl_default;
@@ -6013,7 +6013,7 @@ s32 e1000_setup_led(struct e1000_hw *hw)
6013 /* Fall Through */ 6013 /* Fall Through */
6014 default: 6014 default:
6015 if (hw->media_type == e1000_media_type_fiber) { 6015 if (hw->media_type == e1000_media_type_fiber) {
6016 ledctl = E1000_READ_REG(hw, LEDCTL); 6016 ledctl = er32(LEDCTL);
6017 /* Save current LEDCTL settings */ 6017 /* Save current LEDCTL settings */
6018 hw->ledctl_default = ledctl; 6018 hw->ledctl_default = ledctl;
6019 /* Turn off LED0 */ 6019 /* Turn off LED0 */
@@ -6022,9 +6022,9 @@ s32 e1000_setup_led(struct e1000_hw *hw)
6022 E1000_LEDCTL_LED0_MODE_MASK); 6022 E1000_LEDCTL_LED0_MODE_MASK);
6023 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 6023 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6024 E1000_LEDCTL_LED0_MODE_SHIFT); 6024 E1000_LEDCTL_LED0_MODE_SHIFT);
6025 E1000_WRITE_REG(hw, LEDCTL, ledctl); 6025 ew32(LEDCTL, ledctl);
6026 } else if (hw->media_type == e1000_media_type_copper) 6026 } else if (hw->media_type == e1000_media_type_copper)
6027 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6027 ew32(LEDCTL, hw->ledctl_mode1);
6028 break; 6028 break;
6029 } 6029 }
6030 6030
@@ -6064,7 +6064,7 @@ s32 e1000_blink_led_start(struct e1000_hw *hw)
6064 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); 6064 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6065 } 6065 }
6066 6066
6067 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); 6067 ew32(LEDCTL, ledctl_blink);
6068 6068
6069 return E1000_SUCCESS; 6069 return E1000_SUCCESS;
6070} 6070}
@@ -6103,7 +6103,7 @@ s32 e1000_cleanup_led(struct e1000_hw *hw)
6103 break; 6103 break;
6104 } 6104 }
6105 /* Restore LEDCTL settings */ 6105 /* Restore LEDCTL settings */
6106 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6106 ew32(LEDCTL, hw->ledctl_default);
6107 break; 6107 break;
6108 } 6108 }
6109 6109
@@ -6117,7 +6117,7 @@ s32 e1000_cleanup_led(struct e1000_hw *hw)
6117 *****************************************************************************/ 6117 *****************************************************************************/
6118s32 e1000_led_on(struct e1000_hw *hw) 6118s32 e1000_led_on(struct e1000_hw *hw)
6119{ 6119{
6120 u32 ctrl = E1000_READ_REG(hw, CTRL); 6120 u32 ctrl = er32(CTRL);
6121 6121
6122 DEBUGFUNC("e1000_led_on"); 6122 DEBUGFUNC("e1000_led_on");
6123 6123
@@ -6149,13 +6149,13 @@ s32 e1000_led_on(struct e1000_hw *hw)
6149 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6149 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6150 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 6150 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6151 } else if (hw->media_type == e1000_media_type_copper) { 6151 } else if (hw->media_type == e1000_media_type_copper) {
6152 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6152 ew32(LEDCTL, hw->ledctl_mode2);
6153 return E1000_SUCCESS; 6153 return E1000_SUCCESS;
6154 } 6154 }
6155 break; 6155 break;
6156 } 6156 }
6157 6157
6158 E1000_WRITE_REG(hw, CTRL, ctrl); 6158 ew32(CTRL, ctrl);
6159 6159
6160 return E1000_SUCCESS; 6160 return E1000_SUCCESS;
6161} 6161}
@@ -6167,7 +6167,7 @@ s32 e1000_led_on(struct e1000_hw *hw)
6167 *****************************************************************************/ 6167 *****************************************************************************/
6168s32 e1000_led_off(struct e1000_hw *hw) 6168s32 e1000_led_off(struct e1000_hw *hw)
6169{ 6169{
6170 u32 ctrl = E1000_READ_REG(hw, CTRL); 6170 u32 ctrl = er32(CTRL);
6171 6171
6172 DEBUGFUNC("e1000_led_off"); 6172 DEBUGFUNC("e1000_led_off");
6173 6173
@@ -6199,13 +6199,13 @@ s32 e1000_led_off(struct e1000_hw *hw)
6199 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 6199 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6200 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 6200 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6201 } else if (hw->media_type == e1000_media_type_copper) { 6201 } else if (hw->media_type == e1000_media_type_copper) {
6202 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6202 ew32(LEDCTL, hw->ledctl_mode1);
6203 return E1000_SUCCESS; 6203 return E1000_SUCCESS;
6204 } 6204 }
6205 break; 6205 break;
6206 } 6206 }
6207 6207
6208 E1000_WRITE_REG(hw, CTRL, ctrl); 6208 ew32(CTRL, ctrl);
6209 6209
6210 return E1000_SUCCESS; 6210 return E1000_SUCCESS;
6211} 6211}
@@ -6219,93 +6219,93 @@ static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
6219{ 6219{
6220 volatile u32 temp; 6220 volatile u32 temp;
6221 6221
6222 temp = E1000_READ_REG(hw, CRCERRS); 6222 temp = er32(CRCERRS);
6223 temp = E1000_READ_REG(hw, SYMERRS); 6223 temp = er32(SYMERRS);
6224 temp = E1000_READ_REG(hw, MPC); 6224 temp = er32(MPC);
6225 temp = E1000_READ_REG(hw, SCC); 6225 temp = er32(SCC);
6226 temp = E1000_READ_REG(hw, ECOL); 6226 temp = er32(ECOL);
6227 temp = E1000_READ_REG(hw, MCC); 6227 temp = er32(MCC);
6228 temp = E1000_READ_REG(hw, LATECOL); 6228 temp = er32(LATECOL);
6229 temp = E1000_READ_REG(hw, COLC); 6229 temp = er32(COLC);
6230 temp = E1000_READ_REG(hw, DC); 6230 temp = er32(DC);
6231 temp = E1000_READ_REG(hw, SEC); 6231 temp = er32(SEC);
6232 temp = E1000_READ_REG(hw, RLEC); 6232 temp = er32(RLEC);
6233 temp = E1000_READ_REG(hw, XONRXC); 6233 temp = er32(XONRXC);
6234 temp = E1000_READ_REG(hw, XONTXC); 6234 temp = er32(XONTXC);
6235 temp = E1000_READ_REG(hw, XOFFRXC); 6235 temp = er32(XOFFRXC);
6236 temp = E1000_READ_REG(hw, XOFFTXC); 6236 temp = er32(XOFFTXC);
6237 temp = E1000_READ_REG(hw, FCRUC); 6237 temp = er32(FCRUC);
6238 6238
6239 if (hw->mac_type != e1000_ich8lan) { 6239 if (hw->mac_type != e1000_ich8lan) {
6240 temp = E1000_READ_REG(hw, PRC64); 6240 temp = er32(PRC64);
6241 temp = E1000_READ_REG(hw, PRC127); 6241 temp = er32(PRC127);
6242 temp = E1000_READ_REG(hw, PRC255); 6242 temp = er32(PRC255);
6243 temp = E1000_READ_REG(hw, PRC511); 6243 temp = er32(PRC511);
6244 temp = E1000_READ_REG(hw, PRC1023); 6244 temp = er32(PRC1023);
6245 temp = E1000_READ_REG(hw, PRC1522); 6245 temp = er32(PRC1522);
6246 } 6246 }
6247 6247
6248 temp = E1000_READ_REG(hw, GPRC); 6248 temp = er32(GPRC);
6249 temp = E1000_READ_REG(hw, BPRC); 6249 temp = er32(BPRC);
6250 temp = E1000_READ_REG(hw, MPRC); 6250 temp = er32(MPRC);
6251 temp = E1000_READ_REG(hw, GPTC); 6251 temp = er32(GPTC);
6252 temp = E1000_READ_REG(hw, GORCL); 6252 temp = er32(GORCL);
6253 temp = E1000_READ_REG(hw, GORCH); 6253 temp = er32(GORCH);
6254 temp = E1000_READ_REG(hw, GOTCL); 6254 temp = er32(GOTCL);
6255 temp = E1000_READ_REG(hw, GOTCH); 6255 temp = er32(GOTCH);
6256 temp = E1000_READ_REG(hw, RNBC); 6256 temp = er32(RNBC);
6257 temp = E1000_READ_REG(hw, RUC); 6257 temp = er32(RUC);
6258 temp = E1000_READ_REG(hw, RFC); 6258 temp = er32(RFC);
6259 temp = E1000_READ_REG(hw, ROC); 6259 temp = er32(ROC);
6260 temp = E1000_READ_REG(hw, RJC); 6260 temp = er32(RJC);
6261 temp = E1000_READ_REG(hw, TORL); 6261 temp = er32(TORL);
6262 temp = E1000_READ_REG(hw, TORH); 6262 temp = er32(TORH);
6263 temp = E1000_READ_REG(hw, TOTL); 6263 temp = er32(TOTL);
6264 temp = E1000_READ_REG(hw, TOTH); 6264 temp = er32(TOTH);
6265 temp = E1000_READ_REG(hw, TPR); 6265 temp = er32(TPR);
6266 temp = E1000_READ_REG(hw, TPT); 6266 temp = er32(TPT);
6267 6267
6268 if (hw->mac_type != e1000_ich8lan) { 6268 if (hw->mac_type != e1000_ich8lan) {
6269 temp = E1000_READ_REG(hw, PTC64); 6269 temp = er32(PTC64);
6270 temp = E1000_READ_REG(hw, PTC127); 6270 temp = er32(PTC127);
6271 temp = E1000_READ_REG(hw, PTC255); 6271 temp = er32(PTC255);
6272 temp = E1000_READ_REG(hw, PTC511); 6272 temp = er32(PTC511);
6273 temp = E1000_READ_REG(hw, PTC1023); 6273 temp = er32(PTC1023);
6274 temp = E1000_READ_REG(hw, PTC1522); 6274 temp = er32(PTC1522);
6275 } 6275 }
6276 6276
6277 temp = E1000_READ_REG(hw, MPTC); 6277 temp = er32(MPTC);
6278 temp = E1000_READ_REG(hw, BPTC); 6278 temp = er32(BPTC);
6279 6279
6280 if (hw->mac_type < e1000_82543) return; 6280 if (hw->mac_type < e1000_82543) return;
6281 6281
6282 temp = E1000_READ_REG(hw, ALGNERRC); 6282 temp = er32(ALGNERRC);
6283 temp = E1000_READ_REG(hw, RXERRC); 6283 temp = er32(RXERRC);
6284 temp = E1000_READ_REG(hw, TNCRS); 6284 temp = er32(TNCRS);
6285 temp = E1000_READ_REG(hw, CEXTERR); 6285 temp = er32(CEXTERR);
6286 temp = E1000_READ_REG(hw, TSCTC); 6286 temp = er32(TSCTC);
6287 temp = E1000_READ_REG(hw, TSCTFC); 6287 temp = er32(TSCTFC);
6288 6288
6289 if (hw->mac_type <= e1000_82544) return; 6289 if (hw->mac_type <= e1000_82544) return;
6290 6290
6291 temp = E1000_READ_REG(hw, MGTPRC); 6291 temp = er32(MGTPRC);
6292 temp = E1000_READ_REG(hw, MGTPDC); 6292 temp = er32(MGTPDC);
6293 temp = E1000_READ_REG(hw, MGTPTC); 6293 temp = er32(MGTPTC);
6294 6294
6295 if (hw->mac_type <= e1000_82547_rev_2) return; 6295 if (hw->mac_type <= e1000_82547_rev_2) return;
6296 6296
6297 temp = E1000_READ_REG(hw, IAC); 6297 temp = er32(IAC);
6298 temp = E1000_READ_REG(hw, ICRXOC); 6298 temp = er32(ICRXOC);
6299 6299
6300 if (hw->mac_type == e1000_ich8lan) return; 6300 if (hw->mac_type == e1000_ich8lan) return;
6301 6301
6302 temp = E1000_READ_REG(hw, ICRXPTC); 6302 temp = er32(ICRXPTC);
6303 temp = E1000_READ_REG(hw, ICRXATC); 6303 temp = er32(ICRXATC);
6304 temp = E1000_READ_REG(hw, ICTXPTC); 6304 temp = er32(ICTXPTC);
6305 temp = E1000_READ_REG(hw, ICTXATC); 6305 temp = er32(ICTXATC);
6306 temp = E1000_READ_REG(hw, ICTXQEC); 6306 temp = er32(ICTXQEC);
6307 temp = E1000_READ_REG(hw, ICTXQMTC); 6307 temp = er32(ICTXQMTC);
6308 temp = E1000_READ_REG(hw, ICRXDMTC); 6308 temp = er32(ICRXDMTC);
6309} 6309}
6310 6310
6311/****************************************************************************** 6311/******************************************************************************
@@ -6331,7 +6331,7 @@ void e1000_reset_adaptive(struct e1000_hw *hw)
6331 hw->ifs_ratio = IFS_RATIO; 6331 hw->ifs_ratio = IFS_RATIO;
6332 } 6332 }
6333 hw->in_ifs_mode = false; 6333 hw->in_ifs_mode = false;
6334 E1000_WRITE_REG(hw, AIT, 0); 6334 ew32(AIT, 0);
6335 } else { 6335 } else {
6336 DEBUGOUT("Not in Adaptive IFS mode!\n"); 6336 DEBUGOUT("Not in Adaptive IFS mode!\n");
6337 } 6337 }
@@ -6358,14 +6358,14 @@ void e1000_update_adaptive(struct e1000_hw *hw)
6358 hw->current_ifs_val = hw->ifs_min_val; 6358 hw->current_ifs_val = hw->ifs_min_val;
6359 else 6359 else
6360 hw->current_ifs_val += hw->ifs_step_size; 6360 hw->current_ifs_val += hw->ifs_step_size;
6361 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); 6361 ew32(AIT, hw->current_ifs_val);
6362 } 6362 }
6363 } 6363 }
6364 } else { 6364 } else {
6365 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 6365 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6366 hw->current_ifs_val = 0; 6366 hw->current_ifs_val = 0;
6367 hw->in_ifs_mode = false; 6367 hw->in_ifs_mode = false;
6368 E1000_WRITE_REG(hw, AIT, 0); 6368 ew32(AIT, 0);
6369 } 6369 }
6370 } 6370 }
6371 } else { 6371 } else {
@@ -6489,7 +6489,7 @@ void e1000_get_bus_info(struct e1000_hw *hw)
6489 hw->bus_width = e1000_bus_width_pciex_1; 6489 hw->bus_width = e1000_bus_width_pciex_1;
6490 break; 6490 break;
6491 default: 6491 default:
6492 status = E1000_READ_REG(hw, STATUS); 6492 status = er32(STATUS);
6493 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 6493 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6494 e1000_bus_type_pcix : e1000_bus_type_pci; 6494 e1000_bus_type_pcix : e1000_bus_type_pci;
6495 6495
@@ -7114,7 +7114,7 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7114 /* MAC writes into PHY register based on the state transition 7114 /* MAC writes into PHY register based on the state transition
7115 * and start auto-negotiation. SW driver can overwrite the settings 7115 * and start auto-negotiation. SW driver can overwrite the settings
7116 * in CSR PHY power control E1000_PHY_CTRL register. */ 7116 * in CSR PHY power control E1000_PHY_CTRL register. */
7117 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7117 phy_ctrl = er32(PHY_CTRL);
7118 } else { 7118 } else {
7119 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7119 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7120 if (ret_val) 7120 if (ret_val)
@@ -7131,7 +7131,7 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7131 } else { 7131 } else {
7132 if (hw->mac_type == e1000_ich8lan) { 7132 if (hw->mac_type == e1000_ich8lan) {
7133 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 7133 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7134 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7134 ew32(PHY_CTRL, phy_ctrl);
7135 } else { 7135 } else {
7136 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7136 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7137 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7137 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
@@ -7182,7 +7182,7 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
7182 } else { 7182 } else {
7183 if (hw->mac_type == e1000_ich8lan) { 7183 if (hw->mac_type == e1000_ich8lan) {
7184 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 7184 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7185 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7185 ew32(PHY_CTRL, phy_ctrl);
7186 } else { 7186 } else {
7187 phy_data |= IGP02E1000_PM_D3_LPLU; 7187 phy_data |= IGP02E1000_PM_D3_LPLU;
7188 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7188 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
@@ -7231,7 +7231,7 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7231 return E1000_SUCCESS; 7231 return E1000_SUCCESS;
7232 7232
7233 if (hw->mac_type == e1000_ich8lan) { 7233 if (hw->mac_type == e1000_ich8lan) {
7234 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 7234 phy_ctrl = er32(PHY_CTRL);
7235 } else { 7235 } else {
7236 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7236 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7237 if (ret_val) 7237 if (ret_val)
@@ -7241,7 +7241,7 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7241 if (!active) { 7241 if (!active) {
7242 if (hw->mac_type == e1000_ich8lan) { 7242 if (hw->mac_type == e1000_ich8lan) {
7243 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 7243 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7244 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7244 ew32(PHY_CTRL, phy_ctrl);
7245 } else { 7245 } else {
7246 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7246 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7247 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7247 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
@@ -7282,7 +7282,7 @@ static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
7282 7282
7283 if (hw->mac_type == e1000_ich8lan) { 7283 if (hw->mac_type == e1000_ich8lan) {
7284 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 7284 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7285 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 7285 ew32(PHY_CTRL, phy_ctrl);
7286 } else { 7286 } else {
7287 phy_data |= IGP02E1000_PM_D0_LPLU; 7287 phy_data |= IGP02E1000_PM_D0_LPLU;
7288 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7288 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
@@ -7404,14 +7404,14 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
7404 u8 i; 7404 u8 i;
7405 7405
7406 /* Check that the host interface is enabled. */ 7406 /* Check that the host interface is enabled. */
7407 hicr = E1000_READ_REG(hw, HICR); 7407 hicr = er32(HICR);
7408 if ((hicr & E1000_HICR_EN) == 0) { 7408 if ((hicr & E1000_HICR_EN) == 0) {
7409 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 7409 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7410 return -E1000_ERR_HOST_INTERFACE_COMMAND; 7410 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7411 } 7411 }
7412 /* check the previous command is completed */ 7412 /* check the previous command is completed */
7413 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 7413 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7414 hicr = E1000_READ_REG(hw, HICR); 7414 hicr = er32(HICR);
7415 if (!(hicr & E1000_HICR_C)) 7415 if (!(hicr & E1000_HICR_C))
7416 break; 7416 break;
7417 mdelay(1); 7417 mdelay(1);
@@ -7524,7 +7524,7 @@ static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
7524 /* The device driver writes the relevant command block into the ram area. */ 7524 /* The device driver writes the relevant command block into the ram area. */
7525 for (i = 0; i < length; i++) { 7525 for (i = 0; i < length; i++) {
7526 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i)); 7526 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((u32 *) hdr + i));
7527 E1000_WRITE_FLUSH(hw); 7527 E1000_WRITE_FLUSH();
7528 } 7528 }
7529 7529
7530 return E1000_SUCCESS; 7530 return E1000_SUCCESS;
@@ -7541,9 +7541,9 @@ static s32 e1000_mng_write_commit(struct e1000_hw *hw)
7541{ 7541{
7542 u32 hicr; 7542 u32 hicr;
7543 7543
7544 hicr = E1000_READ_REG(hw, HICR); 7544 hicr = er32(HICR);
7545 /* Setting this bit tells the ARC that a new command is pending. */ 7545 /* Setting this bit tells the ARC that a new command is pending. */
7546 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); 7546 ew32(HICR, hicr | E1000_HICR_C);
7547 7547
7548 return E1000_SUCCESS; 7548 return E1000_SUCCESS;
7549} 7549}
@@ -7558,7 +7558,7 @@ bool e1000_check_mng_mode(struct e1000_hw *hw)
7558{ 7558{
7559 u32 fwsm; 7559 u32 fwsm;
7560 7560
7561 fwsm = E1000_READ_REG(hw, FWSM); 7561 fwsm = er32(FWSM);
7562 7562
7563 if (hw->mac_type == e1000_ich8lan) { 7563 if (hw->mac_type == e1000_ich8lan) {
7564 if ((fwsm & E1000_FWSM_MODE_MASK) == 7564 if ((fwsm & E1000_FWSM_MODE_MASK) ==
@@ -7671,14 +7671,14 @@ u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7671 u32 fwsm, factps; 7671 u32 fwsm, factps;
7672 7672
7673 if (hw->asf_firmware_present) { 7673 if (hw->asf_firmware_present) {
7674 manc = E1000_READ_REG(hw, MANC); 7674 manc = er32(MANC);
7675 7675
7676 if (!(manc & E1000_MANC_RCV_TCO_EN) || 7676 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7677 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 7677 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7678 return false; 7678 return false;
7679 if (e1000_arc_subsystem_valid(hw)) { 7679 if (e1000_arc_subsystem_valid(hw)) {
7680 fwsm = E1000_READ_REG(hw, FWSM); 7680 fwsm = er32(FWSM);
7681 factps = E1000_READ_REG(hw, FACTPS); 7681 factps = er32(FACTPS);
7682 7682
7683 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == 7683 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7684 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) 7684 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
@@ -7792,9 +7792,9 @@ static void e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7792 if (hw->bus_type != e1000_bus_type_pci_express) 7792 if (hw->bus_type != e1000_bus_type_pci_express)
7793 return; 7793 return;
7794 7794
7795 ctrl = E1000_READ_REG(hw, CTRL); 7795 ctrl = er32(CTRL);
7796 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 7796 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7797 E1000_WRITE_REG(hw, CTRL, ctrl); 7797 ew32(CTRL, ctrl);
7798} 7798}
7799 7799
7800/******************************************************************************* 7800/*******************************************************************************
@@ -7820,7 +7820,7 @@ s32 e1000_disable_pciex_master(struct e1000_hw *hw)
7820 e1000_set_pci_express_master_disable(hw); 7820 e1000_set_pci_express_master_disable(hw);
7821 7821
7822 while (timeout) { 7822 while (timeout) {
7823 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 7823 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7824 break; 7824 break;
7825 else 7825 else
7826 udelay(100); 7826 udelay(100);
@@ -7861,7 +7861,7 @@ static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
7861 case e1000_80003es2lan: 7861 case e1000_80003es2lan:
7862 case e1000_ich8lan: 7862 case e1000_ich8lan:
7863 while (timeout) { 7863 while (timeout) {
7864 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 7864 if (er32(EECD) & E1000_EECD_AUTO_RD)
7865 break; 7865 break;
7866 else msleep(1); 7866 else msleep(1);
7867 timeout--; 7867 timeout--;
@@ -7905,13 +7905,13 @@ static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7905 break; 7905 break;
7906 case e1000_80003es2lan: 7906 case e1000_80003es2lan:
7907 /* Separate *_CFG_DONE_* bit for each port */ 7907 /* Separate *_CFG_DONE_* bit for each port */
7908 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7908 if (er32(STATUS) & E1000_STATUS_FUNC_1)
7909 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; 7909 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7910 /* Fall Through */ 7910 /* Fall Through */
7911 case e1000_82571: 7911 case e1000_82571:
7912 case e1000_82572: 7912 case e1000_82572:
7913 while (timeout) { 7913 while (timeout) {
7914 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 7914 if (er32(EEMNGCTL) & cfg_mask)
7915 break; 7915 break;
7916 else 7916 else
7917 msleep(1); 7917 msleep(1);
@@ -7957,11 +7957,11 @@ static s32 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7957 /* Get the FW semaphore. */ 7957 /* Get the FW semaphore. */
7958 timeout = hw->eeprom.word_size + 1; 7958 timeout = hw->eeprom.word_size + 1;
7959 while (timeout) { 7959 while (timeout) {
7960 swsm = E1000_READ_REG(hw, SWSM); 7960 swsm = er32(SWSM);
7961 swsm |= E1000_SWSM_SWESMBI; 7961 swsm |= E1000_SWSM_SWESMBI;
7962 E1000_WRITE_REG(hw, SWSM, swsm); 7962 ew32(SWSM, swsm);
7963 /* if we managed to set the bit we got the semaphore. */ 7963 /* if we managed to set the bit we got the semaphore. */
7964 swsm = E1000_READ_REG(hw, SWSM); 7964 swsm = er32(SWSM);
7965 if (swsm & E1000_SWSM_SWESMBI) 7965 if (swsm & E1000_SWSM_SWESMBI)
7966 break; 7966 break;
7967 7967
@@ -7996,13 +7996,13 @@ static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7996 if (!hw->eeprom_semaphore_present) 7996 if (!hw->eeprom_semaphore_present)
7997 return; 7997 return;
7998 7998
7999 swsm = E1000_READ_REG(hw, SWSM); 7999 swsm = er32(SWSM);
8000 if (hw->mac_type == e1000_80003es2lan) { 8000 if (hw->mac_type == e1000_80003es2lan) {
8001 /* Release both semaphores. */ 8001 /* Release both semaphores. */
8002 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8002 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8003 } else 8003 } else
8004 swsm &= ~(E1000_SWSM_SWESMBI); 8004 swsm &= ~(E1000_SWSM_SWESMBI);
8005 E1000_WRITE_REG(hw, SWSM, swsm); 8005 ew32(SWSM, swsm);
8006} 8006}
8007 8007
8008/*************************************************************************** 8008/***************************************************************************
@@ -8027,7 +8027,7 @@ static s32 e1000_get_software_semaphore(struct e1000_hw *hw)
8027 } 8027 }
8028 8028
8029 while (timeout) { 8029 while (timeout) {
8030 swsm = E1000_READ_REG(hw, SWSM); 8030 swsm = er32(SWSM);
8031 /* If SMBI bit cleared, it is now set and we hold the semaphore */ 8031 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8032 if (!(swsm & E1000_SWSM_SMBI)) 8032 if (!(swsm & E1000_SWSM_SMBI))
8033 break; 8033 break;
@@ -8060,10 +8060,10 @@ static void e1000_release_software_semaphore(struct e1000_hw *hw)
8060 return; 8060 return;
8061 } 8061 }
8062 8062
8063 swsm = E1000_READ_REG(hw, SWSM); 8063 swsm = er32(SWSM);
8064 /* Release the SW semaphores.*/ 8064 /* Release the SW semaphores.*/
8065 swsm &= ~E1000_SWSM_SMBI; 8065 swsm &= ~E1000_SWSM_SMBI;
8066 E1000_WRITE_REG(hw, SWSM, swsm); 8066 ew32(SWSM, swsm);
8067} 8067}
8068 8068
8069/****************************************************************************** 8069/******************************************************************************
@@ -8083,13 +8083,13 @@ s32 e1000_check_phy_reset_block(struct e1000_hw *hw)
8083 u32 fwsm = 0; 8083 u32 fwsm = 0;
8084 8084
8085 if (hw->mac_type == e1000_ich8lan) { 8085 if (hw->mac_type == e1000_ich8lan) {
8086 fwsm = E1000_READ_REG(hw, FWSM); 8086 fwsm = er32(FWSM);
8087 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS 8087 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8088 : E1000_BLK_PHY_RESET; 8088 : E1000_BLK_PHY_RESET;
8089 } 8089 }
8090 8090
8091 if (hw->mac_type > e1000_82547_rev_2) 8091 if (hw->mac_type > e1000_82547_rev_2)
8092 manc = E1000_READ_REG(hw, MANC); 8092 manc = er32(MANC);
8093 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8093 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8094 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8094 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8095} 8095}
@@ -8108,7 +8108,7 @@ static u8 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8108 case e1000_82572: 8108 case e1000_82572:
8109 case e1000_82573: 8109 case e1000_82573:
8110 case e1000_80003es2lan: 8110 case e1000_80003es2lan:
8111 fwsm = E1000_READ_REG(hw, FWSM); 8111 fwsm = er32(FWSM);
8112 if ((fwsm & E1000_FWSM_MODE_MASK) != 0) 8112 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8113 return true; 8113 return true;
8114 break; 8114 break;
@@ -8143,19 +8143,19 @@ static s32 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, u32 no_snoop)
8143 return E1000_SUCCESS; 8143 return E1000_SUCCESS;
8144 8144
8145 if (no_snoop) { 8145 if (no_snoop) {
8146 gcr_reg = E1000_READ_REG(hw, GCR); 8146 gcr_reg = er32(GCR);
8147 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8147 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8148 gcr_reg |= no_snoop; 8148 gcr_reg |= no_snoop;
8149 E1000_WRITE_REG(hw, GCR, gcr_reg); 8149 ew32(GCR, gcr_reg);
8150 } 8150 }
8151 if (hw->mac_type == e1000_ich8lan) { 8151 if (hw->mac_type == e1000_ich8lan) {
8152 u32 ctrl_ext; 8152 u32 ctrl_ext;
8153 8153
8154 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); 8154 ew32(GCR, PCI_EX_82566_SNOOP_ALL);
8155 8155
8156 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 8156 ctrl_ext = er32(CTRL_EXT);
8157 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 8157 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8158 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 8158 ew32(CTRL_EXT, ctrl_ext);
8159 } 8159 }
8160 8160
8161 return E1000_SUCCESS; 8161 return E1000_SUCCESS;
@@ -8179,11 +8179,11 @@ static s32 e1000_get_software_flag(struct e1000_hw *hw)
8179 8179
8180 if (hw->mac_type == e1000_ich8lan) { 8180 if (hw->mac_type == e1000_ich8lan) {
8181 while (timeout) { 8181 while (timeout) {
8182 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8182 extcnf_ctrl = er32(EXTCNF_CTRL);
8183 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 8183 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8184 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8184 ew32(EXTCNF_CTRL, extcnf_ctrl);
8185 8185
8186 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 8186 extcnf_ctrl = er32(EXTCNF_CTRL);
8187 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 8187 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8188 break; 8188 break;
8189 mdelay(1); 8189 mdelay(1);
@@ -8215,9 +8215,9 @@ static void e1000_release_software_flag(struct e1000_hw *hw)
8215 DEBUGFUNC("e1000_release_software_flag"); 8215 DEBUGFUNC("e1000_release_software_flag");
8216 8216
8217 if (hw->mac_type == e1000_ich8lan) { 8217 if (hw->mac_type == e1000_ich8lan) {
8218 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); 8218 extcnf_ctrl= er32(EXTCNF_CTRL);
8219 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 8219 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8220 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 8220 ew32(EXTCNF_CTRL, extcnf_ctrl);
8221 } 8221 }
8222 8222
8223 return; 8223 return;
@@ -8248,7 +8248,7 @@ static s32 e1000_read_eeprom_ich8(struct e1000_hw *hw, u16 offset, u16 words,
8248 * to be updated with each read. 8248 * to be updated with each read.
8249 */ 8249 */
8250 /* Value of bit 22 corresponds to the flash bank we're on. */ 8250 /* Value of bit 22 corresponds to the flash bank we're on. */
8251 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; 8251 flash_bank = (er32(EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8252 8252
8253 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ 8253 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8254 bank_offset = flash_bank * (hw->flash_bank_size * 2); 8254 bank_offset = flash_bank * (hw->flash_bank_size * 2);
@@ -8813,32 +8813,32 @@ static s32 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8813 return E1000_SUCCESS; 8813 return E1000_SUCCESS;
8814 8814
8815 /* Check if SW needs configure the PHY */ 8815 /* Check if SW needs configure the PHY */
8816 reg_data = E1000_READ_REG(hw, FEXTNVM); 8816 reg_data = er32(FEXTNVM);
8817 if (!(reg_data & FEXTNVM_SW_CONFIG)) 8817 if (!(reg_data & FEXTNVM_SW_CONFIG))
8818 return E1000_SUCCESS; 8818 return E1000_SUCCESS;
8819 8819
8820 /* Wait for basic configuration completes before proceeding*/ 8820 /* Wait for basic configuration completes before proceeding*/
8821 loop = 0; 8821 loop = 0;
8822 do { 8822 do {
8823 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 8823 reg_data = er32(STATUS) & E1000_STATUS_LAN_INIT_DONE;
8824 udelay(100); 8824 udelay(100);
8825 loop++; 8825 loop++;
8826 } while ((!reg_data) && (loop < 50)); 8826 } while ((!reg_data) && (loop < 50));
8827 8827
8828 /* Clear the Init Done bit for the next init event */ 8828 /* Clear the Init Done bit for the next init event */
8829 reg_data = E1000_READ_REG(hw, STATUS); 8829 reg_data = er32(STATUS);
8830 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 8830 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8831 E1000_WRITE_REG(hw, STATUS, reg_data); 8831 ew32(STATUS, reg_data);
8832 8832
8833 /* Make sure HW does not configure LCD from PHY extended configuration 8833 /* Make sure HW does not configure LCD from PHY extended configuration
8834 before SW configuration */ 8834 before SW configuration */
8835 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8835 reg_data = er32(EXTCNF_CTRL);
8836 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 8836 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8837 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 8837 reg_data = er32(EXTCNF_SIZE);
8838 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 8838 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8839 cnf_size >>= 16; 8839 cnf_size >>= 16;
8840 if (cnf_size) { 8840 if (cnf_size) {
8841 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 8841 reg_data = er32(EXTCNF_CTRL);
8842 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 8842 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8843 /* cnf_base_addr is in DWORD */ 8843 /* cnf_base_addr is in DWORD */
8844 cnf_base_addr >>= 16; 8844 cnf_base_addr >>= 16;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-25 00:31:51 -0400