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authorBarry Grussling <barry@grussling.com>2013-01-08 11:05:53 -0500
committerDavid S. Miller <davem@davemloft.net>2013-01-10 03:04:34 -0500
commit3675c8d7144e91d9a2a1f6f12e576cb92e06f352 (patch)
treefb113eb9c6445686b169f57f9bd18ba9f70a2416 /drivers/net/dsa/mv88e6131.c
parenta0376db0f234a8053100bddf26c073be79546b2b (diff)
DSA: Convert DSA comments to network-style comments
Convert DSA driver comments to network-style comments as reported by checkpatch.pl. Fix spelling error. Signed-off-by: Barry Grussling <barry@grussling.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6131.c')
-rw-r--r--drivers/net/dsa/mv88e6131.c102
1 files changed, 30 insertions, 72 deletions
diff --git a/drivers/net/dsa/mv88e6131.c b/drivers/net/dsa/mv88e6131.c
index 55888b06d8b4..b61381887587 100644
--- a/drivers/net/dsa/mv88e6131.c
+++ b/drivers/net/dsa/mv88e6131.c
@@ -15,9 +15,7 @@
15#include <net/dsa.h> 15#include <net/dsa.h>
16#include "mv88e6xxx.h" 16#include "mv88e6xxx.h"
17 17
18/* 18/* Switch product IDs */
19 * Switch product IDs
20 */
21#define ID_6085 0x04a0 19#define ID_6085 0x04a0
22#define ID_6095 0x0950 20#define ID_6095 0x0950
23#define ID_6131 0x1060 21#define ID_6131 0x1060
@@ -45,27 +43,19 @@ static int mv88e6131_switch_reset(struct dsa_switch *ds)
45 int i; 43 int i;
46 int ret; 44 int ret;
47 45
48 /* 46 /* Set all ports to the disabled state. */
49 * Set all ports to the disabled state.
50 */
51 for (i = 0; i < 11; i++) { 47 for (i = 0; i < 11; i++) {
52 ret = REG_READ(REG_PORT(i), 0x04); 48 ret = REG_READ(REG_PORT(i), 0x04);
53 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 49 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
54 } 50 }
55 51
56 /* 52 /* Wait for transmit queues to drain. */
57 * Wait for transmit queues to drain.
58 */
59 msleep(2); 53 msleep(2);
60 54
61 /* 55 /* Reset the switch. */
62 * Reset the switch.
63 */
64 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); 56 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
65 57
66 /* 58 /* Wait up to one second for reset to complete. */
67 * Wait up to one second for reset to complete.
68 */
69 for (i = 0; i < 1000; i++) { 59 for (i = 0; i < 1000; i++) {
70 ret = REG_READ(REG_GLOBAL, 0x00); 60 ret = REG_READ(REG_GLOBAL, 0x00);
71 if ((ret & 0xc800) == 0xc800) 61 if ((ret & 0xc800) == 0xc800)
@@ -84,42 +74,34 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
84 int ret; 74 int ret;
85 int i; 75 int i;
86 76
87 /* 77 /* Enable the PHY polling unit, don't discard packets with
88 * Enable the PHY polling unit, don't discard packets with
89 * excessive collisions, use a weighted fair queueing scheme 78 * excessive collisions, use a weighted fair queueing scheme
90 * to arbitrate between packet queues, set the maximum frame 79 * to arbitrate between packet queues, set the maximum frame
91 * size to 1632, and mask all interrupt sources. 80 * size to 1632, and mask all interrupt sources.
92 */ 81 */
93 REG_WRITE(REG_GLOBAL, 0x04, 0x4400); 82 REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
94 83
95 /* 84 /* Set the default address aging time to 5 minutes, and
96 * Set the default address aging time to 5 minutes, and
97 * enable address learn messages to be sent to all message 85 * enable address learn messages to be sent to all message
98 * ports. 86 * ports.
99 */ 87 */
100 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); 88 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
101 89
102 /* 90 /* Configure the priority mapping registers. */
103 * Configure the priority mapping registers.
104 */
105 ret = mv88e6xxx_config_prio(ds); 91 ret = mv88e6xxx_config_prio(ds);
106 if (ret < 0) 92 if (ret < 0)
107 return ret; 93 return ret;
108 94
109 /* 95 /* Set the VLAN ethertype to 0x8100. */
110 * Set the VLAN ethertype to 0x8100.
111 */
112 REG_WRITE(REG_GLOBAL, 0x19, 0x8100); 96 REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
113 97
114 /* 98 /* Disable ARP mirroring, and configure the upstream port as
115 * Disable ARP mirroring, and configure the upstream port as
116 * the port to which ingress and egress monitor frames are to 99 * the port to which ingress and egress monitor frames are to
117 * be sent. 100 * be sent.
118 */ 101 */
119 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); 102 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
120 103
121 /* 104 /* Disable cascade port functionality unless this device
122 * Disable cascade port functionality unless this device
123 * is used in a cascade configuration, and set the switch's 105 * is used in a cascade configuration, and set the switch's
124 * DSA device number. 106 * DSA device number.
125 */ 107 */
@@ -128,23 +110,19 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
128 else 110 else
129 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); 111 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
130 112
131 /* 113 /* Send all frames with destination addresses matching
132 * Send all frames with destination addresses matching
133 * 01:80:c2:00:00:0x to the CPU port. 114 * 01:80:c2:00:00:0x to the CPU port.
134 */ 115 */
135 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); 116 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
136 117
137 /* 118 /* Ignore removed tag data on doubly tagged packets, disable
138 * Ignore removed tag data on doubly tagged packets, disable
139 * flow control messages, force flow control priority to the 119 * flow control messages, force flow control priority to the
140 * highest, and send all special multicast frames to the CPU 120 * highest, and send all special multicast frames to the CPU
141 * port at the highest priority. 121 * port at the highest priority.
142 */ 122 */
143 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); 123 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
144 124
145 /* 125 /* Program the DSA routing table. */
146 * Program the DSA routing table.
147 */
148 for (i = 0; i < 32; i++) { 126 for (i = 0; i < 32; i++) {
149 int nexthop; 127 int nexthop;
150 128
@@ -155,20 +133,15 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
155 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); 133 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
156 } 134 }
157 135
158 /* 136 /* Clear all trunk masks. */
159 * Clear all trunk masks.
160 */
161 for (i = 0; i < 8; i++) 137 for (i = 0; i < 8; i++)
162 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff); 138 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
163 139
164 /* 140 /* Clear all trunk mappings. */
165 * Clear all trunk mappings.
166 */
167 for (i = 0; i < 16; i++) 141 for (i = 0; i < 16; i++)
168 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); 142 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
169 143
170 /* 144 /* Force the priority of IGMP/MLD snoop frames and ARP frames
171 * Force the priority of IGMP/MLD snoop frames and ARP frames
172 * to the highest setting. 145 * to the highest setting.
173 */ 146 */
174 REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff); 147 REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
@@ -182,8 +155,7 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
182 int addr = REG_PORT(p); 155 int addr = REG_PORT(p);
183 u16 val; 156 u16 val;
184 157
185 /* 158 /* MAC Forcing register: don't force link, speed, duplex
186 * MAC Forcing register: don't force link, speed, duplex
187 * or flow control state to any particular values on physical 159 * or flow control state to any particular values on physical
188 * ports, but force the CPU port and all DSA ports to 1000 Mb/s 160 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
189 * (100 Mb/s on 6085) full duplex. 161 * (100 Mb/s on 6085) full duplex.
@@ -196,8 +168,7 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
196 else 168 else
197 REG_WRITE(addr, 0x01, 0x0003); 169 REG_WRITE(addr, 0x01, 0x0003);
198 170
199 /* 171 /* Port Control: disable Core Tag, disable Drop-on-Lock,
200 * Port Control: disable Core Tag, disable Drop-on-Lock,
201 * transmit frames unmodified, disable Header mode, 172 * transmit frames unmodified, disable Header mode,
202 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN 173 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
203 * tunneling, determine priority by looking at 802.1p and 174 * tunneling, determine priority by looking at 802.1p and
@@ -214,8 +185,7 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
214 val = 0x0433; 185 val = 0x0433;
215 if (p == dsa_upstream_port(ds)) { 186 if (p == dsa_upstream_port(ds)) {
216 val |= 0x0104; 187 val |= 0x0104;
217 /* 188 /* On 6085, unknown multicast forward is controlled
218 * On 6085, unknown multicast forward is controlled
219 * here rather than in Port Control 2 register. 189 * here rather than in Port Control 2 register.
220 */ 190 */
221 if (ps->id == ID_6085) 191 if (ps->id == ID_6085)
@@ -225,14 +195,12 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
225 val |= 0x0100; 195 val |= 0x0100;
226 REG_WRITE(addr, 0x04, val); 196 REG_WRITE(addr, 0x04, val);
227 197
228 /* 198 /* Port Control 1: disable trunking. Also, if this is the
229 * Port Control 1: disable trunking. Also, if this is the
230 * CPU port, enable learn messages to be sent to this port. 199 * CPU port, enable learn messages to be sent to this port.
231 */ 200 */
232 REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); 201 REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
233 202
234 /* 203 /* Port based VLAN map: give each port its own address
235 * Port based VLAN map: give each port its own address
236 * database, allow the CPU port to talk to each of the 'real' 204 * database, allow the CPU port to talk to each of the 'real'
237 * ports, and allow each of the 'real' ports to only talk to 205 * ports, and allow each of the 'real' ports to only talk to
238 * the upstream port. 206 * the upstream port.
@@ -244,14 +212,12 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
244 val |= 1 << dsa_upstream_port(ds); 212 val |= 1 << dsa_upstream_port(ds);
245 REG_WRITE(addr, 0x06, val); 213 REG_WRITE(addr, 0x06, val);
246 214
247 /* 215 /* Default VLAN ID and priority: don't set a default VLAN
248 * Default VLAN ID and priority: don't set a default VLAN
249 * ID, and set the default packet priority to zero. 216 * ID, and set the default packet priority to zero.
250 */ 217 */
251 REG_WRITE(addr, 0x07, 0x0000); 218 REG_WRITE(addr, 0x07, 0x0000);
252 219
253 /* 220 /* Port Control 2: don't force a good FCS, don't use
254 * Port Control 2: don't force a good FCS, don't use
255 * VLAN-based, source address-based or destination 221 * VLAN-based, source address-based or destination
256 * address-based priority overrides, don't let the switch 222 * address-based priority overrides, don't let the switch
257 * add or strip 802.1q tags, don't discard tagged or 223 * add or strip 802.1q tags, don't discard tagged or
@@ -264,8 +230,7 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
264 * forwarding of unknown multicast addresses. 230 * forwarding of unknown multicast addresses.
265 */ 231 */
266 if (ps->id == ID_6085) 232 if (ps->id == ID_6085)
267 /* 233 /* on 6085, bits 3:0 are reserved, bit 6 control ARP
268 * on 6085, bits 3:0 are reserved, bit 6 control ARP
269 * mirroring, and multicast forward is handled in 234 * mirroring, and multicast forward is handled in
270 * Port Control register. 235 * Port Control register.
271 */ 236 */
@@ -277,32 +242,25 @@ static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
277 REG_WRITE(addr, 0x08, val); 242 REG_WRITE(addr, 0x08, val);
278 } 243 }
279 244
280 /* 245 /* Rate Control: disable ingress rate limiting. */
281 * Rate Control: disable ingress rate limiting.
282 */
283 REG_WRITE(addr, 0x09, 0x0000); 246 REG_WRITE(addr, 0x09, 0x0000);
284 247
285 /* 248 /* Rate Control 2: disable egress rate limiting. */
286 * Rate Control 2: disable egress rate limiting.
287 */
288 REG_WRITE(addr, 0x0a, 0x0000); 249 REG_WRITE(addr, 0x0a, 0x0000);
289 250
290 /* 251 /* Port Association Vector: when learning source addresses
291 * Port Association Vector: when learning source addresses
292 * of packets, add the address to the address database using 252 * of packets, add the address to the address database using
293 * a port bitmap that has only the bit for this port set and 253 * a port bitmap that has only the bit for this port set and
294 * the other bits clear. 254 * the other bits clear.
295 */ 255 */
296 REG_WRITE(addr, 0x0b, 1 << p); 256 REG_WRITE(addr, 0x0b, 1 << p);
297 257
298 /* 258 /* Tag Remap: use an identity 802.1p prio -> switch prio
299 * Tag Remap: use an identity 802.1p prio -> switch prio
300 * mapping. 259 * mapping.
301 */ 260 */
302 REG_WRITE(addr, 0x18, 0x3210); 261 REG_WRITE(addr, 0x18, 0x3210);
303 262
304 /* 263 /* Tag Remap 2: use an identity 802.1p prio -> switch prio
305 * Tag Remap 2: use an identity 802.1p prio -> switch prio
306 * mapping. 264 * mapping.
307 */ 265 */
308 REG_WRITE(addr, 0x19, 0x7654); 266 REG_WRITE(addr, 0x19, 0x7654);