diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
commit | 6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch) | |
tree | df0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/depca.h | |
parent | 7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff) |
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/depca.h')
-rw-r--r-- | drivers/net/depca.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/depca.h b/drivers/net/depca.h index 11785275a669..ee42648dbde6 100644 --- a/drivers/net/depca.h +++ b/drivers/net/depca.h | |||
@@ -20,17 +20,17 @@ | |||
20 | #define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */ | 20 | #define DEPCA_RBSA ioaddr+0x0e /* RAM buffer starting address (2k buff.) */ |
21 | 21 | ||
22 | /* | 22 | /* |
23 | ** These are LANCE registers addressable through DEPCA_ADDR | 23 | ** These are LANCE registers addressable through DEPCA_ADDR |
24 | */ | 24 | */ |
25 | #define CSR0 0 | 25 | #define CSR0 0 |
26 | #define CSR1 1 | 26 | #define CSR1 1 |
27 | #define CSR2 2 | 27 | #define CSR2 2 |
28 | #define CSR3 3 | 28 | #define CSR3 3 |
29 | 29 | ||
30 | /* | 30 | /* |
31 | ** NETWORK INTERFACE CSR (NI_CSR) bit definitions | 31 | ** NETWORK INTERFACE CSR (NI_CSR) bit definitions |
32 | */ | 32 | */ |
33 | 33 | ||
34 | #define TO 0x0100 /* Time Out for remote boot */ | 34 | #define TO 0x0100 /* Time Out for remote boot */ |
35 | #define SHE 0x0080 /* SHadow memory Enable */ | 35 | #define SHE 0x0080 /* SHadow memory Enable */ |
36 | #define BS 0x0040 /* Bank Select */ | 36 | #define BS 0x0040 /* Bank Select */ |
@@ -42,8 +42,8 @@ | |||
42 | #define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */ | 42 | #define IEN 0x0002 /* Interrupt tristate ENable (1->enable) */ |
43 | #define LED 0x0001 /* LED control */ | 43 | #define LED 0x0001 /* LED control */ |
44 | 44 | ||
45 | /* | 45 | /* |
46 | ** Control and Status Register 0 (CSR0) bit definitions | 46 | ** Control and Status Register 0 (CSR0) bit definitions |
47 | */ | 47 | */ |
48 | 48 | ||
49 | #define ERR 0x8000 /* Error summary */ | 49 | #define ERR 0x8000 /* Error summary */ |
@@ -74,7 +74,7 @@ | |||
74 | #define BCON 0x0001 /* Byte CONtrol */ | 74 | #define BCON 0x0001 /* Byte CONtrol */ |
75 | 75 | ||
76 | /* | 76 | /* |
77 | ** Initialization Block Mode Register | 77 | ** Initialization Block Mode Register |
78 | */ | 78 | */ |
79 | 79 | ||
80 | #define PROM 0x8000 /* Promiscuous Mode */ | 80 | #define PROM 0x8000 /* Promiscuous Mode */ |
@@ -88,7 +88,7 @@ | |||
88 | #define DRX 0x0001 /* Disable the Receiver */ | 88 | #define DRX 0x0001 /* Disable the Receiver */ |
89 | 89 | ||
90 | /* | 90 | /* |
91 | ** Receive Message Descriptor 1 (RMD1) bit definitions. | 91 | ** Receive Message Descriptor 1 (RMD1) bit definitions. |
92 | */ | 92 | */ |
93 | 93 | ||
94 | #define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ | 94 | #define R_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ |
@@ -101,7 +101,7 @@ | |||
101 | #define R_ENP 0x0100 /* End of Packet */ | 101 | #define R_ENP 0x0100 /* End of Packet */ |
102 | 102 | ||
103 | /* | 103 | /* |
104 | ** Transmit Message Descriptor 1 (TMD1) bit definitions. | 104 | ** Transmit Message Descriptor 1 (TMD1) bit definitions. |
105 | */ | 105 | */ |
106 | 106 | ||
107 | #define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ | 107 | #define T_OWN 0x80000000 /* Owner bit 0 = host, 1 = lance */ |
@@ -125,10 +125,10 @@ | |||
125 | #define TMD3_LCAR 0x0800 /* Loss of CARrier */ | 125 | #define TMD3_LCAR 0x0800 /* Loss of CARrier */ |
126 | #define TMD3_RTRY 0x0400 /* ReTRY error */ | 126 | #define TMD3_RTRY 0x0400 /* ReTRY error */ |
127 | 127 | ||
128 | /* | 128 | /* |
129 | ** EISA configuration Register (CNFG) bit definitions | 129 | ** EISA configuration Register (CNFG) bit definitions |
130 | */ | 130 | */ |
131 | 131 | ||
132 | #define TIMEOUT 0x0100 /* 0:2.5 mins, 1: 30 secs */ | 132 | #define TIMEOUT 0x0100 /* 0:2.5 mins, 1: 30 secs */ |
133 | #define REMOTE 0x0080 /* Remote Boot Enable -> 1 */ | 133 | #define REMOTE 0x0080 /* Remote Boot Enable -> 1 */ |
134 | #define IRQ11 0x0040 /* Enable -> 1 */ | 134 | #define IRQ11 0x0040 /* Enable -> 1 */ |
@@ -165,8 +165,8 @@ struct depca_ioctl { | |||
165 | unsigned char __user *data; /* Pointer to the data buffer */ | 165 | unsigned char __user *data; /* Pointer to the data buffer */ |
166 | }; | 166 | }; |
167 | 167 | ||
168 | /* | 168 | /* |
169 | ** Recognised commands for the driver | 169 | ** Recognised commands for the driver |
170 | */ | 170 | */ |
171 | #define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */ | 171 | #define DEPCA_GET_HWADDR 0x01 /* Get the hardware address */ |
172 | #define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */ | 172 | #define DEPCA_SET_HWADDR 0x02 /* Get the hardware address */ |