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authorCyril Chemparathy <cyril@ti.com>2010-09-15 10:11:27 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-09-24 10:40:30 -0400
commit7b3742aff1a9946b9b25f16d6a7ca22c10926391 (patch)
treee4e71aa88a9b019df0970db1c47bda87cad9ce54 /drivers/net/davinci_emac.c
parent3b2a40a0a05cdf4f00f100c55b463d86ae14c383 (diff)
net: davinci_emac: cleanup unused mdio emac code
This patch removes code that has been rendered useless by the previous patches in this series. Signed-off-by: Cyril Chemparathy <cyril@ti.com> Acked-by: David S. Miller <davem@davemloft.net> Tested-by: Michael Williamson <michael.williamson@criticallink.com> Tested-by: Caglar Akyuz <caglarakyuz@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'drivers/net/davinci_emac.c')
-rw-r--r--drivers/net/davinci_emac.c107
1 files changed, 0 insertions, 107 deletions
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 997f5995fce1..d4298cb23b4d 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -113,7 +113,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
113#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 113#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
114#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 114#define EMAC_DEF_TX_CH (0) /* Default 0th channel */
115#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 115#define EMAC_DEF_RX_CH (0) /* Default 0th channel */
116#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */
117#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 116#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
118#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 117#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
119#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 118#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
@@ -303,25 +302,6 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
303#define EMAC_DM644X_INTMIN_INTVL 0x1 302#define EMAC_DM644X_INTMIN_INTVL 0x1
304#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 303#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
305 304
306/* EMAC MDIO related */
307/* Mask & Control defines */
308#define MDIO_CONTROL_CLKDIV (0xFF)
309#define MDIO_CONTROL_ENABLE BIT(30)
310#define MDIO_USERACCESS_GO BIT(31)
311#define MDIO_USERACCESS_WRITE BIT(30)
312#define MDIO_USERACCESS_READ (0)
313#define MDIO_USERACCESS_REGADR (0x1F << 21)
314#define MDIO_USERACCESS_PHYADR (0x1F << 16)
315#define MDIO_USERACCESS_DATA (0xFFFF)
316#define MDIO_USERPHYSEL_LINKSEL BIT(7)
317#define MDIO_VER_MODID (0xFFFF << 16)
318#define MDIO_VER_REVMAJ (0xFF << 8)
319#define MDIO_VER_REVMIN (0xFF)
320
321#define MDIO_USERACCESS(inst) (0x80 + (inst * 8))
322#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8))
323#define MDIO_CONTROL (0x04)
324
325/* EMAC DM646X control module registers */ 305/* EMAC DM646X control module registers */
326#define EMAC_DM646X_CMINTCTRL 0x0C 306#define EMAC_DM646X_CMINTCTRL 0x0C
327#define EMAC_DM646X_CMRXINTEN 0x14 307#define EMAC_DM646X_CMRXINTEN 0x14
@@ -493,13 +473,6 @@ struct emac_priv {
493 u32 mac_hash2; 473 u32 mac_hash2;
494 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 474 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
495 u32 rx_addr_type; 475 u32 rx_addr_type;
496 /* periodic timer required for MDIO polling */
497 struct timer_list periodic_timer;
498 u32 periodic_ticks;
499 u32 timer_active;
500 u32 phy_mask;
501 /* mii_bus,phy members */
502 struct mii_bus *mii_bus;
503 const char *phy_id; 476 const char *phy_id;
504 struct phy_device *phydev; 477 struct phy_device *phydev;
505 spinlock_t lock; 478 spinlock_t lock;
@@ -511,7 +484,6 @@ struct emac_priv {
511/* clock frequency for EMAC */ 484/* clock frequency for EMAC */
512static struct clk *emac_clk; 485static struct clk *emac_clk;
513static unsigned long emac_bus_frequency; 486static unsigned long emac_bus_frequency;
514static unsigned long mdio_max_freq;
515 487
516#define emac_virt_to_phys(addr, priv) \ 488#define emac_virt_to_phys(addr, priv) \
517 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \ 489 (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
@@ -549,9 +521,6 @@ static char *emac_rxhost_errcodes[16] = {
549#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 521#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
550#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 522#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
551 523
552#define emac_mdio_read(reg) ioread32(bus->priv + (reg))
553#define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
554
555/** 524/**
556 * emac_dump_regs: Dump important EMAC registers to debug terminal 525 * emac_dump_regs: Dump important EMAC registers to debug terminal
557 * @priv: The DaVinci EMAC private adapter structure 526 * @priv: The DaVinci EMAC private adapter structure
@@ -657,9 +626,6 @@ static void emac_dump_regs(struct emac_priv *priv)
657 emac_read(EMAC_RXDMAOVERRUNS)); 626 emac_read(EMAC_RXDMAOVERRUNS));
658} 627}
659 628
660/*************************************************************************
661 * EMAC MDIO/Phy Functionality
662 *************************************************************************/
663/** 629/**
664 * emac_get_drvinfo: Get EMAC driver information 630 * emac_get_drvinfo: Get EMAC driver information
665 * @ndev: The DaVinci EMAC network adapter 631 * @ndev: The DaVinci EMAC network adapter
@@ -2349,79 +2315,6 @@ void emac_poll_controller(struct net_device *ndev)
2349} 2315}
2350#endif 2316#endif
2351 2317
2352/* PHY/MII bus related */
2353
2354/* Wait until mdio is ready for next command */
2355#define MDIO_WAIT_FOR_USER_ACCESS\
2356 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2357 MDIO_USERACCESS_GO) != 0)
2358
2359static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2360{
2361 unsigned int phy_data = 0;
2362 unsigned int phy_control;
2363
2364 /* Wait until mdio is ready for next command */
2365 MDIO_WAIT_FOR_USER_ACCESS;
2366
2367 phy_control = (MDIO_USERACCESS_GO |
2368 MDIO_USERACCESS_READ |
2369 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2370 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2371 (phy_data & MDIO_USERACCESS_DATA));
2372 emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2373
2374 /* Wait until mdio is ready for next command */
2375 MDIO_WAIT_FOR_USER_ACCESS;
2376
2377 return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2378
2379}
2380
2381static int emac_mii_write(struct mii_bus *bus, int phy_id,
2382 int phy_reg, u16 phy_data)
2383{
2384
2385 unsigned int control;
2386
2387 /* until mdio is ready for next command */
2388 MDIO_WAIT_FOR_USER_ACCESS;
2389
2390 control = (MDIO_USERACCESS_GO |
2391 MDIO_USERACCESS_WRITE |
2392 ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2393 ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2394 (phy_data & MDIO_USERACCESS_DATA));
2395 emac_mdio_write(MDIO_USERACCESS(0), control);
2396
2397 return 0;
2398}
2399
2400static int emac_mii_reset(struct mii_bus *bus)
2401{
2402 unsigned int clk_div;
2403 int mdio_bus_freq = emac_bus_frequency;
2404
2405 if (mdio_max_freq && mdio_bus_freq)
2406 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2407 else
2408 clk_div = 0xFF;
2409
2410 clk_div &= MDIO_CONTROL_CLKDIV;
2411
2412 /* Set enable and clock divider in MDIOControl */
2413 emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2414
2415 return 0;
2416
2417}
2418
2419static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2420
2421/* emac_driver: EMAC MII bus structure */
2422
2423static struct mii_bus *emac_mii;
2424
2425static void emac_adjust_link(struct net_device *ndev) 2318static void emac_adjust_link(struct net_device *ndev)
2426{ 2319{
2427 struct emac_priv *priv = netdev_priv(ndev); 2320 struct emac_priv *priv = netdev_priv(ndev);