cxgb4: enable PCIe relaxed ordering

Enable relaxed ordering for descriptor reads and packet I/O.

Signed-off-by: Dimitris Michailidis <dm@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 19 insertions, 0 deletions

diff --git a/drivers/net/cxgb4/cxgb4_main.c b/drivers/net/cxgb4/cxgb4_main.c
index 848f89d19fb7..953d62a3403c 100644
--- a/drivers/net/cxgb4/cxgb4_main.c
+++ b/drivers/net/cxgb4/cxgb4_main.c
@@ -3535,6 +3535,19 @@ static void __devinit print_port_info(struct adapter *adap)
         }
 }
 
+static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev)
+{
+        u16 v;
+        int pos;
+
+        pos = pci_pcie_cap(dev);
+        if (pos > 0) {
+                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v);
+                v |= PCI_EXP_DEVCTL_RELAX_EN;
+                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v);
+        }
+}
+
 /*
  * Free the following resources:
  * - memory used for tables
@@ -3609,6 +3622,7 @@ static int __devinit init_one(struct pci_dev *pdev,
         }
 
         pci_enable_pcie_error_reporting(pdev);
+        enable_pcie_relaxed_ordering(pdev);
         pci_set_master(pdev);
         pci_save_state(pdev);
 
diff --git a/drivers/net/cxgb4/sge.c b/drivers/net/cxgb4/sge.c
index 17022258ed68..cc0b9975d472 100644
--- a/drivers/net/cxgb4/sge.c
+++ b/drivers/net/cxgb4/sge.c
@@ -2014,6 +2014,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
 
                 flsz = fl->size / 8 + STAT_LEN / sizeof(struct tx_desc);
                 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN |
+                                            FW_IQ_CMD_FL0FETCHRO(1) |
+                                            FW_IQ_CMD_FL0DATARO(1) |
                                             FW_IQ_CMD_FL0PADEN);
                 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
                                 FW_IQ_CMD_FL0FBMAX(3));
@@ -2106,6 +2108,7 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
         c.viid_pkd = htonl(FW_EQ_ETH_CMD_VIID(pi->viid));
         c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) |
                                    FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_ETH_CMD_FETCHRO(1) |
                                    FW_EQ_ETH_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) |
                                   FW_EQ_ETH_CMD_FBMAX(3) |
@@ -2158,6 +2161,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
         c.physeqid_pkd = htonl(0);
         c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) |
                                    FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_CTRL_CMD_FETCHRO |
                                    FW_EQ_CTRL_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) |
                                   FW_EQ_CTRL_CMD_FBMAX(3) |
@@ -2207,6 +2211,7 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
                                  FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
         c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) |
                                    FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_OFLD_CMD_FETCHRO(1) |
                                    FW_EQ_OFLD_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) |
                                   FW_EQ_OFLD_CMD_FBMAX(3) |