diff options
author | Casey Leedom <leedom@chelsio.com> | 2010-06-25 08:10:32 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-06-29 02:58:55 -0400 |
commit | 81323b74a83d4144367184926a80e030e2354d25 (patch) | |
tree | ddd80aca682c09ff165a52e2d3af1fca3dfef1f6 /drivers/net/cxgb4 | |
parent | 1704d74894912b8ecc3e95cecd7bde336a0b1bf2 (diff) |
cxgb4vf: update to latest T4 firmware API file
Update to latest T4 firmware API file.
Signed-off-by: Casey Leedom
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/cxgb4')
-rw-r--r-- | drivers/net/cxgb4/t4_hw.c | 2 | ||||
-rw-r--r-- | drivers/net/cxgb4/t4fw_api.h | 27 |
2 files changed, 22 insertions, 7 deletions
diff --git a/drivers/net/cxgb4/t4_hw.c b/drivers/net/cxgb4/t4_hw.c index d92129b6c140..3e63d1487f5f 100644 --- a/drivers/net/cxgb4/t4_hw.c +++ b/drivers/net/cxgb4/t4_hw.c | |||
@@ -2518,7 +2518,7 @@ int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, | |||
2518 | c.retval_len16 = htonl(FW_LEN16(c)); | 2518 | c.retval_len16 = htonl(FW_LEN16(c)); |
2519 | c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) | | 2519 | c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) | |
2520 | FW_PFVF_CMD_NIQ(rxq)); | 2520 | FW_PFVF_CMD_NIQ(rxq)); |
2521 | c.cmask_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) | | 2521 | c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) | |
2522 | FW_PFVF_CMD_PMASK(pmask) | | 2522 | FW_PFVF_CMD_PMASK(pmask) | |
2523 | FW_PFVF_CMD_NEQ(txq)); | 2523 | FW_PFVF_CMD_NEQ(txq)); |
2524 | c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) | | 2524 | c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) | |
diff --git a/drivers/net/cxgb4/t4fw_api.h b/drivers/net/cxgb4/t4fw_api.h index 111c2a5763e4..ca45df8954dd 100644 --- a/drivers/net/cxgb4/t4fw_api.h +++ b/drivers/net/cxgb4/t4fw_api.h | |||
@@ -71,6 +71,7 @@ struct fw_wr_hdr { | |||
71 | #define FW_WR_ATOMIC(x) ((x) << 23) | 71 | #define FW_WR_ATOMIC(x) ((x) << 23) |
72 | #define FW_WR_FLUSH(x) ((x) << 22) | 72 | #define FW_WR_FLUSH(x) ((x) << 22) |
73 | #define FW_WR_COMPL(x) ((x) << 21) | 73 | #define FW_WR_COMPL(x) ((x) << 21) |
74 | #define FW_WR_IMMDLEN_MASK 0xff | ||
74 | #define FW_WR_IMMDLEN(x) ((x) << 0) | 75 | #define FW_WR_IMMDLEN(x) ((x) << 0) |
75 | 76 | ||
76 | #define FW_WR_EQUIQ (1U << 31) | 77 | #define FW_WR_EQUIQ (1U << 31) |
@@ -447,7 +448,9 @@ enum fw_params_param_dev { | |||
447 | FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, | 448 | FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, |
448 | FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, | 449 | FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, |
449 | FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, | 450 | FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, |
450 | FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A | 451 | FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, |
452 | FW_PARAMS_PARAM_DEV_FWREV = 0x0B, | ||
453 | FW_PARAMS_PARAM_DEV_TPREV = 0x0C, | ||
451 | }; | 454 | }; |
452 | 455 | ||
453 | /* | 456 | /* |
@@ -518,7 +521,7 @@ struct fw_pfvf_cmd { | |||
518 | __be32 op_to_vfn; | 521 | __be32 op_to_vfn; |
519 | __be32 retval_len16; | 522 | __be32 retval_len16; |
520 | __be32 niqflint_niq; | 523 | __be32 niqflint_niq; |
521 | __be32 cmask_to_neq; | 524 | __be32 type_to_neq; |
522 | __be32 tc_to_nexactf; | 525 | __be32 tc_to_nexactf; |
523 | __be32 r_caps_to_nethctrl; | 526 | __be32 r_caps_to_nethctrl; |
524 | __be16 nricq; | 527 | __be16 nricq; |
@@ -535,11 +538,16 @@ struct fw_pfvf_cmd { | |||
535 | #define FW_PFVF_CMD_NIQ(x) ((x) << 0) | 538 | #define FW_PFVF_CMD_NIQ(x) ((x) << 0) |
536 | #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff) | 539 | #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff) |
537 | 540 | ||
541 | #define FW_PFVF_CMD_TYPE (1 << 31) | ||
542 | #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1) | ||
543 | |||
538 | #define FW_PFVF_CMD_CMASK(x) ((x) << 24) | 544 | #define FW_PFVF_CMD_CMASK(x) ((x) << 24) |
539 | #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & 0xf) | 545 | #define FW_PFVF_CMD_CMASK_MASK 0xf |
546 | #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK) | ||
540 | 547 | ||
541 | #define FW_PFVF_CMD_PMASK(x) ((x) << 20) | 548 | #define FW_PFVF_CMD_PMASK(x) ((x) << 20) |
542 | #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & 0xf) | 549 | #define FW_PFVF_CMD_PMASK_MASK 0xf |
550 | #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK) | ||
543 | 551 | ||
544 | #define FW_PFVF_CMD_NEQ(x) ((x) << 0) | 552 | #define FW_PFVF_CMD_NEQ(x) ((x) << 0) |
545 | #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff) | 553 | #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff) |
@@ -692,6 +700,7 @@ struct fw_eq_eth_cmd { | |||
692 | #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0) | 700 | #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0) |
693 | #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) | 701 | #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff) |
694 | #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0) | 702 | #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0) |
703 | #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff) | ||
695 | 704 | ||
696 | #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26) | 705 | #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26) |
697 | #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25) | 706 | #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25) |
@@ -832,12 +841,14 @@ struct fw_vi_cmd { | |||
832 | #define FW_VI_CMD_VIID(x) ((x) << 0) | 841 | #define FW_VI_CMD_VIID(x) ((x) << 0) |
833 | #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff) | 842 | #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff) |
834 | #define FW_VI_CMD_PORTID(x) ((x) << 4) | 843 | #define FW_VI_CMD_PORTID(x) ((x) << 4) |
844 | #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf) | ||
835 | #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff) | 845 | #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff) |
836 | 846 | ||
837 | /* Special VI_MAC command index ids */ | 847 | /* Special VI_MAC command index ids */ |
838 | #define FW_VI_MAC_ADD_MAC 0x3FF | 848 | #define FW_VI_MAC_ADD_MAC 0x3FF |
839 | #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE | 849 | #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE |
840 | #define FW_VI_MAC_MAC_BASED_FREE 0x3FD | 850 | #define FW_VI_MAC_MAC_BASED_FREE 0x3FD |
851 | #define FW_CLS_TCAM_NUM_ENTRIES 336 | ||
841 | 852 | ||
842 | enum fw_vi_mac_smac { | 853 | enum fw_vi_mac_smac { |
843 | FW_VI_MAC_MPS_TCAM_ENTRY, | 854 | FW_VI_MAC_MPS_TCAM_ENTRY, |
@@ -888,6 +899,7 @@ struct fw_vi_rxmode_cmd { | |||
888 | }; | 899 | }; |
889 | 900 | ||
890 | #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0) | 901 | #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0) |
902 | #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff | ||
891 | #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16) | 903 | #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16) |
892 | #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3 | 904 | #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3 |
893 | #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14) | 905 | #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14) |
@@ -1173,6 +1185,7 @@ struct fw_port_cmd { | |||
1173 | #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf) | 1185 | #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf) |
1174 | 1186 | ||
1175 | #define FW_PORT_CMD_ACTION(x) ((x) << 16) | 1187 | #define FW_PORT_CMD_ACTION(x) ((x) << 16) |
1188 | #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff) | ||
1176 | 1189 | ||
1177 | #define FW_PORT_CMD_CTLBF(x) ((x) << 10) | 1190 | #define FW_PORT_CMD_CTLBF(x) ((x) << 10) |
1178 | #define FW_PORT_CMD_OVLAN3(x) ((x) << 7) | 1191 | #define FW_PORT_CMD_OVLAN3(x) ((x) << 7) |
@@ -1487,6 +1500,7 @@ struct fw_rss_glb_config_cmd { | |||
1487 | }; | 1500 | }; |
1488 | 1501 | ||
1489 | #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28) | 1502 | #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28) |
1503 | #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf) | ||
1490 | 1504 | ||
1491 | #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 | 1505 | #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 |
1492 | #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 | 1506 | #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 |
@@ -1503,13 +1517,14 @@ struct fw_rss_vi_config_cmd { | |||
1503 | } manual; | 1517 | } manual; |
1504 | struct fw_rss_vi_config_basicvirtual { | 1518 | struct fw_rss_vi_config_basicvirtual { |
1505 | __be32 r6; | 1519 | __be32 r6; |
1506 | __be32 defaultq_to_ip4udpen; | 1520 | __be32 defaultq_to_udpen; |
1507 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16) | 1521 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16) |
1522 | #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff) | ||
1508 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4) | 1523 | #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4) |
1509 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3) | 1524 | #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3) |
1510 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2) | 1525 | #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2) |
1511 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1) | 1526 | #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1) |
1512 | #define FW_RSS_VI_CONFIG_CMD_IP4UDPEN (1U << 0) | 1527 | #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0) |
1513 | __be64 r9; | 1528 | __be64 r9; |
1514 | __be64 r10; | 1529 | __be64 r10; |
1515 | } basicvirtual; | 1530 | } basicvirtual; |