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authorBen Hutchings <bhutchings@solarflare.com>2009-04-29 04:07:20 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-29 20:32:32 -0400
commit0f07c4ee8c800923ae7918c231532a9256233eed (patch)
tree659322e8607f681af12a43671b17c5b65f94f4d5 /drivers/net/cxgb3
parent23c3320cb039debfb94b27e8e9bfe26dd47692c3 (diff)
cxgb3: Use generic MDIO definitions and mdio_mii_ioctl()
Compile-tested only. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/cxgb3')
-rw-r--r--drivers/net/cxgb3/ael1002.c146
-rw-r--r--drivers/net/cxgb3/common.h53
-rw-r--r--drivers/net/cxgb3/cxgb3_main.c71
-rw-r--r--drivers/net/cxgb3/t3_hw.c78
-rw-r--r--drivers/net/cxgb3/vsc8211.c70
5 files changed, 194 insertions, 224 deletions
diff --git a/drivers/net/cxgb3/ael1002.c b/drivers/net/cxgb3/ael1002.c
index e1b22490ff59..bebc00d2424d 100644
--- a/drivers/net/cxgb3/ael1002.c
+++ b/drivers/net/cxgb3/ael1002.c
@@ -33,14 +33,6 @@
33#include "regs.h" 33#include "regs.h"
34 34
35enum { 35enum {
36 PMD_RSD = 10, /* PMA/PMD receive signal detect register */
37 PCS_STAT1_X = 24, /* 10GBASE-X PCS status 1 register */
38 PCS_STAT1_R = 32, /* 10GBASE-R PCS status 1 register */
39 XS_LN_STAT = 24 /* XS lane status register */
40};
41
42enum {
43 AEL100X_TX_DISABLE = 9,
44 AEL100X_TX_CONFIG1 = 0xc002, 36 AEL100X_TX_CONFIG1 = 0xc002,
45 AEL1002_PWR_DOWN_HI = 0xc011, 37 AEL1002_PWR_DOWN_HI = 0xc011,
46 AEL1002_PWR_DOWN_LO = 0xc012, 38 AEL1002_PWR_DOWN_LO = 0xc012,
@@ -74,8 +66,8 @@ static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
74 66
75 for (err = 0; rv->mmd_addr && !err; rv++) { 67 for (err = 0; rv->mmd_addr && !err; rv++) {
76 if (rv->clear_bits == 0xffff) 68 if (rv->clear_bits == 0xffff)
77 err = mdio_write(phy, rv->mmd_addr, rv->reg_addr, 69 err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr,
78 rv->set_bits); 70 rv->set_bits);
79 else 71 else
80 err = t3_mdio_change_bits(phy, rv->mmd_addr, 72 err = t3_mdio_change_bits(phy, rv->mmd_addr,
81 rv->reg_addr, rv->clear_bits, 73 rv->reg_addr, rv->clear_bits,
@@ -86,7 +78,8 @@ static int set_phy_regs(struct cphy *phy, const struct reg_val *rv)
86 78
87static void ael100x_txon(struct cphy *phy) 79static void ael100x_txon(struct cphy *phy)
88{ 80{
89 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; 81 int tx_on_gpio =
82 phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
90 83
91 msleep(100); 84 msleep(100);
92 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); 85 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
@@ -97,10 +90,11 @@ static int ael1002_power_down(struct cphy *phy, int enable)
97{ 90{
98 int err; 91 int err;
99 92
100 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable); 93 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable);
101 if (!err) 94 if (!err)
102 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 95 err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
103 BMCR_PDOWN, enable ? BMCR_PDOWN : 0); 96 MDIO_MMD_PMAPMD, MDIO_CTRL1,
97 MDIO_CTRL1_LPOWER, enable);
104 return err; 98 return err;
105} 99}
106 100
@@ -109,11 +103,11 @@ static int ael1002_reset(struct cphy *phy, int wait)
109 int err; 103 int err;
110 104
111 if ((err = ael1002_power_down(phy, 0)) || 105 if ((err = ael1002_power_down(phy, 0)) ||
112 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) || 106 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) ||
113 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) || 107 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) ||
114 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) || 108 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) ||
115 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) || 109 (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) ||
116 (err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN, 110 (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN,
117 0, 1 << 5))) 111 0, 1 << 5)))
118 return err; 112 return err;
119 return 0; 113 return 0;
@@ -132,12 +126,15 @@ static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed,
132{ 126{
133 if (link_ok) { 127 if (link_ok) {
134 unsigned int stat0, stat1, stat2; 128 unsigned int stat0, stat1, stat2;
135 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0); 129 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
130 MDIO_PMA_RXDET, &stat0);
136 131
137 if (!err) 132 if (!err)
138 err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_R, &stat1); 133 err = t3_mdio_read(phy, MDIO_MMD_PCS,
134 MDIO_PCS_10GBRT_STAT1, &stat1);
139 if (!err) 135 if (!err)
140 err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2); 136 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
137 MDIO_PHYXS_LNSTAT, &stat2);
141 if (err) 138 if (err)
142 return err; 139 return err;
143 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1; 140 *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1;
@@ -157,6 +154,7 @@ static struct cphy_ops ael1002_ops = {
157 .intr_handler = ael1002_intr_noop, 154 .intr_handler = ael1002_intr_noop,
158 .get_link_status = get_link_status_r, 155 .get_link_status = get_link_status_r,
159 .power_down = ael1002_power_down, 156 .power_down = ael1002_power_down,
157 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
160}; 158};
161 159
162int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 160int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
@@ -171,13 +169,13 @@ int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
171 169
172static int ael1006_reset(struct cphy *phy, int wait) 170static int ael1006_reset(struct cphy *phy, int wait)
173{ 171{
174 return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); 172 return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait);
175} 173}
176 174
177static int ael1006_power_down(struct cphy *phy, int enable) 175static int ael1006_power_down(struct cphy *phy, int enable)
178{ 176{
179 return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, 177 return mdio_set_flag(&phy->mdio, phy->mdio.prtad, MDIO_MMD_PMAPMD,
180 BMCR_PDOWN, enable ? BMCR_PDOWN : 0); 178 MDIO_CTRL1, MDIO_CTRL1_LPOWER, enable);
181} 179}
182 180
183static struct cphy_ops ael1006_ops = { 181static struct cphy_ops ael1006_ops = {
@@ -188,6 +186,7 @@ static struct cphy_ops ael1006_ops = {
188 .intr_handler = t3_phy_lasi_intr_handler, 186 .intr_handler = t3_phy_lasi_intr_handler,
189 .get_link_status = get_link_status_r, 187 .get_link_status = get_link_status_r,
190 .power_down = ael1006_power_down, 188 .power_down = ael1006_power_down,
189 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
191}; 190};
192 191
193int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 192int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
@@ -203,9 +202,9 @@ int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
203static int ael2005_setup_sr_edc(struct cphy *phy) 202static int ael2005_setup_sr_edc(struct cphy *phy)
204{ 203{
205 static struct reg_val regs[] = { 204 static struct reg_val regs[] = {
206 { MDIO_DEV_PMA_PMD, 0xc003, 0xffff, 0x181 }, 205 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
207 { MDIO_DEV_PMA_PMD, 0xc010, 0xffff, 0x448a }, 206 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
208 { MDIO_DEV_PMA_PMD, 0xc04a, 0xffff, 0x5200 }, 207 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
209 { 0, 0, 0, 0 } 208 { 0, 0, 0, 0 }
210 }; 209 };
211 static u16 sr_edc[] = { 210 static u16 sr_edc[] = {
@@ -490,8 +489,8 @@ static int ael2005_setup_sr_edc(struct cphy *phy)
490 msleep(50); 489 msleep(50);
491 490
492 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2) 491 for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2)
493 err = mdio_write(phy, MDIO_DEV_PMA_PMD, sr_edc[i], 492 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, sr_edc[i],
494 sr_edc[i + 1]); 493 sr_edc[i + 1]);
495 if (!err) 494 if (!err)
496 phy->priv = edc_sr; 495 phy->priv = edc_sr;
497 return err; 496 return err;
@@ -500,12 +499,12 @@ static int ael2005_setup_sr_edc(struct cphy *phy)
500static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) 499static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
501{ 500{
502 static struct reg_val regs[] = { 501 static struct reg_val regs[] = {
503 { MDIO_DEV_PMA_PMD, 0xc04a, 0xffff, 0x5a00 }, 502 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
504 { 0, 0, 0, 0 } 503 { 0, 0, 0, 0 }
505 }; 504 };
506 static struct reg_val preemphasis[] = { 505 static struct reg_val preemphasis[] = {
507 { MDIO_DEV_PMA_PMD, 0xc014, 0xffff, 0xfe16 }, 506 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
508 { MDIO_DEV_PMA_PMD, 0xc015, 0xffff, 0xa000 }, 507 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
509 { 0, 0, 0, 0 } 508 { 0, 0, 0, 0 }
510 }; 509 };
511 static u16 twinax_edc[] = { 510 static u16 twinax_edc[] = {
@@ -887,8 +886,8 @@ static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
887 msleep(50); 886 msleep(50);
888 887
889 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) 888 for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2)
890 err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i], 889 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i],
891 twinax_edc[i + 1]); 890 twinax_edc[i + 1]);
892 if (!err) 891 if (!err)
893 phy->priv = edc_twinax; 892 phy->priv = edc_twinax;
894 return err; 893 return err;
@@ -899,26 +898,26 @@ static int ael2005_i2c_rd(struct cphy *phy, int dev_addr, int word_addr)
899 int i, err; 898 int i, err;
900 unsigned int stat, data; 899 unsigned int stat, data;
901 900
902 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, 901 err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL,
903 (dev_addr << 8) | (1 << 8) | word_addr); 902 (dev_addr << 8) | (1 << 8) | word_addr);
904 if (err) 903 if (err)
905 return err; 904 return err;
906 905
907 for (i = 0; i < 5; i++) { 906 for (i = 0; i < 5; i++) {
908 msleep(1); 907 msleep(1);
909 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); 908 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat);
910 if (err) 909 if (err)
911 return err; 910 return err;
912 if ((stat & 3) == 1) { 911 if ((stat & 3) == 1) {
913 err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, 912 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA,
914 &data); 913 &data);
915 if (err) 914 if (err)
916 return err; 915 return err;
917 return data >> 8; 916 return data >> 8;
918 } 917 }
919 } 918 }
920 CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n", 919 CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n",
921 phy->addr, word_addr); 920 phy->mdio.prtad, word_addr);
922 return -ETIMEDOUT; 921 return -ETIMEDOUT;
923} 922}
924 923
@@ -927,7 +926,7 @@ static int get_module_type(struct cphy *phy, int delay_ms)
927 int v; 926 int v;
928 unsigned int stat; 927 unsigned int stat;
929 928
930 v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, &stat); 929 v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat);
931 if (v) 930 if (v)
932 return v; 931 return v;
933 932
@@ -971,48 +970,48 @@ unknown:
971 970
972static int ael2005_intr_enable(struct cphy *phy) 971static int ael2005_intr_enable(struct cphy *phy)
973{ 972{
974 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x200); 973 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200);
975 return err ? err : t3_phy_lasi_intr_enable(phy); 974 return err ? err : t3_phy_lasi_intr_enable(phy);
976} 975}
977 976
978static int ael2005_intr_disable(struct cphy *phy) 977static int ael2005_intr_disable(struct cphy *phy)
979{ 978{
980 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x100); 979 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100);
981 return err ? err : t3_phy_lasi_intr_disable(phy); 980 return err ? err : t3_phy_lasi_intr_disable(phy);
982} 981}
983 982
984static int ael2005_intr_clear(struct cphy *phy) 983static int ael2005_intr_clear(struct cphy *phy)
985{ 984{
986 int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0xd00); 985 int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00);
987 return err ? err : t3_phy_lasi_intr_clear(phy); 986 return err ? err : t3_phy_lasi_intr_clear(phy);
988} 987}
989 988
990static int ael2005_reset(struct cphy *phy, int wait) 989static int ael2005_reset(struct cphy *phy, int wait)
991{ 990{
992 static struct reg_val regs0[] = { 991 static struct reg_val regs0[] = {
993 { MDIO_DEV_PMA_PMD, 0xc001, 0, 1 << 5 }, 992 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
994 { MDIO_DEV_PMA_PMD, 0xc017, 0, 1 << 5 }, 993 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
995 { MDIO_DEV_PMA_PMD, 0xc013, 0xffff, 0xf341 }, 994 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
996 { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8000 }, 995 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
997 { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8100 }, 996 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 },
998 { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8000 }, 997 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 },
999 { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0 }, 998 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
1000 { 0, 0, 0, 0 } 999 { 0, 0, 0, 0 }
1001 }; 1000 };
1002 static struct reg_val regs1[] = { 1001 static struct reg_val regs1[] = {
1003 { MDIO_DEV_PMA_PMD, 0xca00, 0xffff, 0x0080 }, 1002 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
1004 { MDIO_DEV_PMA_PMD, 0xca12, 0xffff, 0 }, 1003 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
1005 { 0, 0, 0, 0 } 1004 { 0, 0, 0, 0 }
1006 }; 1005 };
1007 1006
1008 int err; 1007 int err;
1009 unsigned int lasi_ctrl; 1008 unsigned int lasi_ctrl;
1010 1009
1011 err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl); 1010 err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, LASI_CTRL, &lasi_ctrl);
1012 if (err) 1011 if (err)
1013 return err; 1012 return err;
1014 1013
1015 err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 0); 1014 err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0);
1016 if (err) 1015 if (err)
1017 return err; 1016 return err;
1018 1017
@@ -1051,13 +1050,13 @@ static int ael2005_intr_handler(struct cphy *phy)
1051 unsigned int stat; 1050 unsigned int stat;
1052 int ret, edc_needed, cause = 0; 1051 int ret, edc_needed, cause = 0;
1053 1052
1054 ret = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_STAT, &stat); 1053 ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat);
1055 if (ret) 1054 if (ret)
1056 return ret; 1055 return ret;
1057 1056
1058 if (stat & AEL2005_MODDET_IRQ) { 1057 if (stat & AEL2005_MODDET_IRQ) {
1059 ret = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 1058 ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL,
1060 0xd00); 1059 0xd00);
1061 if (ret) 1060 if (ret)
1062 return ret; 1061 return ret;
1063 1062
@@ -1098,6 +1097,7 @@ static struct cphy_ops ael2005_ops = {
1098 .intr_handler = ael2005_intr_handler, 1097 .intr_handler = ael2005_intr_handler,
1099 .get_link_status = get_link_status_r, 1098 .get_link_status = get_link_status_r,
1100 .power_down = ael1002_power_down, 1099 .power_down = ael1002_power_down,
1100 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1101}; 1101};
1102 1102
1103int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, 1103int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
@@ -1107,7 +1107,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
1107 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | 1107 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE |
1108 SUPPORTED_IRQ, "10GBASE-R"); 1108 SUPPORTED_IRQ, "10GBASE-R");
1109 msleep(125); 1109 msleep(125);
1110 return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL_OPT_SETTINGS, 0, 1110 return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0,
1111 1 << 5); 1111 1 << 5);
1112} 1112}
1113 1113
@@ -1119,12 +1119,15 @@ static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed,
1119{ 1119{
1120 if (link_ok) { 1120 if (link_ok) {
1121 unsigned int stat0, stat1, stat2; 1121 unsigned int stat0, stat1, stat2;
1122 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0); 1122 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD,
1123 MDIO_PMA_RXDET, &stat0);
1123 1124
1124 if (!err) 1125 if (!err)
1125 err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_X, &stat1); 1126 err = t3_mdio_read(phy, MDIO_MMD_PCS,
1127 MDIO_PCS_10GBX_STAT1, &stat1);
1126 if (!err) 1128 if (!err)
1127 err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2); 1129 err = t3_mdio_read(phy, MDIO_MMD_PHYXS,
1130 MDIO_PHYXS_LNSTAT, &stat2);
1128 if (err) 1131 if (err)
1129 return err; 1132 return err;
1130 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1; 1133 *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1;
@@ -1144,6 +1147,7 @@ static struct cphy_ops qt2045_ops = {
1144 .intr_handler = t3_phy_lasi_intr_handler, 1147 .intr_handler = t3_phy_lasi_intr_handler,
1145 .get_link_status = get_link_status_x, 1148 .get_link_status = get_link_status_x,
1146 .power_down = ael1006_power_down, 1149 .power_down = ael1006_power_down,
1150 .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
1147}; 1151};
1148 1152
1149int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, 1153int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
@@ -1159,9 +1163,10 @@ int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter,
1159 * Some cards where the PHY is supposed to be at address 0 actually 1163 * Some cards where the PHY is supposed to be at address 0 actually
1160 * have it at 1. 1164 * have it at 1.
1161 */ 1165 */
1162 if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) && 1166 if (!phy_addr &&
1167 !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) &&
1163 stat == 0xffff) 1168 stat == 0xffff)
1164 phy->addr = 1; 1169 phy->mdio.prtad = 1;
1165 return 0; 1170 return 0;
1166} 1171}
1167 1172
@@ -1175,15 +1180,16 @@ static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok,
1175{ 1180{
1176 if (link_ok) { 1181 if (link_ok) {
1177 unsigned int status; 1182 unsigned int status;
1183 int prtad = phy->mdio.prtad;
1178 1184
1179 status = t3_read_reg(phy->adapter, 1185 status = t3_read_reg(phy->adapter,
1180 XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) | 1186 XGM_REG(A_XGM_SERDES_STAT0, prtad)) |
1181 t3_read_reg(phy->adapter, 1187 t3_read_reg(phy->adapter,
1182 XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) | 1188 XGM_REG(A_XGM_SERDES_STAT1, prtad)) |
1183 t3_read_reg(phy->adapter, 1189 t3_read_reg(phy->adapter,
1184 XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) | 1190 XGM_REG(A_XGM_SERDES_STAT2, prtad)) |
1185 t3_read_reg(phy->adapter, 1191 t3_read_reg(phy->adapter,
1186 XGM_REG(A_XGM_SERDES_STAT3, phy->addr)); 1192 XGM_REG(A_XGM_SERDES_STAT3, prtad));
1187 *link_ok = !(status & F_LOWSIG0); 1193 *link_ok = !(status & F_LOWSIG0);
1188 } 1194 }
1189 if (speed) 1195 if (speed)
@@ -1211,7 +1217,7 @@ static struct cphy_ops xaui_direct_ops = {
1211int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 1217int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
1212 int phy_addr, const struct mdio_ops *mdio_ops) 1218 int phy_addr, const struct mdio_ops *mdio_ops)
1213{ 1219{
1214 cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops, 1220 cphy_init(phy, adapter, MDIO_PRTAD_NONE, &xaui_direct_ops, mdio_ops,
1215 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, 1221 SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP,
1216 "10GBASE-CX4"); 1222 "10GBASE-CX4");
1217 return 0; 1223 return 0;
diff --git a/drivers/net/cxgb3/common.h b/drivers/net/cxgb3/common.h
index e508dc32f3ec..3147789aecec 100644
--- a/drivers/net/cxgb3/common.h
+++ b/drivers/net/cxgb3/common.h
@@ -39,7 +39,7 @@
39#include <linux/init.h> 39#include <linux/init.h>
40#include <linux/netdevice.h> 40#include <linux/netdevice.h>
41#include <linux/ethtool.h> 41#include <linux/ethtool.h>
42#include <linux/mii.h> 42#include <linux/mdio.h>
43#include "version.h" 43#include "version.h"
44 44
45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) 45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
@@ -184,10 +184,11 @@ struct cphy;
184struct adapter; 184struct adapter;
185 185
186struct mdio_ops { 186struct mdio_ops {
187 int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr, 187 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
188 int reg_addr, unsigned int *val); 188 u16 reg_addr);
189 int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr, 189 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
190 int reg_addr, unsigned int val); 190 u16 reg_addr, u16 val);
191 unsigned mode_support;
191}; 192};
192 193
193struct adapter_info { 194struct adapter_info {
@@ -520,17 +521,6 @@ enum {
520 MAC_RXFIFO_SIZE = 32768 521 MAC_RXFIFO_SIZE = 32768
521}; 522};
522 523
523/* IEEE 802.3 specified MDIO devices */
524enum {
525 MDIO_DEV_PMA_PMD = 1,
526 MDIO_DEV_WIS = 2,
527 MDIO_DEV_PCS = 3,
528 MDIO_DEV_XGXS = 4,
529 MDIO_DEV_ANEG = 7,
530 MDIO_DEV_VEND1 = 30,
531 MDIO_DEV_VEND2 = 31
532};
533
534/* LASI control and status registers */ 524/* LASI control and status registers */
535enum { 525enum {
536 RX_ALARM_CTRL = 0x9000, 526 RX_ALARM_CTRL = 0x9000,
@@ -583,11 +573,12 @@ struct cphy_ops {
583 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 573 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
584 int *duplex, int *fc); 574 int *duplex, int *fc);
585 int (*power_down)(struct cphy *phy, int enable); 575 int (*power_down)(struct cphy *phy, int enable);
576
577 u32 mmds;
586}; 578};
587 579
588/* A PHY instance */ 580/* A PHY instance */
589struct cphy { 581struct cphy {
590 u8 addr; /* PHY address */
591 u8 modtype; /* PHY module type */ 582 u8 modtype; /* PHY module type */
592 short priv; /* scratch pad */ 583 short priv; /* scratch pad */
593 unsigned int caps; /* PHY capabilities */ 584 unsigned int caps; /* PHY capabilities */
@@ -595,23 +586,23 @@ struct cphy {
595 const char *desc; /* PHY description */ 586 const char *desc; /* PHY description */
596 unsigned long fifo_errors; /* FIFO over/under-flows */ 587 unsigned long fifo_errors; /* FIFO over/under-flows */
597 const struct cphy_ops *ops; /* PHY operations */ 588 const struct cphy_ops *ops; /* PHY operations */
598 int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr, 589 struct mdio_if_info mdio;
599 int reg_addr, unsigned int *val);
600 int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr,
601 int reg_addr, unsigned int val);
602}; 590};
603 591
604/* Convenience MDIO read/write wrappers */ 592/* Convenience MDIO read/write wrappers */
605static inline int mdio_read(struct cphy *phy, int mmd, int reg, 593static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
606 unsigned int *valp) 594 unsigned int *valp)
607{ 595{
608 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 596 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
597 *valp = (rc >= 0) ? rc : -1;
598 return (rc >= 0) ? 0 : rc;
609} 599}
610 600
611static inline int mdio_write(struct cphy *phy, int mmd, int reg, 601static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
612 unsigned int val) 602 unsigned int val)
613{ 603{
614 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 604 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
605 reg, val);
615} 606}
616 607
617/* Convenience initializer */ 608/* Convenience initializer */
@@ -620,14 +611,16 @@ static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
620 const struct mdio_ops *mdio_ops, 611 const struct mdio_ops *mdio_ops,
621 unsigned int caps, const char *desc) 612 unsigned int caps, const char *desc)
622{ 613{
623 phy->addr = phy_addr;
624 phy->caps = caps; 614 phy->caps = caps;
625 phy->adapter = adapter; 615 phy->adapter = adapter;
626 phy->desc = desc; 616 phy->desc = desc;
627 phy->ops = phy_ops; 617 phy->ops = phy_ops;
628 if (mdio_ops) { 618 if (mdio_ops) {
629 phy->mdio_read = mdio_ops->read; 619 phy->mdio.prtad = phy_addr;
630 phy->mdio_write = mdio_ops->write; 620 phy->mdio.mmds = phy_ops->mmds;
621 phy->mdio.mode_support = mdio_ops->mode_support;
622 phy->mdio.mdio_read = mdio_ops->read;
623 phy->mdio.mdio_write = mdio_ops->write;
631 } 624 }
632} 625}
633 626
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 7ea48414c6cb..0b87fee023f5 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -37,7 +37,7 @@
37#include <linux/netdevice.h> 37#include <linux/netdevice.h>
38#include <linux/etherdevice.h> 38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h> 39#include <linux/if_vlan.h>
40#include <linux/mii.h> 40#include <linux/mdio.h>
41#include <linux/sockios.h> 41#include <linux/sockios.h>
42#include <linux/workqueue.h> 42#include <linux/workqueue.h>
43#include <linux/proc_fs.h> 43#include <linux/proc_fs.h>
@@ -1593,7 +1593,7 @@ static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1593 } 1593 }
1594 1594
1595 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE; 1595 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
1596 cmd->phy_address = p->phy.addr; 1596 cmd->phy_address = p->phy.mdio.prtad;
1597 cmd->transceiver = XCVR_EXTERNAL; 1597 cmd->transceiver = XCVR_EXTERNAL;
1598 cmd->autoneg = p->link_config.autoneg; 1598 cmd->autoneg = p->link_config.autoneg;
1599 cmd->maxtxpkt = 0; 1599 cmd->maxtxpkt = 0;
@@ -2308,70 +2308,25 @@ static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2308 struct mii_ioctl_data *data = if_mii(req); 2308 struct mii_ioctl_data *data = if_mii(req);
2309 struct port_info *pi = netdev_priv(dev); 2309 struct port_info *pi = netdev_priv(dev);
2310 struct adapter *adapter = pi->adapter; 2310 struct adapter *adapter = pi->adapter;
2311 int ret, mmd;
2312 2311
2313 switch (cmd) { 2312 switch (cmd) {
2314 case SIOCGMIIPHY: 2313 case SIOCGMIIREG:
2315 data->phy_id = pi->phy.addr; 2314 case SIOCSMIIREG:
2315 /* Convert phy_id from older PRTAD/DEVAD format */
2316 if (is_10G(adapter) &&
2317 !mdio_phy_id_is_c45(data->phy_id) &&
2318 (data->phy_id & 0x1f00) &&
2319 !(data->phy_id & 0xe0e0))
2320 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2321 data->phy_id & 0x1f);
2316 /* FALLTHRU */ 2322 /* FALLTHRU */
2317 case SIOCGMIIREG:{ 2323 case SIOCGMIIPHY:
2318 u32 val; 2324 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
2319 struct cphy *phy = &pi->phy;
2320
2321 if (!phy->mdio_read)
2322 return -EOPNOTSUPP;
2323 if (is_10G(adapter)) {
2324 mmd = data->phy_id >> 8;
2325 if (!mmd)
2326 mmd = MDIO_DEV_PCS;
2327 else if (mmd > MDIO_DEV_VEND2)
2328 return -EINVAL;
2329
2330 ret =
2331 phy->mdio_read(adapter, data->phy_id & 0x1f,
2332 mmd, data->reg_num, &val);
2333 } else
2334 ret =
2335 phy->mdio_read(adapter, data->phy_id & 0x1f,
2336 0, data->reg_num & 0x1f,
2337 &val);
2338 if (!ret)
2339 data->val_out = val;
2340 break;
2341 }
2342 case SIOCSMIIREG:{
2343 struct cphy *phy = &pi->phy;
2344
2345 if (!capable(CAP_NET_ADMIN))
2346 return -EPERM;
2347 if (!phy->mdio_write)
2348 return -EOPNOTSUPP;
2349 if (is_10G(adapter)) {
2350 mmd = data->phy_id >> 8;
2351 if (!mmd)
2352 mmd = MDIO_DEV_PCS;
2353 else if (mmd > MDIO_DEV_VEND2)
2354 return -EINVAL;
2355
2356 ret =
2357 phy->mdio_write(adapter,
2358 data->phy_id & 0x1f, mmd,
2359 data->reg_num,
2360 data->val_in);
2361 } else
2362 ret =
2363 phy->mdio_write(adapter,
2364 data->phy_id & 0x1f, 0,
2365 data->reg_num & 0x1f,
2366 data->val_in);
2367 break;
2368 }
2369 case SIOCCHIOCTL: 2325 case SIOCCHIOCTL:
2370 return cxgb_extension_ioctl(dev, req->ifr_data); 2326 return cxgb_extension_ioctl(dev, req->ifr_data);
2371 default: 2327 default:
2372 return -EOPNOTSUPP; 2328 return -EOPNOTSUPP;
2373 } 2329 }
2374 return ret;
2375} 2330}
2376 2331
2377static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2332static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index e1bd690ff831..1dd1637663a3 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -204,35 +204,33 @@ static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
204/* 204/*
205 * MI1 read/write operations for clause 22 PHYs. 205 * MI1 read/write operations for clause 22 PHYs.
206 */ 206 */
207static int t3_mi1_read(struct adapter *adapter, int phy_addr, int mmd_addr, 207static int t3_mi1_read(struct net_device *dev, int phy_addr, int mmd_addr,
208 int reg_addr, unsigned int *valp) 208 u16 reg_addr)
209{ 209{
210 struct port_info *pi = netdev_priv(dev);
211 struct adapter *adapter = pi->adapter;
210 int ret; 212 int ret;
211 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); 213 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
212 214
213 if (mmd_addr)
214 return -EINVAL;
215
216 mutex_lock(&adapter->mdio_lock); 215 mutex_lock(&adapter->mdio_lock);
217 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); 216 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
218 t3_write_reg(adapter, A_MI1_ADDR, addr); 217 t3_write_reg(adapter, A_MI1_ADDR, addr);
219 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); 218 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
220 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); 219 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
221 if (!ret) 220 if (!ret)
222 *valp = t3_read_reg(adapter, A_MI1_DATA); 221 ret = t3_read_reg(adapter, A_MI1_DATA);
223 mutex_unlock(&adapter->mdio_lock); 222 mutex_unlock(&adapter->mdio_lock);
224 return ret; 223 return ret;
225} 224}
226 225
227static int t3_mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr, 226static int t3_mi1_write(struct net_device *dev, int phy_addr, int mmd_addr,
228 int reg_addr, unsigned int val) 227 u16 reg_addr, u16 val)
229{ 228{
229 struct port_info *pi = netdev_priv(dev);
230 struct adapter *adapter = pi->adapter;
230 int ret; 231 int ret;
231 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr); 232 u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
232 233
233 if (mmd_addr)
234 return -EINVAL;
235
236 mutex_lock(&adapter->mdio_lock); 234 mutex_lock(&adapter->mdio_lock);
237 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); 235 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
238 t3_write_reg(adapter, A_MI1_ADDR, addr); 236 t3_write_reg(adapter, A_MI1_ADDR, addr);
@@ -244,8 +242,9 @@ static int t3_mi1_write(struct adapter *adapter, int phy_addr, int mmd_addr,
244} 242}
245 243
246static const struct mdio_ops mi1_mdio_ops = { 244static const struct mdio_ops mi1_mdio_ops = {
247 t3_mi1_read, 245 .read = t3_mi1_read,
248 t3_mi1_write 246 .write = t3_mi1_write,
247 .mode_support = MDIO_SUPPORTS_C22
249}; 248};
250 249
251/* 250/*
@@ -268,9 +267,11 @@ static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr,
268/* 267/*
269 * MI1 read/write operations for indirect-addressed PHYs. 268 * MI1 read/write operations for indirect-addressed PHYs.
270 */ 269 */
271static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr, 270static int mi1_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
272 int reg_addr, unsigned int *valp) 271 u16 reg_addr)
273{ 272{
273 struct port_info *pi = netdev_priv(dev);
274 struct adapter *adapter = pi->adapter;
274 int ret; 275 int ret;
275 276
276 mutex_lock(&adapter->mdio_lock); 277 mutex_lock(&adapter->mdio_lock);
@@ -280,15 +281,17 @@ static int mi1_ext_read(struct adapter *adapter, int phy_addr, int mmd_addr,
280 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, 281 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
281 MDIO_ATTEMPTS, 10); 282 MDIO_ATTEMPTS, 10);
282 if (!ret) 283 if (!ret)
283 *valp = t3_read_reg(adapter, A_MI1_DATA); 284 ret = t3_read_reg(adapter, A_MI1_DATA);
284 } 285 }
285 mutex_unlock(&adapter->mdio_lock); 286 mutex_unlock(&adapter->mdio_lock);
286 return ret; 287 return ret;
287} 288}
288 289
289static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr, 290static int mi1_ext_write(struct net_device *dev, int phy_addr, int mmd_addr,
290 int reg_addr, unsigned int val) 291 u16 reg_addr, u16 val)
291{ 292{
293 struct port_info *pi = netdev_priv(dev);
294 struct adapter *adapter = pi->adapter;
292 int ret; 295 int ret;
293 296
294 mutex_lock(&adapter->mdio_lock); 297 mutex_lock(&adapter->mdio_lock);
@@ -304,8 +307,9 @@ static int mi1_ext_write(struct adapter *adapter, int phy_addr, int mmd_addr,
304} 307}
305 308
306static const struct mdio_ops mi1_mdio_ext_ops = { 309static const struct mdio_ops mi1_mdio_ext_ops = {
307 mi1_ext_read, 310 .read = mi1_ext_read,
308 mi1_ext_write 311 .write = mi1_ext_write,
312 .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
309}; 313};
310 314
311/** 315/**
@@ -325,10 +329,10 @@ int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
325 int ret; 329 int ret;
326 unsigned int val; 330 unsigned int val;
327 331
328 ret = mdio_read(phy, mmd, reg, &val); 332 ret = t3_mdio_read(phy, mmd, reg, &val);
329 if (!ret) { 333 if (!ret) {
330 val &= ~clear; 334 val &= ~clear;
331 ret = mdio_write(phy, mmd, reg, val | set); 335 ret = t3_mdio_write(phy, mmd, reg, val | set);
332 } 336 }
333 return ret; 337 return ret;
334} 338}
@@ -348,15 +352,16 @@ int t3_phy_reset(struct cphy *phy, int mmd, int wait)
348 int err; 352 int err;
349 unsigned int ctl; 353 unsigned int ctl;
350 354
351 err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET); 355 err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER,
356 MDIO_CTRL1_RESET);
352 if (err || !wait) 357 if (err || !wait)
353 return err; 358 return err;
354 359
355 do { 360 do {
356 err = mdio_read(phy, mmd, MII_BMCR, &ctl); 361 err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl);
357 if (err) 362 if (err)
358 return err; 363 return err;
359 ctl &= BMCR_RESET; 364 ctl &= MDIO_CTRL1_RESET;
360 if (ctl) 365 if (ctl)
361 msleep(1); 366 msleep(1);
362 } while (ctl && --wait); 367 } while (ctl && --wait);
@@ -377,7 +382,7 @@ int t3_phy_advertise(struct cphy *phy, unsigned int advert)
377 int err; 382 int err;
378 unsigned int val = 0; 383 unsigned int val = 0;
379 384
380 err = mdio_read(phy, 0, MII_CTRL1000, &val); 385 err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_CTRL1000, &val);
381 if (err) 386 if (err)
382 return err; 387 return err;
383 388
@@ -387,7 +392,7 @@ int t3_phy_advertise(struct cphy *phy, unsigned int advert)
387 if (advert & ADVERTISED_1000baseT_Full) 392 if (advert & ADVERTISED_1000baseT_Full)
388 val |= ADVERTISE_1000FULL; 393 val |= ADVERTISE_1000FULL;
389 394
390 err = mdio_write(phy, 0, MII_CTRL1000, val); 395 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_CTRL1000, val);
391 if (err) 396 if (err)
392 return err; 397 return err;
393 398
@@ -404,7 +409,7 @@ int t3_phy_advertise(struct cphy *phy, unsigned int advert)
404 val |= ADVERTISE_PAUSE_CAP; 409 val |= ADVERTISE_PAUSE_CAP;
405 if (advert & ADVERTISED_Asym_Pause) 410 if (advert & ADVERTISED_Asym_Pause)
406 val |= ADVERTISE_PAUSE_ASYM; 411 val |= ADVERTISE_PAUSE_ASYM;
407 return mdio_write(phy, 0, MII_ADVERTISE, val); 412 return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val);
408} 413}
409 414
410/** 415/**
@@ -427,7 +432,7 @@ int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
427 val |= ADVERTISE_1000XPAUSE; 432 val |= ADVERTISE_1000XPAUSE;
428 if (advert & ADVERTISED_Asym_Pause) 433 if (advert & ADVERTISED_Asym_Pause)
429 val |= ADVERTISE_1000XPSE_ASYM; 434 val |= ADVERTISE_1000XPSE_ASYM;
430 return mdio_write(phy, 0, MII_ADVERTISE, val); 435 return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val);
431} 436}
432 437
433/** 438/**
@@ -444,7 +449,7 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
444 int err; 449 int err;
445 unsigned int ctl; 450 unsigned int ctl;
446 451
447 err = mdio_read(phy, 0, MII_BMCR, &ctl); 452 err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_BMCR, &ctl);
448 if (err) 453 if (err)
449 return err; 454 return err;
450 455
@@ -462,30 +467,30 @@ int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
462 } 467 }
463 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */ 468 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
464 ctl |= BMCR_ANENABLE; 469 ctl |= BMCR_ANENABLE;
465 return mdio_write(phy, 0, MII_BMCR, ctl); 470 return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_BMCR, ctl);
466} 471}
467 472
468int t3_phy_lasi_intr_enable(struct cphy *phy) 473int t3_phy_lasi_intr_enable(struct cphy *phy)
469{ 474{
470 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1); 475 return t3_mdio_write(phy, MDIO_MMD_PMAPMD, LASI_CTRL, 1);
471} 476}
472 477
473int t3_phy_lasi_intr_disable(struct cphy *phy) 478int t3_phy_lasi_intr_disable(struct cphy *phy)
474{ 479{
475 return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0); 480 return t3_mdio_write(phy, MDIO_MMD_PMAPMD, LASI_CTRL, 0);
476} 481}
477 482
478int t3_phy_lasi_intr_clear(struct cphy *phy) 483int t3_phy_lasi_intr_clear(struct cphy *phy)
479{ 484{
480 u32 val; 485 u32 val;
481 486
482 return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val); 487 return t3_mdio_read(phy, MDIO_MMD_PMAPMD, LASI_STAT, &val);
483} 488}
484 489
485int t3_phy_lasi_intr_handler(struct cphy *phy) 490int t3_phy_lasi_intr_handler(struct cphy *phy)
486{ 491{
487 unsigned int status; 492 unsigned int status;
488 int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status); 493 int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, LASI_STAT, &status);
489 494
490 if (err) 495 if (err)
491 return err; 496 return err;
@@ -3863,6 +3868,7 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
3863 ai->mdio_ops); 3868 ai->mdio_ops);
3864 if (ret) 3869 if (ret)
3865 return ret; 3870 return ret;
3871 p->phy.mdio.dev = adapter->port[i];
3866 mac_prep(&p->mac, adapter, j); 3872 mac_prep(&p->mac, adapter, j);
3867 3873
3868 /* 3874 /*
@@ -3918,7 +3924,7 @@ int t3_replay_prep_adapter(struct adapter *adapter)
3918 ; 3924 ;
3919 3925
3920 pti = &port_types[adapter->params.vpd.port_type[j]]; 3926 pti = &port_types[adapter->params.vpd.port_type[j]];
3921 ret = pti->phy_prep(&p->phy, adapter, p->phy.addr, NULL); 3927 ret = pti->phy_prep(&p->phy, adapter, p->phy.mdio.prtad, NULL);
3922 if (ret) 3928 if (ret)
3923 return ret; 3929 return ret;
3924 p->phy.ops->power_down(&p->phy, 1); 3930 p->phy.ops->power_down(&p->phy, 1);
diff --git a/drivers/net/cxgb3/vsc8211.c b/drivers/net/cxgb3/vsc8211.c
index d07130971b8f..4f9a1c2724f4 100644
--- a/drivers/net/cxgb3/vsc8211.c
+++ b/drivers/net/cxgb3/vsc8211.c
@@ -91,17 +91,18 @@ enum {
91 */ 91 */
92static int vsc8211_reset(struct cphy *cphy, int wait) 92static int vsc8211_reset(struct cphy *cphy, int wait)
93{ 93{
94 return t3_phy_reset(cphy, 0, 0); 94 return t3_phy_reset(cphy, MDIO_DEVAD_NONE, 0);
95} 95}
96 96
97static int vsc8211_intr_enable(struct cphy *cphy) 97static int vsc8211_intr_enable(struct cphy *cphy)
98{ 98{
99 return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, INTR_MASK); 99 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE,
100 INTR_MASK);
100} 101}
101 102
102static int vsc8211_intr_disable(struct cphy *cphy) 103static int vsc8211_intr_disable(struct cphy *cphy)
103{ 104{
104 return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, 0); 105 return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, 0);
105} 106}
106 107
107static int vsc8211_intr_clear(struct cphy *cphy) 108static int vsc8211_intr_clear(struct cphy *cphy)
@@ -109,18 +110,20 @@ static int vsc8211_intr_clear(struct cphy *cphy)
109 u32 val; 110 u32 val;
110 111
111 /* Clear PHY interrupts by reading the register. */ 112 /* Clear PHY interrupts by reading the register. */
112 return mdio_read(cphy, 0, VSC8211_INTR_STATUS, &val); 113 return t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &val);
113} 114}
114 115
115static int vsc8211_autoneg_enable(struct cphy *cphy) 116static int vsc8211_autoneg_enable(struct cphy *cphy)
116{ 117{
117 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 118 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
119 BMCR_PDOWN | BMCR_ISOLATE,
118 BMCR_ANENABLE | BMCR_ANRESTART); 120 BMCR_ANENABLE | BMCR_ANRESTART);
119} 121}
120 122
121static int vsc8211_autoneg_restart(struct cphy *cphy) 123static int vsc8211_autoneg_restart(struct cphy *cphy)
122{ 124{
123 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 125 return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
126 BMCR_PDOWN | BMCR_ISOLATE,
124 BMCR_ANRESTART); 127 BMCR_ANRESTART);
125} 128}
126 129
@@ -130,9 +133,9 @@ static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
130 unsigned int bmcr, status, lpa, adv; 133 unsigned int bmcr, status, lpa, adv;
131 int err, sp = -1, dplx = -1, pause = 0; 134 int err, sp = -1, dplx = -1, pause = 0;
132 135
133 err = mdio_read(cphy, 0, MII_BMCR, &bmcr); 136 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
134 if (!err) 137 if (!err)
135 err = mdio_read(cphy, 0, MII_BMSR, &status); 138 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status);
136 if (err) 139 if (err)
137 return err; 140 return err;
138 141
@@ -142,7 +145,8 @@ static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
142 * once more to get the current link state. 145 * once more to get the current link state.
143 */ 146 */
144 if (!(status & BMSR_LSTATUS)) 147 if (!(status & BMSR_LSTATUS))
145 err = mdio_read(cphy, 0, MII_BMSR, &status); 148 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR,
149 &status);
146 if (err) 150 if (err)
147 return err; 151 return err;
148 *link_ok = (status & BMSR_LSTATUS) != 0; 152 *link_ok = (status & BMSR_LSTATUS) != 0;
@@ -156,7 +160,8 @@ static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
156 else 160 else
157 sp = SPEED_10; 161 sp = SPEED_10;
158 } else if (status & BMSR_ANEGCOMPLETE) { 162 } else if (status & BMSR_ANEGCOMPLETE) {
159 err = mdio_read(cphy, 0, VSC8211_AUX_CTRL_STAT, &status); 163 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_AUX_CTRL_STAT,
164 &status);
160 if (err) 165 if (err)
161 return err; 166 return err;
162 167
@@ -170,9 +175,11 @@ static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
170 sp = SPEED_1000; 175 sp = SPEED_1000;
171 176
172 if (fc && dplx == DUPLEX_FULL) { 177 if (fc && dplx == DUPLEX_FULL) {
173 err = mdio_read(cphy, 0, MII_LPA, &lpa); 178 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_LPA,
179 &lpa);
174 if (!err) 180 if (!err)
175 err = mdio_read(cphy, 0, MII_ADVERTISE, &adv); 181 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE,
182 MII_ADVERTISE, &adv);
176 if (err) 183 if (err)
177 return err; 184 return err;
178 185
@@ -202,9 +209,9 @@ static int vsc8211_get_link_status_fiber(struct cphy *cphy, int *link_ok,
202 unsigned int bmcr, status, lpa, adv; 209 unsigned int bmcr, status, lpa, adv;
203 int err, sp = -1, dplx = -1, pause = 0; 210 int err, sp = -1, dplx = -1, pause = 0;
204 211
205 err = mdio_read(cphy, 0, MII_BMCR, &bmcr); 212 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
206 if (!err) 213 if (!err)
207 err = mdio_read(cphy, 0, MII_BMSR, &status); 214 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status);
208 if (err) 215 if (err)
209 return err; 216 return err;
210 217
@@ -214,7 +221,8 @@ static int vsc8211_get_link_status_fiber(struct cphy *cphy, int *link_ok,
214 * once more to get the current link state. 221 * once more to get the current link state.
215 */ 222 */
216 if (!(status & BMSR_LSTATUS)) 223 if (!(status & BMSR_LSTATUS))
217 err = mdio_read(cphy, 0, MII_BMSR, &status); 224 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR,
225 &status);
218 if (err) 226 if (err)
219 return err; 227 return err;
220 *link_ok = (status & BMSR_LSTATUS) != 0; 228 *link_ok = (status & BMSR_LSTATUS) != 0;
@@ -228,9 +236,10 @@ static int vsc8211_get_link_status_fiber(struct cphy *cphy, int *link_ok,
228 else 236 else
229 sp = SPEED_10; 237 sp = SPEED_10;
230 } else if (status & BMSR_ANEGCOMPLETE) { 238 } else if (status & BMSR_ANEGCOMPLETE) {
231 err = mdio_read(cphy, 0, MII_LPA, &lpa); 239 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_LPA, &lpa);
232 if (!err) 240 if (!err)
233 err = mdio_read(cphy, 0, MII_ADVERTISE, &adv); 241 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_ADVERTISE,
242 &adv);
234 if (err) 243 if (err)
235 return err; 244 return err;
236 245
@@ -270,23 +279,23 @@ static int vsc8211_set_automdi(struct cphy *phy, int enable)
270{ 279{
271 int err; 280 int err;
272 281
273 err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0x52b5); 282 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0x52b5);
274 if (err) 283 if (err)
275 return err; 284 return err;
276 285
277 err = mdio_write(phy, 0, 18, 0x12); 286 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 18, 0x12);
278 if (err) 287 if (err)
279 return err; 288 return err;
280 289
281 err = mdio_write(phy, 0, 17, enable ? 0x2803 : 0x3003); 290 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 17, enable ? 0x2803 : 0x3003);
282 if (err) 291 if (err)
283 return err; 292 return err;
284 293
285 err = mdio_write(phy, 0, 16, 0x87fa); 294 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 16, 0x87fa);
286 if (err) 295 if (err)
287 return err; 296 return err;
288 297
289 err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0); 298 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0);
290 if (err) 299 if (err)
291 return err; 300 return err;
292 301
@@ -315,7 +324,7 @@ static int vsc8211_intr_handler(struct cphy *cphy)
315 unsigned int cause; 324 unsigned int cause;
316 int err, cphy_cause = 0; 325 int err, cphy_cause = 0;
317 326
318 err = mdio_read(cphy, 0, VSC8211_INTR_STATUS, &cause); 327 err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &cause);
319 if (err) 328 if (err)
320 return err; 329 return err;
321 330
@@ -367,12 +376,13 @@ int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
367 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); 376 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T");
368 msleep(20); /* PHY needs ~10ms to start responding to MDIO */ 377 msleep(20); /* PHY needs ~10ms to start responding to MDIO */
369 378
370 err = mdio_read(phy, 0, VSC8211_EXT_CTRL, &val); 379 err = t3_mdio_read(phy, MDIO_DEVAD_NONE, VSC8211_EXT_CTRL, &val);
371 if (err) 380 if (err)
372 return err; 381 return err;
373 if (val & VSC_CTRL_MEDIA_MODE_HI) { 382 if (val & VSC_CTRL_MEDIA_MODE_HI) {
374 /* copper interface, just need to configure the LEDs */ 383 /* copper interface, just need to configure the LEDs */
375 return mdio_write(phy, 0, VSC8211_LED_CTRL, 0x100); 384 return t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_LED_CTRL,
385 0x100);
376 } 386 }
377 387
378 phy->caps = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | 388 phy->caps = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
@@ -380,20 +390,20 @@ int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
380 phy->desc = "1000BASE-X"; 390 phy->desc = "1000BASE-X";
381 phy->ops = &vsc8211_fiber_ops; 391 phy->ops = &vsc8211_fiber_ops;
382 392
383 err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 1); 393 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 1);
384 if (err) 394 if (err)
385 return err; 395 return err;
386 396
387 err = mdio_write(phy, 0, VSC8211_SIGDET_CTRL, 1); 397 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_SIGDET_CTRL, 1);
388 if (err) 398 if (err)
389 return err; 399 return err;
390 400
391 err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0); 401 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0);
392 if (err) 402 if (err)
393 return err; 403 return err;
394 404
395 err = mdio_write(phy, 0, VSC8211_EXT_CTRL, 405 err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_CTRL,
396 val | VSC_CTRL_CLAUSE37_VIEW); 406 val | VSC_CTRL_CLAUSE37_VIEW);
397 if (err) 407 if (err)
398 return err; 408 return err;
399 409