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authorDivy Le Ray <divy@chelsio.com>2008-05-06 22:26:01 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-13 01:31:37 -0400
commit204e2f98c2d13f869b8541f3c57c7314f75cab11 (patch)
treea415a3e80acfe19298d0238747aed6b665971558 /drivers/net/cxgb3/regs.h
parent48c4b6dbb7e246957e13302668acf7c77e4f8b3a (diff)
cxgb3 - fix EEH
Reset the chip when the PCI link goes down. Preserve the napi structure when a sge qset's resources are freed. Replay only HW initialization when the chip comes out of reset. Signed-off-by: Divy Le ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/cxgb3/regs.h')
-rw-r--r--drivers/net/cxgb3/regs.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/cxgb3/regs.h b/drivers/net/cxgb3/regs.h
index 02dbbb300929..567178879345 100644
--- a/drivers/net/cxgb3/regs.h
+++ b/drivers/net/cxgb3/regs.h
@@ -444,6 +444,14 @@
444 444
445#define A_PCIE_CFG 0x88 445#define A_PCIE_CFG 0x88
446 446
447#define S_ENABLELINKDWNDRST 21
448#define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
449#define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U)
450
451#define S_ENABLELINKDOWNRST 20
452#define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
453#define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U)
454
447#define S_PCIE_CLIDECEN 16 455#define S_PCIE_CLIDECEN 16
448#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) 456#define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
449#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) 457#define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U)