diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2009-04-29 04:07:20 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-04-29 20:32:32 -0400 |
commit | 0f07c4ee8c800923ae7918c231532a9256233eed (patch) | |
tree | 659322e8607f681af12a43671b17c5b65f94f4d5 /drivers/net/cxgb3/ael1002.c | |
parent | 23c3320cb039debfb94b27e8e9bfe26dd47692c3 (diff) |
cxgb3: Use generic MDIO definitions and mdio_mii_ioctl()
Compile-tested only.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/cxgb3/ael1002.c')
-rw-r--r-- | drivers/net/cxgb3/ael1002.c | 146 |
1 files changed, 76 insertions, 70 deletions
diff --git a/drivers/net/cxgb3/ael1002.c b/drivers/net/cxgb3/ael1002.c index e1b22490ff59..bebc00d2424d 100644 --- a/drivers/net/cxgb3/ael1002.c +++ b/drivers/net/cxgb3/ael1002.c | |||
@@ -33,14 +33,6 @@ | |||
33 | #include "regs.h" | 33 | #include "regs.h" |
34 | 34 | ||
35 | enum { | 35 | enum { |
36 | PMD_RSD = 10, /* PMA/PMD receive signal detect register */ | ||
37 | PCS_STAT1_X = 24, /* 10GBASE-X PCS status 1 register */ | ||
38 | PCS_STAT1_R = 32, /* 10GBASE-R PCS status 1 register */ | ||
39 | XS_LN_STAT = 24 /* XS lane status register */ | ||
40 | }; | ||
41 | |||
42 | enum { | ||
43 | AEL100X_TX_DISABLE = 9, | ||
44 | AEL100X_TX_CONFIG1 = 0xc002, | 36 | AEL100X_TX_CONFIG1 = 0xc002, |
45 | AEL1002_PWR_DOWN_HI = 0xc011, | 37 | AEL1002_PWR_DOWN_HI = 0xc011, |
46 | AEL1002_PWR_DOWN_LO = 0xc012, | 38 | AEL1002_PWR_DOWN_LO = 0xc012, |
@@ -74,8 +66,8 @@ static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) | |||
74 | 66 | ||
75 | for (err = 0; rv->mmd_addr && !err; rv++) { | 67 | for (err = 0; rv->mmd_addr && !err; rv++) { |
76 | if (rv->clear_bits == 0xffff) | 68 | if (rv->clear_bits == 0xffff) |
77 | err = mdio_write(phy, rv->mmd_addr, rv->reg_addr, | 69 | err = t3_mdio_write(phy, rv->mmd_addr, rv->reg_addr, |
78 | rv->set_bits); | 70 | rv->set_bits); |
79 | else | 71 | else |
80 | err = t3_mdio_change_bits(phy, rv->mmd_addr, | 72 | err = t3_mdio_change_bits(phy, rv->mmd_addr, |
81 | rv->reg_addr, rv->clear_bits, | 73 | rv->reg_addr, rv->clear_bits, |
@@ -86,7 +78,8 @@ static int set_phy_regs(struct cphy *phy, const struct reg_val *rv) | |||
86 | 78 | ||
87 | static void ael100x_txon(struct cphy *phy) | 79 | static void ael100x_txon(struct cphy *phy) |
88 | { | 80 | { |
89 | int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; | 81 | int tx_on_gpio = |
82 | phy->mdio.prtad == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; | ||
90 | 83 | ||
91 | msleep(100); | 84 | msleep(100); |
92 | t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); | 85 | t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); |
@@ -97,10 +90,11 @@ static int ael1002_power_down(struct cphy *phy, int enable) | |||
97 | { | 90 | { |
98 | int err; | 91 | int err; |
99 | 92 | ||
100 | err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable); | 93 | err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, !!enable); |
101 | if (!err) | 94 | if (!err) |
102 | err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, | 95 | err = mdio_set_flag(&phy->mdio, phy->mdio.prtad, |
103 | BMCR_PDOWN, enable ? BMCR_PDOWN : 0); | 96 | MDIO_MMD_PMAPMD, MDIO_CTRL1, |
97 | MDIO_CTRL1_LPOWER, enable); | ||
104 | return err; | 98 | return err; |
105 | } | 99 | } |
106 | 100 | ||
@@ -109,11 +103,11 @@ static int ael1002_reset(struct cphy *phy, int wait) | |||
109 | int err; | 103 | int err; |
110 | 104 | ||
111 | if ((err = ael1002_power_down(phy, 0)) || | 105 | if ((err = ael1002_power_down(phy, 0)) || |
112 | (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) || | 106 | (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL100X_TX_CONFIG1, 1)) || |
113 | (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) || | 107 | (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_HI, 0)) || |
114 | (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) || | 108 | (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_PWR_DOWN_LO, 0)) || |
115 | (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) || | 109 | (err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL1002_XFI_EQL, 0x18)) || |
116 | (err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN, | 110 | (err = t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL1002_LB_EN, |
117 | 0, 1 << 5))) | 111 | 0, 1 << 5))) |
118 | return err; | 112 | return err; |
119 | return 0; | 113 | return 0; |
@@ -132,12 +126,15 @@ static int get_link_status_r(struct cphy *phy, int *link_ok, int *speed, | |||
132 | { | 126 | { |
133 | if (link_ok) { | 127 | if (link_ok) { |
134 | unsigned int stat0, stat1, stat2; | 128 | unsigned int stat0, stat1, stat2; |
135 | int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0); | 129 | int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, |
130 | MDIO_PMA_RXDET, &stat0); | ||
136 | 131 | ||
137 | if (!err) | 132 | if (!err) |
138 | err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_R, &stat1); | 133 | err = t3_mdio_read(phy, MDIO_MMD_PCS, |
134 | MDIO_PCS_10GBRT_STAT1, &stat1); | ||
139 | if (!err) | 135 | if (!err) |
140 | err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2); | 136 | err = t3_mdio_read(phy, MDIO_MMD_PHYXS, |
137 | MDIO_PHYXS_LNSTAT, &stat2); | ||
141 | if (err) | 138 | if (err) |
142 | return err; | 139 | return err; |
143 | *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1; | 140 | *link_ok = (stat0 & stat1 & (stat2 >> 12)) & 1; |
@@ -157,6 +154,7 @@ static struct cphy_ops ael1002_ops = { | |||
157 | .intr_handler = ael1002_intr_noop, | 154 | .intr_handler = ael1002_intr_noop, |
158 | .get_link_status = get_link_status_r, | 155 | .get_link_status = get_link_status_r, |
159 | .power_down = ael1002_power_down, | 156 | .power_down = ael1002_power_down, |
157 | .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, | ||
160 | }; | 158 | }; |
161 | 159 | ||
162 | int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, | 160 | int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, |
@@ -171,13 +169,13 @@ int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, | |||
171 | 169 | ||
172 | static int ael1006_reset(struct cphy *phy, int wait) | 170 | static int ael1006_reset(struct cphy *phy, int wait) |
173 | { | 171 | { |
174 | return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait); | 172 | return t3_phy_reset(phy, MDIO_MMD_PMAPMD, wait); |
175 | } | 173 | } |
176 | 174 | ||
177 | static int ael1006_power_down(struct cphy *phy, int enable) | 175 | static int ael1006_power_down(struct cphy *phy, int enable) |
178 | { | 176 | { |
179 | return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, | 177 | return mdio_set_flag(&phy->mdio, phy->mdio.prtad, MDIO_MMD_PMAPMD, |
180 | BMCR_PDOWN, enable ? BMCR_PDOWN : 0); | 178 | MDIO_CTRL1, MDIO_CTRL1_LPOWER, enable); |
181 | } | 179 | } |
182 | 180 | ||
183 | static struct cphy_ops ael1006_ops = { | 181 | static struct cphy_ops ael1006_ops = { |
@@ -188,6 +186,7 @@ static struct cphy_ops ael1006_ops = { | |||
188 | .intr_handler = t3_phy_lasi_intr_handler, | 186 | .intr_handler = t3_phy_lasi_intr_handler, |
189 | .get_link_status = get_link_status_r, | 187 | .get_link_status = get_link_status_r, |
190 | .power_down = ael1006_power_down, | 188 | .power_down = ael1006_power_down, |
189 | .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, | ||
191 | }; | 190 | }; |
192 | 191 | ||
193 | int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, | 192 | int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, |
@@ -203,9 +202,9 @@ int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, | |||
203 | static int ael2005_setup_sr_edc(struct cphy *phy) | 202 | static int ael2005_setup_sr_edc(struct cphy *phy) |
204 | { | 203 | { |
205 | static struct reg_val regs[] = { | 204 | static struct reg_val regs[] = { |
206 | { MDIO_DEV_PMA_PMD, 0xc003, 0xffff, 0x181 }, | 205 | { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 }, |
207 | { MDIO_DEV_PMA_PMD, 0xc010, 0xffff, 0x448a }, | 206 | { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a }, |
208 | { MDIO_DEV_PMA_PMD, 0xc04a, 0xffff, 0x5200 }, | 207 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 }, |
209 | { 0, 0, 0, 0 } | 208 | { 0, 0, 0, 0 } |
210 | }; | 209 | }; |
211 | static u16 sr_edc[] = { | 210 | static u16 sr_edc[] = { |
@@ -490,8 +489,8 @@ static int ael2005_setup_sr_edc(struct cphy *phy) | |||
490 | msleep(50); | 489 | msleep(50); |
491 | 490 | ||
492 | for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2) | 491 | for (i = 0; i < ARRAY_SIZE(sr_edc) && !err; i += 2) |
493 | err = mdio_write(phy, MDIO_DEV_PMA_PMD, sr_edc[i], | 492 | err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, sr_edc[i], |
494 | sr_edc[i + 1]); | 493 | sr_edc[i + 1]); |
495 | if (!err) | 494 | if (!err) |
496 | phy->priv = edc_sr; | 495 | phy->priv = edc_sr; |
497 | return err; | 496 | return err; |
@@ -500,12 +499,12 @@ static int ael2005_setup_sr_edc(struct cphy *phy) | |||
500 | static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) | 499 | static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) |
501 | { | 500 | { |
502 | static struct reg_val regs[] = { | 501 | static struct reg_val regs[] = { |
503 | { MDIO_DEV_PMA_PMD, 0xc04a, 0xffff, 0x5a00 }, | 502 | { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 }, |
504 | { 0, 0, 0, 0 } | 503 | { 0, 0, 0, 0 } |
505 | }; | 504 | }; |
506 | static struct reg_val preemphasis[] = { | 505 | static struct reg_val preemphasis[] = { |
507 | { MDIO_DEV_PMA_PMD, 0xc014, 0xffff, 0xfe16 }, | 506 | { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 }, |
508 | { MDIO_DEV_PMA_PMD, 0xc015, 0xffff, 0xa000 }, | 507 | { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 }, |
509 | { 0, 0, 0, 0 } | 508 | { 0, 0, 0, 0 } |
510 | }; | 509 | }; |
511 | static u16 twinax_edc[] = { | 510 | static u16 twinax_edc[] = { |
@@ -887,8 +886,8 @@ static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype) | |||
887 | msleep(50); | 886 | msleep(50); |
888 | 887 | ||
889 | for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) | 888 | for (i = 0; i < ARRAY_SIZE(twinax_edc) && !err; i += 2) |
890 | err = mdio_write(phy, MDIO_DEV_PMA_PMD, twinax_edc[i], | 889 | err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, twinax_edc[i], |
891 | twinax_edc[i + 1]); | 890 | twinax_edc[i + 1]); |
892 | if (!err) | 891 | if (!err) |
893 | phy->priv = edc_twinax; | 892 | phy->priv = edc_twinax; |
894 | return err; | 893 | return err; |
@@ -899,26 +898,26 @@ static int ael2005_i2c_rd(struct cphy *phy, int dev_addr, int word_addr) | |||
899 | int i, err; | 898 | int i, err; |
900 | unsigned int stat, data; | 899 | unsigned int stat, data; |
901 | 900 | ||
902 | err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL_I2C_CTRL, | 901 | err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL_I2C_CTRL, |
903 | (dev_addr << 8) | (1 << 8) | word_addr); | 902 | (dev_addr << 8) | (1 << 8) | word_addr); |
904 | if (err) | 903 | if (err) |
905 | return err; | 904 | return err; |
906 | 905 | ||
907 | for (i = 0; i < 5; i++) { | 906 | for (i = 0; i < 5; i++) { |
908 | msleep(1); | 907 | msleep(1); |
909 | err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_STAT, &stat); | 908 | err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_STAT, &stat); |
910 | if (err) | 909 | if (err) |
911 | return err; | 910 | return err; |
912 | if ((stat & 3) == 1) { | 911 | if ((stat & 3) == 1) { |
913 | err = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL_I2C_DATA, | 912 | err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL_I2C_DATA, |
914 | &data); | 913 | &data); |
915 | if (err) | 914 | if (err) |
916 | return err; | 915 | return err; |
917 | return data >> 8; | 916 | return data >> 8; |
918 | } | 917 | } |
919 | } | 918 | } |
920 | CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n", | 919 | CH_WARN(phy->adapter, "PHY %u I2C read of addr %u timed out\n", |
921 | phy->addr, word_addr); | 920 | phy->mdio.prtad, word_addr); |
922 | return -ETIMEDOUT; | 921 | return -ETIMEDOUT; |
923 | } | 922 | } |
924 | 923 | ||
@@ -927,7 +926,7 @@ static int get_module_type(struct cphy *phy, int delay_ms) | |||
927 | int v; | 926 | int v; |
928 | unsigned int stat; | 927 | unsigned int stat; |
929 | 928 | ||
930 | v = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, &stat); | 929 | v = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, &stat); |
931 | if (v) | 930 | if (v) |
932 | return v; | 931 | return v; |
933 | 932 | ||
@@ -971,48 +970,48 @@ unknown: | |||
971 | 970 | ||
972 | static int ael2005_intr_enable(struct cphy *phy) | 971 | static int ael2005_intr_enable(struct cphy *phy) |
973 | { | 972 | { |
974 | int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x200); | 973 | int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x200); |
975 | return err ? err : t3_phy_lasi_intr_enable(phy); | 974 | return err ? err : t3_phy_lasi_intr_enable(phy); |
976 | } | 975 | } |
977 | 976 | ||
978 | static int ael2005_intr_disable(struct cphy *phy) | 977 | static int ael2005_intr_disable(struct cphy *phy) |
979 | { | 978 | { |
980 | int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0x100); | 979 | int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0x100); |
981 | return err ? err : t3_phy_lasi_intr_disable(phy); | 980 | return err ? err : t3_phy_lasi_intr_disable(phy); |
982 | } | 981 | } |
983 | 982 | ||
984 | static int ael2005_intr_clear(struct cphy *phy) | 983 | static int ael2005_intr_clear(struct cphy *phy) |
985 | { | 984 | { |
986 | int err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, 0xd00); | 985 | int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, 0xd00); |
987 | return err ? err : t3_phy_lasi_intr_clear(phy); | 986 | return err ? err : t3_phy_lasi_intr_clear(phy); |
988 | } | 987 | } |
989 | 988 | ||
990 | static int ael2005_reset(struct cphy *phy, int wait) | 989 | static int ael2005_reset(struct cphy *phy, int wait) |
991 | { | 990 | { |
992 | static struct reg_val regs0[] = { | 991 | static struct reg_val regs0[] = { |
993 | { MDIO_DEV_PMA_PMD, 0xc001, 0, 1 << 5 }, | 992 | { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 }, |
994 | { MDIO_DEV_PMA_PMD, 0xc017, 0, 1 << 5 }, | 993 | { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 }, |
995 | { MDIO_DEV_PMA_PMD, 0xc013, 0xffff, 0xf341 }, | 994 | { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 }, |
996 | { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8000 }, | 995 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, |
997 | { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8100 }, | 996 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8100 }, |
998 | { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0x8000 }, | 997 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0x8000 }, |
999 | { MDIO_DEV_PMA_PMD, 0xc210, 0xffff, 0 }, | 998 | { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 }, |
1000 | { 0, 0, 0, 0 } | 999 | { 0, 0, 0, 0 } |
1001 | }; | 1000 | }; |
1002 | static struct reg_val regs1[] = { | 1001 | static struct reg_val regs1[] = { |
1003 | { MDIO_DEV_PMA_PMD, 0xca00, 0xffff, 0x0080 }, | 1002 | { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 }, |
1004 | { MDIO_DEV_PMA_PMD, 0xca12, 0xffff, 0 }, | 1003 | { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 }, |
1005 | { 0, 0, 0, 0 } | 1004 | { 0, 0, 0, 0 } |
1006 | }; | 1005 | }; |
1007 | 1006 | ||
1008 | int err; | 1007 | int err; |
1009 | unsigned int lasi_ctrl; | 1008 | unsigned int lasi_ctrl; |
1010 | 1009 | ||
1011 | err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, &lasi_ctrl); | 1010 | err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, LASI_CTRL, &lasi_ctrl); |
1012 | if (err) | 1011 | if (err) |
1013 | return err; | 1012 | return err; |
1014 | 1013 | ||
1015 | err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, 0); | 1014 | err = t3_phy_reset(phy, MDIO_MMD_PMAPMD, 0); |
1016 | if (err) | 1015 | if (err) |
1017 | return err; | 1016 | return err; |
1018 | 1017 | ||
@@ -1051,13 +1050,13 @@ static int ael2005_intr_handler(struct cphy *phy) | |||
1051 | unsigned int stat; | 1050 | unsigned int stat; |
1052 | int ret, edc_needed, cause = 0; | 1051 | int ret, edc_needed, cause = 0; |
1053 | 1052 | ||
1054 | ret = mdio_read(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_STAT, &stat); | 1053 | ret = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_STAT, &stat); |
1055 | if (ret) | 1054 | if (ret) |
1056 | return ret; | 1055 | return ret; |
1057 | 1056 | ||
1058 | if (stat & AEL2005_MODDET_IRQ) { | 1057 | if (stat & AEL2005_MODDET_IRQ) { |
1059 | ret = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL2005_GPIO_CTRL, | 1058 | ret = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AEL2005_GPIO_CTRL, |
1060 | 0xd00); | 1059 | 0xd00); |
1061 | if (ret) | 1060 | if (ret) |
1062 | return ret; | 1061 | return ret; |
1063 | 1062 | ||
@@ -1098,6 +1097,7 @@ static struct cphy_ops ael2005_ops = { | |||
1098 | .intr_handler = ael2005_intr_handler, | 1097 | .intr_handler = ael2005_intr_handler, |
1099 | .get_link_status = get_link_status_r, | 1098 | .get_link_status = get_link_status_r, |
1100 | .power_down = ael1002_power_down, | 1099 | .power_down = ael1002_power_down, |
1100 | .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, | ||
1101 | }; | 1101 | }; |
1102 | 1102 | ||
1103 | int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, | 1103 | int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, |
@@ -1107,7 +1107,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, | |||
1107 | SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | | 1107 | SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_FIBRE | |
1108 | SUPPORTED_IRQ, "10GBASE-R"); | 1108 | SUPPORTED_IRQ, "10GBASE-R"); |
1109 | msleep(125); | 1109 | msleep(125); |
1110 | return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL_OPT_SETTINGS, 0, | 1110 | return t3_mdio_change_bits(phy, MDIO_MMD_PMAPMD, AEL_OPT_SETTINGS, 0, |
1111 | 1 << 5); | 1111 | 1 << 5); |
1112 | } | 1112 | } |
1113 | 1113 | ||
@@ -1119,12 +1119,15 @@ static int get_link_status_x(struct cphy *phy, int *link_ok, int *speed, | |||
1119 | { | 1119 | { |
1120 | if (link_ok) { | 1120 | if (link_ok) { |
1121 | unsigned int stat0, stat1, stat2; | 1121 | unsigned int stat0, stat1, stat2; |
1122 | int err = mdio_read(phy, MDIO_DEV_PMA_PMD, PMD_RSD, &stat0); | 1122 | int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, |
1123 | MDIO_PMA_RXDET, &stat0); | ||
1123 | 1124 | ||
1124 | if (!err) | 1125 | if (!err) |
1125 | err = mdio_read(phy, MDIO_DEV_PCS, PCS_STAT1_X, &stat1); | 1126 | err = t3_mdio_read(phy, MDIO_MMD_PCS, |
1127 | MDIO_PCS_10GBX_STAT1, &stat1); | ||
1126 | if (!err) | 1128 | if (!err) |
1127 | err = mdio_read(phy, MDIO_DEV_XGXS, XS_LN_STAT, &stat2); | 1129 | err = t3_mdio_read(phy, MDIO_MMD_PHYXS, |
1130 | MDIO_PHYXS_LNSTAT, &stat2); | ||
1128 | if (err) | 1131 | if (err) |
1129 | return err; | 1132 | return err; |
1130 | *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1; | 1133 | *link_ok = (stat0 & (stat1 >> 12) & (stat2 >> 12)) & 1; |
@@ -1144,6 +1147,7 @@ static struct cphy_ops qt2045_ops = { | |||
1144 | .intr_handler = t3_phy_lasi_intr_handler, | 1147 | .intr_handler = t3_phy_lasi_intr_handler, |
1145 | .get_link_status = get_link_status_x, | 1148 | .get_link_status = get_link_status_x, |
1146 | .power_down = ael1006_power_down, | 1149 | .power_down = ael1006_power_down, |
1150 | .mmds = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS, | ||
1147 | }; | 1151 | }; |
1148 | 1152 | ||
1149 | int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, | 1153 | int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, |
@@ -1159,9 +1163,10 @@ int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, | |||
1159 | * Some cards where the PHY is supposed to be at address 0 actually | 1163 | * Some cards where the PHY is supposed to be at address 0 actually |
1160 | * have it at 1. | 1164 | * have it at 1. |
1161 | */ | 1165 | */ |
1162 | if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) && | 1166 | if (!phy_addr && |
1167 | !t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &stat) && | ||
1163 | stat == 0xffff) | 1168 | stat == 0xffff) |
1164 | phy->addr = 1; | 1169 | phy->mdio.prtad = 1; |
1165 | return 0; | 1170 | return 0; |
1166 | } | 1171 | } |
1167 | 1172 | ||
@@ -1175,15 +1180,16 @@ static int xaui_direct_get_link_status(struct cphy *phy, int *link_ok, | |||
1175 | { | 1180 | { |
1176 | if (link_ok) { | 1181 | if (link_ok) { |
1177 | unsigned int status; | 1182 | unsigned int status; |
1183 | int prtad = phy->mdio.prtad; | ||
1178 | 1184 | ||
1179 | status = t3_read_reg(phy->adapter, | 1185 | status = t3_read_reg(phy->adapter, |
1180 | XGM_REG(A_XGM_SERDES_STAT0, phy->addr)) | | 1186 | XGM_REG(A_XGM_SERDES_STAT0, prtad)) | |
1181 | t3_read_reg(phy->adapter, | 1187 | t3_read_reg(phy->adapter, |
1182 | XGM_REG(A_XGM_SERDES_STAT1, phy->addr)) | | 1188 | XGM_REG(A_XGM_SERDES_STAT1, prtad)) | |
1183 | t3_read_reg(phy->adapter, | 1189 | t3_read_reg(phy->adapter, |
1184 | XGM_REG(A_XGM_SERDES_STAT2, phy->addr)) | | 1190 | XGM_REG(A_XGM_SERDES_STAT2, prtad)) | |
1185 | t3_read_reg(phy->adapter, | 1191 | t3_read_reg(phy->adapter, |
1186 | XGM_REG(A_XGM_SERDES_STAT3, phy->addr)); | 1192 | XGM_REG(A_XGM_SERDES_STAT3, prtad)); |
1187 | *link_ok = !(status & F_LOWSIG0); | 1193 | *link_ok = !(status & F_LOWSIG0); |
1188 | } | 1194 | } |
1189 | if (speed) | 1195 | if (speed) |
@@ -1211,7 +1217,7 @@ static struct cphy_ops xaui_direct_ops = { | |||
1211 | int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, | 1217 | int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, |
1212 | int phy_addr, const struct mdio_ops *mdio_ops) | 1218 | int phy_addr, const struct mdio_ops *mdio_ops) |
1213 | { | 1219 | { |
1214 | cphy_init(phy, adapter, phy_addr, &xaui_direct_ops, mdio_ops, | 1220 | cphy_init(phy, adapter, MDIO_PRTAD_NONE, &xaui_direct_ops, mdio_ops, |
1215 | SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, | 1221 | SUPPORTED_10000baseT_Full | SUPPORTED_AUI | SUPPORTED_TP, |
1216 | "10GBASE-CX4"); | 1222 | "10GBASE-CX4"); |
1217 | return 0; | 1223 | return 0; |