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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-07 09:57:17 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-10 22:54:52 -0400
commitf7917c009c28c941ba151ee66f04dc7f6a2e1e0b (patch)
tree91cd66b3b846b1113654de2ac31f085d0d7989ba /drivers/net/chelsio
parentadfc5217e9db68d3f0cec8dd847c1a6d3ab549ee (diff)
chelsio: Move the Chelsio drivers
Moves the drivers for the Chelsio chipsets into drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile changes. CC: Divy Le Ray <divy@chelsio.com> CC: Dimitris Michailidis <dm@chelsio.com> CC: Casey Leedom <leedom@chelsio.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/chelsio')
-rw-r--r--drivers/net/chelsio/Makefile9
-rw-r--r--drivers/net/chelsio/common.h353
-rw-r--r--drivers/net/chelsio/cphy.h175
-rw-r--r--drivers/net/chelsio/cpl5_cmd.h639
-rw-r--r--drivers/net/chelsio/cxgb2.c1379
-rw-r--r--drivers/net/chelsio/elmer0.h158
-rw-r--r--drivers/net/chelsio/espi.c373
-rw-r--r--drivers/net/chelsio/espi.h68
-rw-r--r--drivers/net/chelsio/fpga_defs.h232
-rw-r--r--drivers/net/chelsio/gmac.h142
-rw-r--r--drivers/net/chelsio/mv88e1xxx.c397
-rw-r--r--drivers/net/chelsio/mv88e1xxx.h127
-rw-r--r--drivers/net/chelsio/mv88x201x.c260
-rw-r--r--drivers/net/chelsio/my3126.c209
-rw-r--r--drivers/net/chelsio/pm3393.c796
-rw-r--r--drivers/net/chelsio/regs.h2168
-rw-r--r--drivers/net/chelsio/sge.c2140
-rw-r--r--drivers/net/chelsio/sge.h94
-rw-r--r--drivers/net/chelsio/subr.c1130
-rw-r--r--drivers/net/chelsio/suni1x10gexp_regs.h1643
-rw-r--r--drivers/net/chelsio/tp.c171
-rw-r--r--drivers/net/chelsio/tp.h72
-rw-r--r--drivers/net/chelsio/vsc7326.c730
-rw-r--r--drivers/net/chelsio/vsc7326_reg.h297
24 files changed, 0 insertions, 13762 deletions
diff --git a/drivers/net/chelsio/Makefile b/drivers/net/chelsio/Makefile
deleted file mode 100644
index 57a4b262fd3f..000000000000
--- a/drivers/net/chelsio/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1#
2# Chelsio T1 driver
3#
4
5obj-$(CONFIG_CHELSIO_T1) += cxgb.o
6
7cxgb-$(CONFIG_CHELSIO_T1_1G) += mv88e1xxx.o vsc7326.o
8cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \
9 mv88x201x.o my3126.o $(cxgb-y)
diff --git a/drivers/net/chelsio/common.h b/drivers/net/chelsio/common.h
deleted file mode 100644
index 5ccbed1784d2..000000000000
--- a/drivers/net/chelsio/common.h
+++ /dev/null
@@ -1,353 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: common.h *
4 * $Revision: 1.21 $ *
5 * $Date: 2005/06/22 00:43:25 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#define pr_fmt(fmt) "cxgb: " fmt
40
41#ifndef _CXGB_COMMON_H_
42#define _CXGB_COMMON_H_
43
44#include <linux/module.h>
45#include <linux/netdevice.h>
46#include <linux/types.h>
47#include <linux/delay.h>
48#include <linux/pci.h>
49#include <linux/ethtool.h>
50#include <linux/if_vlan.h>
51#include <linux/mdio.h>
52#include <linux/crc32.h>
53#include <linux/init.h>
54#include <linux/slab.h>
55#include <asm/io.h>
56#include <linux/pci_ids.h>
57
58#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
59#define DRV_NAME "cxgb"
60#define DRV_VERSION "2.2"
61
62#define CH_DEVICE(devid, ssid, idx) \
63 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
64
65#define SUPPORTED_PAUSE (1 << 13)
66#define SUPPORTED_LOOPBACK (1 << 15)
67
68#define ADVERTISED_PAUSE (1 << 13)
69#define ADVERTISED_ASYM_PAUSE (1 << 14)
70
71typedef struct adapter adapter_t;
72
73struct t1_rx_mode {
74 struct net_device *dev;
75};
76
77#define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
78#define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
79#define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev))
80#define t1_get_netdev(rm) (rm->dev)
81
82#define MAX_NPORTS 4
83#define PORT_MASK ((1 << MAX_NPORTS) - 1)
84#define NMTUS 8
85#define TCB_SIZE 128
86
87#define SPEED_INVALID 0xffff
88#define DUPLEX_INVALID 0xff
89
90enum {
91 CHBT_BOARD_N110,
92 CHBT_BOARD_N210,
93 CHBT_BOARD_7500,
94 CHBT_BOARD_8000,
95 CHBT_BOARD_CHT101,
96 CHBT_BOARD_CHT110,
97 CHBT_BOARD_CHT210,
98 CHBT_BOARD_CHT204,
99 CHBT_BOARD_CHT204V,
100 CHBT_BOARD_CHT204E,
101 CHBT_BOARD_CHN204,
102 CHBT_BOARD_COUGAR,
103 CHBT_BOARD_6800,
104 CHBT_BOARD_SIMUL,
105};
106
107enum {
108 CHBT_TERM_FPGA,
109 CHBT_TERM_T1,
110 CHBT_TERM_T2,
111 CHBT_TERM_T3
112};
113
114enum {
115 CHBT_MAC_CHELSIO_A,
116 CHBT_MAC_IXF1010,
117 CHBT_MAC_PM3393,
118 CHBT_MAC_VSC7321,
119 CHBT_MAC_DUMMY
120};
121
122enum {
123 CHBT_PHY_88E1041,
124 CHBT_PHY_88E1111,
125 CHBT_PHY_88X2010,
126 CHBT_PHY_XPAK,
127 CHBT_PHY_MY3126,
128 CHBT_PHY_8244,
129 CHBT_PHY_DUMMY
130};
131
132enum {
133 PAUSE_RX = 1 << 0,
134 PAUSE_TX = 1 << 1,
135 PAUSE_AUTONEG = 1 << 2
136};
137
138/* Revisions of T1 chip */
139enum {
140 TERM_T1A = 0,
141 TERM_T1B = 1,
142 TERM_T2 = 3
143};
144
145struct sge_params {
146 unsigned int cmdQ_size[2];
147 unsigned int freelQ_size[2];
148 unsigned int large_buf_capacity;
149 unsigned int rx_coalesce_usecs;
150 unsigned int last_rx_coalesce_raw;
151 unsigned int default_rx_coalesce_usecs;
152 unsigned int sample_interval_usecs;
153 unsigned int coalesce_enable;
154 unsigned int polling;
155};
156
157struct chelsio_pci_params {
158 unsigned short speed;
159 unsigned char width;
160 unsigned char is_pcix;
161};
162
163struct tp_params {
164 unsigned int pm_size;
165 unsigned int cm_size;
166 unsigned int pm_rx_base;
167 unsigned int pm_tx_base;
168 unsigned int pm_rx_pg_size;
169 unsigned int pm_tx_pg_size;
170 unsigned int pm_rx_num_pgs;
171 unsigned int pm_tx_num_pgs;
172 unsigned int rx_coalescing_size;
173 unsigned int use_5tuple_mode;
174};
175
176struct mc5_params {
177 unsigned int mode; /* selects MC5 width */
178 unsigned int nservers; /* size of server region */
179 unsigned int nroutes; /* size of routing region */
180};
181
182/* Default MC5 region sizes */
183#define DEFAULT_SERVER_REGION_LEN 256
184#define DEFAULT_RT_REGION_LEN 1024
185
186struct adapter_params {
187 struct sge_params sge;
188 struct mc5_params mc5;
189 struct tp_params tp;
190 struct chelsio_pci_params pci;
191
192 const struct board_info *brd_info;
193
194 unsigned short mtus[NMTUS];
195 unsigned int nports; /* # of ethernet ports */
196 unsigned int stats_update_period;
197 unsigned short chip_revision;
198 unsigned char chip_version;
199 unsigned char is_asic;
200 unsigned char has_msi;
201};
202
203struct link_config {
204 unsigned int supported; /* link capabilities */
205 unsigned int advertising; /* advertised capabilities */
206 unsigned short requested_speed; /* speed user has requested */
207 unsigned short speed; /* actual link speed */
208 unsigned char requested_duplex; /* duplex user has requested */
209 unsigned char duplex; /* actual link duplex */
210 unsigned char requested_fc; /* flow control user has requested */
211 unsigned char fc; /* actual link flow control */
212 unsigned char autoneg; /* autonegotiating? */
213};
214
215struct cmac;
216struct cphy;
217
218struct port_info {
219 struct net_device *dev;
220 struct cmac *mac;
221 struct cphy *phy;
222 struct link_config link_config;
223 struct net_device_stats netstats;
224};
225
226struct sge;
227struct peespi;
228
229struct adapter {
230 u8 __iomem *regs;
231 struct pci_dev *pdev;
232 unsigned long registered_device_map;
233 unsigned long open_device_map;
234 unsigned long flags;
235
236 const char *name;
237 int msg_enable;
238 u32 mmio_len;
239
240 struct work_struct ext_intr_handler_task;
241 struct adapter_params params;
242
243 /* Terminator modules. */
244 struct sge *sge;
245 struct peespi *espi;
246 struct petp *tp;
247
248 struct napi_struct napi;
249 struct port_info port[MAX_NPORTS];
250 struct delayed_work stats_update_task;
251 struct timer_list stats_update_timer;
252
253 spinlock_t tpi_lock;
254 spinlock_t work_lock;
255 spinlock_t mac_lock;
256
257 /* guards async operations */
258 spinlock_t async_lock ____cacheline_aligned;
259 u32 slow_intr_mask;
260 int t1powersave;
261};
262
263enum { /* adapter flags */
264 FULL_INIT_DONE = 1 << 0,
265};
266
267struct mdio_ops;
268struct gmac;
269struct gphy;
270
271struct board_info {
272 unsigned char board;
273 unsigned char port_number;
274 unsigned long caps;
275 unsigned char chip_term;
276 unsigned char chip_mac;
277 unsigned char chip_phy;
278 unsigned int clock_core;
279 unsigned int clock_mc3;
280 unsigned int clock_mc4;
281 unsigned int espi_nports;
282 unsigned int clock_elmer0;
283 unsigned char mdio_mdien;
284 unsigned char mdio_mdiinv;
285 unsigned char mdio_mdc;
286 unsigned char mdio_phybaseaddr;
287 const struct gmac *gmac;
288 const struct gphy *gphy;
289 const struct mdio_ops *mdio_ops;
290 const char *desc;
291};
292
293static inline int t1_is_asic(const adapter_t *adapter)
294{
295 return adapter->params.is_asic;
296}
297
298extern const struct pci_device_id t1_pci_tbl[];
299
300static inline int adapter_matches_type(const adapter_t *adapter,
301 int version, int revision)
302{
303 return adapter->params.chip_version == version &&
304 adapter->params.chip_revision == revision;
305}
306
307#define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
308#define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
309
310/* Returns true if an adapter supports VLAN acceleration and TSO */
311static inline int vlan_tso_capable(const adapter_t *adapter)
312{
313 return !t1_is_T1B(adapter);
314}
315
316#define for_each_port(adapter, iter) \
317 for (iter = 0; iter < (adapter)->params.nports; ++iter)
318
319#define board_info(adapter) ((adapter)->params.brd_info)
320#define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
321
322static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
323{
324 return board_info(adap)->clock_core / 1000000;
325}
326
327extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
328extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
329extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
330extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
331
332extern void t1_interrupts_enable(adapter_t *adapter);
333extern void t1_interrupts_disable(adapter_t *adapter);
334extern void t1_interrupts_clear(adapter_t *adapter);
335extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
336extern void t1_elmer0_ext_intr(adapter_t *adapter);
337extern int t1_slow_intr_handler(adapter_t *adapter);
338
339extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
340extern const struct board_info *t1_get_board_info(unsigned int board_id);
341extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
342 unsigned short ssid);
343extern int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
344extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
345 struct adapter_params *p);
346extern int t1_init_hw_modules(adapter_t *adapter);
347extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
348extern void t1_free_sw_modules(adapter_t *adapter);
349extern void t1_fatal_err(adapter_t *adapter);
350extern void t1_link_changed(adapter_t *adapter, int port_id);
351extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
352 int speed, int duplex, int pause);
353#endif /* _CXGB_COMMON_H_ */
diff --git a/drivers/net/chelsio/cphy.h b/drivers/net/chelsio/cphy.h
deleted file mode 100644
index 1f095a9fc739..000000000000
--- a/drivers/net/chelsio/cphy.h
+++ /dev/null
@@ -1,175 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: cphy.h *
4 * $Revision: 1.7 $ *
5 * $Date: 2005/06/21 18:29:47 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_CPHY_H_
40#define _CXGB_CPHY_H_
41
42#include "common.h"
43
44struct mdio_ops {
45 void (*init)(adapter_t *adapter, const struct board_info *bi);
46 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
47 u16 reg_addr);
48 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
49 u16 reg_addr, u16 val);
50 unsigned mode_support;
51};
52
53/* PHY interrupt types */
54enum {
55 cphy_cause_link_change = 0x1,
56 cphy_cause_error = 0x2,
57 cphy_cause_fifo_error = 0x3
58};
59
60enum {
61 PHY_LINK_UP = 0x1,
62 PHY_AUTONEG_RDY = 0x2,
63 PHY_AUTONEG_EN = 0x4
64};
65
66struct cphy;
67
68/* PHY operations */
69struct cphy_ops {
70 void (*destroy)(struct cphy *);
71 int (*reset)(struct cphy *, int wait);
72
73 int (*interrupt_enable)(struct cphy *);
74 int (*interrupt_disable)(struct cphy *);
75 int (*interrupt_clear)(struct cphy *);
76 int (*interrupt_handler)(struct cphy *);
77
78 int (*autoneg_enable)(struct cphy *);
79 int (*autoneg_disable)(struct cphy *);
80 int (*autoneg_restart)(struct cphy *);
81
82 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
83 int (*set_loopback)(struct cphy *, int on);
84 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
85 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
86 int *duplex, int *fc);
87
88 u32 mmds;
89};
90
91/* A PHY instance */
92struct cphy {
93 int state; /* Link status state machine */
94 adapter_t *adapter; /* associated adapter */
95
96 struct delayed_work phy_update;
97
98 u16 bmsr;
99 int count;
100 int act_count;
101 int act_on;
102
103 u32 elmer_gpo;
104
105 const struct cphy_ops *ops; /* PHY operations */
106 struct mdio_if_info mdio;
107 struct cphy_instance *instance;
108};
109
110/* Convenience MDIO read/write wrappers */
111static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg,
112 unsigned int *valp)
113{
114 int rc = cphy->mdio.mdio_read(cphy->mdio.dev, cphy->mdio.prtad, mmd,
115 reg);
116 *valp = (rc >= 0) ? rc : -1;
117 return (rc >= 0) ? 0 : rc;
118}
119
120static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg,
121 unsigned int val)
122{
123 return cphy->mdio.mdio_write(cphy->mdio.dev, cphy->mdio.prtad, mmd,
124 reg, val);
125}
126
127static inline int simple_mdio_read(struct cphy *cphy, int reg,
128 unsigned int *valp)
129{
130 return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp);
131}
132
133static inline int simple_mdio_write(struct cphy *cphy, int reg,
134 unsigned int val)
135{
136 return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val);
137}
138
139/* Convenience initializer */
140static inline void cphy_init(struct cphy *phy, struct net_device *dev,
141 int phy_addr, struct cphy_ops *phy_ops,
142 const struct mdio_ops *mdio_ops)
143{
144 struct adapter *adapter = netdev_priv(dev);
145 phy->adapter = adapter;
146 phy->ops = phy_ops;
147 if (mdio_ops) {
148 phy->mdio.prtad = phy_addr;
149 phy->mdio.mmds = phy_ops->mmds;
150 phy->mdio.mode_support = mdio_ops->mode_support;
151 phy->mdio.mdio_read = mdio_ops->read;
152 phy->mdio.mdio_write = mdio_ops->write;
153 }
154 phy->mdio.dev = dev;
155}
156
157/* Operations of the PHY-instance factory */
158struct gphy {
159 /* Construct a PHY instance with the given PHY address */
160 struct cphy *(*create)(struct net_device *dev, int phy_addr,
161 const struct mdio_ops *mdio_ops);
162
163 /*
164 * Reset the PHY chip. This resets the whole PHY chip, not individual
165 * ports.
166 */
167 int (*reset)(adapter_t *adapter);
168};
169
170extern const struct gphy t1_my3126_ops;
171extern const struct gphy t1_mv88e1xxx_ops;
172extern const struct gphy t1_vsc8244_ops;
173extern const struct gphy t1_mv88x201x_ops;
174
175#endif /* _CXGB_CPHY_H_ */
diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h
deleted file mode 100644
index e36d45b78cc7..000000000000
--- a/drivers/net/chelsio/cpl5_cmd.h
+++ /dev/null
@@ -1,639 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: cpl5_cmd.h *
4 * $Revision: 1.6 $ *
5 * $Date: 2005/06/21 18:29:47 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_CPL5_CMD_H_
40#define _CXGB_CPL5_CMD_H_
41
42#include <asm/byteorder.h>
43
44#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
45#error "Adjust your <asm/byteorder.h> defines"
46#endif
47
48enum CPL_opcode {
49 CPL_PASS_OPEN_REQ = 0x1,
50 CPL_PASS_OPEN_RPL = 0x2,
51 CPL_PASS_ESTABLISH = 0x3,
52 CPL_PASS_ACCEPT_REQ = 0xE,
53 CPL_PASS_ACCEPT_RPL = 0x4,
54 CPL_ACT_OPEN_REQ = 0x5,
55 CPL_ACT_OPEN_RPL = 0x6,
56 CPL_CLOSE_CON_REQ = 0x7,
57 CPL_CLOSE_CON_RPL = 0x8,
58 CPL_CLOSE_LISTSRV_REQ = 0x9,
59 CPL_CLOSE_LISTSRV_RPL = 0xA,
60 CPL_ABORT_REQ = 0xB,
61 CPL_ABORT_RPL = 0xC,
62 CPL_PEER_CLOSE = 0xD,
63 CPL_ACT_ESTABLISH = 0x17,
64
65 CPL_GET_TCB = 0x24,
66 CPL_GET_TCB_RPL = 0x25,
67 CPL_SET_TCB = 0x26,
68 CPL_SET_TCB_FIELD = 0x27,
69 CPL_SET_TCB_RPL = 0x28,
70 CPL_PCMD = 0x29,
71
72 CPL_PCMD_READ = 0x31,
73 CPL_PCMD_READ_RPL = 0x32,
74
75
76 CPL_RX_DATA = 0xA0,
77 CPL_RX_DATA_DDP = 0xA1,
78 CPL_RX_DATA_ACK = 0xA3,
79 CPL_RX_PKT = 0xAD,
80 CPL_RX_ISCSI_HDR = 0xAF,
81 CPL_TX_DATA_ACK = 0xB0,
82 CPL_TX_DATA = 0xB1,
83 CPL_TX_PKT = 0xB2,
84 CPL_TX_PKT_LSO = 0xB6,
85
86 CPL_RTE_DELETE_REQ = 0xC0,
87 CPL_RTE_DELETE_RPL = 0xC1,
88 CPL_RTE_WRITE_REQ = 0xC2,
89 CPL_RTE_WRITE_RPL = 0xD3,
90 CPL_RTE_READ_REQ = 0xC3,
91 CPL_RTE_READ_RPL = 0xC4,
92 CPL_L2T_WRITE_REQ = 0xC5,
93 CPL_L2T_WRITE_RPL = 0xD4,
94 CPL_L2T_READ_REQ = 0xC6,
95 CPL_L2T_READ_RPL = 0xC7,
96 CPL_SMT_WRITE_REQ = 0xC8,
97 CPL_SMT_WRITE_RPL = 0xD5,
98 CPL_SMT_READ_REQ = 0xC9,
99 CPL_SMT_READ_RPL = 0xCA,
100 CPL_ARP_MISS_REQ = 0xCD,
101 CPL_ARP_MISS_RPL = 0xCE,
102 CPL_MIGRATE_C2T_REQ = 0xDC,
103 CPL_MIGRATE_C2T_RPL = 0xDD,
104 CPL_ERROR = 0xD7,
105
106 /* internal: driver -> TOM */
107 CPL_MSS_CHANGE = 0xE1
108};
109
110#define NUM_CPL_CMDS 256
111
112enum CPL_error {
113 CPL_ERR_NONE = 0,
114 CPL_ERR_TCAM_PARITY = 1,
115 CPL_ERR_TCAM_FULL = 3,
116 CPL_ERR_CONN_RESET = 20,
117 CPL_ERR_CONN_EXIST = 22,
118 CPL_ERR_ARP_MISS = 23,
119 CPL_ERR_BAD_SYN = 24,
120 CPL_ERR_CONN_TIMEDOUT = 30,
121 CPL_ERR_XMIT_TIMEDOUT = 31,
122 CPL_ERR_PERSIST_TIMEDOUT = 32,
123 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
124 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
125 CPL_ERR_ABORT_FAILED = 42,
126 CPL_ERR_GENERAL = 99
127};
128
129enum {
130 CPL_CONN_POLICY_AUTO = 0,
131 CPL_CONN_POLICY_ASK = 1,
132 CPL_CONN_POLICY_DENY = 3
133};
134
135enum {
136 ULP_MODE_NONE = 0,
137 ULP_MODE_TCPDDP = 1,
138 ULP_MODE_ISCSI = 2,
139 ULP_MODE_IWARP = 3,
140 ULP_MODE_SSL = 4
141};
142
143enum {
144 CPL_PASS_OPEN_ACCEPT,
145 CPL_PASS_OPEN_REJECT
146};
147
148enum {
149 CPL_ABORT_SEND_RST = 0,
150 CPL_ABORT_NO_RST,
151 CPL_ABORT_POST_CLOSE_REQ = 2
152};
153
154enum { // TX_PKT_LSO ethernet types
155 CPL_ETH_II,
156 CPL_ETH_II_VLAN,
157 CPL_ETH_802_3,
158 CPL_ETH_802_3_VLAN
159};
160
161union opcode_tid {
162 u32 opcode_tid;
163 u8 opcode;
164};
165
166#define S_OPCODE 24
167#define V_OPCODE(x) ((x) << S_OPCODE)
168#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
169#define G_TID(x) ((x) & 0xFFFFFF)
170
171/* tid is assumed to be 24-bits */
172#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
173
174#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
175
176/* extract the TID from a CPL command */
177#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
178
179struct tcp_options {
180 u16 mss;
181 u8 wsf;
182#if defined(__LITTLE_ENDIAN_BITFIELD)
183 u8 rsvd:4;
184 u8 ecn:1;
185 u8 sack:1;
186 u8 tstamp:1;
187#else
188 u8 tstamp:1;
189 u8 sack:1;
190 u8 ecn:1;
191 u8 rsvd:4;
192#endif
193};
194
195struct cpl_pass_open_req {
196 union opcode_tid ot;
197 u16 local_port;
198 u16 peer_port;
199 u32 local_ip;
200 u32 peer_ip;
201 u32 opt0h;
202 u32 opt0l;
203 u32 peer_netmask;
204 u32 opt1;
205};
206
207struct cpl_pass_open_rpl {
208 union opcode_tid ot;
209 u16 local_port;
210 u16 peer_port;
211 u32 local_ip;
212 u32 peer_ip;
213 u8 resvd[7];
214 u8 status;
215};
216
217struct cpl_pass_establish {
218 union opcode_tid ot;
219 u16 local_port;
220 u16 peer_port;
221 u32 local_ip;
222 u32 peer_ip;
223 u32 tos_tid;
224 u8 l2t_idx;
225 u8 rsvd[3];
226 u32 snd_isn;
227 u32 rcv_isn;
228};
229
230struct cpl_pass_accept_req {
231 union opcode_tid ot;
232 u16 local_port;
233 u16 peer_port;
234 u32 local_ip;
235 u32 peer_ip;
236 u32 tos_tid;
237 struct tcp_options tcp_options;
238 u8 dst_mac[6];
239 u16 vlan_tag;
240 u8 src_mac[6];
241 u8 rsvd[2];
242 u32 rcv_isn;
243 u32 unknown_tcp_options;
244};
245
246struct cpl_pass_accept_rpl {
247 union opcode_tid ot;
248 u32 rsvd0;
249 u32 rsvd1;
250 u32 peer_ip;
251 u32 opt0h;
252 union {
253 u32 opt0l;
254 struct {
255 u8 rsvd[3];
256 u8 status;
257 };
258 };
259};
260
261struct cpl_act_open_req {
262 union opcode_tid ot;
263 u16 local_port;
264 u16 peer_port;
265 u32 local_ip;
266 u32 peer_ip;
267 u32 opt0h;
268 u32 opt0l;
269 u32 iff_vlantag;
270 u32 rsvd;
271};
272
273struct cpl_act_open_rpl {
274 union opcode_tid ot;
275 u16 local_port;
276 u16 peer_port;
277 u32 local_ip;
278 u32 peer_ip;
279 u32 new_tid;
280 u8 rsvd[3];
281 u8 status;
282};
283
284struct cpl_act_establish {
285 union opcode_tid ot;
286 u16 local_port;
287 u16 peer_port;
288 u32 local_ip;
289 u32 peer_ip;
290 u32 tos_tid;
291 u32 rsvd;
292 u32 snd_isn;
293 u32 rcv_isn;
294};
295
296struct cpl_get_tcb {
297 union opcode_tid ot;
298 u32 rsvd;
299};
300
301struct cpl_get_tcb_rpl {
302 union opcode_tid ot;
303 u16 len;
304 u8 rsvd;
305 u8 status;
306};
307
308struct cpl_set_tcb {
309 union opcode_tid ot;
310 u16 len;
311 u16 rsvd;
312};
313
314struct cpl_set_tcb_field {
315 union opcode_tid ot;
316 u8 rsvd[3];
317 u8 offset;
318 u32 mask;
319 u32 val;
320};
321
322struct cpl_set_tcb_rpl {
323 union opcode_tid ot;
324 u8 rsvd[3];
325 u8 status;
326};
327
328struct cpl_pcmd {
329 union opcode_tid ot;
330 u16 dlen_in;
331 u16 dlen_out;
332 u32 pcmd_parm[2];
333};
334
335struct cpl_pcmd_read {
336 union opcode_tid ot;
337 u32 rsvd1;
338 u16 rsvd2;
339 u32 addr;
340 u16 len;
341};
342
343struct cpl_pcmd_read_rpl {
344 union opcode_tid ot;
345 u16 len;
346};
347
348struct cpl_close_con_req {
349 union opcode_tid ot;
350 u32 rsvd;
351};
352
353struct cpl_close_con_rpl {
354 union opcode_tid ot;
355 u8 rsvd[3];
356 u8 status;
357 u32 snd_nxt;
358 u32 rcv_nxt;
359};
360
361struct cpl_close_listserv_req {
362 union opcode_tid ot;
363 u32 rsvd;
364};
365
366struct cpl_close_listserv_rpl {
367 union opcode_tid ot;
368 u8 rsvd[3];
369 u8 status;
370};
371
372struct cpl_abort_req {
373 union opcode_tid ot;
374 u32 rsvd0;
375 u8 rsvd1;
376 u8 cmd;
377 u8 rsvd2[6];
378};
379
380struct cpl_abort_rpl {
381 union opcode_tid ot;
382 u32 rsvd0;
383 u8 rsvd1;
384 u8 status;
385 u8 rsvd2[6];
386};
387
388struct cpl_peer_close {
389 union opcode_tid ot;
390 u32 rsvd;
391};
392
393struct cpl_tx_data {
394 union opcode_tid ot;
395 u32 len;
396 u32 rsvd0;
397 u16 urg;
398 u16 flags;
399};
400
401struct cpl_tx_data_ack {
402 union opcode_tid ot;
403 u32 ack_seq;
404};
405
406struct cpl_rx_data {
407 union opcode_tid ot;
408 u32 len;
409 u32 seq;
410 u16 urg;
411 u8 rsvd;
412 u8 status;
413};
414
415struct cpl_rx_data_ack {
416 union opcode_tid ot;
417 u32 credit;
418};
419
420struct cpl_rx_data_ddp {
421 union opcode_tid ot;
422 u32 len;
423 u32 seq;
424 u32 nxt_seq;
425 u32 ulp_crc;
426 u16 ddp_status;
427 u8 rsvd;
428 u8 status;
429};
430
431/*
432 * We want this header's alignment to be no more stringent than 2-byte aligned.
433 * All fields are u8 or u16 except for the length. However that field is not
434 * used so we break it into 2 16-bit parts to easily meet our alignment needs.
435 */
436struct cpl_tx_pkt {
437 u8 opcode;
438#if defined(__LITTLE_ENDIAN_BITFIELD)
439 u8 iff:4;
440 u8 ip_csum_dis:1;
441 u8 l4_csum_dis:1;
442 u8 vlan_valid:1;
443 u8 rsvd:1;
444#else
445 u8 rsvd:1;
446 u8 vlan_valid:1;
447 u8 l4_csum_dis:1;
448 u8 ip_csum_dis:1;
449 u8 iff:4;
450#endif
451 u16 vlan;
452 u16 len_hi;
453 u16 len_lo;
454};
455
456struct cpl_tx_pkt_lso {
457 u8 opcode;
458#if defined(__LITTLE_ENDIAN_BITFIELD)
459 u8 iff:4;
460 u8 ip_csum_dis:1;
461 u8 l4_csum_dis:1;
462 u8 vlan_valid:1;
463 u8 :1;
464#else
465 u8 :1;
466 u8 vlan_valid:1;
467 u8 l4_csum_dis:1;
468 u8 ip_csum_dis:1;
469 u8 iff:4;
470#endif
471 u16 vlan;
472 __be32 len;
473
474 u8 rsvd[5];
475#if defined(__LITTLE_ENDIAN_BITFIELD)
476 u8 tcp_hdr_words:4;
477 u8 ip_hdr_words:4;
478#else
479 u8 ip_hdr_words:4;
480 u8 tcp_hdr_words:4;
481#endif
482 __be16 eth_type_mss;
483};
484
485struct cpl_rx_pkt {
486 u8 opcode;
487#if defined(__LITTLE_ENDIAN_BITFIELD)
488 u8 iff:4;
489 u8 csum_valid:1;
490 u8 bad_pkt:1;
491 u8 vlan_valid:1;
492 u8 rsvd:1;
493#else
494 u8 rsvd:1;
495 u8 vlan_valid:1;
496 u8 bad_pkt:1;
497 u8 csum_valid:1;
498 u8 iff:4;
499#endif
500 u16 csum;
501 u16 vlan;
502 u16 len;
503};
504
505struct cpl_l2t_write_req {
506 union opcode_tid ot;
507 u32 params;
508 u8 rsvd1[2];
509 u8 dst_mac[6];
510};
511
512struct cpl_l2t_write_rpl {
513 union opcode_tid ot;
514 u8 status;
515 u8 rsvd[3];
516};
517
518struct cpl_l2t_read_req {
519 union opcode_tid ot;
520 u8 rsvd[3];
521 u8 l2t_idx;
522};
523
524struct cpl_l2t_read_rpl {
525 union opcode_tid ot;
526 u32 params;
527 u8 rsvd1[2];
528 u8 dst_mac[6];
529};
530
531struct cpl_smt_write_req {
532 union opcode_tid ot;
533 u8 rsvd0;
534#if defined(__LITTLE_ENDIAN_BITFIELD)
535 u8 rsvd1:1;
536 u8 mtu_idx:3;
537 u8 iff:4;
538#else
539 u8 iff:4;
540 u8 mtu_idx:3;
541 u8 rsvd1:1;
542#endif
543 u16 rsvd2;
544 u16 rsvd3;
545 u8 src_mac1[6];
546 u16 rsvd4;
547 u8 src_mac0[6];
548};
549
550struct cpl_smt_write_rpl {
551 union opcode_tid ot;
552 u8 status;
553 u8 rsvd[3];
554};
555
556struct cpl_smt_read_req {
557 union opcode_tid ot;
558 u8 rsvd0;
559#if defined(__LITTLE_ENDIAN_BITFIELD)
560 u8 rsvd1:4;
561 u8 iff:4;
562#else
563 u8 iff:4;
564 u8 rsvd1:4;
565#endif
566 u16 rsvd2;
567};
568
569struct cpl_smt_read_rpl {
570 union opcode_tid ot;
571 u8 status;
572#if defined(__LITTLE_ENDIAN_BITFIELD)
573 u8 rsvd1:1;
574 u8 mtu_idx:3;
575 u8 rsvd0:4;
576#else
577 u8 rsvd0:4;
578 u8 mtu_idx:3;
579 u8 rsvd1:1;
580#endif
581 u16 rsvd2;
582 u16 rsvd3;
583 u8 src_mac1[6];
584 u16 rsvd4;
585 u8 src_mac0[6];
586};
587
588struct cpl_rte_delete_req {
589 union opcode_tid ot;
590 u32 params;
591};
592
593struct cpl_rte_delete_rpl {
594 union opcode_tid ot;
595 u8 status;
596 u8 rsvd[3];
597};
598
599struct cpl_rte_write_req {
600 union opcode_tid ot;
601 u32 params;
602 u32 netmask;
603 u32 faddr;
604};
605
606struct cpl_rte_write_rpl {
607 union opcode_tid ot;
608 u8 status;
609 u8 rsvd[3];
610};
611
612struct cpl_rte_read_req {
613 union opcode_tid ot;
614 u32 params;
615};
616
617struct cpl_rte_read_rpl {
618 union opcode_tid ot;
619 u8 status;
620 u8 rsvd0[2];
621 u8 l2t_idx;
622#if defined(__LITTLE_ENDIAN_BITFIELD)
623 u8 rsvd1:7;
624 u8 select:1;
625#else
626 u8 select:1;
627 u8 rsvd1:7;
628#endif
629 u8 rsvd2[3];
630 u32 addr;
631};
632
633struct cpl_mss_change {
634 union opcode_tid ot;
635 u32 mss;
636};
637
638#endif /* _CXGB_CPL5_CMD_H_ */
639
diff --git a/drivers/net/chelsio/cxgb2.c b/drivers/net/chelsio/cxgb2.c
deleted file mode 100644
index 3edbbc4c5112..000000000000
--- a/drivers/net/chelsio/cxgb2.c
+++ /dev/null
@@ -1,1379 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: cxgb2.c *
4 * $Revision: 1.25 $ *
5 * $Date: 2005/06/22 00:43:25 $ *
6 * Description: *
7 * Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#include "common.h"
40#include <linux/module.h>
41#include <linux/init.h>
42#include <linux/pci.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/if_vlan.h>
46#include <linux/mii.h>
47#include <linux/sockios.h>
48#include <linux/dma-mapping.h>
49#include <asm/uaccess.h>
50
51#include "cpl5_cmd.h"
52#include "regs.h"
53#include "gmac.h"
54#include "cphy.h"
55#include "sge.h"
56#include "tp.h"
57#include "espi.h"
58#include "elmer0.h"
59
60#include <linux/workqueue.h>
61
62static inline void schedule_mac_stats_update(struct adapter *ap, int secs)
63{
64 schedule_delayed_work(&ap->stats_update_task, secs * HZ);
65}
66
67static inline void cancel_mac_stats_update(struct adapter *ap)
68{
69 cancel_delayed_work(&ap->stats_update_task);
70}
71
72#define MAX_CMDQ_ENTRIES 16384
73#define MAX_CMDQ1_ENTRIES 1024
74#define MAX_RX_BUFFERS 16384
75#define MAX_RX_JUMBO_BUFFERS 16384
76#define MAX_TX_BUFFERS_HIGH 16384U
77#define MAX_TX_BUFFERS_LOW 1536U
78#define MAX_TX_BUFFERS 1460U
79#define MIN_FL_ENTRIES 32
80
81#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
82 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
83 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
84
85/*
86 * The EEPROM is actually bigger but only the first few bytes are used so we
87 * only report those.
88 */
89#define EEPROM_SIZE 32
90
91MODULE_DESCRIPTION(DRV_DESCRIPTION);
92MODULE_AUTHOR("Chelsio Communications");
93MODULE_LICENSE("GPL");
94
95static int dflt_msg_enable = DFLT_MSG_ENABLE;
96
97module_param(dflt_msg_enable, int, 0);
98MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T1 default message enable bitmap");
99
100#define HCLOCK 0x0
101#define LCLOCK 0x1
102
103/* T1 cards powersave mode */
104static int t1_clock(struct adapter *adapter, int mode);
105static int t1powersave = 1; /* HW default is powersave mode. */
106
107module_param(t1powersave, int, 0);
108MODULE_PARM_DESC(t1powersave, "Enable/Disable T1 powersaving mode");
109
110static int disable_msi = 0;
111module_param(disable_msi, int, 0);
112MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
113
114static const char pci_speed[][4] = {
115 "33", "66", "100", "133"
116};
117
118/*
119 * Setup MAC to receive the types of packets we want.
120 */
121static void t1_set_rxmode(struct net_device *dev)
122{
123 struct adapter *adapter = dev->ml_priv;
124 struct cmac *mac = adapter->port[dev->if_port].mac;
125 struct t1_rx_mode rm;
126
127 rm.dev = dev;
128 mac->ops->set_rx_mode(mac, &rm);
129}
130
131static void link_report(struct port_info *p)
132{
133 if (!netif_carrier_ok(p->dev))
134 printk(KERN_INFO "%s: link down\n", p->dev->name);
135 else {
136 const char *s = "10Mbps";
137
138 switch (p->link_config.speed) {
139 case SPEED_10000: s = "10Gbps"; break;
140 case SPEED_1000: s = "1000Mbps"; break;
141 case SPEED_100: s = "100Mbps"; break;
142 }
143
144 printk(KERN_INFO "%s: link up, %s, %s-duplex\n",
145 p->dev->name, s,
146 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
147 }
148}
149
150void t1_link_negotiated(struct adapter *adapter, int port_id, int link_stat,
151 int speed, int duplex, int pause)
152{
153 struct port_info *p = &adapter->port[port_id];
154
155 if (link_stat != netif_carrier_ok(p->dev)) {
156 if (link_stat)
157 netif_carrier_on(p->dev);
158 else
159 netif_carrier_off(p->dev);
160 link_report(p);
161
162 /* multi-ports: inform toe */
163 if ((speed > 0) && (adapter->params.nports > 1)) {
164 unsigned int sched_speed = 10;
165 switch (speed) {
166 case SPEED_1000:
167 sched_speed = 1000;
168 break;
169 case SPEED_100:
170 sched_speed = 100;
171 break;
172 case SPEED_10:
173 sched_speed = 10;
174 break;
175 }
176 t1_sched_update_parms(adapter->sge, port_id, 0, sched_speed);
177 }
178 }
179}
180
181static void link_start(struct port_info *p)
182{
183 struct cmac *mac = p->mac;
184
185 mac->ops->reset(mac);
186 if (mac->ops->macaddress_set)
187 mac->ops->macaddress_set(mac, p->dev->dev_addr);
188 t1_set_rxmode(p->dev);
189 t1_link_start(p->phy, mac, &p->link_config);
190 mac->ops->enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
191}
192
193static void enable_hw_csum(struct adapter *adapter)
194{
195 if (adapter->port[0].dev->hw_features & NETIF_F_TSO)
196 t1_tp_set_ip_checksum_offload(adapter->tp, 1); /* for TSO only */
197 t1_tp_set_tcp_checksum_offload(adapter->tp, 1);
198}
199
200/*
201 * Things to do upon first use of a card.
202 * This must run with the rtnl lock held.
203 */
204static int cxgb_up(struct adapter *adapter)
205{
206 int err = 0;
207
208 if (!(adapter->flags & FULL_INIT_DONE)) {
209 err = t1_init_hw_modules(adapter);
210 if (err)
211 goto out_err;
212
213 enable_hw_csum(adapter);
214 adapter->flags |= FULL_INIT_DONE;
215 }
216
217 t1_interrupts_clear(adapter);
218
219 adapter->params.has_msi = !disable_msi && !pci_enable_msi(adapter->pdev);
220 err = request_irq(adapter->pdev->irq, t1_interrupt,
221 adapter->params.has_msi ? 0 : IRQF_SHARED,
222 adapter->name, adapter);
223 if (err) {
224 if (adapter->params.has_msi)
225 pci_disable_msi(adapter->pdev);
226
227 goto out_err;
228 }
229
230 t1_sge_start(adapter->sge);
231 t1_interrupts_enable(adapter);
232out_err:
233 return err;
234}
235
236/*
237 * Release resources when all the ports have been stopped.
238 */
239static void cxgb_down(struct adapter *adapter)
240{
241 t1_sge_stop(adapter->sge);
242 t1_interrupts_disable(adapter);
243 free_irq(adapter->pdev->irq, adapter);
244 if (adapter->params.has_msi)
245 pci_disable_msi(adapter->pdev);
246}
247
248static int cxgb_open(struct net_device *dev)
249{
250 int err;
251 struct adapter *adapter = dev->ml_priv;
252 int other_ports = adapter->open_device_map & PORT_MASK;
253
254 napi_enable(&adapter->napi);
255 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0) {
256 napi_disable(&adapter->napi);
257 return err;
258 }
259
260 __set_bit(dev->if_port, &adapter->open_device_map);
261 link_start(&adapter->port[dev->if_port]);
262 netif_start_queue(dev);
263 if (!other_ports && adapter->params.stats_update_period)
264 schedule_mac_stats_update(adapter,
265 adapter->params.stats_update_period);
266
267 t1_vlan_mode(adapter, dev->features);
268 return 0;
269}
270
271static int cxgb_close(struct net_device *dev)
272{
273 struct adapter *adapter = dev->ml_priv;
274 struct port_info *p = &adapter->port[dev->if_port];
275 struct cmac *mac = p->mac;
276
277 netif_stop_queue(dev);
278 napi_disable(&adapter->napi);
279 mac->ops->disable(mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
280 netif_carrier_off(dev);
281
282 clear_bit(dev->if_port, &adapter->open_device_map);
283 if (adapter->params.stats_update_period &&
284 !(adapter->open_device_map & PORT_MASK)) {
285 /* Stop statistics accumulation. */
286 smp_mb__after_clear_bit();
287 spin_lock(&adapter->work_lock); /* sync with update task */
288 spin_unlock(&adapter->work_lock);
289 cancel_mac_stats_update(adapter);
290 }
291
292 if (!adapter->open_device_map)
293 cxgb_down(adapter);
294 return 0;
295}
296
297static struct net_device_stats *t1_get_stats(struct net_device *dev)
298{
299 struct adapter *adapter = dev->ml_priv;
300 struct port_info *p = &adapter->port[dev->if_port];
301 struct net_device_stats *ns = &p->netstats;
302 const struct cmac_statistics *pstats;
303
304 /* Do a full update of the MAC stats */
305 pstats = p->mac->ops->statistics_update(p->mac,
306 MAC_STATS_UPDATE_FULL);
307
308 ns->tx_packets = pstats->TxUnicastFramesOK +
309 pstats->TxMulticastFramesOK + pstats->TxBroadcastFramesOK;
310
311 ns->rx_packets = pstats->RxUnicastFramesOK +
312 pstats->RxMulticastFramesOK + pstats->RxBroadcastFramesOK;
313
314 ns->tx_bytes = pstats->TxOctetsOK;
315 ns->rx_bytes = pstats->RxOctetsOK;
316
317 ns->tx_errors = pstats->TxLateCollisions + pstats->TxLengthErrors +
318 pstats->TxUnderrun + pstats->TxFramesAbortedDueToXSCollisions;
319 ns->rx_errors = pstats->RxDataErrors + pstats->RxJabberErrors +
320 pstats->RxFCSErrors + pstats->RxAlignErrors +
321 pstats->RxSequenceErrors + pstats->RxFrameTooLongErrors +
322 pstats->RxSymbolErrors + pstats->RxRuntErrors;
323
324 ns->multicast = pstats->RxMulticastFramesOK;
325 ns->collisions = pstats->TxTotalCollisions;
326
327 /* detailed rx_errors */
328 ns->rx_length_errors = pstats->RxFrameTooLongErrors +
329 pstats->RxJabberErrors;
330 ns->rx_over_errors = 0;
331 ns->rx_crc_errors = pstats->RxFCSErrors;
332 ns->rx_frame_errors = pstats->RxAlignErrors;
333 ns->rx_fifo_errors = 0;
334 ns->rx_missed_errors = 0;
335
336 /* detailed tx_errors */
337 ns->tx_aborted_errors = pstats->TxFramesAbortedDueToXSCollisions;
338 ns->tx_carrier_errors = 0;
339 ns->tx_fifo_errors = pstats->TxUnderrun;
340 ns->tx_heartbeat_errors = 0;
341 ns->tx_window_errors = pstats->TxLateCollisions;
342 return ns;
343}
344
345static u32 get_msglevel(struct net_device *dev)
346{
347 struct adapter *adapter = dev->ml_priv;
348
349 return adapter->msg_enable;
350}
351
352static void set_msglevel(struct net_device *dev, u32 val)
353{
354 struct adapter *adapter = dev->ml_priv;
355
356 adapter->msg_enable = val;
357}
358
359static char stats_strings[][ETH_GSTRING_LEN] = {
360 "TxOctetsOK",
361 "TxOctetsBad",
362 "TxUnicastFramesOK",
363 "TxMulticastFramesOK",
364 "TxBroadcastFramesOK",
365 "TxPauseFrames",
366 "TxFramesWithDeferredXmissions",
367 "TxLateCollisions",
368 "TxTotalCollisions",
369 "TxFramesAbortedDueToXSCollisions",
370 "TxUnderrun",
371 "TxLengthErrors",
372 "TxInternalMACXmitError",
373 "TxFramesWithExcessiveDeferral",
374 "TxFCSErrors",
375 "TxJumboFramesOk",
376 "TxJumboOctetsOk",
377
378 "RxOctetsOK",
379 "RxOctetsBad",
380 "RxUnicastFramesOK",
381 "RxMulticastFramesOK",
382 "RxBroadcastFramesOK",
383 "RxPauseFrames",
384 "RxFCSErrors",
385 "RxAlignErrors",
386 "RxSymbolErrors",
387 "RxDataErrors",
388 "RxSequenceErrors",
389 "RxRuntErrors",
390 "RxJabberErrors",
391 "RxInternalMACRcvError",
392 "RxInRangeLengthErrors",
393 "RxOutOfRangeLengthField",
394 "RxFrameTooLongErrors",
395 "RxJumboFramesOk",
396 "RxJumboOctetsOk",
397
398 /* Port stats */
399 "RxCsumGood",
400 "TxCsumOffload",
401 "TxTso",
402 "RxVlan",
403 "TxVlan",
404 "TxNeedHeadroom",
405
406 /* Interrupt stats */
407 "rx drops",
408 "pure_rsps",
409 "unhandled irqs",
410 "respQ_empty",
411 "respQ_overflow",
412 "freelistQ_empty",
413 "pkt_too_big",
414 "pkt_mismatch",
415 "cmdQ_full0",
416 "cmdQ_full1",
417
418 "espi_DIP2ParityErr",
419 "espi_DIP4Err",
420 "espi_RxDrops",
421 "espi_TxDrops",
422 "espi_RxOvfl",
423 "espi_ParityErr"
424};
425
426#define T2_REGMAP_SIZE (3 * 1024)
427
428static int get_regs_len(struct net_device *dev)
429{
430 return T2_REGMAP_SIZE;
431}
432
433static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
434{
435 struct adapter *adapter = dev->ml_priv;
436
437 strcpy(info->driver, DRV_NAME);
438 strcpy(info->version, DRV_VERSION);
439 strcpy(info->fw_version, "N/A");
440 strcpy(info->bus_info, pci_name(adapter->pdev));
441}
442
443static int get_sset_count(struct net_device *dev, int sset)
444{
445 switch (sset) {
446 case ETH_SS_STATS:
447 return ARRAY_SIZE(stats_strings);
448 default:
449 return -EOPNOTSUPP;
450 }
451}
452
453static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
454{
455 if (stringset == ETH_SS_STATS)
456 memcpy(data, stats_strings, sizeof(stats_strings));
457}
458
459static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
460 u64 *data)
461{
462 struct adapter *adapter = dev->ml_priv;
463 struct cmac *mac = adapter->port[dev->if_port].mac;
464 const struct cmac_statistics *s;
465 const struct sge_intr_counts *t;
466 struct sge_port_stats ss;
467
468 s = mac->ops->statistics_update(mac, MAC_STATS_UPDATE_FULL);
469 t = t1_sge_get_intr_counts(adapter->sge);
470 t1_sge_get_port_stats(adapter->sge, dev->if_port, &ss);
471
472 *data++ = s->TxOctetsOK;
473 *data++ = s->TxOctetsBad;
474 *data++ = s->TxUnicastFramesOK;
475 *data++ = s->TxMulticastFramesOK;
476 *data++ = s->TxBroadcastFramesOK;
477 *data++ = s->TxPauseFrames;
478 *data++ = s->TxFramesWithDeferredXmissions;
479 *data++ = s->TxLateCollisions;
480 *data++ = s->TxTotalCollisions;
481 *data++ = s->TxFramesAbortedDueToXSCollisions;
482 *data++ = s->TxUnderrun;
483 *data++ = s->TxLengthErrors;
484 *data++ = s->TxInternalMACXmitError;
485 *data++ = s->TxFramesWithExcessiveDeferral;
486 *data++ = s->TxFCSErrors;
487 *data++ = s->TxJumboFramesOK;
488 *data++ = s->TxJumboOctetsOK;
489
490 *data++ = s->RxOctetsOK;
491 *data++ = s->RxOctetsBad;
492 *data++ = s->RxUnicastFramesOK;
493 *data++ = s->RxMulticastFramesOK;
494 *data++ = s->RxBroadcastFramesOK;
495 *data++ = s->RxPauseFrames;
496 *data++ = s->RxFCSErrors;
497 *data++ = s->RxAlignErrors;
498 *data++ = s->RxSymbolErrors;
499 *data++ = s->RxDataErrors;
500 *data++ = s->RxSequenceErrors;
501 *data++ = s->RxRuntErrors;
502 *data++ = s->RxJabberErrors;
503 *data++ = s->RxInternalMACRcvError;
504 *data++ = s->RxInRangeLengthErrors;
505 *data++ = s->RxOutOfRangeLengthField;
506 *data++ = s->RxFrameTooLongErrors;
507 *data++ = s->RxJumboFramesOK;
508 *data++ = s->RxJumboOctetsOK;
509
510 *data++ = ss.rx_cso_good;
511 *data++ = ss.tx_cso;
512 *data++ = ss.tx_tso;
513 *data++ = ss.vlan_xtract;
514 *data++ = ss.vlan_insert;
515 *data++ = ss.tx_need_hdrroom;
516
517 *data++ = t->rx_drops;
518 *data++ = t->pure_rsps;
519 *data++ = t->unhandled_irqs;
520 *data++ = t->respQ_empty;
521 *data++ = t->respQ_overflow;
522 *data++ = t->freelistQ_empty;
523 *data++ = t->pkt_too_big;
524 *data++ = t->pkt_mismatch;
525 *data++ = t->cmdQ_full[0];
526 *data++ = t->cmdQ_full[1];
527
528 if (adapter->espi) {
529 const struct espi_intr_counts *e;
530
531 e = t1_espi_get_intr_counts(adapter->espi);
532 *data++ = e->DIP2_parity_err;
533 *data++ = e->DIP4_err;
534 *data++ = e->rx_drops;
535 *data++ = e->tx_drops;
536 *data++ = e->rx_ovflw;
537 *data++ = e->parity_err;
538 }
539}
540
541static inline void reg_block_dump(struct adapter *ap, void *buf,
542 unsigned int start, unsigned int end)
543{
544 u32 *p = buf + start;
545
546 for ( ; start <= end; start += sizeof(u32))
547 *p++ = readl(ap->regs + start);
548}
549
550static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
551 void *buf)
552{
553 struct adapter *ap = dev->ml_priv;
554
555 /*
556 * Version scheme: bits 0..9: chip version, bits 10..15: chip revision
557 */
558 regs->version = 2;
559
560 memset(buf, 0, T2_REGMAP_SIZE);
561 reg_block_dump(ap, buf, 0, A_SG_RESPACCUTIMER);
562 reg_block_dump(ap, buf, A_MC3_CFG, A_MC4_INT_CAUSE);
563 reg_block_dump(ap, buf, A_TPI_ADDR, A_TPI_PAR);
564 reg_block_dump(ap, buf, A_TP_IN_CONFIG, A_TP_TX_DROP_COUNT);
565 reg_block_dump(ap, buf, A_RAT_ROUTE_CONTROL, A_RAT_INTR_CAUSE);
566 reg_block_dump(ap, buf, A_CSPI_RX_AE_WM, A_CSPI_INTR_ENABLE);
567 reg_block_dump(ap, buf, A_ESPI_SCH_TOKEN0, A_ESPI_GOSTAT);
568 reg_block_dump(ap, buf, A_ULP_ULIMIT, A_ULP_PIO_CTRL);
569 reg_block_dump(ap, buf, A_PL_ENABLE, A_PL_CAUSE);
570 reg_block_dump(ap, buf, A_MC5_CONFIG, A_MC5_MASK_WRITE_CMD);
571}
572
573static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
574{
575 struct adapter *adapter = dev->ml_priv;
576 struct port_info *p = &adapter->port[dev->if_port];
577
578 cmd->supported = p->link_config.supported;
579 cmd->advertising = p->link_config.advertising;
580
581 if (netif_carrier_ok(dev)) {
582 ethtool_cmd_speed_set(cmd, p->link_config.speed);
583 cmd->duplex = p->link_config.duplex;
584 } else {
585 ethtool_cmd_speed_set(cmd, -1);
586 cmd->duplex = -1;
587 }
588
589 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
590 cmd->phy_address = p->phy->mdio.prtad;
591 cmd->transceiver = XCVR_EXTERNAL;
592 cmd->autoneg = p->link_config.autoneg;
593 cmd->maxtxpkt = 0;
594 cmd->maxrxpkt = 0;
595 return 0;
596}
597
598static int speed_duplex_to_caps(int speed, int duplex)
599{
600 int cap = 0;
601
602 switch (speed) {
603 case SPEED_10:
604 if (duplex == DUPLEX_FULL)
605 cap = SUPPORTED_10baseT_Full;
606 else
607 cap = SUPPORTED_10baseT_Half;
608 break;
609 case SPEED_100:
610 if (duplex == DUPLEX_FULL)
611 cap = SUPPORTED_100baseT_Full;
612 else
613 cap = SUPPORTED_100baseT_Half;
614 break;
615 case SPEED_1000:
616 if (duplex == DUPLEX_FULL)
617 cap = SUPPORTED_1000baseT_Full;
618 else
619 cap = SUPPORTED_1000baseT_Half;
620 break;
621 case SPEED_10000:
622 if (duplex == DUPLEX_FULL)
623 cap = SUPPORTED_10000baseT_Full;
624 }
625 return cap;
626}
627
628#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
629 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
630 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
631 ADVERTISED_10000baseT_Full)
632
633static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
634{
635 struct adapter *adapter = dev->ml_priv;
636 struct port_info *p = &adapter->port[dev->if_port];
637 struct link_config *lc = &p->link_config;
638
639 if (!(lc->supported & SUPPORTED_Autoneg))
640 return -EOPNOTSUPP; /* can't change speed/duplex */
641
642 if (cmd->autoneg == AUTONEG_DISABLE) {
643 u32 speed = ethtool_cmd_speed(cmd);
644 int cap = speed_duplex_to_caps(speed, cmd->duplex);
645
646 if (!(lc->supported & cap) || (speed == SPEED_1000))
647 return -EINVAL;
648 lc->requested_speed = speed;
649 lc->requested_duplex = cmd->duplex;
650 lc->advertising = 0;
651 } else {
652 cmd->advertising &= ADVERTISED_MASK;
653 if (cmd->advertising & (cmd->advertising - 1))
654 cmd->advertising = lc->supported;
655 cmd->advertising &= lc->supported;
656 if (!cmd->advertising)
657 return -EINVAL;
658 lc->requested_speed = SPEED_INVALID;
659 lc->requested_duplex = DUPLEX_INVALID;
660 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
661 }
662 lc->autoneg = cmd->autoneg;
663 if (netif_running(dev))
664 t1_link_start(p->phy, p->mac, lc);
665 return 0;
666}
667
668static void get_pauseparam(struct net_device *dev,
669 struct ethtool_pauseparam *epause)
670{
671 struct adapter *adapter = dev->ml_priv;
672 struct port_info *p = &adapter->port[dev->if_port];
673
674 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
675 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
676 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
677}
678
679static int set_pauseparam(struct net_device *dev,
680 struct ethtool_pauseparam *epause)
681{
682 struct adapter *adapter = dev->ml_priv;
683 struct port_info *p = &adapter->port[dev->if_port];
684 struct link_config *lc = &p->link_config;
685
686 if (epause->autoneg == AUTONEG_DISABLE)
687 lc->requested_fc = 0;
688 else if (lc->supported & SUPPORTED_Autoneg)
689 lc->requested_fc = PAUSE_AUTONEG;
690 else
691 return -EINVAL;
692
693 if (epause->rx_pause)
694 lc->requested_fc |= PAUSE_RX;
695 if (epause->tx_pause)
696 lc->requested_fc |= PAUSE_TX;
697 if (lc->autoneg == AUTONEG_ENABLE) {
698 if (netif_running(dev))
699 t1_link_start(p->phy, p->mac, lc);
700 } else {
701 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
702 if (netif_running(dev))
703 p->mac->ops->set_speed_duplex_fc(p->mac, -1, -1,
704 lc->fc);
705 }
706 return 0;
707}
708
709static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
710{
711 struct adapter *adapter = dev->ml_priv;
712 int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
713
714 e->rx_max_pending = MAX_RX_BUFFERS;
715 e->rx_mini_max_pending = 0;
716 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
717 e->tx_max_pending = MAX_CMDQ_ENTRIES;
718
719 e->rx_pending = adapter->params.sge.freelQ_size[!jumbo_fl];
720 e->rx_mini_pending = 0;
721 e->rx_jumbo_pending = adapter->params.sge.freelQ_size[jumbo_fl];
722 e->tx_pending = adapter->params.sge.cmdQ_size[0];
723}
724
725static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
726{
727 struct adapter *adapter = dev->ml_priv;
728 int jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
729
730 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_mini_pending ||
731 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
732 e->tx_pending > MAX_CMDQ_ENTRIES ||
733 e->rx_pending < MIN_FL_ENTRIES ||
734 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
735 e->tx_pending < (adapter->params.nports + 1) * (MAX_SKB_FRAGS + 1))
736 return -EINVAL;
737
738 if (adapter->flags & FULL_INIT_DONE)
739 return -EBUSY;
740
741 adapter->params.sge.freelQ_size[!jumbo_fl] = e->rx_pending;
742 adapter->params.sge.freelQ_size[jumbo_fl] = e->rx_jumbo_pending;
743 adapter->params.sge.cmdQ_size[0] = e->tx_pending;
744 adapter->params.sge.cmdQ_size[1] = e->tx_pending > MAX_CMDQ1_ENTRIES ?
745 MAX_CMDQ1_ENTRIES : e->tx_pending;
746 return 0;
747}
748
749static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
750{
751 struct adapter *adapter = dev->ml_priv;
752
753 adapter->params.sge.rx_coalesce_usecs = c->rx_coalesce_usecs;
754 adapter->params.sge.coalesce_enable = c->use_adaptive_rx_coalesce;
755 adapter->params.sge.sample_interval_usecs = c->rate_sample_interval;
756 t1_sge_set_coalesce_params(adapter->sge, &adapter->params.sge);
757 return 0;
758}
759
760static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
761{
762 struct adapter *adapter = dev->ml_priv;
763
764 c->rx_coalesce_usecs = adapter->params.sge.rx_coalesce_usecs;
765 c->rate_sample_interval = adapter->params.sge.sample_interval_usecs;
766 c->use_adaptive_rx_coalesce = adapter->params.sge.coalesce_enable;
767 return 0;
768}
769
770static int get_eeprom_len(struct net_device *dev)
771{
772 struct adapter *adapter = dev->ml_priv;
773
774 return t1_is_asic(adapter) ? EEPROM_SIZE : 0;
775}
776
777#define EEPROM_MAGIC(ap) \
778 (PCI_VENDOR_ID_CHELSIO | ((ap)->params.chip_version << 16))
779
780static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
781 u8 *data)
782{
783 int i;
784 u8 buf[EEPROM_SIZE] __attribute__((aligned(4)));
785 struct adapter *adapter = dev->ml_priv;
786
787 e->magic = EEPROM_MAGIC(adapter);
788 for (i = e->offset & ~3; i < e->offset + e->len; i += sizeof(u32))
789 t1_seeprom_read(adapter, i, (__le32 *)&buf[i]);
790 memcpy(data, buf + e->offset, e->len);
791 return 0;
792}
793
794static const struct ethtool_ops t1_ethtool_ops = {
795 .get_settings = get_settings,
796 .set_settings = set_settings,
797 .get_drvinfo = get_drvinfo,
798 .get_msglevel = get_msglevel,
799 .set_msglevel = set_msglevel,
800 .get_ringparam = get_sge_param,
801 .set_ringparam = set_sge_param,
802 .get_coalesce = get_coalesce,
803 .set_coalesce = set_coalesce,
804 .get_eeprom_len = get_eeprom_len,
805 .get_eeprom = get_eeprom,
806 .get_pauseparam = get_pauseparam,
807 .set_pauseparam = set_pauseparam,
808 .get_link = ethtool_op_get_link,
809 .get_strings = get_strings,
810 .get_sset_count = get_sset_count,
811 .get_ethtool_stats = get_stats,
812 .get_regs_len = get_regs_len,
813 .get_regs = get_regs,
814};
815
816static int t1_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
817{
818 struct adapter *adapter = dev->ml_priv;
819 struct mdio_if_info *mdio = &adapter->port[dev->if_port].phy->mdio;
820
821 return mdio_mii_ioctl(mdio, if_mii(req), cmd);
822}
823
824static int t1_change_mtu(struct net_device *dev, int new_mtu)
825{
826 int ret;
827 struct adapter *adapter = dev->ml_priv;
828 struct cmac *mac = adapter->port[dev->if_port].mac;
829
830 if (!mac->ops->set_mtu)
831 return -EOPNOTSUPP;
832 if (new_mtu < 68)
833 return -EINVAL;
834 if ((ret = mac->ops->set_mtu(mac, new_mtu)))
835 return ret;
836 dev->mtu = new_mtu;
837 return 0;
838}
839
840static int t1_set_mac_addr(struct net_device *dev, void *p)
841{
842 struct adapter *adapter = dev->ml_priv;
843 struct cmac *mac = adapter->port[dev->if_port].mac;
844 struct sockaddr *addr = p;
845
846 if (!mac->ops->macaddress_set)
847 return -EOPNOTSUPP;
848
849 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
850 mac->ops->macaddress_set(mac, dev->dev_addr);
851 return 0;
852}
853
854static u32 t1_fix_features(struct net_device *dev, u32 features)
855{
856 /*
857 * Since there is no support for separate rx/tx vlan accel
858 * enable/disable make sure tx flag is always in same state as rx.
859 */
860 if (features & NETIF_F_HW_VLAN_RX)
861 features |= NETIF_F_HW_VLAN_TX;
862 else
863 features &= ~NETIF_F_HW_VLAN_TX;
864
865 return features;
866}
867
868static int t1_set_features(struct net_device *dev, u32 features)
869{
870 u32 changed = dev->features ^ features;
871 struct adapter *adapter = dev->ml_priv;
872
873 if (changed & NETIF_F_HW_VLAN_RX)
874 t1_vlan_mode(adapter, features);
875
876 return 0;
877}
878#ifdef CONFIG_NET_POLL_CONTROLLER
879static void t1_netpoll(struct net_device *dev)
880{
881 unsigned long flags;
882 struct adapter *adapter = dev->ml_priv;
883
884 local_irq_save(flags);
885 t1_interrupt(adapter->pdev->irq, adapter);
886 local_irq_restore(flags);
887}
888#endif
889
890/*
891 * Periodic accumulation of MAC statistics. This is used only if the MAC
892 * does not have any other way to prevent stats counter overflow.
893 */
894static void mac_stats_task(struct work_struct *work)
895{
896 int i;
897 struct adapter *adapter =
898 container_of(work, struct adapter, stats_update_task.work);
899
900 for_each_port(adapter, i) {
901 struct port_info *p = &adapter->port[i];
902
903 if (netif_running(p->dev))
904 p->mac->ops->statistics_update(p->mac,
905 MAC_STATS_UPDATE_FAST);
906 }
907
908 /* Schedule the next statistics update if any port is active. */
909 spin_lock(&adapter->work_lock);
910 if (adapter->open_device_map & PORT_MASK)
911 schedule_mac_stats_update(adapter,
912 adapter->params.stats_update_period);
913 spin_unlock(&adapter->work_lock);
914}
915
916/*
917 * Processes elmer0 external interrupts in process context.
918 */
919static void ext_intr_task(struct work_struct *work)
920{
921 struct adapter *adapter =
922 container_of(work, struct adapter, ext_intr_handler_task);
923
924 t1_elmer0_ext_intr_handler(adapter);
925
926 /* Now reenable external interrupts */
927 spin_lock_irq(&adapter->async_lock);
928 adapter->slow_intr_mask |= F_PL_INTR_EXT;
929 writel(F_PL_INTR_EXT, adapter->regs + A_PL_CAUSE);
930 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
931 adapter->regs + A_PL_ENABLE);
932 spin_unlock_irq(&adapter->async_lock);
933}
934
935/*
936 * Interrupt-context handler for elmer0 external interrupts.
937 */
938void t1_elmer0_ext_intr(struct adapter *adapter)
939{
940 /*
941 * Schedule a task to handle external interrupts as we require
942 * a process context. We disable EXT interrupts in the interim
943 * and let the task reenable them when it's done.
944 */
945 adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
946 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
947 adapter->regs + A_PL_ENABLE);
948 schedule_work(&adapter->ext_intr_handler_task);
949}
950
951void t1_fatal_err(struct adapter *adapter)
952{
953 if (adapter->flags & FULL_INIT_DONE) {
954 t1_sge_stop(adapter->sge);
955 t1_interrupts_disable(adapter);
956 }
957 pr_alert("%s: encountered fatal error, operation suspended\n",
958 adapter->name);
959}
960
961static const struct net_device_ops cxgb_netdev_ops = {
962 .ndo_open = cxgb_open,
963 .ndo_stop = cxgb_close,
964 .ndo_start_xmit = t1_start_xmit,
965 .ndo_get_stats = t1_get_stats,
966 .ndo_validate_addr = eth_validate_addr,
967 .ndo_set_multicast_list = t1_set_rxmode,
968 .ndo_do_ioctl = t1_ioctl,
969 .ndo_change_mtu = t1_change_mtu,
970 .ndo_set_mac_address = t1_set_mac_addr,
971 .ndo_fix_features = t1_fix_features,
972 .ndo_set_features = t1_set_features,
973#ifdef CONFIG_NET_POLL_CONTROLLER
974 .ndo_poll_controller = t1_netpoll,
975#endif
976};
977
978static int __devinit init_one(struct pci_dev *pdev,
979 const struct pci_device_id *ent)
980{
981 static int version_printed;
982
983 int i, err, pci_using_dac = 0;
984 unsigned long mmio_start, mmio_len;
985 const struct board_info *bi;
986 struct adapter *adapter = NULL;
987 struct port_info *pi;
988
989 if (!version_printed) {
990 printk(KERN_INFO "%s - version %s\n", DRV_DESCRIPTION,
991 DRV_VERSION);
992 ++version_printed;
993 }
994
995 err = pci_enable_device(pdev);
996 if (err)
997 return err;
998
999 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1000 pr_err("%s: cannot find PCI device memory base address\n",
1001 pci_name(pdev));
1002 err = -ENODEV;
1003 goto out_disable_pdev;
1004 }
1005
1006 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1007 pci_using_dac = 1;
1008
1009 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1010 pr_err("%s: unable to obtain 64-bit DMA for "
1011 "consistent allocations\n", pci_name(pdev));
1012 err = -ENODEV;
1013 goto out_disable_pdev;
1014 }
1015
1016 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
1017 pr_err("%s: no usable DMA configuration\n", pci_name(pdev));
1018 goto out_disable_pdev;
1019 }
1020
1021 err = pci_request_regions(pdev, DRV_NAME);
1022 if (err) {
1023 pr_err("%s: cannot obtain PCI resources\n", pci_name(pdev));
1024 goto out_disable_pdev;
1025 }
1026
1027 pci_set_master(pdev);
1028
1029 mmio_start = pci_resource_start(pdev, 0);
1030 mmio_len = pci_resource_len(pdev, 0);
1031 bi = t1_get_board_info(ent->driver_data);
1032
1033 for (i = 0; i < bi->port_number; ++i) {
1034 struct net_device *netdev;
1035
1036 netdev = alloc_etherdev(adapter ? 0 : sizeof(*adapter));
1037 if (!netdev) {
1038 err = -ENOMEM;
1039 goto out_free_dev;
1040 }
1041
1042 SET_NETDEV_DEV(netdev, &pdev->dev);
1043
1044 if (!adapter) {
1045 adapter = netdev_priv(netdev);
1046 adapter->pdev = pdev;
1047 adapter->port[0].dev = netdev; /* so we don't leak it */
1048
1049 adapter->regs = ioremap(mmio_start, mmio_len);
1050 if (!adapter->regs) {
1051 pr_err("%s: cannot map device registers\n",
1052 pci_name(pdev));
1053 err = -ENOMEM;
1054 goto out_free_dev;
1055 }
1056
1057 if (t1_get_board_rev(adapter, bi, &adapter->params)) {
1058 err = -ENODEV; /* Can't handle this chip rev */
1059 goto out_free_dev;
1060 }
1061
1062 adapter->name = pci_name(pdev);
1063 adapter->msg_enable = dflt_msg_enable;
1064 adapter->mmio_len = mmio_len;
1065
1066 spin_lock_init(&adapter->tpi_lock);
1067 spin_lock_init(&adapter->work_lock);
1068 spin_lock_init(&adapter->async_lock);
1069 spin_lock_init(&adapter->mac_lock);
1070
1071 INIT_WORK(&adapter->ext_intr_handler_task,
1072 ext_intr_task);
1073 INIT_DELAYED_WORK(&adapter->stats_update_task,
1074 mac_stats_task);
1075
1076 pci_set_drvdata(pdev, netdev);
1077 }
1078
1079 pi = &adapter->port[i];
1080 pi->dev = netdev;
1081 netif_carrier_off(netdev);
1082 netdev->irq = pdev->irq;
1083 netdev->if_port = i;
1084 netdev->mem_start = mmio_start;
1085 netdev->mem_end = mmio_start + mmio_len - 1;
1086 netdev->ml_priv = adapter;
1087 netdev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
1088 NETIF_F_RXCSUM;
1089 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM |
1090 NETIF_F_RXCSUM | NETIF_F_LLTX;
1091
1092 if (pci_using_dac)
1093 netdev->features |= NETIF_F_HIGHDMA;
1094 if (vlan_tso_capable(adapter)) {
1095 netdev->features |=
1096 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1097 netdev->hw_features |= NETIF_F_HW_VLAN_RX;
1098
1099 /* T204: disable TSO */
1100 if (!(is_T2(adapter)) || bi->port_number != 4) {
1101 netdev->hw_features |= NETIF_F_TSO;
1102 netdev->features |= NETIF_F_TSO;
1103 }
1104 }
1105
1106 netdev->netdev_ops = &cxgb_netdev_ops;
1107 netdev->hard_header_len += (netdev->hw_features & NETIF_F_TSO) ?
1108 sizeof(struct cpl_tx_pkt_lso) : sizeof(struct cpl_tx_pkt);
1109
1110 netif_napi_add(netdev, &adapter->napi, t1_poll, 64);
1111
1112 SET_ETHTOOL_OPS(netdev, &t1_ethtool_ops);
1113 }
1114
1115 if (t1_init_sw_modules(adapter, bi) < 0) {
1116 err = -ENODEV;
1117 goto out_free_dev;
1118 }
1119
1120 /*
1121 * The card is now ready to go. If any errors occur during device
1122 * registration we do not fail the whole card but rather proceed only
1123 * with the ports we manage to register successfully. However we must
1124 * register at least one net device.
1125 */
1126 for (i = 0; i < bi->port_number; ++i) {
1127 err = register_netdev(adapter->port[i].dev);
1128 if (err)
1129 pr_warning("%s: cannot register net device %s, skipping\n",
1130 pci_name(pdev), adapter->port[i].dev->name);
1131 else {
1132 /*
1133 * Change the name we use for messages to the name of
1134 * the first successfully registered interface.
1135 */
1136 if (!adapter->registered_device_map)
1137 adapter->name = adapter->port[i].dev->name;
1138
1139 __set_bit(i, &adapter->registered_device_map);
1140 }
1141 }
1142 if (!adapter->registered_device_map) {
1143 pr_err("%s: could not register any net devices\n",
1144 pci_name(pdev));
1145 goto out_release_adapter_res;
1146 }
1147
1148 printk(KERN_INFO "%s: %s (rev %d), %s %dMHz/%d-bit\n", adapter->name,
1149 bi->desc, adapter->params.chip_revision,
1150 adapter->params.pci.is_pcix ? "PCIX" : "PCI",
1151 adapter->params.pci.speed, adapter->params.pci.width);
1152
1153 /*
1154 * Set the T1B ASIC and memory clocks.
1155 */
1156 if (t1powersave)
1157 adapter->t1powersave = LCLOCK; /* HW default is powersave mode. */
1158 else
1159 adapter->t1powersave = HCLOCK;
1160 if (t1_is_T1B(adapter))
1161 t1_clock(adapter, t1powersave);
1162
1163 return 0;
1164
1165out_release_adapter_res:
1166 t1_free_sw_modules(adapter);
1167out_free_dev:
1168 if (adapter) {
1169 if (adapter->regs)
1170 iounmap(adapter->regs);
1171 for (i = bi->port_number - 1; i >= 0; --i)
1172 if (adapter->port[i].dev)
1173 free_netdev(adapter->port[i].dev);
1174 }
1175 pci_release_regions(pdev);
1176out_disable_pdev:
1177 pci_disable_device(pdev);
1178 pci_set_drvdata(pdev, NULL);
1179 return err;
1180}
1181
1182static void bit_bang(struct adapter *adapter, int bitdata, int nbits)
1183{
1184 int data;
1185 int i;
1186 u32 val;
1187
1188 enum {
1189 S_CLOCK = 1 << 3,
1190 S_DATA = 1 << 4
1191 };
1192
1193 for (i = (nbits - 1); i > -1; i--) {
1194
1195 udelay(50);
1196
1197 data = ((bitdata >> i) & 0x1);
1198 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1199
1200 if (data)
1201 val |= S_DATA;
1202 else
1203 val &= ~S_DATA;
1204
1205 udelay(50);
1206
1207 /* Set SCLOCK low */
1208 val &= ~S_CLOCK;
1209 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1210
1211 udelay(50);
1212
1213 /* Write SCLOCK high */
1214 val |= S_CLOCK;
1215 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1216
1217 }
1218}
1219
1220static int t1_clock(struct adapter *adapter, int mode)
1221{
1222 u32 val;
1223 int M_CORE_VAL;
1224 int M_MEM_VAL;
1225
1226 enum {
1227 M_CORE_BITS = 9,
1228 T_CORE_VAL = 0,
1229 T_CORE_BITS = 2,
1230 N_CORE_VAL = 0,
1231 N_CORE_BITS = 2,
1232 M_MEM_BITS = 9,
1233 T_MEM_VAL = 0,
1234 T_MEM_BITS = 2,
1235 N_MEM_VAL = 0,
1236 N_MEM_BITS = 2,
1237 NP_LOAD = 1 << 17,
1238 S_LOAD_MEM = 1 << 5,
1239 S_LOAD_CORE = 1 << 6,
1240 S_CLOCK = 1 << 3
1241 };
1242
1243 if (!t1_is_T1B(adapter))
1244 return -ENODEV; /* Can't re-clock this chip. */
1245
1246 if (mode & 2)
1247 return 0; /* show current mode. */
1248
1249 if ((adapter->t1powersave & 1) == (mode & 1))
1250 return -EALREADY; /* ASIC already running in mode. */
1251
1252 if ((mode & 1) == HCLOCK) {
1253 M_CORE_VAL = 0x14;
1254 M_MEM_VAL = 0x18;
1255 adapter->t1powersave = HCLOCK; /* overclock */
1256 } else {
1257 M_CORE_VAL = 0xe;
1258 M_MEM_VAL = 0x10;
1259 adapter->t1powersave = LCLOCK; /* underclock */
1260 }
1261
1262 /* Don't interrupt this serial stream! */
1263 spin_lock(&adapter->tpi_lock);
1264
1265 /* Initialize for ASIC core */
1266 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1267 val |= NP_LOAD;
1268 udelay(50);
1269 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1270 udelay(50);
1271 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1272 val &= ~S_LOAD_CORE;
1273 val &= ~S_CLOCK;
1274 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1275 udelay(50);
1276
1277 /* Serial program the ASIC clock synthesizer */
1278 bit_bang(adapter, T_CORE_VAL, T_CORE_BITS);
1279 bit_bang(adapter, N_CORE_VAL, N_CORE_BITS);
1280 bit_bang(adapter, M_CORE_VAL, M_CORE_BITS);
1281 udelay(50);
1282
1283 /* Finish ASIC core */
1284 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1285 val |= S_LOAD_CORE;
1286 udelay(50);
1287 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1288 udelay(50);
1289 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1290 val &= ~S_LOAD_CORE;
1291 udelay(50);
1292 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1293 udelay(50);
1294
1295 /* Initialize for memory */
1296 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1297 val |= NP_LOAD;
1298 udelay(50);
1299 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1300 udelay(50);
1301 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1302 val &= ~S_LOAD_MEM;
1303 val &= ~S_CLOCK;
1304 udelay(50);
1305 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1306 udelay(50);
1307
1308 /* Serial program the memory clock synthesizer */
1309 bit_bang(adapter, T_MEM_VAL, T_MEM_BITS);
1310 bit_bang(adapter, N_MEM_VAL, N_MEM_BITS);
1311 bit_bang(adapter, M_MEM_VAL, M_MEM_BITS);
1312 udelay(50);
1313
1314 /* Finish memory */
1315 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1316 val |= S_LOAD_MEM;
1317 udelay(50);
1318 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1319 udelay(50);
1320 __t1_tpi_read(adapter, A_ELMER0_GPO, &val);
1321 val &= ~S_LOAD_MEM;
1322 udelay(50);
1323 __t1_tpi_write(adapter, A_ELMER0_GPO, val);
1324
1325 spin_unlock(&adapter->tpi_lock);
1326
1327 return 0;
1328}
1329
1330static inline void t1_sw_reset(struct pci_dev *pdev)
1331{
1332 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 3);
1333 pci_write_config_dword(pdev, A_PCICFG_PM_CSR, 0);
1334}
1335
1336static void __devexit remove_one(struct pci_dev *pdev)
1337{
1338 struct net_device *dev = pci_get_drvdata(pdev);
1339 struct adapter *adapter = dev->ml_priv;
1340 int i;
1341
1342 for_each_port(adapter, i) {
1343 if (test_bit(i, &adapter->registered_device_map))
1344 unregister_netdev(adapter->port[i].dev);
1345 }
1346
1347 t1_free_sw_modules(adapter);
1348 iounmap(adapter->regs);
1349
1350 while (--i >= 0) {
1351 if (adapter->port[i].dev)
1352 free_netdev(adapter->port[i].dev);
1353 }
1354
1355 pci_release_regions(pdev);
1356 pci_disable_device(pdev);
1357 pci_set_drvdata(pdev, NULL);
1358 t1_sw_reset(pdev);
1359}
1360
1361static struct pci_driver driver = {
1362 .name = DRV_NAME,
1363 .id_table = t1_pci_tbl,
1364 .probe = init_one,
1365 .remove = __devexit_p(remove_one),
1366};
1367
1368static int __init t1_init_module(void)
1369{
1370 return pci_register_driver(&driver);
1371}
1372
1373static void __exit t1_cleanup_module(void)
1374{
1375 pci_unregister_driver(&driver);
1376}
1377
1378module_init(t1_init_module);
1379module_exit(t1_cleanup_module);
diff --git a/drivers/net/chelsio/elmer0.h b/drivers/net/chelsio/elmer0.h
deleted file mode 100644
index eef655c827d9..000000000000
--- a/drivers/net/chelsio/elmer0.h
+++ /dev/null
@@ -1,158 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: elmer0.h *
4 * $Revision: 1.6 $ *
5 * $Date: 2005/06/21 22:49:43 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_ELMER0_H_
40#define _CXGB_ELMER0_H_
41
42/* ELMER0 flavors */
43enum {
44 ELMER0_XC2S300E_6FT256_C,
45 ELMER0_XC2S100E_6TQ144_C
46};
47
48/* ELMER0 registers */
49#define A_ELMER0_VERSION 0x100000
50#define A_ELMER0_PHY_CFG 0x100004
51#define A_ELMER0_INT_ENABLE 0x100008
52#define A_ELMER0_INT_CAUSE 0x10000c
53#define A_ELMER0_GPI_CFG 0x100010
54#define A_ELMER0_GPI_STAT 0x100014
55#define A_ELMER0_GPO 0x100018
56#define A_ELMER0_PORT0_MI1_CFG 0x400000
57
58#define S_MI1_MDI_ENABLE 0
59#define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
60#define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)
61
62#define S_MI1_MDI_INVERT 1
63#define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
64#define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)
65
66#define S_MI1_PREAMBLE_ENABLE 2
67#define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
68#define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)
69
70#define S_MI1_SOF 3
71#define M_MI1_SOF 0x3
72#define V_MI1_SOF(x) ((x) << S_MI1_SOF)
73#define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
74
75#define S_MI1_CLK_DIV 5
76#define M_MI1_CLK_DIV 0xff
77#define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
78#define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
79
80#define A_ELMER0_PORT0_MI1_ADDR 0x400004
81
82#define S_MI1_REG_ADDR 0
83#define M_MI1_REG_ADDR 0x1f
84#define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
85#define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
86
87#define S_MI1_PHY_ADDR 5
88#define M_MI1_PHY_ADDR 0x1f
89#define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
90#define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
91
92#define A_ELMER0_PORT0_MI1_DATA 0x400008
93
94#define S_MI1_DATA 0
95#define M_MI1_DATA 0xffff
96#define V_MI1_DATA(x) ((x) << S_MI1_DATA)
97#define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
98
99#define A_ELMER0_PORT0_MI1_OP 0x40000c
100
101#define S_MI1_OP 0
102#define M_MI1_OP 0x3
103#define V_MI1_OP(x) ((x) << S_MI1_OP)
104#define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
105
106#define S_MI1_ADDR_AUTOINC 2
107#define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
108#define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)
109
110#define S_MI1_OP_BUSY 31
111#define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
112#define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)
113
114#define A_ELMER0_PORT1_MI1_CFG 0x500000
115#define A_ELMER0_PORT1_MI1_ADDR 0x500004
116#define A_ELMER0_PORT1_MI1_DATA 0x500008
117#define A_ELMER0_PORT1_MI1_OP 0x50000c
118#define A_ELMER0_PORT2_MI1_CFG 0x600000
119#define A_ELMER0_PORT2_MI1_ADDR 0x600004
120#define A_ELMER0_PORT2_MI1_DATA 0x600008
121#define A_ELMER0_PORT2_MI1_OP 0x60000c
122#define A_ELMER0_PORT3_MI1_CFG 0x700000
123#define A_ELMER0_PORT3_MI1_ADDR 0x700004
124#define A_ELMER0_PORT3_MI1_DATA 0x700008
125#define A_ELMER0_PORT3_MI1_OP 0x70000c
126
127/* Simple bit definition for GPI and GP0 registers. */
128#define ELMER0_GP_BIT0 0x0001
129#define ELMER0_GP_BIT1 0x0002
130#define ELMER0_GP_BIT2 0x0004
131#define ELMER0_GP_BIT3 0x0008
132#define ELMER0_GP_BIT4 0x0010
133#define ELMER0_GP_BIT5 0x0020
134#define ELMER0_GP_BIT6 0x0040
135#define ELMER0_GP_BIT7 0x0080
136#define ELMER0_GP_BIT8 0x0100
137#define ELMER0_GP_BIT9 0x0200
138#define ELMER0_GP_BIT10 0x0400
139#define ELMER0_GP_BIT11 0x0800
140#define ELMER0_GP_BIT12 0x1000
141#define ELMER0_GP_BIT13 0x2000
142#define ELMER0_GP_BIT14 0x4000
143#define ELMER0_GP_BIT15 0x8000
144#define ELMER0_GP_BIT16 0x10000
145#define ELMER0_GP_BIT17 0x20000
146#define ELMER0_GP_BIT18 0x40000
147#define ELMER0_GP_BIT19 0x80000
148
149#define MI1_OP_DIRECT_WRITE 1
150#define MI1_OP_DIRECT_READ 2
151
152#define MI1_OP_INDIRECT_ADDRESS 0
153#define MI1_OP_INDIRECT_WRITE 1
154#define MI1_OP_INDIRECT_READ_INC 2
155#define MI1_OP_INDIRECT_READ 3
156
157#endif /* _CXGB_ELMER0_H_ */
158
diff --git a/drivers/net/chelsio/espi.c b/drivers/net/chelsio/espi.c
deleted file mode 100644
index 639ff1955739..000000000000
--- a/drivers/net/chelsio/espi.c
+++ /dev/null
@@ -1,373 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: espi.c *
4 * $Revision: 1.14 $ *
5 * $Date: 2005/05/14 00:59:32 $ *
6 * Description: *
7 * Ethernet SPI functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41#include "regs.h"
42#include "espi.h"
43
44struct peespi {
45 adapter_t *adapter;
46 struct espi_intr_counts intr_cnt;
47 u32 misc_ctrl;
48 spinlock_t lock;
49};
50
51#define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
52 F_RAMPARITYERR | F_DIP2PARITYERR)
53#define MON_MASK (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
54 | F_MONITORED_INTERFACE)
55
56#define TRICN_CNFG 14
57#define TRICN_CMD_READ 0x11
58#define TRICN_CMD_WRITE 0x21
59#define TRICN_CMD_ATTEMPTS 10
60
61static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
62 int ch_addr, int reg_offset, u32 wr_data)
63{
64 int busy, attempts = TRICN_CMD_ATTEMPTS;
65
66 writel(V_WRITE_DATA(wr_data) |
67 V_REGISTER_OFFSET(reg_offset) |
68 V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
69 V_BUNDLE_ADDR(bundle_addr) |
70 V_SPI4_COMMAND(TRICN_CMD_WRITE),
71 adapter->regs + A_ESPI_CMD_ADDR);
72 writel(0, adapter->regs + A_ESPI_GOSTAT);
73
74 do {
75 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
76 } while (busy && --attempts);
77
78 if (busy)
79 pr_err("%s: TRICN write timed out\n", adapter->name);
80
81 return busy;
82}
83
84static int tricn_init(adapter_t *adapter)
85{
86 int i, sme = 1;
87
88 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) {
89 pr_err("%s: ESPI clock not ready\n", adapter->name);
90 return -1;
91 }
92
93 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
94
95 if (sme) {
96 tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
97 tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
98 tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
99 }
100 for (i = 1; i <= 8; i++)
101 tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
102 for (i = 1; i <= 2; i++)
103 tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
104 for (i = 1; i <= 3; i++)
105 tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
106 tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
107 tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
108 tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
109 tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
110 tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
111
112 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
113 adapter->regs + A_ESPI_RX_RESET);
114
115 return 0;
116}
117
118void t1_espi_intr_enable(struct peespi *espi)
119{
120 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
121
122 /*
123 * Cannot enable ESPI interrupts on T1B because HW asserts the
124 * interrupt incorrectly, namely the driver gets ESPI interrupts
125 * but no data is actually dropped (can verify this reading the ESPI
126 * drop registers). Also, once the ESPI interrupt is asserted it
127 * cannot be cleared (HW bug).
128 */
129 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
130 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
131 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
132}
133
134void t1_espi_intr_clear(struct peespi *espi)
135{
136 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
137 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
138 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
139}
140
141void t1_espi_intr_disable(struct peespi *espi)
142{
143 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
144
145 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
146 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
147}
148
149int t1_espi_intr_handler(struct peespi *espi)
150{
151 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
152
153 if (status & F_DIP4ERR)
154 espi->intr_cnt.DIP4_err++;
155 if (status & F_RXDROP)
156 espi->intr_cnt.rx_drops++;
157 if (status & F_TXDROP)
158 espi->intr_cnt.tx_drops++;
159 if (status & F_RXOVERFLOW)
160 espi->intr_cnt.rx_ovflw++;
161 if (status & F_RAMPARITYERR)
162 espi->intr_cnt.parity_err++;
163 if (status & F_DIP2PARITYERR) {
164 espi->intr_cnt.DIP2_parity_err++;
165
166 /*
167 * Must read the error count to clear the interrupt
168 * that it causes.
169 */
170 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
171 }
172
173 /*
174 * For T1B we need to write 1 to clear ESPI interrupts. For T2+ we
175 * write the status as is.
176 */
177 if (status && t1_is_T1B(espi->adapter))
178 status = 1;
179 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
180 return 0;
181}
182
183const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
184{
185 return &espi->intr_cnt;
186}
187
188static void espi_setup_for_pm3393(adapter_t *adapter)
189{
190 u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
191
192 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
193 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
194 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
195 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
196 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
197 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
198 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
199 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
200 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
201}
202
203static void espi_setup_for_vsc7321(adapter_t *adapter)
204{
205 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
206 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
207 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
208 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
209 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
210 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
211 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
212
213 writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
214}
215
216/*
217 * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
218 */
219static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
220{
221 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
222 if (nports == 4) {
223 if (is_T2(adapter)) {
224 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
225 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
226 } else {
227 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
228 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
229 }
230 } else {
231 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
232 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
233 }
234 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
235
236}
237
238int t1_espi_init(struct peespi *espi, int mac_type, int nports)
239{
240 u32 status_enable_extra = 0;
241 adapter_t *adapter = espi->adapter;
242
243 /* Disable ESPI training. MACs that can handle it enable it below. */
244 writel(0, adapter->regs + A_ESPI_TRAIN);
245
246 if (is_T2(adapter)) {
247 writel(V_OUT_OF_SYNC_COUNT(4) |
248 V_DIP2_PARITY_ERR_THRES(3) |
249 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
250 writel(nports == 4 ? 0x200040 : 0x1000080,
251 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
252 } else
253 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
254
255 if (mac_type == CHBT_MAC_PM3393)
256 espi_setup_for_pm3393(adapter);
257 else if (mac_type == CHBT_MAC_VSC7321)
258 espi_setup_for_vsc7321(adapter);
259 else if (mac_type == CHBT_MAC_IXF1010) {
260 status_enable_extra = F_INTEL1010MODE;
261 espi_setup_for_ixf1010(adapter, nports);
262 } else
263 return -1;
264
265 writel(status_enable_extra | F_RXSTATUSENABLE,
266 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
267
268 if (is_T2(adapter)) {
269 tricn_init(adapter);
270 /*
271 * Always position the control at the 1st port egress IN
272 * (sop,eop) counter to reduce PIOs for T/N210 workaround.
273 */
274 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
275 espi->misc_ctrl &= ~MON_MASK;
276 espi->misc_ctrl |= F_MONITORED_DIRECTION;
277 if (adapter->params.nports == 1)
278 espi->misc_ctrl |= F_MONITORED_INTERFACE;
279 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
280 spin_lock_init(&espi->lock);
281 }
282
283 return 0;
284}
285
286void t1_espi_destroy(struct peespi *espi)
287{
288 kfree(espi);
289}
290
291struct peespi *t1_espi_create(adapter_t *adapter)
292{
293 struct peespi *espi = kzalloc(sizeof(*espi), GFP_KERNEL);
294
295 if (espi)
296 espi->adapter = adapter;
297 return espi;
298}
299
300#if 0
301void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
302{
303 struct peespi *espi = adapter->espi;
304
305 if (!is_T2(adapter))
306 return;
307 spin_lock(&espi->lock);
308 espi->misc_ctrl = (val & ~MON_MASK) |
309 (espi->misc_ctrl & MON_MASK);
310 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
311 spin_unlock(&espi->lock);
312}
313#endif /* 0 */
314
315u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
316{
317 struct peespi *espi = adapter->espi;
318 u32 sel;
319
320 if (!is_T2(adapter))
321 return 0;
322
323 sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
324 if (!wait) {
325 if (!spin_trylock(&espi->lock))
326 return 0;
327 } else
328 spin_lock(&espi->lock);
329
330 if ((sel != (espi->misc_ctrl & MON_MASK))) {
331 writel(((espi->misc_ctrl & ~MON_MASK) | sel),
332 adapter->regs + A_ESPI_MISC_CONTROL);
333 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
334 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
335 } else
336 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
337 spin_unlock(&espi->lock);
338 return sel;
339}
340
341/*
342 * This function is for T204 only.
343 * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
344 * one shot, since there is no per port counter on the out side.
345 */
346int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
347{
348 struct peespi *espi = adapter->espi;
349 u8 i, nport = (u8)adapter->params.nports;
350
351 if (!wait) {
352 if (!spin_trylock(&espi->lock))
353 return -1;
354 } else
355 spin_lock(&espi->lock);
356
357 if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION) {
358 espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
359 F_MONITORED_DIRECTION;
360 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
361 }
362 for (i = 0 ; i < nport; i++, valp++) {
363 if (i) {
364 writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i),
365 adapter->regs + A_ESPI_MISC_CONTROL);
366 }
367 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
368 }
369
370 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
371 spin_unlock(&espi->lock);
372 return 0;
373}
diff --git a/drivers/net/chelsio/espi.h b/drivers/net/chelsio/espi.h
deleted file mode 100644
index 5694aad4fbc0..000000000000
--- a/drivers/net/chelsio/espi.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: espi.h *
4 * $Revision: 1.7 $ *
5 * $Date: 2005/06/21 18:29:47 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_ESPI_H_
40#define _CXGB_ESPI_H_
41
42#include "common.h"
43
44struct espi_intr_counts {
45 unsigned int DIP4_err;
46 unsigned int rx_drops;
47 unsigned int tx_drops;
48 unsigned int rx_ovflw;
49 unsigned int parity_err;
50 unsigned int DIP2_parity_err;
51};
52
53struct peespi;
54
55struct peespi *t1_espi_create(adapter_t *adapter);
56void t1_espi_destroy(struct peespi *espi);
57int t1_espi_init(struct peespi *espi, int mac_type, int nports);
58
59void t1_espi_intr_enable(struct peespi *);
60void t1_espi_intr_clear(struct peespi *);
61void t1_espi_intr_disable(struct peespi *);
62int t1_espi_intr_handler(struct peespi *);
63const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi);
64
65u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait);
66int t1_espi_get_mon_t204(adapter_t *, u32 *, u8);
67
68#endif /* _CXGB_ESPI_H_ */
diff --git a/drivers/net/chelsio/fpga_defs.h b/drivers/net/chelsio/fpga_defs.h
deleted file mode 100644
index ccdb2bc9ae98..000000000000
--- a/drivers/net/chelsio/fpga_defs.h
+++ /dev/null
@@ -1,232 +0,0 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: fpga_defs.h,v $ $Revision: 1.4 $ */
2
3/*
4 * FPGA specific definitions
5 */
6
7#ifndef __CHELSIO_FPGA_DEFS_H__
8#define __CHELSIO_FPGA_DEFS_H__
9
10#define FPGA_PCIX_ADDR_VERSION 0xA08
11#define FPGA_PCIX_ADDR_STAT 0xA0C
12
13/* FPGA master interrupt Cause/Enable bits */
14#define FPGA_PCIX_INTERRUPT_SGE_ERROR 0x1
15#define FPGA_PCIX_INTERRUPT_SGE_DATA 0x2
16#define FPGA_PCIX_INTERRUPT_TP 0x4
17#define FPGA_PCIX_INTERRUPT_MC3 0x8
18#define FPGA_PCIX_INTERRUPT_GMAC 0x10
19#define FPGA_PCIX_INTERRUPT_PCIX 0x20
20
21/* TP interrupt register addresses */
22#define FPGA_TP_ADDR_INTERRUPT_ENABLE 0xA10
23#define FPGA_TP_ADDR_INTERRUPT_CAUSE 0xA14
24#define FPGA_TP_ADDR_VERSION 0xA18
25
26/* TP interrupt Cause/Enable bits */
27#define FPGA_TP_INTERRUPT_MC4 0x1
28#define FPGA_TP_INTERRUPT_MC5 0x2
29
30/*
31 * PM interrupt register addresses
32 */
33#define FPGA_MC3_REG_INTRENABLE 0xA20
34#define FPGA_MC3_REG_INTRCAUSE 0xA24
35#define FPGA_MC3_REG_VERSION 0xA28
36
37/*
38 * GMAC interrupt register addresses
39 */
40#define FPGA_GMAC_ADDR_INTERRUPT_ENABLE 0xA30
41#define FPGA_GMAC_ADDR_INTERRUPT_CAUSE 0xA34
42#define FPGA_GMAC_ADDR_VERSION 0xA38
43
44/* GMAC Cause/Enable bits */
45#define FPGA_GMAC_INTERRUPT_PORT0 0x1
46#define FPGA_GMAC_INTERRUPT_PORT1 0x2
47#define FPGA_GMAC_INTERRUPT_PORT2 0x4
48#define FPGA_GMAC_INTERRUPT_PORT3 0x8
49
50/* MI0 registers */
51#define A_MI0_CLK 0xb00
52
53#define S_MI0_CLK_DIV 0
54#define M_MI0_CLK_DIV 0xff
55#define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
56#define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
57
58#define S_MI0_CLK_CNT 8
59#define M_MI0_CLK_CNT 0xff
60#define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
61#define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
62
63#define A_MI0_CSR 0xb04
64
65#define S_MI0_CSR_POLL 0
66#define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
67#define F_MI0_CSR_POLL V_MI0_CSR_POLL(1U)
68
69#define S_MI0_PREAMBLE 1
70#define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
71#define F_MI0_PREAMBLE V_MI0_PREAMBLE(1U)
72
73#define S_MI0_INTR_ENABLE 2
74#define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
75#define F_MI0_INTR_ENABLE V_MI0_INTR_ENABLE(1U)
76
77#define S_MI0_BUSY 3
78#define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
79#define F_MI0_BUSY V_MI0_BUSY(1U)
80
81#define S_MI0_MDIO 4
82#define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
83#define F_MI0_MDIO V_MI0_MDIO(1U)
84
85#define A_MI0_ADDR 0xb08
86
87#define S_MI0_PHY_REG_ADDR 0
88#define M_MI0_PHY_REG_ADDR 0x1f
89#define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
90#define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
91
92#define S_MI0_PHY_ADDR 5
93#define M_MI0_PHY_ADDR 0x1f
94#define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
95#define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
96
97#define A_MI0_DATA_EXT 0xb0c
98#define A_MI0_DATA_INT 0xb10
99
100/* GMAC registers */
101#define A_GMAC_MACID_LO 0x28
102#define A_GMAC_MACID_HI 0x2c
103#define A_GMAC_CSR 0x30
104
105#define S_INTERFACE 0
106#define M_INTERFACE 0x3
107#define V_INTERFACE(x) ((x) << S_INTERFACE)
108#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
109
110#define S_MAC_TX_ENABLE 2
111#define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
112#define F_MAC_TX_ENABLE V_MAC_TX_ENABLE(1U)
113
114#define S_MAC_RX_ENABLE 3
115#define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
116#define F_MAC_RX_ENABLE V_MAC_RX_ENABLE(1U)
117
118#define S_MAC_LB_ENABLE 4
119#define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
120#define F_MAC_LB_ENABLE V_MAC_LB_ENABLE(1U)
121
122#define S_MAC_SPEED 5
123#define M_MAC_SPEED 0x3
124#define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
125#define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
126
127#define S_MAC_HD_FC_ENABLE 7
128#define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
129#define F_MAC_HD_FC_ENABLE V_MAC_HD_FC_ENABLE(1U)
130
131#define S_MAC_HALF_DUPLEX 8
132#define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
133#define F_MAC_HALF_DUPLEX V_MAC_HALF_DUPLEX(1U)
134
135#define S_MAC_PROMISC 9
136#define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
137#define F_MAC_PROMISC V_MAC_PROMISC(1U)
138
139#define S_MAC_MC_ENABLE 10
140#define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
141#define F_MAC_MC_ENABLE V_MAC_MC_ENABLE(1U)
142
143#define S_MAC_RESET 11
144#define V_MAC_RESET(x) ((x) << S_MAC_RESET)
145#define F_MAC_RESET V_MAC_RESET(1U)
146
147#define S_MAC_RX_PAUSE_ENABLE 12
148#define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
149#define F_MAC_RX_PAUSE_ENABLE V_MAC_RX_PAUSE_ENABLE(1U)
150
151#define S_MAC_TX_PAUSE_ENABLE 13
152#define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
153#define F_MAC_TX_PAUSE_ENABLE V_MAC_TX_PAUSE_ENABLE(1U)
154
155#define S_MAC_LWM_ENABLE 14
156#define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
157#define F_MAC_LWM_ENABLE V_MAC_LWM_ENABLE(1U)
158
159#define S_MAC_MAGIC_PKT_ENABLE 15
160#define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
161#define F_MAC_MAGIC_PKT_ENABLE V_MAC_MAGIC_PKT_ENABLE(1U)
162
163#define S_MAC_ISL_ENABLE 16
164#define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
165#define F_MAC_ISL_ENABLE V_MAC_ISL_ENABLE(1U)
166
167#define S_MAC_JUMBO_ENABLE 17
168#define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
169#define F_MAC_JUMBO_ENABLE V_MAC_JUMBO_ENABLE(1U)
170
171#define S_MAC_RX_PAD_ENABLE 18
172#define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
173#define F_MAC_RX_PAD_ENABLE V_MAC_RX_PAD_ENABLE(1U)
174
175#define S_MAC_RX_CRC_ENABLE 19
176#define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
177#define F_MAC_RX_CRC_ENABLE V_MAC_RX_CRC_ENABLE(1U)
178
179#define A_GMAC_IFS 0x34
180
181#define S_MAC_IFS2 0
182#define M_MAC_IFS2 0x3f
183#define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
184#define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
185
186#define S_MAC_IFS1 8
187#define M_MAC_IFS1 0x7f
188#define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
189#define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
190
191#define A_GMAC_JUMBO_FRAME_LEN 0x38
192#define A_GMAC_LNK_DLY 0x3c
193#define A_GMAC_PAUSETIME 0x40
194#define A_GMAC_MCAST_LO 0x44
195#define A_GMAC_MCAST_HI 0x48
196#define A_GMAC_MCAST_MASK_LO 0x4c
197#define A_GMAC_MCAST_MASK_HI 0x50
198#define A_GMAC_RMT_CNT 0x54
199#define A_GMAC_RMT_DATA 0x58
200#define A_GMAC_BACKOFF_SEED 0x5c
201#define A_GMAC_TXF_THRES 0x60
202
203#define S_TXF_READ_THRESHOLD 0
204#define M_TXF_READ_THRESHOLD 0xff
205#define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
206#define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
207
208#define S_TXF_WRITE_THRESHOLD 16
209#define M_TXF_WRITE_THRESHOLD 0xff
210#define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
211#define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
212
213#define MAC_REG_BASE 0x600
214#define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
215
216#define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
217#define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
218#define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR)
219#define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS)
220#define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
221#define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
222#define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
223#define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
224#define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
225#define MAC_REG_CASTMASKLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
226#define MAC_REG_MCASTMASKHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
227#define MAC_REG_RMCNT(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
228#define MAC_REG_RMDATA(idx) MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
229#define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
230#define MAC_REG_TXFTHRESHOLDS(idx) MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
231
232#endif
diff --git a/drivers/net/chelsio/gmac.h b/drivers/net/chelsio/gmac.h
deleted file mode 100644
index d42337457cf7..000000000000
--- a/drivers/net/chelsio/gmac.h
+++ /dev/null
@@ -1,142 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: gmac.h *
4 * $Revision: 1.6 $ *
5 * $Date: 2005/06/21 18:29:47 $ *
6 * Description: *
7 * Generic MAC functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#ifndef _CXGB_GMAC_H_
41#define _CXGB_GMAC_H_
42
43#include "common.h"
44
45enum {
46 MAC_STATS_UPDATE_FAST,
47 MAC_STATS_UPDATE_FULL
48};
49
50enum {
51 MAC_DIRECTION_RX = 1,
52 MAC_DIRECTION_TX = 2
53};
54
55struct cmac_statistics {
56 /* Transmit */
57 u64 TxOctetsOK;
58 u64 TxOctetsBad;
59 u64 TxUnicastFramesOK;
60 u64 TxMulticastFramesOK;
61 u64 TxBroadcastFramesOK;
62 u64 TxPauseFrames;
63 u64 TxFramesWithDeferredXmissions;
64 u64 TxLateCollisions;
65 u64 TxTotalCollisions;
66 u64 TxFramesAbortedDueToXSCollisions;
67 u64 TxUnderrun;
68 u64 TxLengthErrors;
69 u64 TxInternalMACXmitError;
70 u64 TxFramesWithExcessiveDeferral;
71 u64 TxFCSErrors;
72 u64 TxJumboFramesOK;
73 u64 TxJumboOctetsOK;
74
75 /* Receive */
76 u64 RxOctetsOK;
77 u64 RxOctetsBad;
78 u64 RxUnicastFramesOK;
79 u64 RxMulticastFramesOK;
80 u64 RxBroadcastFramesOK;
81 u64 RxPauseFrames;
82 u64 RxFCSErrors;
83 u64 RxAlignErrors;
84 u64 RxSymbolErrors;
85 u64 RxDataErrors;
86 u64 RxSequenceErrors;
87 u64 RxRuntErrors;
88 u64 RxJabberErrors;
89 u64 RxInternalMACRcvError;
90 u64 RxInRangeLengthErrors;
91 u64 RxOutOfRangeLengthField;
92 u64 RxFrameTooLongErrors;
93 u64 RxJumboFramesOK;
94 u64 RxJumboOctetsOK;
95};
96
97struct cmac_ops {
98 void (*destroy)(struct cmac *);
99 int (*reset)(struct cmac *);
100 int (*interrupt_enable)(struct cmac *);
101 int (*interrupt_disable)(struct cmac *);
102 int (*interrupt_clear)(struct cmac *);
103 int (*interrupt_handler)(struct cmac *);
104
105 int (*enable)(struct cmac *, int);
106 int (*disable)(struct cmac *, int);
107
108 int (*loopback_enable)(struct cmac *);
109 int (*loopback_disable)(struct cmac *);
110
111 int (*set_mtu)(struct cmac *, int mtu);
112 int (*set_rx_mode)(struct cmac *, struct t1_rx_mode *rm);
113
114 int (*set_speed_duplex_fc)(struct cmac *, int speed, int duplex, int fc);
115 int (*get_speed_duplex_fc)(struct cmac *, int *speed, int *duplex,
116 int *fc);
117
118 const struct cmac_statistics *(*statistics_update)(struct cmac *, int);
119
120 int (*macaddress_get)(struct cmac *, u8 mac_addr[6]);
121 int (*macaddress_set)(struct cmac *, u8 mac_addr[6]);
122};
123
124typedef struct _cmac_instance cmac_instance;
125
126struct cmac {
127 struct cmac_statistics stats;
128 adapter_t *adapter;
129 const struct cmac_ops *ops;
130 cmac_instance *instance;
131};
132
133struct gmac {
134 unsigned int stats_update_period;
135 struct cmac *(*create)(adapter_t *adapter, int index);
136 int (*reset)(adapter_t *);
137};
138
139extern const struct gmac t1_pm3393_ops;
140extern const struct gmac t1_vsc7326_ops;
141
142#endif /* _CXGB_GMAC_H_ */
diff --git a/drivers/net/chelsio/mv88e1xxx.c b/drivers/net/chelsio/mv88e1xxx.c
deleted file mode 100644
index 71018a4fdf15..000000000000
--- a/drivers/net/chelsio/mv88e1xxx.c
+++ /dev/null
@@ -1,397 +0,0 @@
1/* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */
2#include "common.h"
3#include "mv88e1xxx.h"
4#include "cphy.h"
5#include "elmer0.h"
6
7/* MV88E1XXX MDI crossover register values */
8#define CROSSOVER_MDI 0
9#define CROSSOVER_MDIX 1
10#define CROSSOVER_AUTO 3
11
12#define INTR_ENABLE_MASK 0x6CA0
13
14/*
15 * Set the bits given by 'bitval' in PHY register 'reg'.
16 */
17static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
18{
19 u32 val;
20
21 (void) simple_mdio_read(cphy, reg, &val);
22 (void) simple_mdio_write(cphy, reg, val | bitval);
23}
24
25/*
26 * Clear the bits given by 'bitval' in PHY register 'reg'.
27 */
28static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
29{
30 u32 val;
31
32 (void) simple_mdio_read(cphy, reg, &val);
33 (void) simple_mdio_write(cphy, reg, val & ~bitval);
34}
35
36/*
37 * NAME: phy_reset
38 *
39 * DESC: Reset the given PHY's port. NOTE: This is not a global
40 * chip reset.
41 *
42 * PARAMS: cphy - Pointer to PHY instance data.
43 *
44 * RETURN: 0 - Successful reset.
45 * -1 - Timeout.
46 */
47static int mv88e1xxx_reset(struct cphy *cphy, int wait)
48{
49 u32 ctl;
50 int time_out = 1000;
51
52 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
53
54 do {
55 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
56 ctl &= BMCR_RESET;
57 if (ctl)
58 udelay(1);
59 } while (ctl && --time_out);
60
61 return ctl ? -1 : 0;
62}
63
64static int mv88e1xxx_interrupt_enable(struct cphy *cphy)
65{
66 /* Enable PHY interrupts. */
67 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,
68 INTR_ENABLE_MASK);
69
70 /* Enable Marvell interrupts through Elmer0. */
71 if (t1_is_asic(cphy->adapter)) {
72 u32 elmer;
73
74 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
75 elmer |= ELMER0_GP_BIT1;
76 if (is_T2(cphy->adapter))
77 elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4;
78 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
79 }
80 return 0;
81}
82
83static int mv88e1xxx_interrupt_disable(struct cphy *cphy)
84{
85 /* Disable all phy interrupts. */
86 (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);
87
88 /* Disable Marvell interrupts through Elmer0. */
89 if (t1_is_asic(cphy->adapter)) {
90 u32 elmer;
91
92 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
93 elmer &= ~ELMER0_GP_BIT1;
94 if (is_T2(cphy->adapter))
95 elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
96 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
97 }
98 return 0;
99}
100
101static int mv88e1xxx_interrupt_clear(struct cphy *cphy)
102{
103 u32 elmer;
104
105 /* Clear PHY interrupts by reading the register. */
106 (void) simple_mdio_read(cphy,
107 MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);
108
109 /* Clear Marvell interrupts through Elmer0. */
110 if (t1_is_asic(cphy->adapter)) {
111 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
112 elmer |= ELMER0_GP_BIT1;
113 if (is_T2(cphy->adapter))
114 elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
115 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
116 }
117 return 0;
118}
119
120/*
121 * Set the PHY speed and duplex. This also disables auto-negotiation, except
122 * for 1Gb/s, where auto-negotiation is mandatory.
123 */
124static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
125{
126 u32 ctl;
127
128 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
129 if (speed >= 0) {
130 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
131 if (speed == SPEED_100)
132 ctl |= BMCR_SPEED100;
133 else if (speed == SPEED_1000)
134 ctl |= BMCR_SPEED1000;
135 }
136 if (duplex >= 0) {
137 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
138 if (duplex == DUPLEX_FULL)
139 ctl |= BMCR_FULLDPLX;
140 }
141 if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */
142 ctl |= BMCR_ANENABLE;
143 (void) simple_mdio_write(phy, MII_BMCR, ctl);
144 return 0;
145}
146
147static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
148{
149 u32 data32;
150
151 (void) simple_mdio_read(cphy,
152 MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32);
153 data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE);
154 data32 |= V_PSCR_MDI_XOVER_MODE(crossover);
155 (void) simple_mdio_write(cphy,
156 MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32);
157 return 0;
158}
159
160static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
161{
162 u32 ctl;
163
164 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
165
166 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
167 /* restart autoneg for change to take effect */
168 ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
169 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
170 return 0;
171}
172
173static int mv88e1xxx_autoneg_disable(struct cphy *cphy)
174{
175 u32 ctl;
176
177 /*
178 * Crossover *must* be set to manual in order to disable auto-neg.
179 * The Alaska FAQs document highlights this point.
180 */
181 (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI);
182
183 /*
184 * Must include autoneg reset when disabling auto-neg. This
185 * is described in the Alaska FAQ document.
186 */
187 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
188 ctl &= ~BMCR_ANENABLE;
189 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
190 return 0;
191}
192
193static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
194{
195 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
196 return 0;
197}
198
199static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map)
200{
201 u32 val = 0;
202
203 if (advertise_map &
204 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
205 (void) simple_mdio_read(phy, MII_GBCR, &val);
206 val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL);
207 if (advertise_map & ADVERTISED_1000baseT_Half)
208 val |= GBCR_ADV_1000HALF;
209 if (advertise_map & ADVERTISED_1000baseT_Full)
210 val |= GBCR_ADV_1000FULL;
211 }
212 (void) simple_mdio_write(phy, MII_GBCR, val);
213
214 val = 1;
215 if (advertise_map & ADVERTISED_10baseT_Half)
216 val |= ADVERTISE_10HALF;
217 if (advertise_map & ADVERTISED_10baseT_Full)
218 val |= ADVERTISE_10FULL;
219 if (advertise_map & ADVERTISED_100baseT_Half)
220 val |= ADVERTISE_100HALF;
221 if (advertise_map & ADVERTISED_100baseT_Full)
222 val |= ADVERTISE_100FULL;
223 if (advertise_map & ADVERTISED_PAUSE)
224 val |= ADVERTISE_PAUSE;
225 if (advertise_map & ADVERTISED_ASYM_PAUSE)
226 val |= ADVERTISE_PAUSE_ASYM;
227 (void) simple_mdio_write(phy, MII_ADVERTISE, val);
228 return 0;
229}
230
231static int mv88e1xxx_set_loopback(struct cphy *cphy, int on)
232{
233 if (on)
234 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
235 else
236 mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
237 return 0;
238}
239
240static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
241 int *speed, int *duplex, int *fc)
242{
243 u32 status;
244 int sp = -1, dplx = -1, pause = 0;
245
246 (void) simple_mdio_read(cphy,
247 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
248 if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
249 if (status & V_PSSR_RX_PAUSE)
250 pause |= PAUSE_RX;
251 if (status & V_PSSR_TX_PAUSE)
252 pause |= PAUSE_TX;
253 dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
254 sp = G_PSSR_SPEED(status);
255 if (sp == 0)
256 sp = SPEED_10;
257 else if (sp == 1)
258 sp = SPEED_100;
259 else
260 sp = SPEED_1000;
261 }
262 if (link_ok)
263 *link_ok = (status & V_PSSR_LINK) != 0;
264 if (speed)
265 *speed = sp;
266 if (duplex)
267 *duplex = dplx;
268 if (fc)
269 *fc = pause;
270 return 0;
271}
272
273static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
274{
275 u32 val;
276
277 (void) simple_mdio_read(cphy,
278 MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val);
279
280 /*
281 * Set the downshift counter to 2 so we try to establish Gb link
282 * twice before downshifting.
283 */
284 val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT));
285
286 if (downshift_enable)
287 val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2);
288 (void) simple_mdio_write(cphy,
289 MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val);
290 return 0;
291}
292
293static int mv88e1xxx_interrupt_handler(struct cphy *cphy)
294{
295 int cphy_cause = 0;
296 u32 status;
297
298 /*
299 * Loop until cause reads zero. Need to handle bouncing interrupts.
300 */
301 while (1) {
302 u32 cause;
303
304 (void) simple_mdio_read(cphy,
305 MV88E1XXX_INTERRUPT_STATUS_REGISTER,
306 &cause);
307 cause &= INTR_ENABLE_MASK;
308 if (!cause)
309 break;
310
311 if (cause & MV88E1XXX_INTR_LINK_CHNG) {
312 (void) simple_mdio_read(cphy,
313 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
314
315 if (status & MV88E1XXX_INTR_LINK_CHNG)
316 cphy->state |= PHY_LINK_UP;
317 else {
318 cphy->state &= ~PHY_LINK_UP;
319 if (cphy->state & PHY_AUTONEG_EN)
320 cphy->state &= ~PHY_AUTONEG_RDY;
321 cphy_cause |= cphy_cause_link_change;
322 }
323 }
324
325 if (cause & MV88E1XXX_INTR_AUTONEG_DONE)
326 cphy->state |= PHY_AUTONEG_RDY;
327
328 if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) ==
329 (PHY_LINK_UP | PHY_AUTONEG_RDY))
330 cphy_cause |= cphy_cause_link_change;
331 }
332 return cphy_cause;
333}
334
335static void mv88e1xxx_destroy(struct cphy *cphy)
336{
337 kfree(cphy);
338}
339
340static struct cphy_ops mv88e1xxx_ops = {
341 .destroy = mv88e1xxx_destroy,
342 .reset = mv88e1xxx_reset,
343 .interrupt_enable = mv88e1xxx_interrupt_enable,
344 .interrupt_disable = mv88e1xxx_interrupt_disable,
345 .interrupt_clear = mv88e1xxx_interrupt_clear,
346 .interrupt_handler = mv88e1xxx_interrupt_handler,
347 .autoneg_enable = mv88e1xxx_autoneg_enable,
348 .autoneg_disable = mv88e1xxx_autoneg_disable,
349 .autoneg_restart = mv88e1xxx_autoneg_restart,
350 .advertise = mv88e1xxx_advertise,
351 .set_loopback = mv88e1xxx_set_loopback,
352 .set_speed_duplex = mv88e1xxx_set_speed_duplex,
353 .get_link_status = mv88e1xxx_get_link_status,
354};
355
356static struct cphy *mv88e1xxx_phy_create(struct net_device *dev, int phy_addr,
357 const struct mdio_ops *mdio_ops)
358{
359 struct adapter *adapter = netdev_priv(dev);
360 struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
361
362 if (!cphy)
363 return NULL;
364
365 cphy_init(cphy, dev, phy_addr, &mv88e1xxx_ops, mdio_ops);
366
367 /* Configure particular PHY's to run in a different mode. */
368 if ((board_info(adapter)->caps & SUPPORTED_TP) &&
369 board_info(adapter)->chip_phy == CHBT_PHY_88E1111) {
370 /*
371 * Configure the PHY transmitter as class A to reduce EMI.
372 */
373 (void) simple_mdio_write(cphy,
374 MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB);
375 (void) simple_mdio_write(cphy,
376 MV88E1XXX_EXTENDED_REGISTER, 0x8004);
377 }
378 (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */
379
380 /* LED */
381 if (is_T2(adapter)) {
382 (void) simple_mdio_write(cphy,
383 MV88E1XXX_LED_CONTROL_REGISTER, 0x1);
384 }
385
386 return cphy;
387}
388
389static int mv88e1xxx_phy_reset(adapter_t* adapter)
390{
391 return 0;
392}
393
394const struct gphy t1_mv88e1xxx_ops = {
395 .create = mv88e1xxx_phy_create,
396 .reset = mv88e1xxx_phy_reset
397};
diff --git a/drivers/net/chelsio/mv88e1xxx.h b/drivers/net/chelsio/mv88e1xxx.h
deleted file mode 100644
index 967cc4286359..000000000000
--- a/drivers/net/chelsio/mv88e1xxx.h
+++ /dev/null
@@ -1,127 +0,0 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
2#ifndef CHELSIO_MV8E1XXX_H
3#define CHELSIO_MV8E1XXX_H
4
5#ifndef BMCR_SPEED1000
6# define BMCR_SPEED1000 0x40
7#endif
8
9#ifndef ADVERTISE_PAUSE
10# define ADVERTISE_PAUSE 0x400
11#endif
12#ifndef ADVERTISE_PAUSE_ASYM
13# define ADVERTISE_PAUSE_ASYM 0x800
14#endif
15
16/* Gigabit MII registers */
17#define MII_GBCR 9 /* 1000Base-T control register */
18#define MII_GBSR 10 /* 1000Base-T status register */
19
20/* 1000Base-T control register fields */
21#define GBCR_ADV_1000HALF 0x100
22#define GBCR_ADV_1000FULL 0x200
23#define GBCR_PREFER_MASTER 0x400
24#define GBCR_MANUAL_AS_MASTER 0x800
25#define GBCR_MANUAL_CONFIG_ENABLE 0x1000
26
27/* 1000Base-T status register fields */
28#define GBSR_LP_1000HALF 0x400
29#define GBSR_LP_1000FULL 0x800
30#define GBSR_REMOTE_OK 0x1000
31#define GBSR_LOCAL_OK 0x2000
32#define GBSR_LOCAL_MASTER 0x4000
33#define GBSR_MASTER_FAULT 0x8000
34
35/* Marvell PHY interrupt status bits. */
36#define MV88E1XXX_INTR_JABBER 0x0001
37#define MV88E1XXX_INTR_POLARITY_CHNG 0x0002
38#define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
39#define MV88E1XXX_INTR_DOWNSHIFT 0x0020
40#define MV88E1XXX_INTR_MDI_XOVER_CHNG 0x0040
41#define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
42#define MV88E1XXX_INTR_FALSE_CARRIER 0x0100
43#define MV88E1XXX_INTR_SYMBOL_ERROR 0x0200
44#define MV88E1XXX_INTR_LINK_CHNG 0x0400
45#define MV88E1XXX_INTR_AUTONEG_DONE 0x0800
46#define MV88E1XXX_INTR_PAGE_RECV 0x1000
47#define MV88E1XXX_INTR_DUPLEX_CHNG 0x2000
48#define MV88E1XXX_INTR_SPEED_CHNG 0x4000
49#define MV88E1XXX_INTR_AUTONEG_ERR 0x8000
50
51/* Marvell PHY specific registers. */
52#define MV88E1XXX_SPECIFIC_CNTRL_REGISTER 16
53#define MV88E1XXX_SPECIFIC_STATUS_REGISTER 17
54#define MV88E1XXX_INTERRUPT_ENABLE_REGISTER 18
55#define MV88E1XXX_INTERRUPT_STATUS_REGISTER 19
56#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER 20
57#define MV88E1XXX_RECV_ERR_CNTR_REGISTER 21
58#define MV88E1XXX_RES_REGISTER 22
59#define MV88E1XXX_GLOBAL_STATUS_REGISTER 23
60#define MV88E1XXX_LED_CONTROL_REGISTER 24
61#define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER 25
62#define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER 26
63#define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER 27
64#define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER 28
65#define MV88E1XXX_EXTENDED_ADDR_REGISTER 29
66#define MV88E1XXX_EXTENDED_REGISTER 30
67
68/* PHY specific control register fields */
69#define S_PSCR_MDI_XOVER_MODE 5
70#define M_PSCR_MDI_XOVER_MODE 0x3
71#define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
72#define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
73
74/* Extended PHY specific control register fields */
75#define S_DOWNSHIFT_ENABLE 8
76#define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
77
78#define S_DOWNSHIFT_CNT 9
79#define M_DOWNSHIFT_CNT 0x7
80#define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
81#define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
82
83/* PHY specific status register fields */
84#define S_PSSR_JABBER 0
85#define V_PSSR_JABBER (1 << S_PSSR_JABBER)
86
87#define S_PSSR_POLARITY 1
88#define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
89
90#define S_PSSR_RX_PAUSE 2
91#define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
92
93#define S_PSSR_TX_PAUSE 3
94#define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
95
96#define S_PSSR_ENERGY_DETECT 4
97#define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
98
99#define S_PSSR_DOWNSHIFT_STATUS 5
100#define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
101
102#define S_PSSR_MDI 6
103#define V_PSSR_MDI (1 << S_PSSR_MDI)
104
105#define S_PSSR_CABLE_LEN 7
106#define M_PSSR_CABLE_LEN 0x7
107#define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
108#define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
109
110#define S_PSSR_LINK 10
111#define V_PSSR_LINK (1 << S_PSSR_LINK)
112
113#define S_PSSR_STATUS_RESOLVED 11
114#define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
115
116#define S_PSSR_PAGE_RECEIVED 12
117#define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
118
119#define S_PSSR_DUPLEX 13
120#define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
121
122#define S_PSSR_SPEED 14
123#define M_PSSR_SPEED 0x3
124#define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
125#define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
126
127#endif
diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c
deleted file mode 100644
index f7136b2fd1e5..000000000000
--- a/drivers/net/chelsio/mv88x201x.c
+++ /dev/null
@@ -1,260 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: mv88x201x.c *
4 * $Revision: 1.12 $ *
5 * $Date: 2005/04/15 19:27:14 $ *
6 * Description: *
7 * Marvell PHY (mv88x201x) functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "cphy.h"
41#include "elmer0.h"
42
43/*
44 * The 88x2010 Rev C. requires some link status registers * to be read
45 * twice in order to get the right values. Future * revisions will fix
46 * this problem and then this macro * can disappear.
47 */
48#define MV88x2010_LINK_STATUS_BUGS 1
49
50static int led_init(struct cphy *cphy)
51{
52 /* Setup the LED registers so we can turn on/off.
53 * Writing these bits maps control to another
54 * register. mmd(0x1) addr(0x7)
55 */
56 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8304, 0xdddd);
57 return 0;
58}
59
60static int led_link(struct cphy *cphy, u32 do_enable)
61{
62 u32 led = 0;
63#define LINK_ENABLE_BIT 0x1
64
65 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, &led);
66
67 if (do_enable & LINK_ENABLE_BIT) {
68 led |= LINK_ENABLE_BIT;
69 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
70 } else {
71 led &= ~LINK_ENABLE_BIT;
72 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_CTRL2, led);
73 }
74 return 0;
75}
76
77/* Port Reset */
78static int mv88x201x_reset(struct cphy *cphy, int wait)
79{
80 /* This can be done through registers. It is not required since
81 * a full chip reset is used.
82 */
83 return 0;
84}
85
86static int mv88x201x_interrupt_enable(struct cphy *cphy)
87{
88 /* Enable PHY LASI interrupts. */
89 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
90 MDIO_PMA_LASI_LSALARM);
91
92 /* Enable Marvell interrupts through Elmer0. */
93 if (t1_is_asic(cphy->adapter)) {
94 u32 elmer;
95
96 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
97 elmer |= ELMER0_GP_BIT6;
98 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
99 }
100 return 0;
101}
102
103static int mv88x201x_interrupt_disable(struct cphy *cphy)
104{
105 /* Disable PHY LASI interrupts. */
106 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);
107
108 /* Disable Marvell interrupts through Elmer0. */
109 if (t1_is_asic(cphy->adapter)) {
110 u32 elmer;
111
112 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
113 elmer &= ~ELMER0_GP_BIT6;
114 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
115 }
116 return 0;
117}
118
119static int mv88x201x_interrupt_clear(struct cphy *cphy)
120{
121 u32 elmer;
122 u32 val;
123
124#ifdef MV88x2010_LINK_STATUS_BUGS
125 /* Required to read twice before clear takes affect. */
126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
128 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
129
130 /* Read this register after the others above it else
131 * the register doesn't clear correctly.
132 */
133 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
134#endif
135
136 /* Clear link status. */
137 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
138 /* Clear PHY LASI interrupts. */
139 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
140
141#ifdef MV88x2010_LINK_STATUS_BUGS
142 /* Do it again. */
143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
144 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
145#endif
146
147 /* Clear Marvell interrupts through Elmer0. */
148 if (t1_is_asic(cphy->adapter)) {
149 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
150 elmer |= ELMER0_GP_BIT6;
151 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
152 }
153 return 0;
154}
155
156static int mv88x201x_interrupt_handler(struct cphy *cphy)
157{
158 /* Clear interrupts */
159 mv88x201x_interrupt_clear(cphy);
160
161 /* We have only enabled link change interrupts and so
162 * cphy_cause must be a link change interrupt.
163 */
164 return cphy_cause_link_change;
165}
166
167static int mv88x201x_set_loopback(struct cphy *cphy, int on)
168{
169 return 0;
170}
171
172static int mv88x201x_get_link_status(struct cphy *cphy, int *link_ok,
173 int *speed, int *duplex, int *fc)
174{
175 u32 val = 0;
176
177 if (link_ok) {
178 /* Read link status. */
179 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
180 val &= MDIO_STAT1_LSTATUS;
181 *link_ok = (val == MDIO_STAT1_LSTATUS);
182 /* Turn on/off Link LED */
183 led_link(cphy, *link_ok);
184 }
185 if (speed)
186 *speed = SPEED_10000;
187 if (duplex)
188 *duplex = DUPLEX_FULL;
189 if (fc)
190 *fc = PAUSE_RX | PAUSE_TX;
191 return 0;
192}
193
194static void mv88x201x_destroy(struct cphy *cphy)
195{
196 kfree(cphy);
197}
198
199static struct cphy_ops mv88x201x_ops = {
200 .destroy = mv88x201x_destroy,
201 .reset = mv88x201x_reset,
202 .interrupt_enable = mv88x201x_interrupt_enable,
203 .interrupt_disable = mv88x201x_interrupt_disable,
204 .interrupt_clear = mv88x201x_interrupt_clear,
205 .interrupt_handler = mv88x201x_interrupt_handler,
206 .get_link_status = mv88x201x_get_link_status,
207 .set_loopback = mv88x201x_set_loopback,
208 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
209 MDIO_DEVS_PHYXS | MDIO_DEVS_WIS),
210};
211
212static struct cphy *mv88x201x_phy_create(struct net_device *dev, int phy_addr,
213 const struct mdio_ops *mdio_ops)
214{
215 u32 val;
216 struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
217
218 if (!cphy)
219 return NULL;
220
221 cphy_init(cphy, dev, phy_addr, &mv88x201x_ops, mdio_ops);
222
223 /* Commands the PHY to enable XFP's clock. */
224 cphy_mdio_read(cphy, MDIO_MMD_PCS, 0x8300, &val);
225 cphy_mdio_write(cphy, MDIO_MMD_PCS, 0x8300, val | 1);
226
227 /* Clear link status. Required because of a bug in the PHY. */
228 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT2, &val);
229 cphy_mdio_read(cphy, MDIO_MMD_PCS, MDIO_STAT2, &val);
230
231 /* Allows for Link,Ack LED turn on/off */
232 led_init(cphy);
233 return cphy;
234}
235
236/* Chip Reset */
237static int mv88x201x_phy_reset(adapter_t *adapter)
238{
239 u32 val;
240
241 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
242 val &= ~4;
243 t1_tpi_write(adapter, A_ELMER0_GPO, val);
244 msleep(100);
245
246 t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
247 msleep(1000);
248
249 /* Now lets enable the Laser. Delay 100us */
250 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
251 val |= 0x8000;
252 t1_tpi_write(adapter, A_ELMER0_GPO, val);
253 udelay(100);
254 return 0;
255}
256
257const struct gphy t1_mv88x201x_ops = {
258 .create = mv88x201x_phy_create,
259 .reset = mv88x201x_phy_reset
260};
diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c
deleted file mode 100644
index a683fd3bb624..000000000000
--- a/drivers/net/chelsio/my3126.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/* $Date: 2005/11/12 02:13:49 $ $RCSfile: my3126.c,v $ $Revision: 1.15 $ */
2#include "cphy.h"
3#include "elmer0.h"
4#include "suni1x10gexp_regs.h"
5
6/* Port Reset */
7static int my3126_reset(struct cphy *cphy, int wait)
8{
9 /*
10 * This can be done through registers. It is not required since
11 * a full chip reset is used.
12 */
13 return 0;
14}
15
16static int my3126_interrupt_enable(struct cphy *cphy)
17{
18 schedule_delayed_work(&cphy->phy_update, HZ/30);
19 t1_tpi_read(cphy->adapter, A_ELMER0_GPO, &cphy->elmer_gpo);
20 return 0;
21}
22
23static int my3126_interrupt_disable(struct cphy *cphy)
24{
25 cancel_delayed_work_sync(&cphy->phy_update);
26 return 0;
27}
28
29static int my3126_interrupt_clear(struct cphy *cphy)
30{
31 return 0;
32}
33
34#define OFFSET(REG_ADDR) (REG_ADDR << 2)
35
36static int my3126_interrupt_handler(struct cphy *cphy)
37{
38 u32 val;
39 u16 val16;
40 u16 status;
41 u32 act_count;
42 adapter_t *adapter;
43 adapter = cphy->adapter;
44
45 if (cphy->count == 50) {
46 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
47 val16 = (u16) val;
48 status = cphy->bmsr ^ val16;
49
50 if (status & MDIO_STAT1_LSTATUS)
51 t1_link_changed(adapter, 0);
52 cphy->bmsr = val16;
53
54 /* We have only enabled link change interrupts so it
55 must be that
56 */
57 cphy->count = 0;
58 }
59
60 t1_tpi_write(adapter, OFFSET(SUNI1x10GEXP_REG_MSTAT_CONTROL),
61 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
62 t1_tpi_read(adapter,
63 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW), &act_count);
64 t1_tpi_read(adapter,
65 OFFSET(SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW), &val);
66 act_count += val;
67
68 /* Populate elmer_gpo with the register value */
69 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
70 cphy->elmer_gpo = val;
71
72 if ( (val & (1 << 8)) || (val & (1 << 19)) ||
73 (cphy->act_count == act_count) || cphy->act_on ) {
74 if (is_T2(adapter))
75 val |= (1 << 9);
76 else if (t1_is_T1B(adapter))
77 val |= (1 << 20);
78 cphy->act_on = 0;
79 } else {
80 if (is_T2(adapter))
81 val &= ~(1 << 9);
82 else if (t1_is_T1B(adapter))
83 val &= ~(1 << 20);
84 cphy->act_on = 1;
85 }
86
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
88
89 cphy->elmer_gpo = val;
90 cphy->act_count = act_count;
91 cphy->count++;
92
93 return cphy_cause_link_change;
94}
95
96static void my3216_poll(struct work_struct *work)
97{
98 struct cphy *cphy = container_of(work, struct cphy, phy_update.work);
99
100 my3126_interrupt_handler(cphy);
101}
102
103static int my3126_set_loopback(struct cphy *cphy, int on)
104{
105 return 0;
106}
107
108/* To check the activity LED */
109static int my3126_get_link_status(struct cphy *cphy,
110 int *link_ok, int *speed, int *duplex, int *fc)
111{
112 u32 val;
113 u16 val16;
114 adapter_t *adapter;
115
116 adapter = cphy->adapter;
117 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
118 val16 = (u16) val;
119
120 /* Populate elmer_gpo with the register value */
121 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
122 cphy->elmer_gpo = val;
123
124 *link_ok = (val16 & MDIO_STAT1_LSTATUS);
125
126 if (*link_ok) {
127 /* Turn on the LED. */
128 if (is_T2(adapter))
129 val &= ~(1 << 8);
130 else if (t1_is_T1B(adapter))
131 val &= ~(1 << 19);
132 } else {
133 /* Turn off the LED. */
134 if (is_T2(adapter))
135 val |= (1 << 8);
136 else if (t1_is_T1B(adapter))
137 val |= (1 << 19);
138 }
139
140 t1_tpi_write(adapter, A_ELMER0_GPO, val);
141 cphy->elmer_gpo = val;
142 *speed = SPEED_10000;
143 *duplex = DUPLEX_FULL;
144
145 /* need to add flow control */
146 if (fc)
147 *fc = PAUSE_RX | PAUSE_TX;
148
149 return 0;
150}
151
152static void my3126_destroy(struct cphy *cphy)
153{
154 kfree(cphy);
155}
156
157static struct cphy_ops my3126_ops = {
158 .destroy = my3126_destroy,
159 .reset = my3126_reset,
160 .interrupt_enable = my3126_interrupt_enable,
161 .interrupt_disable = my3126_interrupt_disable,
162 .interrupt_clear = my3126_interrupt_clear,
163 .interrupt_handler = my3126_interrupt_handler,
164 .get_link_status = my3126_get_link_status,
165 .set_loopback = my3126_set_loopback,
166 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
167 MDIO_DEVS_PHYXS),
168};
169
170static struct cphy *my3126_phy_create(struct net_device *dev,
171 int phy_addr, const struct mdio_ops *mdio_ops)
172{
173 struct cphy *cphy = kzalloc(sizeof (*cphy), GFP_KERNEL);
174
175 if (!cphy)
176 return NULL;
177
178 cphy_init(cphy, dev, phy_addr, &my3126_ops, mdio_ops);
179 INIT_DELAYED_WORK(&cphy->phy_update, my3216_poll);
180 cphy->bmsr = 0;
181
182 return cphy;
183}
184
185/* Chip Reset */
186static int my3126_phy_reset(adapter_t * adapter)
187{
188 u32 val;
189
190 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
191 val &= ~4;
192 t1_tpi_write(adapter, A_ELMER0_GPO, val);
193 msleep(100);
194
195 t1_tpi_write(adapter, A_ELMER0_GPO, val | 4);
196 msleep(1000);
197
198 /* Now lets enable the Laser. Delay 100us */
199 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
200 val |= 0x8000;
201 t1_tpi_write(adapter, A_ELMER0_GPO, val);
202 udelay(100);
203 return 0;
204}
205
206const struct gphy t1_my3126_ops = {
207 .create = my3126_phy_create,
208 .reset = my3126_phy_reset
209};
diff --git a/drivers/net/chelsio/pm3393.c b/drivers/net/chelsio/pm3393.c
deleted file mode 100644
index 40c7b93ababc..000000000000
--- a/drivers/net/chelsio/pm3393.c
+++ /dev/null
@@ -1,796 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: pm3393.c *
4 * $Revision: 1.16 $ *
5 * $Date: 2005/05/14 00:59:32 $ *
6 * Description: *
7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41#include "regs.h"
42#include "gmac.h"
43#include "elmer0.h"
44#include "suni1x10gexp_regs.h"
45
46#include <linux/crc32.h>
47#include <linux/slab.h>
48
49#define OFFSET(REG_ADDR) ((REG_ADDR) << 2)
50
51/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
52#define MAX_FRAME_SIZE 9600
53
54#define IPG 12
55#define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
56 SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
57 SUNI1x10GEXP_BITMSK_TXXG_PADEN)
58#define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
59 SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
60
61/* Update statistics every 15 minutes */
62#define STATS_TICK_SECS (15 * 60)
63
64enum { /* RMON registers */
65 RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
66 RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
67 RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
68 RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
69 RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
70 RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
71 RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
72 RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
73 RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
74 RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
75 RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
76 RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
77 RxUndersizedFrames = SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
78 RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
79 RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
80
81 TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
82 TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
83 TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
84 TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
85 TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
86 TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
87 TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
88 TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
89 TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
90};
91
92struct _cmac_instance {
93 u8 enabled;
94 u8 fc;
95 u8 mac_addr[6];
96};
97
98static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
99{
100 t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
101 return 0;
102}
103
104static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
105{
106 t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
107 return 0;
108}
109
110/* Port reset. */
111static int pm3393_reset(struct cmac *cmac)
112{
113 return 0;
114}
115
116/*
117 * Enable interrupts for the PM3393
118 *
119 * 1. Enable PM3393 BLOCK interrupts.
120 * 2. Enable PM3393 Master Interrupt bit(INTE)
121 * 3. Enable ELMER's PM3393 bit.
122 * 4. Enable Terminator external interrupt.
123 */
124static int pm3393_interrupt_enable(struct cmac *cmac)
125{
126 u32 pl_intr;
127
128 /* PM3393 - Enabling all hardware block interrupts.
129 */
130 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
131 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
132 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
133 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
134
135 /* Don't interrupt on statistics overflow, we are polling */
136 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
137 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
138 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
139 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
140
141 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
142 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
143 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
144 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
145 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
146 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
147 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
148 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
149 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
150
151 /* PM3393 - Global interrupt enable
152 */
153 /* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
154 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
155 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
156
157 /* TERMINATOR - PL_INTERUPTS_EXT */
158 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
159 pl_intr |= F_PL_INTR_EXT;
160 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
161 return 0;
162}
163
164static int pm3393_interrupt_disable(struct cmac *cmac)
165{
166 u32 elmer;
167
168 /* PM3393 - Enabling HW interrupt blocks. */
169 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
170 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
171 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
172 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
173 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
174 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
175 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
176 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
177 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
178 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
179 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
180 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
181 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
182 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
183 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
184 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
185 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
186
187 /* PM3393 - Global interrupt enable */
188 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
189
190 /* ELMER - External chip interrupts. */
191 t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
192 elmer &= ~ELMER0_GP_BIT1;
193 t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
194
195 /* TERMINATOR - PL_INTERUPTS_EXT */
196 /* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
197 * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
198 */
199
200 return 0;
201}
202
203static int pm3393_interrupt_clear(struct cmac *cmac)
204{
205 u32 elmer;
206 u32 pl_intr;
207 u32 val32;
208
209 /* PM3393 - Clearing HW interrupt blocks. Note, this assumes
210 * bit WCIMODE=0 for a clear-on-read.
211 */
212 pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
213 pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
214 pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
215 pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
216 pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
217 pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
218 pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
219 pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
220 pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
221 pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
222 pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
223 pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
224 &val32);
225 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
226 pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
227
228 /* PM3393 - Global interrupt status
229 */
230 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
231
232 /* ELMER - External chip interrupts.
233 */
234 t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
235 elmer |= ELMER0_GP_BIT1;
236 t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
237
238 /* TERMINATOR - PL_INTERUPTS_EXT
239 */
240 pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
241 pl_intr |= F_PL_INTR_EXT;
242 writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
243
244 return 0;
245}
246
247/* Interrupt handler */
248static int pm3393_interrupt_handler(struct cmac *cmac)
249{
250 u32 master_intr_status;
251
252 /* Read the master interrupt status register. */
253 pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
254 &master_intr_status);
255 if (netif_msg_intr(cmac->adapter))
256 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
257 master_intr_status);
258
259 /* TBD XXX Lets just clear everything for now */
260 pm3393_interrupt_clear(cmac);
261
262 return 0;
263}
264
265static int pm3393_enable(struct cmac *cmac, int which)
266{
267 if (which & MAC_DIRECTION_RX)
268 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
269 (RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
270
271 if (which & MAC_DIRECTION_TX) {
272 u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
273
274 if (cmac->instance->fc & PAUSE_RX)
275 val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
276 if (cmac->instance->fc & PAUSE_TX)
277 val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
278 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
279 }
280
281 cmac->instance->enabled |= which;
282 return 0;
283}
284
285static int pm3393_enable_port(struct cmac *cmac, int which)
286{
287 /* Clear port statistics */
288 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
289 SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
290 udelay(2);
291 memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
292
293 pm3393_enable(cmac, which);
294
295 /*
296 * XXX This should be done by the PHY and preferably not at all.
297 * The PHY doesn't give us link status indication on its own so have
298 * the link management code query it instead.
299 */
300 t1_link_changed(cmac->adapter, 0);
301 return 0;
302}
303
304static int pm3393_disable(struct cmac *cmac, int which)
305{
306 if (which & MAC_DIRECTION_RX)
307 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
308 if (which & MAC_DIRECTION_TX)
309 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
310
311 /*
312 * The disable is graceful. Give the PM3393 time. Can't wait very
313 * long here, we may be holding locks.
314 */
315 udelay(20);
316
317 cmac->instance->enabled &= ~which;
318 return 0;
319}
320
321static int pm3393_loopback_enable(struct cmac *cmac)
322{
323 return 0;
324}
325
326static int pm3393_loopback_disable(struct cmac *cmac)
327{
328 return 0;
329}
330
331static int pm3393_set_mtu(struct cmac *cmac, int mtu)
332{
333 int enabled = cmac->instance->enabled;
334
335 /* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */
336 mtu += 14 + 4;
337 if (mtu > MAX_FRAME_SIZE)
338 return -EINVAL;
339
340 /* Disable Rx/Tx MAC before configuring it. */
341 if (enabled)
342 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
343
344 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
345 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
346
347 if (enabled)
348 pm3393_enable(cmac, enabled);
349 return 0;
350}
351
352static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
353{
354 int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
355 u32 rx_mode;
356
357 /* Disable MAC RX before reconfiguring it */
358 if (enabled)
359 pm3393_disable(cmac, MAC_DIRECTION_RX);
360
361 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
362 rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
363 SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
364 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
365 (u16)rx_mode);
366
367 if (t1_rx_mode_promisc(rm)) {
368 /* Promiscuous mode. */
369 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
370 }
371 if (t1_rx_mode_allmulti(rm)) {
372 /* Accept all multicast. */
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
374 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
375 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
376 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
377 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
378 } else if (t1_rx_mode_mc_cnt(rm)) {
379 /* Accept one or more multicast(s). */
380 struct netdev_hw_addr *ha;
381 int bit;
382 u16 mc_filter[4] = { 0, };
383
384 netdev_for_each_mc_addr(ha, t1_get_netdev(rm)) {
385 /* bit[23:28] */
386 bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f;
387 mc_filter[bit >> 4] |= 1 << (bit & 0xf);
388 }
389 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
390 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
391 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
392 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
393 rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
394 }
395
396 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
397
398 if (enabled)
399 pm3393_enable(cmac, MAC_DIRECTION_RX);
400
401 return 0;
402}
403
404static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
405 int *duplex, int *fc)
406{
407 if (speed)
408 *speed = SPEED_10000;
409 if (duplex)
410 *duplex = DUPLEX_FULL;
411 if (fc)
412 *fc = cmac->instance->fc;
413 return 0;
414}
415
416static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
417 int fc)
418{
419 if (speed >= 0 && speed != SPEED_10000)
420 return -1;
421 if (duplex >= 0 && duplex != DUPLEX_FULL)
422 return -1;
423 if (fc & ~(PAUSE_TX | PAUSE_RX))
424 return -1;
425
426 if (fc != cmac->instance->fc) {
427 cmac->instance->fc = (u8) fc;
428 if (cmac->instance->enabled & MAC_DIRECTION_TX)
429 pm3393_enable(cmac, MAC_DIRECTION_TX);
430 }
431 return 0;
432}
433
434#define RMON_UPDATE(mac, name, stat_name) \
435{ \
436 t1_tpi_read((mac)->adapter, OFFSET(name), &val0); \
437 t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
438 t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
439 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
440 ((u64)(val1 & 0xffff) << 16) | \
441 ((u64)(val2 & 0xff) << 32) | \
442 ((mac)->stats.stat_name & \
443 0xffffff0000000000ULL); \
444 if (ro & \
445 (1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \
446 (mac)->stats.stat_name += 1ULL << 40; \
447}
448
449static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
450 int flag)
451{
452 u64 ro;
453 u32 val0, val1, val2, val3;
454
455 /* Snap the counters */
456 pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
457 SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
458
459 /* Counter rollover, clear on read */
460 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
461 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
462 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
463 pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
464 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
465 (((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
466
467 /* Rx stats */
468 RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
469 RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
470 RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
471 RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
472 RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
473 RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
474 RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
475 RxInternalMACRcvError);
476 RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
477 RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
478 RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
479 RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
480 RMON_UPDATE(mac, RxFragments, RxRuntErrors);
481 RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
482 RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
483 RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
484
485 /* Tx stats */
486 RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
487 RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
488 TxInternalMACXmitError);
489 RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
490 RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
491 RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
492 RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
493 RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
494 RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
495 RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
496
497 return &mac->stats;
498}
499
500static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
501{
502 memcpy(mac_addr, cmac->instance->mac_addr, 6);
503 return 0;
504}
505
506static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
507{
508 u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
509
510 /*
511 * MAC addr: 00:07:43:00:13:09
512 *
513 * ma[5] = 0x09
514 * ma[4] = 0x13
515 * ma[3] = 0x00
516 * ma[2] = 0x43
517 * ma[1] = 0x07
518 * ma[0] = 0x00
519 *
520 * The PM3393 requires byte swapping and reverse order entry
521 * when programming MAC addresses:
522 *
523 * low_bits[15:0] = ma[1]:ma[0]
524 * mid_bits[31:16] = ma[3]:ma[2]
525 * high_bits[47:32] = ma[5]:ma[4]
526 */
527
528 /* Store local copy */
529 memcpy(cmac->instance->mac_addr, ma, 6);
530
531 lo = ((u32) ma[1] << 8) | (u32) ma[0];
532 mid = ((u32) ma[3] << 8) | (u32) ma[2];
533 hi = ((u32) ma[5] << 8) | (u32) ma[4];
534
535 /* Disable Rx/Tx MAC before configuring it. */
536 if (enabled)
537 pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
538
539 /* Set RXXG Station Address */
540 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
541 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
542 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
543
544 /* Set TXXG Station Address */
545 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
546 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
547 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
548
549 /* Setup Exact Match Filter 1 with our MAC address
550 *
551 * Must disable exact match filter before configuring it.
552 */
553 pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
554 val &= 0xff0f;
555 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
556
557 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
558 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
559 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
560
561 val |= 0x0090;
562 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
563
564 if (enabled)
565 pm3393_enable(cmac, enabled);
566 return 0;
567}
568
569static void pm3393_destroy(struct cmac *cmac)
570{
571 kfree(cmac);
572}
573
574static struct cmac_ops pm3393_ops = {
575 .destroy = pm3393_destroy,
576 .reset = pm3393_reset,
577 .interrupt_enable = pm3393_interrupt_enable,
578 .interrupt_disable = pm3393_interrupt_disable,
579 .interrupt_clear = pm3393_interrupt_clear,
580 .interrupt_handler = pm3393_interrupt_handler,
581 .enable = pm3393_enable_port,
582 .disable = pm3393_disable,
583 .loopback_enable = pm3393_loopback_enable,
584 .loopback_disable = pm3393_loopback_disable,
585 .set_mtu = pm3393_set_mtu,
586 .set_rx_mode = pm3393_set_rx_mode,
587 .get_speed_duplex_fc = pm3393_get_speed_duplex_fc,
588 .set_speed_duplex_fc = pm3393_set_speed_duplex_fc,
589 .statistics_update = pm3393_update_statistics,
590 .macaddress_get = pm3393_macaddress_get,
591 .macaddress_set = pm3393_macaddress_set
592};
593
594static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
595{
596 struct cmac *cmac;
597
598 cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
599 if (!cmac)
600 return NULL;
601
602 cmac->ops = &pm3393_ops;
603 cmac->instance = (cmac_instance *) (cmac + 1);
604 cmac->adapter = adapter;
605 cmac->instance->fc = PAUSE_TX | PAUSE_RX;
606
607 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
608 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
609 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
610 t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */
611 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
612 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
613 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
614 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
615 t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
616 t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
617 t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
618 t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
619 t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
620 t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
621 t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
622 t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
623 t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
624 t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
625 t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
626 t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
627 t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
628 t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */
629
630 t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */
631 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */
632 t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */
633 t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */
634 t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */
635 t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */
636 t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */
637 t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */
638 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */
639 t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */
640 t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */
641 t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit are undocumented */
642 t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */
643
644 t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */
645 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */
646 t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */
647 t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */
648 t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */
649 t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */
650 t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */
651 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */
652 t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */
653 t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */
654 t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other bit are undocumented */
655
656 t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */
657 t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */
658 t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */
659 t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */
660 t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */
661 t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */
662
663 t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */
664 t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */
665
666 t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
667 t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */
668
669 t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */
670 /* For T1 use timer based Mac flow control. */
671 t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
672 t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */
673 t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */
674 t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */
675
676 /* Setup Exact Match Filter 0 to allow broadcast packets.
677 */
678 t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */
679 t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */
680 t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */
681 t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */
682 t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */
683
684 t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */
685 t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */
686 t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */
687
688 return cmac;
689}
690
691static int pm3393_mac_reset(adapter_t * adapter)
692{
693 u32 val;
694 u32 x;
695 u32 is_pl4_reset_finished;
696 u32 is_pl4_outof_lock;
697 u32 is_xaui_mabc_pll_locked;
698 u32 successful_reset;
699 int i;
700
701 /* The following steps are required to properly reset
702 * the PM3393. This information is provided in the
703 * PM3393 datasheet (Issue 2: November 2002)
704 * section 13.1 -- Device Reset.
705 *
706 * The PM3393 has three types of components that are
707 * individually reset:
708 *
709 * DRESETB - Digital circuitry
710 * PL4_ARESETB - PL4 analog circuitry
711 * XAUI_ARESETB - XAUI bus analog circuitry
712 *
713 * Steps to reset PM3393 using RSTB pin:
714 *
715 * 1. Assert RSTB pin low ( write 0 )
716 * 2. Wait at least 1ms to initiate a complete initialization of device.
717 * 3. Wait until all external clocks and REFSEL are stable.
718 * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
719 * 5. De-assert RSTB ( write 1 )
720 * 6. Wait until internal timers to expires after ~14ms.
721 * - Allows analog clock synthesizer(PL4CSU) to stabilize to
722 * selected reference frequency before allowing the digital
723 * portion of the device to operate.
724 * 7. Wait at least 200us for XAUI interface to stabilize.
725 * 8. Verify the PM3393 came out of reset successfully.
726 * Set successful reset flag if everything worked else try again
727 * a few more times.
728 */
729
730 successful_reset = 0;
731 for (i = 0; i < 3 && !successful_reset; i++) {
732 /* 1 */
733 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
734 val &= ~1;
735 t1_tpi_write(adapter, A_ELMER0_GPO, val);
736
737 /* 2 */
738 msleep(1);
739
740 /* 3 */
741 msleep(1);
742
743 /* 4 */
744 msleep(2 /*1 extra ms for safety */ );
745
746 /* 5 */
747 val |= 1;
748 t1_tpi_write(adapter, A_ELMER0_GPO, val);
749
750 /* 6 */
751 msleep(15 /*1 extra ms for safety */ );
752
753 /* 7 */
754 msleep(1);
755
756 /* 8 */
757
758 /* Has PL4 analog block come out of reset correctly? */
759 t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
760 is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
761
762 /* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
763 * figure out why? */
764
765 /* Have all PL4 block clocks locked? */
766 x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
767 /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */ |
768 SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
769 SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
770 SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
771 is_pl4_outof_lock = (val & x);
772
773 /* ??? If this fails, might be able to software reset the XAUI part
774 * and try to recover... thus saving us from doing another HW reset */
775 /* Has the XAUI MABC PLL circuitry stablized? */
776 is_xaui_mabc_pll_locked =
777 (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
778
779 successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
780 && is_xaui_mabc_pll_locked);
781
782 if (netif_msg_hw(adapter))
783 dev_dbg(&adapter->pdev->dev,
784 "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
785 "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
786 i, is_pl4_reset_finished, val,
787 is_pl4_outof_lock, is_xaui_mabc_pll_locked);
788 }
789 return successful_reset ? 0 : 1;
790}
791
792const struct gmac t1_pm3393_ops = {
793 .stats_update_period = STATS_TICK_SECS,
794 .create = pm3393_mac_create,
795 .reset = pm3393_mac_reset,
796};
diff --git a/drivers/net/chelsio/regs.h b/drivers/net/chelsio/regs.h
deleted file mode 100644
index c80bf4d6d0a6..000000000000
--- a/drivers/net/chelsio/regs.h
+++ /dev/null
@@ -1,2168 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: regs.h *
4 * $Revision: 1.8 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_REGS_H_
40#define _CXGB_REGS_H_
41
42/* SGE registers */
43#define A_SG_CONTROL 0x0
44
45#define S_CMDQ0_ENABLE 0
46#define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
47#define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U)
48
49#define S_CMDQ1_ENABLE 1
50#define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
51#define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U)
52
53#define S_FL0_ENABLE 2
54#define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
55#define F_FL0_ENABLE V_FL0_ENABLE(1U)
56
57#define S_FL1_ENABLE 3
58#define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
59#define F_FL1_ENABLE V_FL1_ENABLE(1U)
60
61#define S_CPL_ENABLE 4
62#define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
63#define F_CPL_ENABLE V_CPL_ENABLE(1U)
64
65#define S_RESPONSE_QUEUE_ENABLE 5
66#define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
67#define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U)
68
69#define S_CMDQ_PRIORITY 6
70#define M_CMDQ_PRIORITY 0x3
71#define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
72#define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
73
74#define S_DISABLE_CMDQ0_GTS 8
75#define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
76#define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U)
77
78#define S_DISABLE_CMDQ1_GTS 9
79#define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
80#define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U)
81
82#define S_DISABLE_FL0_GTS 10
83#define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
84#define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U)
85
86#define S_DISABLE_FL1_GTS 11
87#define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
88#define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U)
89
90#define S_ENABLE_BIG_ENDIAN 12
91#define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
92#define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U)
93
94#define S_FL_SELECTION_CRITERIA 13
95#define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
96#define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U)
97
98#define S_ISCSI_COALESCE 14
99#define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
100#define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U)
101
102#define S_RX_PKT_OFFSET 15
103#define M_RX_PKT_OFFSET 0x7
104#define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
105#define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
106
107#define S_VLAN_XTRACT 18
108#define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
109#define F_VLAN_XTRACT V_VLAN_XTRACT(1U)
110
111#define A_SG_DOORBELL 0x4
112#define A_SG_CMD0BASELWR 0x8
113#define A_SG_CMD0BASEUPR 0xc
114#define A_SG_CMD1BASELWR 0x10
115#define A_SG_CMD1BASEUPR 0x14
116#define A_SG_FL0BASELWR 0x18
117#define A_SG_FL0BASEUPR 0x1c
118#define A_SG_FL1BASELWR 0x20
119#define A_SG_FL1BASEUPR 0x24
120#define A_SG_CMD0SIZE 0x28
121
122#define S_CMDQ0_SIZE 0
123#define M_CMDQ0_SIZE 0x1ffff
124#define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
125#define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
126
127#define A_SG_FL0SIZE 0x2c
128
129#define S_FL0_SIZE 0
130#define M_FL0_SIZE 0x1ffff
131#define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
132#define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
133
134#define A_SG_RSPSIZE 0x30
135
136#define S_RESPQ_SIZE 0
137#define M_RESPQ_SIZE 0x1ffff
138#define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
139#define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
140
141#define A_SG_RSPBASELWR 0x34
142#define A_SG_RSPBASEUPR 0x38
143#define A_SG_FLTHRESHOLD 0x3c
144
145#define S_FL_THRESHOLD 0
146#define M_FL_THRESHOLD 0xffff
147#define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
148#define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
149
150#define A_SG_RSPQUEUECREDIT 0x40
151
152#define S_RESPQ_CREDIT 0
153#define M_RESPQ_CREDIT 0x1ffff
154#define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
155#define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
156
157#define A_SG_SLEEPING 0x48
158
159#define S_SLEEPING 0
160#define M_SLEEPING 0xffff
161#define V_SLEEPING(x) ((x) << S_SLEEPING)
162#define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
163
164#define A_SG_INTRTIMER 0x4c
165
166#define S_INTERRUPT_TIMER_COUNT 0
167#define M_INTERRUPT_TIMER_COUNT 0xffffff
168#define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
169#define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
170
171#define A_SG_CMD0PTR 0x50
172
173#define S_CMDQ0_POINTER 0
174#define M_CMDQ0_POINTER 0xffff
175#define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
176#define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
177
178#define S_CURRENT_GENERATION_BIT 16
179#define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
180#define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U)
181
182#define A_SG_CMD1PTR 0x54
183
184#define S_CMDQ1_POINTER 0
185#define M_CMDQ1_POINTER 0xffff
186#define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
187#define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
188
189#define A_SG_FL0PTR 0x58
190
191#define S_FL0_POINTER 0
192#define M_FL0_POINTER 0xffff
193#define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
194#define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
195
196#define A_SG_FL1PTR 0x5c
197
198#define S_FL1_POINTER 0
199#define M_FL1_POINTER 0xffff
200#define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
201#define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
202
203#define A_SG_VERSION 0x6c
204
205#define S_DAY 0
206#define M_DAY 0x1f
207#define V_DAY(x) ((x) << S_DAY)
208#define G_DAY(x) (((x) >> S_DAY) & M_DAY)
209
210#define S_MONTH 5
211#define M_MONTH 0xf
212#define V_MONTH(x) ((x) << S_MONTH)
213#define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
214
215#define A_SG_CMD1SIZE 0xb0
216
217#define S_CMDQ1_SIZE 0
218#define M_CMDQ1_SIZE 0x1ffff
219#define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
220#define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
221
222#define A_SG_FL1SIZE 0xb4
223
224#define S_FL1_SIZE 0
225#define M_FL1_SIZE 0x1ffff
226#define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
227#define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
228
229#define A_SG_INT_ENABLE 0xb8
230
231#define S_RESPQ_EXHAUSTED 0
232#define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
233#define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U)
234
235#define S_RESPQ_OVERFLOW 1
236#define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
237#define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U)
238
239#define S_FL_EXHAUSTED 2
240#define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
241#define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U)
242
243#define S_PACKET_TOO_BIG 3
244#define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
245#define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U)
246
247#define S_PACKET_MISMATCH 4
248#define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
249#define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U)
250
251#define A_SG_INT_CAUSE 0xbc
252#define A_SG_RESPACCUTIMER 0xc0
253
254/* MC3 registers */
255#define A_MC3_CFG 0x100
256
257#define S_CLK_ENABLE 0
258#define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
259#define F_CLK_ENABLE V_CLK_ENABLE(1U)
260
261#define S_READY 1
262#define V_READY(x) ((x) << S_READY)
263#define F_READY V_READY(1U)
264
265#define S_READ_TO_WRITE_DELAY 2
266#define M_READ_TO_WRITE_DELAY 0x7
267#define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
268#define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
269
270#define S_WRITE_TO_READ_DELAY 5
271#define M_WRITE_TO_READ_DELAY 0x7
272#define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
273#define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
274
275#define S_MC3_BANK_CYCLE 8
276#define M_MC3_BANK_CYCLE 0xf
277#define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
278#define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
279
280#define S_REFRESH_CYCLE 12
281#define M_REFRESH_CYCLE 0xf
282#define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
283#define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
284
285#define S_PRECHARGE_CYCLE 16
286#define M_PRECHARGE_CYCLE 0x3
287#define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
288#define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
289
290#define S_ACTIVE_TO_READ_WRITE_DELAY 18
291#define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
292#define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U)
293
294#define S_ACTIVE_TO_PRECHARGE_DELAY 19
295#define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
296#define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
297#define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
298
299#define S_WRITE_RECOVERY_DELAY 22
300#define M_WRITE_RECOVERY_DELAY 0x3
301#define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
302#define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
303
304#define S_DENSITY 24
305#define M_DENSITY 0x3
306#define V_DENSITY(x) ((x) << S_DENSITY)
307#define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
308
309#define S_ORGANIZATION 26
310#define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
311#define F_ORGANIZATION V_ORGANIZATION(1U)
312
313#define S_BANKS 27
314#define V_BANKS(x) ((x) << S_BANKS)
315#define F_BANKS V_BANKS(1U)
316
317#define S_UNREGISTERED 28
318#define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
319#define F_UNREGISTERED V_UNREGISTERED(1U)
320
321#define S_MC3_WIDTH 29
322#define M_MC3_WIDTH 0x3
323#define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
324#define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
325
326#define S_MC3_SLOW 31
327#define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
328#define F_MC3_SLOW V_MC3_SLOW(1U)
329
330#define A_MC3_MODE 0x104
331
332#define S_MC3_MODE 0
333#define M_MC3_MODE 0x3fff
334#define V_MC3_MODE(x) ((x) << S_MC3_MODE)
335#define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
336
337#define S_BUSY 31
338#define V_BUSY(x) ((x) << S_BUSY)
339#define F_BUSY V_BUSY(1U)
340
341#define A_MC3_EXT_MODE 0x108
342
343#define S_MC3_EXTENDED_MODE 0
344#define M_MC3_EXTENDED_MODE 0x3fff
345#define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
346#define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
347
348#define A_MC3_PRECHARG 0x10c
349#define A_MC3_REFRESH 0x110
350
351#define S_REFRESH_ENABLE 0
352#define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
353#define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U)
354
355#define S_REFRESH_DIVISOR 1
356#define M_REFRESH_DIVISOR 0x3fff
357#define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
358#define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
359
360#define A_MC3_STROBE 0x114
361
362#define S_MASTER_DLL_RESET 0
363#define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
364#define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U)
365
366#define S_MASTER_DLL_TAP_COUNT 1
367#define M_MASTER_DLL_TAP_COUNT 0xff
368#define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
369#define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
370
371#define S_MASTER_DLL_LOCKED 9
372#define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
373#define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U)
374
375#define S_MASTER_DLL_MAX_TAP_COUNT 10
376#define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
377#define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U)
378
379#define S_MASTER_DLL_TAP_COUNT_OFFSET 11
380#define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
381#define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
382#define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
383
384#define S_SLAVE_DLL_RESET 11
385#define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
386#define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U)
387
388#define S_SLAVE_DLL_DELTA 12
389#define M_SLAVE_DLL_DELTA 0xf
390#define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
391#define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
392
393#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17
394#define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
395#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
396#define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
397
398#define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23
399#define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
400#define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
401
402#define S_SLAVE_DELAY_LINE_TAP_COUNT 24
403#define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
404#define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
405#define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
406
407#define A_MC3_ECC_CNTL 0x118
408
409#define S_ECC_GENERATION_ENABLE 0
410#define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
411#define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U)
412
413#define S_ECC_CHECK_ENABLE 1
414#define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
415#define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U)
416
417#define S_CORRECTABLE_ERROR_COUNT 2
418#define M_CORRECTABLE_ERROR_COUNT 0xff
419#define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
420#define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
421
422#define S_UNCORRECTABLE_ERROR_COUNT 10
423#define M_UNCORRECTABLE_ERROR_COUNT 0xff
424#define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
425#define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
426
427#define A_MC3_CE_ADDR 0x11c
428
429#define S_MC3_CE_ADDR 4
430#define M_MC3_CE_ADDR 0xfffffff
431#define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
432#define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
433
434#define A_MC3_CE_DATA0 0x120
435#define A_MC3_CE_DATA1 0x124
436#define A_MC3_CE_DATA2 0x128
437#define A_MC3_CE_DATA3 0x12c
438#define A_MC3_CE_DATA4 0x130
439#define A_MC3_UE_ADDR 0x134
440
441#define S_MC3_UE_ADDR 4
442#define M_MC3_UE_ADDR 0xfffffff
443#define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
444#define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
445
446#define A_MC3_UE_DATA0 0x138
447#define A_MC3_UE_DATA1 0x13c
448#define A_MC3_UE_DATA2 0x140
449#define A_MC3_UE_DATA3 0x144
450#define A_MC3_UE_DATA4 0x148
451#define A_MC3_BD_ADDR 0x14c
452#define A_MC3_BD_DATA0 0x150
453#define A_MC3_BD_DATA1 0x154
454#define A_MC3_BD_DATA2 0x158
455#define A_MC3_BD_DATA3 0x15c
456#define A_MC3_BD_DATA4 0x160
457#define A_MC3_BD_OP 0x164
458
459#define S_BACK_DOOR_OPERATION 0
460#define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
461#define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U)
462
463#define A_MC3_BIST_ADDR_BEG 0x168
464#define A_MC3_BIST_ADDR_END 0x16c
465#define A_MC3_BIST_DATA 0x170
466#define A_MC3_BIST_OP 0x174
467
468#define S_OP 0
469#define V_OP(x) ((x) << S_OP)
470#define F_OP V_OP(1U)
471
472#define S_DATA_PATTERN 1
473#define M_DATA_PATTERN 0x3
474#define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
475#define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
476
477#define S_CONTINUOUS 3
478#define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
479#define F_CONTINUOUS V_CONTINUOUS(1U)
480
481#define A_MC3_INT_ENABLE 0x178
482
483#define S_MC3_CORR_ERR 0
484#define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
485#define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U)
486
487#define S_MC3_UNCORR_ERR 1
488#define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
489#define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U)
490
491#define S_MC3_PARITY_ERR 2
492#define M_MC3_PARITY_ERR 0xff
493#define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
494#define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
495
496#define S_MC3_ADDR_ERR 10
497#define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
498#define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U)
499
500#define A_MC3_INT_CAUSE 0x17c
501
502/* MC4 registers */
503#define A_MC4_CFG 0x180
504
505#define S_POWER_UP 0
506#define V_POWER_UP(x) ((x) << S_POWER_UP)
507#define F_POWER_UP V_POWER_UP(1U)
508
509#define S_MC4_BANK_CYCLE 8
510#define M_MC4_BANK_CYCLE 0x7
511#define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
512#define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
513
514#define S_MC4_NARROW 24
515#define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
516#define F_MC4_NARROW V_MC4_NARROW(1U)
517
518#define S_MC4_SLOW 25
519#define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
520#define F_MC4_SLOW V_MC4_SLOW(1U)
521
522#define S_MC4A_WIDTH 24
523#define M_MC4A_WIDTH 0x3
524#define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
525#define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
526
527#define S_MC4A_SLOW 26
528#define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
529#define F_MC4A_SLOW V_MC4A_SLOW(1U)
530
531#define A_MC4_MODE 0x184
532
533#define S_MC4_MODE 0
534#define M_MC4_MODE 0x7fff
535#define V_MC4_MODE(x) ((x) << S_MC4_MODE)
536#define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
537
538#define A_MC4_EXT_MODE 0x188
539
540#define S_MC4_EXTENDED_MODE 0
541#define M_MC4_EXTENDED_MODE 0x7fff
542#define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
543#define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
544
545#define A_MC4_REFRESH 0x190
546#define A_MC4_STROBE 0x194
547#define A_MC4_ECC_CNTL 0x198
548#define A_MC4_CE_ADDR 0x19c
549
550#define S_MC4_CE_ADDR 4
551#define M_MC4_CE_ADDR 0xffffff
552#define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
553#define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
554
555#define A_MC4_CE_DATA0 0x1a0
556#define A_MC4_CE_DATA1 0x1a4
557#define A_MC4_CE_DATA2 0x1a8
558#define A_MC4_CE_DATA3 0x1ac
559#define A_MC4_CE_DATA4 0x1b0
560#define A_MC4_UE_ADDR 0x1b4
561
562#define S_MC4_UE_ADDR 4
563#define M_MC4_UE_ADDR 0xffffff
564#define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
565#define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
566
567#define A_MC4_UE_DATA0 0x1b8
568#define A_MC4_UE_DATA1 0x1bc
569#define A_MC4_UE_DATA2 0x1c0
570#define A_MC4_UE_DATA3 0x1c4
571#define A_MC4_UE_DATA4 0x1c8
572#define A_MC4_BD_ADDR 0x1cc
573
574#define S_MC4_BACK_DOOR_ADDR 0
575#define M_MC4_BACK_DOOR_ADDR 0xfffffff
576#define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
577#define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
578
579#define A_MC4_BD_DATA0 0x1d0
580#define A_MC4_BD_DATA1 0x1d4
581#define A_MC4_BD_DATA2 0x1d8
582#define A_MC4_BD_DATA3 0x1dc
583#define A_MC4_BD_DATA4 0x1e0
584#define A_MC4_BD_OP 0x1e4
585
586#define S_OPERATION 0
587#define V_OPERATION(x) ((x) << S_OPERATION)
588#define F_OPERATION V_OPERATION(1U)
589
590#define A_MC4_BIST_ADDR_BEG 0x1e8
591#define A_MC4_BIST_ADDR_END 0x1ec
592#define A_MC4_BIST_DATA 0x1f0
593#define A_MC4_BIST_OP 0x1f4
594#define A_MC4_INT_ENABLE 0x1f8
595
596#define S_MC4_CORR_ERR 0
597#define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
598#define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U)
599
600#define S_MC4_UNCORR_ERR 1
601#define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
602#define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U)
603
604#define S_MC4_ADDR_ERR 2
605#define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
606#define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U)
607
608#define A_MC4_INT_CAUSE 0x1fc
609
610/* TPI registers */
611#define A_TPI_ADDR 0x280
612
613#define S_TPI_ADDRESS 0
614#define M_TPI_ADDRESS 0xffffff
615#define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
616#define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
617
618#define A_TPI_WR_DATA 0x284
619#define A_TPI_RD_DATA 0x288
620#define A_TPI_CSR 0x28c
621
622#define S_TPIWR 0
623#define V_TPIWR(x) ((x) << S_TPIWR)
624#define F_TPIWR V_TPIWR(1U)
625
626#define S_TPIRDY 1
627#define V_TPIRDY(x) ((x) << S_TPIRDY)
628#define F_TPIRDY V_TPIRDY(1U)
629
630#define S_INT_DIR 31
631#define V_INT_DIR(x) ((x) << S_INT_DIR)
632#define F_INT_DIR V_INT_DIR(1U)
633
634#define A_TPI_PAR 0x29c
635
636#define S_TPIPAR 0
637#define M_TPIPAR 0x7f
638#define V_TPIPAR(x) ((x) << S_TPIPAR)
639#define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
640
641
642/* TP registers */
643#define A_TP_IN_CONFIG 0x300
644
645#define S_TP_IN_CSPI_TUNNEL 0
646#define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
647#define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U)
648
649#define S_TP_IN_CSPI_ETHERNET 1
650#define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
651#define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U)
652
653#define S_TP_IN_CSPI_CPL 3
654#define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
655#define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U)
656
657#define S_TP_IN_CSPI_POS 4
658#define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
659#define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U)
660
661#define S_TP_IN_CSPI_CHECK_IP_CSUM 5
662#define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
663#define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
664
665#define S_TP_IN_CSPI_CHECK_TCP_CSUM 6
666#define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
667#define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
668
669#define S_TP_IN_ESPI_TUNNEL 7
670#define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
671#define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U)
672
673#define S_TP_IN_ESPI_ETHERNET 8
674#define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
675#define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U)
676
677#define S_TP_IN_ESPI_CPL 10
678#define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
679#define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U)
680
681#define S_TP_IN_ESPI_POS 11
682#define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
683#define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U)
684
685#define S_TP_IN_ESPI_CHECK_IP_CSUM 12
686#define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
687#define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
688
689#define S_TP_IN_ESPI_CHECK_TCP_CSUM 13
690#define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
691#define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
692
693#define S_OFFLOAD_DISABLE 14
694#define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
695#define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U)
696
697#define A_TP_OUT_CONFIG 0x304
698
699#define S_TP_OUT_C_ETH 0
700#define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
701#define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U)
702
703#define S_TP_OUT_CSPI_CPL 2
704#define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
705#define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U)
706
707#define S_TP_OUT_CSPI_POS 3
708#define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
709#define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U)
710
711#define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4
712#define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
713#define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
714
715#define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5
716#define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
717#define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
718
719#define S_TP_OUT_ESPI_ETHERNET 6
720#define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
721#define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U)
722
723#define S_TP_OUT_ESPI_TAG_ETHERNET 7
724#define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
725#define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U)
726
727#define S_TP_OUT_ESPI_CPL 8
728#define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
729#define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U)
730
731#define S_TP_OUT_ESPI_POS 9
732#define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
733#define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U)
734
735#define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10
736#define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
737#define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
738
739#define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11
740#define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
741#define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
742
743#define A_TP_GLOBAL_CONFIG 0x308
744
745#define S_IP_TTL 0
746#define M_IP_TTL 0xff
747#define V_IP_TTL(x) ((x) << S_IP_TTL)
748#define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
749
750#define S_TCAM_SERVER_REGION_USAGE 8
751#define M_TCAM_SERVER_REGION_USAGE 0x3
752#define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
753#define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
754
755#define S_QOS_MAPPING 10
756#define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
757#define F_QOS_MAPPING V_QOS_MAPPING(1U)
758
759#define S_TCP_CSUM 11
760#define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
761#define F_TCP_CSUM V_TCP_CSUM(1U)
762
763#define S_UDP_CSUM 12
764#define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
765#define F_UDP_CSUM V_UDP_CSUM(1U)
766
767#define S_IP_CSUM 13
768#define V_IP_CSUM(x) ((x) << S_IP_CSUM)
769#define F_IP_CSUM V_IP_CSUM(1U)
770
771#define S_IP_ID_SPLIT 14
772#define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
773#define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U)
774
775#define S_PATH_MTU 15
776#define V_PATH_MTU(x) ((x) << S_PATH_MTU)
777#define F_PATH_MTU V_PATH_MTU(1U)
778
779#define S_5TUPLE_LOOKUP 17
780#define M_5TUPLE_LOOKUP 0x3
781#define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
782#define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
783
784#define S_IP_FRAGMENT_DROP 19
785#define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
786#define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U)
787
788#define S_PING_DROP 20
789#define V_PING_DROP(x) ((x) << S_PING_DROP)
790#define F_PING_DROP V_PING_DROP(1U)
791
792#define S_PROTECT_MODE 21
793#define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
794#define F_PROTECT_MODE V_PROTECT_MODE(1U)
795
796#define S_SYN_COOKIE_ALGORITHM 22
797#define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
798#define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U)
799
800#define S_ATTACK_FILTER 23
801#define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
802#define F_ATTACK_FILTER V_ATTACK_FILTER(1U)
803
804#define S_INTERFACE_TYPE 24
805#define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
806#define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U)
807
808#define S_DISABLE_RX_FLOW_CONTROL 25
809#define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
810#define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U)
811
812#define S_SYN_COOKIE_PARAMETER 26
813#define M_SYN_COOKIE_PARAMETER 0x3f
814#define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
815#define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
816
817#define A_TP_GLOBAL_RX_CREDITS 0x30c
818#define A_TP_CM_SIZE 0x310
819#define A_TP_CM_MM_BASE 0x314
820
821#define S_CM_MEMMGR_BASE 0
822#define M_CM_MEMMGR_BASE 0xfffffff
823#define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
824#define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
825
826#define A_TP_CM_TIMER_BASE 0x318
827
828#define S_CM_TIMER_BASE 0
829#define M_CM_TIMER_BASE 0xfffffff
830#define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
831#define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
832
833#define A_TP_PM_SIZE 0x31c
834#define A_TP_PM_TX_BASE 0x320
835#define A_TP_PM_DEFRAG_BASE 0x324
836#define A_TP_PM_RX_BASE 0x328
837#define A_TP_PM_RX_PG_SIZE 0x32c
838#define A_TP_PM_RX_MAX_PGS 0x330
839#define A_TP_PM_TX_PG_SIZE 0x334
840#define A_TP_PM_TX_MAX_PGS 0x338
841#define A_TP_TCP_OPTIONS 0x340
842
843#define S_TIMESTAMP 0
844#define M_TIMESTAMP 0x3
845#define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
846#define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
847
848#define S_WINDOW_SCALE 2
849#define M_WINDOW_SCALE 0x3
850#define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
851#define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
852
853#define S_SACK 4
854#define M_SACK 0x3
855#define V_SACK(x) ((x) << S_SACK)
856#define G_SACK(x) (((x) >> S_SACK) & M_SACK)
857
858#define S_ECN 6
859#define M_ECN 0x3
860#define V_ECN(x) ((x) << S_ECN)
861#define G_ECN(x) (((x) >> S_ECN) & M_ECN)
862
863#define S_SACK_ALGORITHM 8
864#define M_SACK_ALGORITHM 0x3
865#define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
866#define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
867
868#define S_MSS 10
869#define V_MSS(x) ((x) << S_MSS)
870#define F_MSS V_MSS(1U)
871
872#define S_DEFAULT_PEER_MSS 16
873#define M_DEFAULT_PEER_MSS 0xffff
874#define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
875#define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
876
877#define A_TP_DACK_CONFIG 0x344
878
879#define S_DACK_MODE 0
880#define V_DACK_MODE(x) ((x) << S_DACK_MODE)
881#define F_DACK_MODE V_DACK_MODE(1U)
882
883#define S_DACK_AUTO_MGMT 1
884#define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
885#define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U)
886
887#define S_DACK_AUTO_CAREFUL 2
888#define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
889#define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U)
890
891#define S_DACK_MSS_SELECTOR 3
892#define M_DACK_MSS_SELECTOR 0x3
893#define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
894#define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
895
896#define S_DACK_BYTE_THRESHOLD 5
897#define M_DACK_BYTE_THRESHOLD 0xfffff
898#define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
899#define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
900
901#define A_TP_PC_CONFIG 0x348
902
903#define S_TP_ACCESS_LATENCY 0
904#define M_TP_ACCESS_LATENCY 0xf
905#define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
906#define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
907
908#define S_HELD_FIN_DISABLE 4
909#define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
910#define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U)
911
912#define S_DDP_FC_ENABLE 5
913#define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
914#define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U)
915
916#define S_RDMA_ERR_ENABLE 6
917#define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
918#define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U)
919
920#define S_FAST_PDU_DELIVERY 7
921#define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
922#define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U)
923
924#define S_CLEAR_FIN 8
925#define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
926#define F_CLEAR_FIN V_CLEAR_FIN(1U)
927
928#define S_DIS_TX_FILL_WIN_PUSH 12
929#define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
930#define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U)
931
932#define S_TP_PC_REV 30
933#define M_TP_PC_REV 0x3
934#define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
935#define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
936
937#define A_TP_BACKOFF0 0x350
938
939#define S_ELEMENT0 0
940#define M_ELEMENT0 0xff
941#define V_ELEMENT0(x) ((x) << S_ELEMENT0)
942#define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
943
944#define S_ELEMENT1 8
945#define M_ELEMENT1 0xff
946#define V_ELEMENT1(x) ((x) << S_ELEMENT1)
947#define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
948
949#define S_ELEMENT2 16
950#define M_ELEMENT2 0xff
951#define V_ELEMENT2(x) ((x) << S_ELEMENT2)
952#define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
953
954#define S_ELEMENT3 24
955#define M_ELEMENT3 0xff
956#define V_ELEMENT3(x) ((x) << S_ELEMENT3)
957#define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
958
959#define A_TP_BACKOFF1 0x354
960#define A_TP_BACKOFF2 0x358
961#define A_TP_BACKOFF3 0x35c
962#define A_TP_PARA_REG0 0x360
963
964#define S_VAR_MULT 0
965#define M_VAR_MULT 0xf
966#define V_VAR_MULT(x) ((x) << S_VAR_MULT)
967#define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
968
969#define S_VAR_GAIN 4
970#define M_VAR_GAIN 0xf
971#define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
972#define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
973
974#define S_SRTT_GAIN 8
975#define M_SRTT_GAIN 0xf
976#define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
977#define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
978
979#define S_RTTVAR_INIT 12
980#define M_RTTVAR_INIT 0xf
981#define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
982#define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
983
984#define S_DUP_THRESH 20
985#define M_DUP_THRESH 0xf
986#define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
987#define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
988
989#define S_INIT_CONG_WIN 24
990#define M_INIT_CONG_WIN 0x7
991#define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
992#define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
993
994#define A_TP_PARA_REG1 0x364
995
996#define S_INITIAL_SLOW_START_THRESHOLD 0
997#define M_INITIAL_SLOW_START_THRESHOLD 0xffff
998#define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
999#define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
1000
1001#define S_RECEIVE_BUFFER_SIZE 16
1002#define M_RECEIVE_BUFFER_SIZE 0xffff
1003#define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
1004#define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
1005
1006#define A_TP_PARA_REG2 0x368
1007
1008#define S_RX_COALESCE_SIZE 0
1009#define M_RX_COALESCE_SIZE 0xffff
1010#define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
1011#define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
1012
1013#define S_MAX_RX_SIZE 16
1014#define M_MAX_RX_SIZE 0xffff
1015#define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1016#define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1017
1018#define A_TP_PARA_REG3 0x36c
1019
1020#define S_RX_COALESCING_PSH_DELIVER 0
1021#define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1022#define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U)
1023
1024#define S_RX_COALESCING_ENABLE 1
1025#define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1026#define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U)
1027
1028#define S_TAHOE_ENABLE 2
1029#define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1030#define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U)
1031
1032#define S_MAX_REORDER_FRAGMENTS 12
1033#define M_MAX_REORDER_FRAGMENTS 0x7
1034#define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1035#define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1036
1037#define A_TP_TIMER_RESOLUTION 0x390
1038
1039#define S_DELAYED_ACK_TIMER_RESOLUTION 0
1040#define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
1041#define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1042#define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1043
1044#define S_GENERIC_TIMER_RESOLUTION 16
1045#define M_GENERIC_TIMER_RESOLUTION 0x3f
1046#define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1047#define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1048
1049#define A_TP_2MSL 0x394
1050
1051#define S_2MSL 0
1052#define M_2MSL 0x3fffffff
1053#define V_2MSL(x) ((x) << S_2MSL)
1054#define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1055
1056#define A_TP_RXT_MIN 0x398
1057
1058#define S_RETRANSMIT_TIMER_MIN 0
1059#define M_RETRANSMIT_TIMER_MIN 0xffff
1060#define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1061#define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1062
1063#define A_TP_RXT_MAX 0x39c
1064
1065#define S_RETRANSMIT_TIMER_MAX 0
1066#define M_RETRANSMIT_TIMER_MAX 0x3fffffff
1067#define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1068#define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1069
1070#define A_TP_PERS_MIN 0x3a0
1071
1072#define S_PERSIST_TIMER_MIN 0
1073#define M_PERSIST_TIMER_MIN 0xffff
1074#define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1075#define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1076
1077#define A_TP_PERS_MAX 0x3a4
1078
1079#define S_PERSIST_TIMER_MAX 0
1080#define M_PERSIST_TIMER_MAX 0x3fffffff
1081#define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1082#define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1083
1084#define A_TP_KEEP_IDLE 0x3ac
1085
1086#define S_KEEP_ALIVE_IDLE_TIME 0
1087#define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
1088#define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1089#define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1090
1091#define A_TP_KEEP_INTVL 0x3b0
1092
1093#define S_KEEP_ALIVE_INTERVAL_TIME 0
1094#define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
1095#define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1096#define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1097
1098#define A_TP_INIT_SRTT 0x3b4
1099
1100#define S_INITIAL_SRTT 0
1101#define M_INITIAL_SRTT 0xffff
1102#define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1103#define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1104
1105#define A_TP_DACK_TIME 0x3b8
1106
1107#define S_DELAYED_ACK_TIME 0
1108#define M_DELAYED_ACK_TIME 0x7ff
1109#define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1110#define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1111
1112#define A_TP_FINWAIT2_TIME 0x3bc
1113
1114#define S_FINWAIT2_TIME 0
1115#define M_FINWAIT2_TIME 0x3fffffff
1116#define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1117#define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1118
1119#define A_TP_FAST_FINWAIT2_TIME 0x3c0
1120
1121#define S_FAST_FINWAIT2_TIME 0
1122#define M_FAST_FINWAIT2_TIME 0x3fffffff
1123#define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1124#define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1125
1126#define A_TP_SHIFT_CNT 0x3c4
1127
1128#define S_KEEPALIVE_MAX 0
1129#define M_KEEPALIVE_MAX 0xff
1130#define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1131#define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1132
1133#define S_WINDOWPROBE_MAX 8
1134#define M_WINDOWPROBE_MAX 0xff
1135#define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1136#define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1137
1138#define S_RETRANSMISSION_MAX 16
1139#define M_RETRANSMISSION_MAX 0xff
1140#define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1141#define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1142
1143#define S_SYN_MAX 24
1144#define M_SYN_MAX 0xff
1145#define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1146#define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1147
1148#define A_TP_QOS_REG0 0x3e0
1149
1150#define S_L3_VALUE 0
1151#define M_L3_VALUE 0x3f
1152#define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1153#define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1154
1155#define A_TP_QOS_REG1 0x3e4
1156#define A_TP_QOS_REG2 0x3e8
1157#define A_TP_QOS_REG3 0x3ec
1158#define A_TP_QOS_REG4 0x3f0
1159#define A_TP_QOS_REG5 0x3f4
1160#define A_TP_QOS_REG6 0x3f8
1161#define A_TP_QOS_REG7 0x3fc
1162#define A_TP_MTU_REG0 0x404
1163#define A_TP_MTU_REG1 0x408
1164#define A_TP_MTU_REG2 0x40c
1165#define A_TP_MTU_REG3 0x410
1166#define A_TP_MTU_REG4 0x414
1167#define A_TP_MTU_REG5 0x418
1168#define A_TP_MTU_REG6 0x41c
1169#define A_TP_MTU_REG7 0x420
1170#define A_TP_RESET 0x44c
1171
1172#define S_TP_RESET 0
1173#define V_TP_RESET(x) ((x) << S_TP_RESET)
1174#define F_TP_RESET V_TP_RESET(1U)
1175
1176#define S_CM_MEMMGR_INIT 1
1177#define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1178#define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U)
1179
1180#define A_TP_MIB_INDEX 0x450
1181#define A_TP_MIB_DATA 0x454
1182#define A_TP_SYNC_TIME_HI 0x458
1183#define A_TP_SYNC_TIME_LO 0x45c
1184#define A_TP_CM_MM_RX_FLST_BASE 0x460
1185
1186#define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
1187#define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
1188#define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1189#define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1190
1191#define A_TP_CM_MM_TX_FLST_BASE 0x464
1192
1193#define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
1194#define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
1195#define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1196#define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1197
1198#define A_TP_CM_MM_P_FLST_BASE 0x468
1199
1200#define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
1201#define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
1202#define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1203#define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1204
1205#define A_TP_CM_MM_MAX_P 0x46c
1206
1207#define S_CM_MEMMGR_MAX_PSTRUCT 0
1208#define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
1209#define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1210#define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1211
1212#define A_TP_INT_ENABLE 0x470
1213
1214#define S_TX_FREE_LIST_EMPTY 0
1215#define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1216#define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U)
1217
1218#define S_RX_FREE_LIST_EMPTY 1
1219#define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1220#define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U)
1221
1222#define A_TP_INT_CAUSE 0x474
1223#define A_TP_TIMER_SEPARATOR 0x4a4
1224
1225#define S_DISABLE_PAST_TIMER_INSERTION 0
1226#define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1227#define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U)
1228
1229#define S_MODULATION_TIMER_SEPARATOR 1
1230#define M_MODULATION_TIMER_SEPARATOR 0x7fff
1231#define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1232#define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1233
1234#define S_GLOBAL_TIMER_SEPARATOR 16
1235#define M_GLOBAL_TIMER_SEPARATOR 0xffff
1236#define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1237#define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1238
1239#define A_TP_CM_FC_MODE 0x4b0
1240#define A_TP_PC_CONGESTION_CNTL 0x4b4
1241#define A_TP_TX_DROP_CONFIG 0x4b8
1242
1243#define S_ENABLE_TX_DROP 31
1244#define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
1245#define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U)
1246
1247#define S_ENABLE_TX_ERROR 30
1248#define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
1249#define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U)
1250
1251#define S_DROP_TICKS_CNT 4
1252#define M_DROP_TICKS_CNT 0x3ffffff
1253#define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1254#define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
1255
1256#define S_NUM_PKTS_DROPPED 0
1257#define M_NUM_PKTS_DROPPED 0xf
1258#define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1259#define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1260
1261#define A_TP_TX_DROP_COUNT 0x4bc
1262
1263/* RAT registers */
1264#define A_RAT_ROUTE_CONTROL 0x580
1265
1266#define S_USE_ROUTE_TABLE 0
1267#define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1268#define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U)
1269
1270#define S_ENABLE_CSPI 1
1271#define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1272#define F_ENABLE_CSPI V_ENABLE_CSPI(1U)
1273
1274#define S_ENABLE_PCIX 2
1275#define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1276#define F_ENABLE_PCIX V_ENABLE_PCIX(1U)
1277
1278#define A_RAT_ROUTE_TABLE_INDEX 0x584
1279
1280#define S_ROUTE_TABLE_INDEX 0
1281#define M_ROUTE_TABLE_INDEX 0xf
1282#define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1283#define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1284
1285#define A_RAT_ROUTE_TABLE_DATA 0x588
1286#define A_RAT_NO_ROUTE 0x58c
1287
1288#define S_CPL_OPCODE 0
1289#define M_CPL_OPCODE 0xff
1290#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1291#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1292
1293#define A_RAT_INTR_ENABLE 0x590
1294
1295#define S_ZEROROUTEERROR 0
1296#define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1297#define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U)
1298
1299#define S_CSPIFRAMINGERROR 1
1300#define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1301#define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U)
1302
1303#define S_SGEFRAMINGERROR 2
1304#define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1305#define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U)
1306
1307#define S_TPFRAMINGERROR 3
1308#define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1309#define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U)
1310
1311#define A_RAT_INTR_CAUSE 0x594
1312
1313/* CSPI registers */
1314#define A_CSPI_RX_AE_WM 0x810
1315#define A_CSPI_RX_AF_WM 0x814
1316#define A_CSPI_CALENDAR_LEN 0x818
1317
1318#define S_CALENDARLENGTH 0
1319#define M_CALENDARLENGTH 0xffff
1320#define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1321#define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1322
1323#define A_CSPI_FIFO_STATUS_ENABLE 0x820
1324
1325#define S_FIFOSTATUSENABLE 0
1326#define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1327#define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U)
1328
1329#define A_CSPI_MAXBURST1_MAXBURST2 0x828
1330
1331#define S_MAXBURST1 0
1332#define M_MAXBURST1 0xffff
1333#define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1334#define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1335
1336#define S_MAXBURST2 16
1337#define M_MAXBURST2 0xffff
1338#define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1339#define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1340
1341#define A_CSPI_TRAIN 0x82c
1342
1343#define S_CSPI_TRAIN_ALPHA 0
1344#define M_CSPI_TRAIN_ALPHA 0xffff
1345#define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1346#define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1347
1348#define S_CSPI_TRAIN_DATA_MAXT 16
1349#define M_CSPI_TRAIN_DATA_MAXT 0xffff
1350#define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1351#define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1352
1353#define A_CSPI_INTR_STATUS 0x848
1354
1355#define S_DIP4ERR 0
1356#define V_DIP4ERR(x) ((x) << S_DIP4ERR)
1357#define F_DIP4ERR V_DIP4ERR(1U)
1358
1359#define S_RXDROP 1
1360#define V_RXDROP(x) ((x) << S_RXDROP)
1361#define F_RXDROP V_RXDROP(1U)
1362
1363#define S_TXDROP 2
1364#define V_TXDROP(x) ((x) << S_TXDROP)
1365#define F_TXDROP V_TXDROP(1U)
1366
1367#define S_RXOVERFLOW 3
1368#define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
1369#define F_RXOVERFLOW V_RXOVERFLOW(1U)
1370
1371#define S_RAMPARITYERR 4
1372#define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
1373#define F_RAMPARITYERR V_RAMPARITYERR(1U)
1374
1375#define A_CSPI_INTR_ENABLE 0x84c
1376
1377/* ESPI registers */
1378#define A_ESPI_SCH_TOKEN0 0x880
1379
1380#define S_SCHTOKEN0 0
1381#define M_SCHTOKEN0 0xffff
1382#define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1383#define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1384
1385#define A_ESPI_SCH_TOKEN1 0x884
1386
1387#define S_SCHTOKEN1 0
1388#define M_SCHTOKEN1 0xffff
1389#define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1390#define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1391
1392#define A_ESPI_SCH_TOKEN2 0x888
1393
1394#define S_SCHTOKEN2 0
1395#define M_SCHTOKEN2 0xffff
1396#define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1397#define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1398
1399#define A_ESPI_SCH_TOKEN3 0x88c
1400
1401#define S_SCHTOKEN3 0
1402#define M_SCHTOKEN3 0xffff
1403#define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1404#define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1405
1406#define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1407
1408#define S_ALMOSTEMPTY 0
1409#define M_ALMOSTEMPTY 0xffff
1410#define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1411#define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1412
1413#define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1414
1415#define S_ALMOSTFULL 0
1416#define M_ALMOSTFULL 0xffff
1417#define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1418#define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1419
1420#define A_ESPI_CALENDAR_LENGTH 0x898
1421#define A_PORT_CONFIG 0x89c
1422
1423#define S_RX_NPORTS 0
1424#define M_RX_NPORTS 0xff
1425#define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1426#define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
1427
1428#define S_TX_NPORTS 8
1429#define M_TX_NPORTS 0xff
1430#define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1431#define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
1432
1433#define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1434
1435#define S_RXSTATUSENABLE 0
1436#define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
1437#define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U)
1438
1439#define S_TXDROPENABLE 1
1440#define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1441#define F_TXDROPENABLE V_TXDROPENABLE(1U)
1442
1443#define S_RXENDIANMODE 2
1444#define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1445#define F_RXENDIANMODE V_RXENDIANMODE(1U)
1446
1447#define S_TXENDIANMODE 3
1448#define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1449#define F_TXENDIANMODE V_TXENDIANMODE(1U)
1450
1451#define S_INTEL1010MODE 4
1452#define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
1453#define F_INTEL1010MODE V_INTEL1010MODE(1U)
1454
1455#define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
1456#define A_ESPI_TRAIN 0x8ac
1457
1458#define S_MAXTRAINALPHA 0
1459#define M_MAXTRAINALPHA 0xffff
1460#define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1461#define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1462
1463#define S_MAXTRAINDATA 16
1464#define M_MAXTRAINDATA 0xffff
1465#define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1466#define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1467
1468#define A_RAM_STATUS 0x8b0
1469
1470#define S_RXFIFOPARITYERROR 0
1471#define M_RXFIFOPARITYERROR 0x3ff
1472#define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1473#define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1474
1475#define S_TXFIFOPARITYERROR 10
1476#define M_TXFIFOPARITYERROR 0x3ff
1477#define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1478#define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1479
1480#define S_RXFIFOOVERFLOW 20
1481#define M_RXFIFOOVERFLOW 0x3ff
1482#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1483#define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1484
1485#define A_TX_DROP_COUNT0 0x8b4
1486
1487#define S_TXPORT0DROPCNT 0
1488#define M_TXPORT0DROPCNT 0xffff
1489#define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1490#define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1491
1492#define S_TXPORT1DROPCNT 16
1493#define M_TXPORT1DROPCNT 0xffff
1494#define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1495#define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1496
1497#define A_TX_DROP_COUNT1 0x8b8
1498
1499#define S_TXPORT2DROPCNT 0
1500#define M_TXPORT2DROPCNT 0xffff
1501#define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1502#define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1503
1504#define S_TXPORT3DROPCNT 16
1505#define M_TXPORT3DROPCNT 0xffff
1506#define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1507#define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1508
1509#define A_RX_DROP_COUNT0 0x8bc
1510
1511#define S_RXPORT0DROPCNT 0
1512#define M_RXPORT0DROPCNT 0xffff
1513#define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1514#define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1515
1516#define S_RXPORT1DROPCNT 16
1517#define M_RXPORT1DROPCNT 0xffff
1518#define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1519#define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1520
1521#define A_RX_DROP_COUNT1 0x8c0
1522
1523#define S_RXPORT2DROPCNT 0
1524#define M_RXPORT2DROPCNT 0xffff
1525#define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1526#define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1527
1528#define S_RXPORT3DROPCNT 16
1529#define M_RXPORT3DROPCNT 0xffff
1530#define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1531#define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1532
1533#define A_DIP4_ERROR_COUNT 0x8c4
1534
1535#define S_DIP4ERRORCNT 0
1536#define M_DIP4ERRORCNT 0xfff
1537#define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1538#define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1539
1540#define S_DIP4ERRORCNTSHADOW 12
1541#define M_DIP4ERRORCNTSHADOW 0xfff
1542#define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1543#define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1544
1545#define S_TRICN_RX_TRAIN_ERR 24
1546#define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1547#define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U)
1548
1549#define S_TRICN_RX_TRAINING 25
1550#define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1551#define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U)
1552
1553#define S_TRICN_RX_TRAIN_OK 26
1554#define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1555#define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U)
1556
1557#define A_ESPI_INTR_STATUS 0x8c8
1558
1559#define S_DIP2PARITYERR 5
1560#define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
1561#define F_DIP2PARITYERR V_DIP2PARITYERR(1U)
1562
1563#define A_ESPI_INTR_ENABLE 0x8cc
1564#define A_RX_DROP_THRESHOLD 0x8d0
1565#define A_ESPI_RX_RESET 0x8ec
1566
1567#define S_ESPI_RX_LNK_RST 0
1568#define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1569#define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U)
1570
1571#define S_ESPI_RX_CORE_RST 1
1572#define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1573#define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U)
1574
1575#define S_RX_CLK_STATUS 2
1576#define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1577#define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U)
1578
1579#define A_ESPI_MISC_CONTROL 0x8f0
1580
1581#define S_OUT_OF_SYNC_COUNT 0
1582#define M_OUT_OF_SYNC_COUNT 0xf
1583#define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1584#define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1585
1586#define S_DIP2_COUNT_MODE_ENABLE 4
1587#define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1588#define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U)
1589
1590#define S_DIP2_PARITY_ERR_THRES 5
1591#define M_DIP2_PARITY_ERR_THRES 0xf
1592#define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1593#define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
1594
1595#define S_DIP4_THRES 9
1596#define M_DIP4_THRES 0xfff
1597#define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1598#define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1599
1600#define S_DIP4_THRES_ENABLE 21
1601#define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1602#define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U)
1603
1604#define S_FORCE_DISABLE_STATUS 22
1605#define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1606#define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U)
1607
1608#define S_DYNAMIC_DESKEW 23
1609#define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1610#define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U)
1611
1612#define S_MONITORED_PORT_NUM 25
1613#define M_MONITORED_PORT_NUM 0x3
1614#define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1615#define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
1616
1617#define S_MONITORED_DIRECTION 27
1618#define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
1619#define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U)
1620
1621#define S_MONITORED_INTERFACE 28
1622#define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
1623#define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U)
1624
1625#define A_ESPI_DIP2_ERR_COUNT 0x8f4
1626
1627#define S_DIP2_ERR_CNT 0
1628#define M_DIP2_ERR_CNT 0xf
1629#define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1630#define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1631
1632#define A_ESPI_CMD_ADDR 0x8f8
1633
1634#define S_WRITE_DATA 0
1635#define M_WRITE_DATA 0xff
1636#define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1637#define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
1638
1639#define S_REGISTER_OFFSET 8
1640#define M_REGISTER_OFFSET 0xf
1641#define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1642#define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
1643
1644#define S_CHANNEL_ADDR 12
1645#define M_CHANNEL_ADDR 0xf
1646#define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1647#define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
1648
1649#define S_MODULE_ADDR 16
1650#define M_MODULE_ADDR 0x3
1651#define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1652#define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
1653
1654#define S_BUNDLE_ADDR 20
1655#define M_BUNDLE_ADDR 0x3
1656#define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1657#define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
1658
1659#define S_SPI4_COMMAND 24
1660#define M_SPI4_COMMAND 0xff
1661#define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1662#define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
1663
1664#define A_ESPI_GOSTAT 0x8fc
1665
1666#define S_READ_DATA 0
1667#define M_READ_DATA 0xff
1668#define V_READ_DATA(x) ((x) << S_READ_DATA)
1669#define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1670
1671#define S_ESPI_CMD_BUSY 8
1672#define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
1673#define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U)
1674
1675#define S_ERROR_ACK 9
1676#define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1677#define F_ERROR_ACK V_ERROR_ACK(1U)
1678
1679#define S_UNMAPPED_ERR 10
1680#define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1681#define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U)
1682
1683#define S_TRANSACTION_TIMER 16
1684#define M_TRANSACTION_TIMER 0xff
1685#define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1686#define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1687
1688
1689/* ULP registers */
1690#define A_ULP_ULIMIT 0x980
1691#define A_ULP_TAGMASK 0x984
1692#define A_ULP_HREG_INDEX 0x988
1693#define A_ULP_HREG_DATA 0x98c
1694#define A_ULP_INT_ENABLE 0x990
1695#define A_ULP_INT_CAUSE 0x994
1696
1697#define S_HREG_PAR_ERR 0
1698#define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1699#define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U)
1700
1701#define S_EGRS_DATA_PAR_ERR 1
1702#define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1703#define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U)
1704
1705#define S_INGRS_DATA_PAR_ERR 2
1706#define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1707#define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U)
1708
1709#define S_PM_INTR 3
1710#define V_PM_INTR(x) ((x) << S_PM_INTR)
1711#define F_PM_INTR V_PM_INTR(1U)
1712
1713#define S_PM_E2C_SYNC_ERR 4
1714#define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1715#define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U)
1716
1717#define S_PM_C2E_SYNC_ERR 5
1718#define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1719#define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U)
1720
1721#define S_PM_E2C_EMPTY_ERR 6
1722#define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1723#define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U)
1724
1725#define S_PM_C2E_EMPTY_ERR 7
1726#define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1727#define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U)
1728
1729#define S_PM_PAR_ERR 8
1730#define M_PM_PAR_ERR 0xffff
1731#define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1732#define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1733
1734#define S_PM_E2C_WRT_FULL 24
1735#define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1736#define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U)
1737
1738#define S_PM_C2E_WRT_FULL 25
1739#define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1740#define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U)
1741
1742#define A_ULP_PIO_CTRL 0x998
1743
1744/* PL registers */
1745#define A_PL_ENABLE 0xa00
1746
1747#define S_PL_INTR_SGE_ERR 0
1748#define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
1749#define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U)
1750
1751#define S_PL_INTR_SGE_DATA 1
1752#define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
1753#define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U)
1754
1755#define S_PL_INTR_MC3 2
1756#define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1757#define F_PL_INTR_MC3 V_PL_INTR_MC3(1U)
1758
1759#define S_PL_INTR_MC4 3
1760#define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1761#define F_PL_INTR_MC4 V_PL_INTR_MC4(1U)
1762
1763#define S_PL_INTR_MC5 4
1764#define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1765#define F_PL_INTR_MC5 V_PL_INTR_MC5(1U)
1766
1767#define S_PL_INTR_RAT 5
1768#define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1769#define F_PL_INTR_RAT V_PL_INTR_RAT(1U)
1770
1771#define S_PL_INTR_TP 6
1772#define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
1773#define F_PL_INTR_TP V_PL_INTR_TP(1U)
1774
1775#define S_PL_INTR_ULP 7
1776#define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1777#define F_PL_INTR_ULP V_PL_INTR_ULP(1U)
1778
1779#define S_PL_INTR_ESPI 8
1780#define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
1781#define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U)
1782
1783#define S_PL_INTR_CSPI 9
1784#define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1785#define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U)
1786
1787#define S_PL_INTR_PCIX 10
1788#define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
1789#define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U)
1790
1791#define S_PL_INTR_EXT 11
1792#define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
1793#define F_PL_INTR_EXT V_PL_INTR_EXT(1U)
1794
1795#define A_PL_CAUSE 0xa04
1796
1797/* MC5 registers */
1798#define A_MC5_CONFIG 0xc04
1799
1800#define S_MODE 0
1801#define V_MODE(x) ((x) << S_MODE)
1802#define F_MODE V_MODE(1U)
1803
1804#define S_TCAM_RESET 1
1805#define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
1806#define F_TCAM_RESET V_TCAM_RESET(1U)
1807
1808#define S_TCAM_READY 2
1809#define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1810#define F_TCAM_READY V_TCAM_READY(1U)
1811
1812#define S_DBGI_ENABLE 4
1813#define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1814#define F_DBGI_ENABLE V_DBGI_ENABLE(1U)
1815
1816#define S_M_BUS_ENABLE 5
1817#define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
1818#define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U)
1819
1820#define S_PARITY_ENABLE 6
1821#define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1822#define F_PARITY_ENABLE V_PARITY_ENABLE(1U)
1823
1824#define S_SYN_ISSUE_MODE 7
1825#define M_SYN_ISSUE_MODE 0x3
1826#define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1827#define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1828
1829#define S_BUILD 16
1830#define V_BUILD(x) ((x) << S_BUILD)
1831#define F_BUILD V_BUILD(1U)
1832
1833#define S_COMPRESSION_ENABLE 17
1834#define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1835#define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U)
1836
1837#define S_NUM_LIP 18
1838#define M_NUM_LIP 0x3f
1839#define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1840#define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1841
1842#define S_TCAM_PART_CNT 24
1843#define M_TCAM_PART_CNT 0x3
1844#define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1845#define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1846
1847#define S_TCAM_PART_TYPE 26
1848#define M_TCAM_PART_TYPE 0x3
1849#define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1850#define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1851
1852#define S_TCAM_PART_SIZE 28
1853#define M_TCAM_PART_SIZE 0x3
1854#define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1855#define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1856
1857#define S_TCAM_PART_TYPE_HI 30
1858#define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1859#define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U)
1860
1861#define A_MC5_SIZE 0xc08
1862
1863#define S_SIZE 0
1864#define M_SIZE 0x3fffff
1865#define V_SIZE(x) ((x) << S_SIZE)
1866#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1867
1868#define A_MC5_ROUTING_TABLE_INDEX 0xc0c
1869
1870#define S_START_OF_ROUTING_TABLE 0
1871#define M_START_OF_ROUTING_TABLE 0x3fffff
1872#define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1873#define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1874
1875#define A_MC5_SERVER_INDEX 0xc14
1876
1877#define S_START_OF_SERVER_INDEX 0
1878#define M_START_OF_SERVER_INDEX 0x3fffff
1879#define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1880#define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1881
1882#define A_MC5_LIP_RAM_ADDR 0xc18
1883
1884#define S_LOCAL_IP_RAM_ADDR 0
1885#define M_LOCAL_IP_RAM_ADDR 0x3f
1886#define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1887#define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1888
1889#define S_RAM_WRITE_ENABLE 8
1890#define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1891#define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U)
1892
1893#define A_MC5_LIP_RAM_DATA 0xc1c
1894#define A_MC5_RSP_LATENCY 0xc20
1895
1896#define S_SEARCH_RESPONSE_LATENCY 0
1897#define M_SEARCH_RESPONSE_LATENCY 0x1f
1898#define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1899#define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1900
1901#define S_LEARN_RESPONSE_LATENCY 8
1902#define M_LEARN_RESPONSE_LATENCY 0x1f
1903#define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1904#define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1905
1906#define A_MC5_PARITY_LATENCY 0xc24
1907
1908#define S_SRCHLAT 0
1909#define M_SRCHLAT 0x1f
1910#define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1911#define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1912
1913#define S_PARLAT 8
1914#define M_PARLAT 0x1f
1915#define V_PARLAT(x) ((x) << S_PARLAT)
1916#define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1917
1918#define A_MC5_WR_LRN_VERIFY 0xc28
1919
1920#define S_POVEREN 0
1921#define V_POVEREN(x) ((x) << S_POVEREN)
1922#define F_POVEREN V_POVEREN(1U)
1923
1924#define S_LRNVEREN 1
1925#define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1926#define F_LRNVEREN V_LRNVEREN(1U)
1927
1928#define S_VWVEREN 2
1929#define V_VWVEREN(x) ((x) << S_VWVEREN)
1930#define F_VWVEREN V_VWVEREN(1U)
1931
1932#define A_MC5_PART_ID_INDEX 0xc2c
1933
1934#define S_IDINDEX 0
1935#define M_IDINDEX 0xf
1936#define V_IDINDEX(x) ((x) << S_IDINDEX)
1937#define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1938
1939#define A_MC5_RESET_MAX 0xc30
1940
1941#define S_RSTMAX 0
1942#define M_RSTMAX 0x1ff
1943#define V_RSTMAX(x) ((x) << S_RSTMAX)
1944#define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1945
1946#define A_MC5_INT_ENABLE 0xc40
1947
1948#define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0
1949#define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1950#define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1951
1952#define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1
1953#define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1954#define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1955
1956#define S_MC5_INT_HIT_IN_RT_REGION_ERR 2
1957#define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1958#define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1959
1960#define S_MC5_INT_MISS_ERR 3
1961#define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1962#define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U)
1963
1964#define S_MC5_INT_LIP0_ERR 4
1965#define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1966#define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U)
1967
1968#define S_MC5_INT_LIP_MISS_ERR 5
1969#define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1970#define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U)
1971
1972#define S_MC5_INT_PARITY_ERR 6
1973#define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1974#define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U)
1975
1976#define S_MC5_INT_ACTIVE_REGION_FULL 7
1977#define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1978#define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U)
1979
1980#define S_MC5_INT_NFA_SRCH_ERR 8
1981#define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1982#define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U)
1983
1984#define S_MC5_INT_SYN_COOKIE 9
1985#define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1986#define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U)
1987
1988#define S_MC5_INT_SYN_COOKIE_BAD 10
1989#define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1990#define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U)
1991
1992#define S_MC5_INT_SYN_COOKIE_OFF 11
1993#define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1994#define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U)
1995
1996#define S_MC5_INT_UNKNOWN_CMD 15
1997#define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1998#define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U)
1999
2000#define S_MC5_INT_REQUESTQ_PARITY_ERR 16
2001#define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
2002#define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
2003
2004#define S_MC5_INT_DISPATCHQ_PARITY_ERR 17
2005#define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
2006#define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
2007
2008#define S_MC5_INT_DEL_ACT_EMPTY 18
2009#define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
2010#define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U)
2011
2012#define A_MC5_INT_CAUSE 0xc44
2013#define A_MC5_INT_TID 0xc48
2014#define A_MC5_INT_PTID 0xc4c
2015#define A_MC5_DBGI_CONFIG 0xc74
2016#define A_MC5_DBGI_REQ_CMD 0xc78
2017
2018#define S_CMDMODE 0
2019#define M_CMDMODE 0x7
2020#define V_CMDMODE(x) ((x) << S_CMDMODE)
2021#define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2022
2023#define S_SADRSEL 4
2024#define V_SADRSEL(x) ((x) << S_SADRSEL)
2025#define F_SADRSEL V_SADRSEL(1U)
2026
2027#define S_WRITE_BURST_SIZE 22
2028#define M_WRITE_BURST_SIZE 0x3ff
2029#define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2030#define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2031
2032#define A_MC5_DBGI_REQ_ADDR0 0xc7c
2033#define A_MC5_DBGI_REQ_ADDR1 0xc80
2034#define A_MC5_DBGI_REQ_ADDR2 0xc84
2035#define A_MC5_DBGI_REQ_DATA0 0xc88
2036#define A_MC5_DBGI_REQ_DATA1 0xc8c
2037#define A_MC5_DBGI_REQ_DATA2 0xc90
2038#define A_MC5_DBGI_REQ_DATA3 0xc94
2039#define A_MC5_DBGI_REQ_DATA4 0xc98
2040#define A_MC5_DBGI_REQ_MASK0 0xc9c
2041#define A_MC5_DBGI_REQ_MASK1 0xca0
2042#define A_MC5_DBGI_REQ_MASK2 0xca4
2043#define A_MC5_DBGI_REQ_MASK3 0xca8
2044#define A_MC5_DBGI_REQ_MASK4 0xcac
2045#define A_MC5_DBGI_RSP_STATUS 0xcb0
2046
2047#define S_DBGI_RSP_VALID 0
2048#define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2049#define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U)
2050
2051#define S_DBGI_RSP_HIT 1
2052#define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2053#define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U)
2054
2055#define S_DBGI_RSP_ERR 2
2056#define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2057#define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U)
2058
2059#define S_DBGI_RSP_ERR_REASON 8
2060#define M_DBGI_RSP_ERR_REASON 0x7
2061#define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2062#define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2063
2064#define A_MC5_DBGI_RSP_DATA0 0xcb4
2065#define A_MC5_DBGI_RSP_DATA1 0xcb8
2066#define A_MC5_DBGI_RSP_DATA2 0xcbc
2067#define A_MC5_DBGI_RSP_DATA3 0xcc0
2068#define A_MC5_DBGI_RSP_DATA4 0xcc4
2069#define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2070#define A_MC5_POPEN_DATA_WR_CMD 0xccc
2071#define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2072#define A_MC5_AOPEN_SRCH_CMD 0xcd4
2073#define A_MC5_AOPEN_LRN_CMD 0xcd8
2074#define A_MC5_SYN_SRCH_CMD 0xcdc
2075#define A_MC5_SYN_LRN_CMD 0xce0
2076#define A_MC5_ACK_SRCH_CMD 0xce4
2077#define A_MC5_ACK_LRN_CMD 0xce8
2078#define A_MC5_ILOOKUP_CMD 0xcec
2079#define A_MC5_ELOOKUP_CMD 0xcf0
2080#define A_MC5_DATA_WRITE_CMD 0xcf4
2081#define A_MC5_DATA_READ_CMD 0xcf8
2082#define A_MC5_MASK_WRITE_CMD 0xcfc
2083
2084/* PCICFG registers */
2085#define A_PCICFG_PM_CSR 0x44
2086#define A_PCICFG_VPD_ADDR 0x4a
2087
2088#define S_VPD_ADDR 0
2089#define M_VPD_ADDR 0x7fff
2090#define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2091#define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2092
2093#define S_VPD_OP_FLAG 15
2094#define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
2095#define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U)
2096
2097#define A_PCICFG_VPD_DATA 0x4c
2098#define A_PCICFG_PCIX_CMD 0x60
2099#define A_PCICFG_INTR_ENABLE 0xf4
2100
2101#define S_MASTER_PARITY_ERR 0
2102#define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2103#define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U)
2104
2105#define S_SIG_TARGET_ABORT 1
2106#define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2107#define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U)
2108
2109#define S_RCV_TARGET_ABORT 2
2110#define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2111#define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U)
2112
2113#define S_RCV_MASTER_ABORT 3
2114#define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2115#define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U)
2116
2117#define S_SIG_SYS_ERR 4
2118#define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2119#define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U)
2120
2121#define S_DET_PARITY_ERR 5
2122#define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2123#define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U)
2124
2125#define S_PIO_PARITY_ERR 6
2126#define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2127#define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U)
2128
2129#define S_WF_PARITY_ERR 7
2130#define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2131#define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U)
2132
2133#define S_RF_PARITY_ERR 8
2134#define M_RF_PARITY_ERR 0x3
2135#define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2136#define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2137
2138#define S_CF_PARITY_ERR 10
2139#define M_CF_PARITY_ERR 0x3
2140#define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2141#define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2142
2143#define A_PCICFG_INTR_CAUSE 0xf8
2144#define A_PCICFG_MODE 0xfc
2145
2146#define S_PCI_MODE_64BIT 0
2147#define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
2148#define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U)
2149
2150#define S_PCI_MODE_66MHZ 1
2151#define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2152#define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U)
2153
2154#define S_PCI_MODE_PCIX_INITPAT 2
2155#define M_PCI_MODE_PCIX_INITPAT 0x7
2156#define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2157#define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2158
2159#define S_PCI_MODE_PCIX 5
2160#define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
2161#define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U)
2162
2163#define S_PCI_MODE_CLK 6
2164#define M_PCI_MODE_CLK 0x3
2165#define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
2166#define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
2167
2168#endif /* _CXGB_REGS_H_ */
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
deleted file mode 100644
index e9a03fffef15..000000000000
--- a/drivers/net/chelsio/sge.c
+++ /dev/null
@@ -1,2140 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: sge.c *
4 * $Revision: 1.26 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * DMA engine. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41
42#include <linux/types.h>
43#include <linux/errno.h>
44#include <linux/pci.h>
45#include <linux/ktime.h>
46#include <linux/netdevice.h>
47#include <linux/etherdevice.h>
48#include <linux/if_vlan.h>
49#include <linux/skbuff.h>
50#include <linux/init.h>
51#include <linux/mm.h>
52#include <linux/tcp.h>
53#include <linux/ip.h>
54#include <linux/in.h>
55#include <linux/if_arp.h>
56#include <linux/slab.h>
57#include <linux/prefetch.h>
58
59#include "cpl5_cmd.h"
60#include "sge.h"
61#include "regs.h"
62#include "espi.h"
63
64/* This belongs in if_ether.h */
65#define ETH_P_CPL5 0xf
66
67#define SGE_CMDQ_N 2
68#define SGE_FREELQ_N 2
69#define SGE_CMDQ0_E_N 1024
70#define SGE_CMDQ1_E_N 128
71#define SGE_FREEL_SIZE 4096
72#define SGE_JUMBO_FREEL_SIZE 512
73#define SGE_FREEL_REFILL_THRESH 16
74#define SGE_RESPQ_E_N 1024
75#define SGE_INTRTIMER_NRES 1000
76#define SGE_RX_SM_BUF_SIZE 1536
77#define SGE_TX_DESC_MAX_PLEN 16384
78
79#define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
80
81/*
82 * Period of the TX buffer reclaim timer. This timer does not need to run
83 * frequently as TX buffers are usually reclaimed by new TX packets.
84 */
85#define TX_RECLAIM_PERIOD (HZ / 4)
86
87#define M_CMD_LEN 0x7fffffff
88#define V_CMD_LEN(v) (v)
89#define G_CMD_LEN(v) ((v) & M_CMD_LEN)
90#define V_CMD_GEN1(v) ((v) << 31)
91#define V_CMD_GEN2(v) (v)
92#define F_CMD_DATAVALID (1 << 1)
93#define F_CMD_SOP (1 << 2)
94#define V_CMD_EOP(v) ((v) << 3)
95
96/*
97 * Command queue, receive buffer list, and response queue descriptors.
98 */
99#if defined(__BIG_ENDIAN_BITFIELD)
100struct cmdQ_e {
101 u32 addr_lo;
102 u32 len_gen;
103 u32 flags;
104 u32 addr_hi;
105};
106
107struct freelQ_e {
108 u32 addr_lo;
109 u32 len_gen;
110 u32 gen2;
111 u32 addr_hi;
112};
113
114struct respQ_e {
115 u32 Qsleeping : 4;
116 u32 Cmdq1CreditReturn : 5;
117 u32 Cmdq1DmaComplete : 5;
118 u32 Cmdq0CreditReturn : 5;
119 u32 Cmdq0DmaComplete : 5;
120 u32 FreelistQid : 2;
121 u32 CreditValid : 1;
122 u32 DataValid : 1;
123 u32 Offload : 1;
124 u32 Eop : 1;
125 u32 Sop : 1;
126 u32 GenerationBit : 1;
127 u32 BufferLength;
128};
129#elif defined(__LITTLE_ENDIAN_BITFIELD)
130struct cmdQ_e {
131 u32 len_gen;
132 u32 addr_lo;
133 u32 addr_hi;
134 u32 flags;
135};
136
137struct freelQ_e {
138 u32 len_gen;
139 u32 addr_lo;
140 u32 addr_hi;
141 u32 gen2;
142};
143
144struct respQ_e {
145 u32 BufferLength;
146 u32 GenerationBit : 1;
147 u32 Sop : 1;
148 u32 Eop : 1;
149 u32 Offload : 1;
150 u32 DataValid : 1;
151 u32 CreditValid : 1;
152 u32 FreelistQid : 2;
153 u32 Cmdq0DmaComplete : 5;
154 u32 Cmdq0CreditReturn : 5;
155 u32 Cmdq1DmaComplete : 5;
156 u32 Cmdq1CreditReturn : 5;
157 u32 Qsleeping : 4;
158} ;
159#endif
160
161/*
162 * SW Context Command and Freelist Queue Descriptors
163 */
164struct cmdQ_ce {
165 struct sk_buff *skb;
166 DEFINE_DMA_UNMAP_ADDR(dma_addr);
167 DEFINE_DMA_UNMAP_LEN(dma_len);
168};
169
170struct freelQ_ce {
171 struct sk_buff *skb;
172 DEFINE_DMA_UNMAP_ADDR(dma_addr);
173 DEFINE_DMA_UNMAP_LEN(dma_len);
174};
175
176/*
177 * SW command, freelist and response rings
178 */
179struct cmdQ {
180 unsigned long status; /* HW DMA fetch status */
181 unsigned int in_use; /* # of in-use command descriptors */
182 unsigned int size; /* # of descriptors */
183 unsigned int processed; /* total # of descs HW has processed */
184 unsigned int cleaned; /* total # of descs SW has reclaimed */
185 unsigned int stop_thres; /* SW TX queue suspend threshold */
186 u16 pidx; /* producer index (SW) */
187 u16 cidx; /* consumer index (HW) */
188 u8 genbit; /* current generation (=valid) bit */
189 u8 sop; /* is next entry start of packet? */
190 struct cmdQ_e *entries; /* HW command descriptor Q */
191 struct cmdQ_ce *centries; /* SW command context descriptor Q */
192 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
193 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
194};
195
196struct freelQ {
197 unsigned int credits; /* # of available RX buffers */
198 unsigned int size; /* free list capacity */
199 u16 pidx; /* producer index (SW) */
200 u16 cidx; /* consumer index (HW) */
201 u16 rx_buffer_size; /* Buffer size on this free list */
202 u16 dma_offset; /* DMA offset to align IP headers */
203 u16 recycleq_idx; /* skb recycle q to use */
204 u8 genbit; /* current generation (=valid) bit */
205 struct freelQ_e *entries; /* HW freelist descriptor Q */
206 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
207 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */
208};
209
210struct respQ {
211 unsigned int credits; /* credits to be returned to SGE */
212 unsigned int size; /* # of response Q descriptors */
213 u16 cidx; /* consumer index (SW) */
214 u8 genbit; /* current generation(=valid) bit */
215 struct respQ_e *entries; /* HW response descriptor Q */
216 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */
217};
218
219/* Bit flags for cmdQ.status */
220enum {
221 CMDQ_STAT_RUNNING = 1, /* fetch engine is running */
222 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
223};
224
225/* T204 TX SW scheduler */
226
227/* Per T204 TX port */
228struct sched_port {
229 unsigned int avail; /* available bits - quota */
230 unsigned int drain_bits_per_1024ns; /* drain rate */
231 unsigned int speed; /* drain rate, mbps */
232 unsigned int mtu; /* mtu size */
233 struct sk_buff_head skbq; /* pending skbs */
234};
235
236/* Per T204 device */
237struct sched {
238 ktime_t last_updated; /* last time quotas were computed */
239 unsigned int max_avail; /* max bits to be sent to any port */
240 unsigned int port; /* port index (round robin ports) */
241 unsigned int num; /* num skbs in per port queues */
242 struct sched_port p[MAX_NPORTS];
243 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
244};
245static void restart_sched(unsigned long);
246
247
248/*
249 * Main SGE data structure
250 *
251 * Interrupts are handled by a single CPU and it is likely that on a MP system
252 * the application is migrated to another CPU. In that scenario, we try to
253 * separate the RX(in irq context) and TX state in order to decrease memory
254 * contention.
255 */
256struct sge {
257 struct adapter *adapter; /* adapter backpointer */
258 struct net_device *netdev; /* netdevice backpointer */
259 struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */
260 struct respQ respQ; /* response Q */
261 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */
262 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
263 unsigned int jumbo_fl; /* jumbo freelist Q index */
264 unsigned int intrtimer_nres; /* no-resource interrupt timer */
265 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
266 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
267 struct timer_list espibug_timer;
268 unsigned long espibug_timeout;
269 struct sk_buff *espibug_skb[MAX_NPORTS];
270 u32 sge_control; /* shadow value of sge control reg */
271 struct sge_intr_counts stats;
272 struct sge_port_stats __percpu *port_stats[MAX_NPORTS];
273 struct sched *tx_sched;
274 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
275};
276
277static const u8 ch_mac_addr[ETH_ALEN] = {
278 0x0, 0x7, 0x43, 0x0, 0x0, 0x0
279};
280
281/*
282 * stop tasklet and free all pending skb's
283 */
284static void tx_sched_stop(struct sge *sge)
285{
286 struct sched *s = sge->tx_sched;
287 int i;
288
289 tasklet_kill(&s->sched_tsk);
290
291 for (i = 0; i < MAX_NPORTS; i++)
292 __skb_queue_purge(&s->p[s->port].skbq);
293}
294
295/*
296 * t1_sched_update_parms() is called when the MTU or link speed changes. It
297 * re-computes scheduler parameters to scope with the change.
298 */
299unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
300 unsigned int mtu, unsigned int speed)
301{
302 struct sched *s = sge->tx_sched;
303 struct sched_port *p = &s->p[port];
304 unsigned int max_avail_segs;
305
306 pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
307 if (speed)
308 p->speed = speed;
309 if (mtu)
310 p->mtu = mtu;
311
312 if (speed || mtu) {
313 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
314 do_div(drain, (p->mtu + 50) * 1000);
315 p->drain_bits_per_1024ns = (unsigned int) drain;
316
317 if (p->speed < 1000)
318 p->drain_bits_per_1024ns =
319 90 * p->drain_bits_per_1024ns / 100;
320 }
321
322 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
323 p->drain_bits_per_1024ns -= 16;
324 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
325 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
326 } else {
327 s->max_avail = 16384;
328 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
329 }
330
331 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
332 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
333 p->speed, s->max_avail, max_avail_segs,
334 p->drain_bits_per_1024ns);
335
336 return max_avail_segs * (p->mtu - 40);
337}
338
339#if 0
340
341/*
342 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
343 * data that can be pushed per port.
344 */
345void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
346{
347 struct sched *s = sge->tx_sched;
348 unsigned int i;
349
350 s->max_avail = val;
351 for (i = 0; i < MAX_NPORTS; i++)
352 t1_sched_update_parms(sge, i, 0, 0);
353}
354
355/*
356 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
357 * is draining.
358 */
359void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
360 unsigned int val)
361{
362 struct sched *s = sge->tx_sched;
363 struct sched_port *p = &s->p[port];
364 p->drain_bits_per_1024ns = val * 1024 / 1000;
365 t1_sched_update_parms(sge, port, 0, 0);
366}
367
368#endif /* 0 */
369
370
371/*
372 * get_clock() implements a ns clock (see ktime_get)
373 */
374static inline ktime_t get_clock(void)
375{
376 struct timespec ts;
377
378 ktime_get_ts(&ts);
379 return timespec_to_ktime(ts);
380}
381
382/*
383 * tx_sched_init() allocates resources and does basic initialization.
384 */
385static int tx_sched_init(struct sge *sge)
386{
387 struct sched *s;
388 int i;
389
390 s = kzalloc(sizeof (struct sched), GFP_KERNEL);
391 if (!s)
392 return -ENOMEM;
393
394 pr_debug("tx_sched_init\n");
395 tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
396 sge->tx_sched = s;
397
398 for (i = 0; i < MAX_NPORTS; i++) {
399 skb_queue_head_init(&s->p[i].skbq);
400 t1_sched_update_parms(sge, i, 1500, 1000);
401 }
402
403 return 0;
404}
405
406/*
407 * sched_update_avail() computes the delta since the last time it was called
408 * and updates the per port quota (number of bits that can be sent to the any
409 * port).
410 */
411static inline int sched_update_avail(struct sge *sge)
412{
413 struct sched *s = sge->tx_sched;
414 ktime_t now = get_clock();
415 unsigned int i;
416 long long delta_time_ns;
417
418 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
419
420 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
421 if (delta_time_ns < 15000)
422 return 0;
423
424 for (i = 0; i < MAX_NPORTS; i++) {
425 struct sched_port *p = &s->p[i];
426 unsigned int delta_avail;
427
428 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
429 p->avail = min(p->avail + delta_avail, s->max_avail);
430 }
431
432 s->last_updated = now;
433
434 return 1;
435}
436
437/*
438 * sched_skb() is called from two different places. In the tx path, any
439 * packet generating load on an output port will call sched_skb()
440 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
441 * context (skb == NULL).
442 * The scheduler only returns a skb (which will then be sent) if the
443 * length of the skb is <= the current quota of the output port.
444 */
445static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
446 unsigned int credits)
447{
448 struct sched *s = sge->tx_sched;
449 struct sk_buff_head *skbq;
450 unsigned int i, len, update = 1;
451
452 pr_debug("sched_skb %p\n", skb);
453 if (!skb) {
454 if (!s->num)
455 return NULL;
456 } else {
457 skbq = &s->p[skb->dev->if_port].skbq;
458 __skb_queue_tail(skbq, skb);
459 s->num++;
460 skb = NULL;
461 }
462
463 if (credits < MAX_SKB_FRAGS + 1)
464 goto out;
465
466again:
467 for (i = 0; i < MAX_NPORTS; i++) {
468 s->port = (s->port + 1) & (MAX_NPORTS - 1);
469 skbq = &s->p[s->port].skbq;
470
471 skb = skb_peek(skbq);
472
473 if (!skb)
474 continue;
475
476 len = skb->len;
477 if (len <= s->p[s->port].avail) {
478 s->p[s->port].avail -= len;
479 s->num--;
480 __skb_unlink(skb, skbq);
481 goto out;
482 }
483 skb = NULL;
484 }
485
486 if (update-- && sched_update_avail(sge))
487 goto again;
488
489out:
490 /* If there are more pending skbs, we use the hardware to schedule us
491 * again.
492 */
493 if (s->num && !skb) {
494 struct cmdQ *q = &sge->cmdQ[0];
495 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
496 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
497 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
498 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
499 }
500 }
501 pr_debug("sched_skb ret %p\n", skb);
502
503 return skb;
504}
505
506/*
507 * PIO to indicate that memory mapped Q contains valid descriptor(s).
508 */
509static inline void doorbell_pio(struct adapter *adapter, u32 val)
510{
511 wmb();
512 writel(val, adapter->regs + A_SG_DOORBELL);
513}
514
515/*
516 * Frees all RX buffers on the freelist Q. The caller must make sure that
517 * the SGE is turned off before calling this function.
518 */
519static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
520{
521 unsigned int cidx = q->cidx;
522
523 while (q->credits--) {
524 struct freelQ_ce *ce = &q->centries[cidx];
525
526 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
527 dma_unmap_len(ce, dma_len),
528 PCI_DMA_FROMDEVICE);
529 dev_kfree_skb(ce->skb);
530 ce->skb = NULL;
531 if (++cidx == q->size)
532 cidx = 0;
533 }
534}
535
536/*
537 * Free RX free list and response queue resources.
538 */
539static void free_rx_resources(struct sge *sge)
540{
541 struct pci_dev *pdev = sge->adapter->pdev;
542 unsigned int size, i;
543
544 if (sge->respQ.entries) {
545 size = sizeof(struct respQ_e) * sge->respQ.size;
546 pci_free_consistent(pdev, size, sge->respQ.entries,
547 sge->respQ.dma_addr);
548 }
549
550 for (i = 0; i < SGE_FREELQ_N; i++) {
551 struct freelQ *q = &sge->freelQ[i];
552
553 if (q->centries) {
554 free_freelQ_buffers(pdev, q);
555 kfree(q->centries);
556 }
557 if (q->entries) {
558 size = sizeof(struct freelQ_e) * q->size;
559 pci_free_consistent(pdev, size, q->entries,
560 q->dma_addr);
561 }
562 }
563}
564
565/*
566 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
567 * response queue.
568 */
569static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
570{
571 struct pci_dev *pdev = sge->adapter->pdev;
572 unsigned int size, i;
573
574 for (i = 0; i < SGE_FREELQ_N; i++) {
575 struct freelQ *q = &sge->freelQ[i];
576
577 q->genbit = 1;
578 q->size = p->freelQ_size[i];
579 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
580 size = sizeof(struct freelQ_e) * q->size;
581 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
582 if (!q->entries)
583 goto err_no_mem;
584
585 size = sizeof(struct freelQ_ce) * q->size;
586 q->centries = kzalloc(size, GFP_KERNEL);
587 if (!q->centries)
588 goto err_no_mem;
589 }
590
591 /*
592 * Calculate the buffer sizes for the two free lists. FL0 accommodates
593 * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
594 * including all the sk_buff overhead.
595 *
596 * Note: For T2 FL0 and FL1 are reversed.
597 */
598 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
599 sizeof(struct cpl_rx_data) +
600 sge->freelQ[!sge->jumbo_fl].dma_offset;
601
602 size = (16 * 1024) -
603 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
604
605 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
606
607 /*
608 * Setup which skb recycle Q should be used when recycling buffers from
609 * each free list.
610 */
611 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
612 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
613
614 sge->respQ.genbit = 1;
615 sge->respQ.size = SGE_RESPQ_E_N;
616 sge->respQ.credits = 0;
617 size = sizeof(struct respQ_e) * sge->respQ.size;
618 sge->respQ.entries =
619 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
620 if (!sge->respQ.entries)
621 goto err_no_mem;
622 return 0;
623
624err_no_mem:
625 free_rx_resources(sge);
626 return -ENOMEM;
627}
628
629/*
630 * Reclaims n TX descriptors and frees the buffers associated with them.
631 */
632static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
633{
634 struct cmdQ_ce *ce;
635 struct pci_dev *pdev = sge->adapter->pdev;
636 unsigned int cidx = q->cidx;
637
638 q->in_use -= n;
639 ce = &q->centries[cidx];
640 while (n--) {
641 if (likely(dma_unmap_len(ce, dma_len))) {
642 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
643 dma_unmap_len(ce, dma_len),
644 PCI_DMA_TODEVICE);
645 if (q->sop)
646 q->sop = 0;
647 }
648 if (ce->skb) {
649 dev_kfree_skb_any(ce->skb);
650 q->sop = 1;
651 }
652 ce++;
653 if (++cidx == q->size) {
654 cidx = 0;
655 ce = q->centries;
656 }
657 }
658 q->cidx = cidx;
659}
660
661/*
662 * Free TX resources.
663 *
664 * Assumes that SGE is stopped and all interrupts are disabled.
665 */
666static void free_tx_resources(struct sge *sge)
667{
668 struct pci_dev *pdev = sge->adapter->pdev;
669 unsigned int size, i;
670
671 for (i = 0; i < SGE_CMDQ_N; i++) {
672 struct cmdQ *q = &sge->cmdQ[i];
673
674 if (q->centries) {
675 if (q->in_use)
676 free_cmdQ_buffers(sge, q, q->in_use);
677 kfree(q->centries);
678 }
679 if (q->entries) {
680 size = sizeof(struct cmdQ_e) * q->size;
681 pci_free_consistent(pdev, size, q->entries,
682 q->dma_addr);
683 }
684 }
685}
686
687/*
688 * Allocates basic TX resources, consisting of memory mapped command Qs.
689 */
690static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
691{
692 struct pci_dev *pdev = sge->adapter->pdev;
693 unsigned int size, i;
694
695 for (i = 0; i < SGE_CMDQ_N; i++) {
696 struct cmdQ *q = &sge->cmdQ[i];
697
698 q->genbit = 1;
699 q->sop = 1;
700 q->size = p->cmdQ_size[i];
701 q->in_use = 0;
702 q->status = 0;
703 q->processed = q->cleaned = 0;
704 q->stop_thres = 0;
705 spin_lock_init(&q->lock);
706 size = sizeof(struct cmdQ_e) * q->size;
707 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
708 if (!q->entries)
709 goto err_no_mem;
710
711 size = sizeof(struct cmdQ_ce) * q->size;
712 q->centries = kzalloc(size, GFP_KERNEL);
713 if (!q->centries)
714 goto err_no_mem;
715 }
716
717 /*
718 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
719 * only. For queue 0 set the stop threshold so we can handle one more
720 * packet from each port, plus reserve an additional 24 entries for
721 * Ethernet packets only. Queue 1 never suspends nor do we reserve
722 * space for Ethernet packets.
723 */
724 sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
725 (MAX_SKB_FRAGS + 1);
726 return 0;
727
728err_no_mem:
729 free_tx_resources(sge);
730 return -ENOMEM;
731}
732
733static inline void setup_ring_params(struct adapter *adapter, u64 addr,
734 u32 size, int base_reg_lo,
735 int base_reg_hi, int size_reg)
736{
737 writel((u32)addr, adapter->regs + base_reg_lo);
738 writel(addr >> 32, adapter->regs + base_reg_hi);
739 writel(size, adapter->regs + size_reg);
740}
741
742/*
743 * Enable/disable VLAN acceleration.
744 */
745void t1_vlan_mode(struct adapter *adapter, u32 features)
746{
747 struct sge *sge = adapter->sge;
748
749 if (features & NETIF_F_HW_VLAN_RX)
750 sge->sge_control |= F_VLAN_XTRACT;
751 else
752 sge->sge_control &= ~F_VLAN_XTRACT;
753 if (adapter->open_device_map) {
754 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
755 readl(adapter->regs + A_SG_CONTROL); /* flush */
756 }
757}
758
759/*
760 * Programs the various SGE registers. However, the engine is not yet enabled,
761 * but sge->sge_control is setup and ready to go.
762 */
763static void configure_sge(struct sge *sge, struct sge_params *p)
764{
765 struct adapter *ap = sge->adapter;
766
767 writel(0, ap->regs + A_SG_CONTROL);
768 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
769 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
770 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
771 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
772 setup_ring_params(ap, sge->freelQ[0].dma_addr,
773 sge->freelQ[0].size, A_SG_FL0BASELWR,
774 A_SG_FL0BASEUPR, A_SG_FL0SIZE);
775 setup_ring_params(ap, sge->freelQ[1].dma_addr,
776 sge->freelQ[1].size, A_SG_FL1BASELWR,
777 A_SG_FL1BASEUPR, A_SG_FL1SIZE);
778
779 /* The threshold comparison uses <. */
780 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
781
782 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
783 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
784 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
785
786 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
787 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
788 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
789 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
790
791#if defined(__BIG_ENDIAN_BITFIELD)
792 sge->sge_control |= F_ENABLE_BIG_ENDIAN;
793#endif
794
795 /* Initialize no-resource timer */
796 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
797
798 t1_sge_set_coalesce_params(sge, p);
799}
800
801/*
802 * Return the payload capacity of the jumbo free-list buffers.
803 */
804static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
805{
806 return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
807 sge->freelQ[sge->jumbo_fl].dma_offset -
808 sizeof(struct cpl_rx_data);
809}
810
811/*
812 * Frees all SGE related resources and the sge structure itself
813 */
814void t1_sge_destroy(struct sge *sge)
815{
816 int i;
817
818 for_each_port(sge->adapter, i)
819 free_percpu(sge->port_stats[i]);
820
821 kfree(sge->tx_sched);
822 free_tx_resources(sge);
823 free_rx_resources(sge);
824 kfree(sge);
825}
826
827/*
828 * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
829 * context Q) until the Q is full or alloc_skb fails.
830 *
831 * It is possible that the generation bits already match, indicating that the
832 * buffer is already valid and nothing needs to be done. This happens when we
833 * copied a received buffer into a new sk_buff during the interrupt processing.
834 *
835 * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
836 * we specify a RX_OFFSET in order to make sure that the IP header is 4B
837 * aligned.
838 */
839static void refill_free_list(struct sge *sge, struct freelQ *q)
840{
841 struct pci_dev *pdev = sge->adapter->pdev;
842 struct freelQ_ce *ce = &q->centries[q->pidx];
843 struct freelQ_e *e = &q->entries[q->pidx];
844 unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
845
846 while (q->credits < q->size) {
847 struct sk_buff *skb;
848 dma_addr_t mapping;
849
850 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
851 if (!skb)
852 break;
853
854 skb_reserve(skb, q->dma_offset);
855 mapping = pci_map_single(pdev, skb->data, dma_len,
856 PCI_DMA_FROMDEVICE);
857 skb_reserve(skb, sge->rx_pkt_pad);
858
859 ce->skb = skb;
860 dma_unmap_addr_set(ce, dma_addr, mapping);
861 dma_unmap_len_set(ce, dma_len, dma_len);
862 e->addr_lo = (u32)mapping;
863 e->addr_hi = (u64)mapping >> 32;
864 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
865 wmb();
866 e->gen2 = V_CMD_GEN2(q->genbit);
867
868 e++;
869 ce++;
870 if (++q->pidx == q->size) {
871 q->pidx = 0;
872 q->genbit ^= 1;
873 ce = q->centries;
874 e = q->entries;
875 }
876 q->credits++;
877 }
878}
879
880/*
881 * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
882 * of both rings, we go into 'few interrupt mode' in order to give the system
883 * time to free up resources.
884 */
885static void freelQs_empty(struct sge *sge)
886{
887 struct adapter *adapter = sge->adapter;
888 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
889 u32 irqholdoff_reg;
890
891 refill_free_list(sge, &sge->freelQ[0]);
892 refill_free_list(sge, &sge->freelQ[1]);
893
894 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
895 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
896 irq_reg |= F_FL_EXHAUSTED;
897 irqholdoff_reg = sge->fixed_intrtimer;
898 } else {
899 /* Clear the F_FL_EXHAUSTED interrupts for now */
900 irq_reg &= ~F_FL_EXHAUSTED;
901 irqholdoff_reg = sge->intrtimer_nres;
902 }
903 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
904 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
905
906 /* We reenable the Qs to force a freelist GTS interrupt later */
907 doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
908}
909
910#define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
911#define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
912#define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
913 F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
914
915/*
916 * Disable SGE Interrupts
917 */
918void t1_sge_intr_disable(struct sge *sge)
919{
920 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
921
922 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
923 writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
924}
925
926/*
927 * Enable SGE interrupts.
928 */
929void t1_sge_intr_enable(struct sge *sge)
930{
931 u32 en = SGE_INT_ENABLE;
932 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
933
934 if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO)
935 en &= ~F_PACKET_TOO_BIG;
936 writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
937 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
938}
939
940/*
941 * Clear SGE interrupts.
942 */
943void t1_sge_intr_clear(struct sge *sge)
944{
945 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
946 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
947}
948
949/*
950 * SGE 'Error' interrupt handler
951 */
952int t1_sge_intr_error_handler(struct sge *sge)
953{
954 struct adapter *adapter = sge->adapter;
955 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
956
957 if (adapter->port[0].dev->hw_features & NETIF_F_TSO)
958 cause &= ~F_PACKET_TOO_BIG;
959 if (cause & F_RESPQ_EXHAUSTED)
960 sge->stats.respQ_empty++;
961 if (cause & F_RESPQ_OVERFLOW) {
962 sge->stats.respQ_overflow++;
963 pr_alert("%s: SGE response queue overflow\n",
964 adapter->name);
965 }
966 if (cause & F_FL_EXHAUSTED) {
967 sge->stats.freelistQ_empty++;
968 freelQs_empty(sge);
969 }
970 if (cause & F_PACKET_TOO_BIG) {
971 sge->stats.pkt_too_big++;
972 pr_alert("%s: SGE max packet size exceeded\n",
973 adapter->name);
974 }
975 if (cause & F_PACKET_MISMATCH) {
976 sge->stats.pkt_mismatch++;
977 pr_alert("%s: SGE packet mismatch\n", adapter->name);
978 }
979 if (cause & SGE_INT_FATAL)
980 t1_fatal_err(adapter);
981
982 writel(cause, adapter->regs + A_SG_INT_CAUSE);
983 return 0;
984}
985
986const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
987{
988 return &sge->stats;
989}
990
991void t1_sge_get_port_stats(const struct sge *sge, int port,
992 struct sge_port_stats *ss)
993{
994 int cpu;
995
996 memset(ss, 0, sizeof(*ss));
997 for_each_possible_cpu(cpu) {
998 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
999
1000 ss->rx_cso_good += st->rx_cso_good;
1001 ss->tx_cso += st->tx_cso;
1002 ss->tx_tso += st->tx_tso;
1003 ss->tx_need_hdrroom += st->tx_need_hdrroom;
1004 ss->vlan_xtract += st->vlan_xtract;
1005 ss->vlan_insert += st->vlan_insert;
1006 }
1007}
1008
1009/**
1010 * recycle_fl_buf - recycle a free list buffer
1011 * @fl: the free list
1012 * @idx: index of buffer to recycle
1013 *
1014 * Recycles the specified buffer on the given free list by adding it at
1015 * the next available slot on the list.
1016 */
1017static void recycle_fl_buf(struct freelQ *fl, int idx)
1018{
1019 struct freelQ_e *from = &fl->entries[idx];
1020 struct freelQ_e *to = &fl->entries[fl->pidx];
1021
1022 fl->centries[fl->pidx] = fl->centries[idx];
1023 to->addr_lo = from->addr_lo;
1024 to->addr_hi = from->addr_hi;
1025 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1026 wmb();
1027 to->gen2 = V_CMD_GEN2(fl->genbit);
1028 fl->credits++;
1029
1030 if (++fl->pidx == fl->size) {
1031 fl->pidx = 0;
1032 fl->genbit ^= 1;
1033 }
1034}
1035
1036static int copybreak __read_mostly = 256;
1037module_param(copybreak, int, 0);
1038MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1039
1040/**
1041 * get_packet - return the next ingress packet buffer
1042 * @pdev: the PCI device that received the packet
1043 * @fl: the SGE free list holding the packet
1044 * @len: the actual packet length, excluding any SGE padding
1045 *
1046 * Get the next packet from a free list and complete setup of the
1047 * sk_buff. If the packet is small we make a copy and recycle the
1048 * original buffer, otherwise we use the original buffer itself. If a
1049 * positive drop threshold is supplied packets are dropped and their
1050 * buffers recycled if (a) the number of remaining buffers is under the
1051 * threshold and the packet is too big to copy, or (b) the packet should
1052 * be copied but there is no memory for the copy.
1053 */
1054static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1055 struct freelQ *fl, unsigned int len)
1056{
1057 struct sk_buff *skb;
1058 const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1059
1060 if (len < copybreak) {
1061 skb = alloc_skb(len + 2, GFP_ATOMIC);
1062 if (!skb)
1063 goto use_orig_buf;
1064
1065 skb_reserve(skb, 2); /* align IP header */
1066 skb_put(skb, len);
1067 pci_dma_sync_single_for_cpu(pdev,
1068 dma_unmap_addr(ce, dma_addr),
1069 dma_unmap_len(ce, dma_len),
1070 PCI_DMA_FROMDEVICE);
1071 skb_copy_from_linear_data(ce->skb, skb->data, len);
1072 pci_dma_sync_single_for_device(pdev,
1073 dma_unmap_addr(ce, dma_addr),
1074 dma_unmap_len(ce, dma_len),
1075 PCI_DMA_FROMDEVICE);
1076 recycle_fl_buf(fl, fl->cidx);
1077 return skb;
1078 }
1079
1080use_orig_buf:
1081 if (fl->credits < 2) {
1082 recycle_fl_buf(fl, fl->cidx);
1083 return NULL;
1084 }
1085
1086 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
1087 dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1088 skb = ce->skb;
1089 prefetch(skb->data);
1090
1091 skb_put(skb, len);
1092 return skb;
1093}
1094
1095/**
1096 * unexpected_offload - handle an unexpected offload packet
1097 * @adapter: the adapter
1098 * @fl: the free list that received the packet
1099 *
1100 * Called when we receive an unexpected offload packet (e.g., the TOE
1101 * function is disabled or the card is a NIC). Prints a message and
1102 * recycles the buffer.
1103 */
1104static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1105{
1106 struct freelQ_ce *ce = &fl->centries[fl->cidx];
1107 struct sk_buff *skb = ce->skb;
1108
1109 pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr),
1110 dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1111 pr_err("%s: unexpected offload packet, cmd %u\n",
1112 adapter->name, *skb->data);
1113 recycle_fl_buf(fl, fl->cidx);
1114}
1115
1116/*
1117 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1118 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1119 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1120 * Note that the *_large_page_tx_descs stuff will be optimized out when
1121 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1122 *
1123 * compute_large_page_descs() computes how many additional descriptors are
1124 * required to break down the stack's request.
1125 */
1126static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1127{
1128 unsigned int count = 0;
1129
1130 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1131 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1132 unsigned int i, len = skb_headlen(skb);
1133 while (len > SGE_TX_DESC_MAX_PLEN) {
1134 count++;
1135 len -= SGE_TX_DESC_MAX_PLEN;
1136 }
1137 for (i = 0; nfrags--; i++) {
1138 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1139 len = frag->size;
1140 while (len > SGE_TX_DESC_MAX_PLEN) {
1141 count++;
1142 len -= SGE_TX_DESC_MAX_PLEN;
1143 }
1144 }
1145 }
1146 return count;
1147}
1148
1149/*
1150 * Write a cmdQ entry.
1151 *
1152 * Since this function writes the 'flags' field, it must not be used to
1153 * write the first cmdQ entry.
1154 */
1155static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1156 unsigned int len, unsigned int gen,
1157 unsigned int eop)
1158{
1159 BUG_ON(len > SGE_TX_DESC_MAX_PLEN);
1160
1161 e->addr_lo = (u32)mapping;
1162 e->addr_hi = (u64)mapping >> 32;
1163 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1164 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1165}
1166
1167/*
1168 * See comment for previous function.
1169 *
1170 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1171 * *desc_len exceeds HW's capability.
1172 */
1173static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1174 struct cmdQ_e **e,
1175 struct cmdQ_ce **ce,
1176 unsigned int *gen,
1177 dma_addr_t *desc_mapping,
1178 unsigned int *desc_len,
1179 unsigned int nfrags,
1180 struct cmdQ *q)
1181{
1182 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1183 struct cmdQ_e *e1 = *e;
1184 struct cmdQ_ce *ce1 = *ce;
1185
1186 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1187 *desc_len -= SGE_TX_DESC_MAX_PLEN;
1188 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1189 *gen, nfrags == 0 && *desc_len == 0);
1190 ce1->skb = NULL;
1191 dma_unmap_len_set(ce1, dma_len, 0);
1192 *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1193 if (*desc_len) {
1194 ce1++;
1195 e1++;
1196 if (++pidx == q->size) {
1197 pidx = 0;
1198 *gen ^= 1;
1199 ce1 = q->centries;
1200 e1 = q->entries;
1201 }
1202 }
1203 }
1204 *e = e1;
1205 *ce = ce1;
1206 }
1207 return pidx;
1208}
1209
1210/*
1211 * Write the command descriptors to transmit the given skb starting at
1212 * descriptor pidx with the given generation.
1213 */
1214static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1215 unsigned int pidx, unsigned int gen,
1216 struct cmdQ *q)
1217{
1218 dma_addr_t mapping, desc_mapping;
1219 struct cmdQ_e *e, *e1;
1220 struct cmdQ_ce *ce;
1221 unsigned int i, flags, first_desc_len, desc_len,
1222 nfrags = skb_shinfo(skb)->nr_frags;
1223
1224 e = e1 = &q->entries[pidx];
1225 ce = &q->centries[pidx];
1226
1227 mapping = pci_map_single(adapter->pdev, skb->data,
1228 skb_headlen(skb), PCI_DMA_TODEVICE);
1229
1230 desc_mapping = mapping;
1231 desc_len = skb_headlen(skb);
1232
1233 flags = F_CMD_DATAVALID | F_CMD_SOP |
1234 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1235 V_CMD_GEN2(gen);
1236 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1237 desc_len : SGE_TX_DESC_MAX_PLEN;
1238 e->addr_lo = (u32)desc_mapping;
1239 e->addr_hi = (u64)desc_mapping >> 32;
1240 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1241 ce->skb = NULL;
1242 dma_unmap_len_set(ce, dma_len, 0);
1243
1244 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1245 desc_len > SGE_TX_DESC_MAX_PLEN) {
1246 desc_mapping += first_desc_len;
1247 desc_len -= first_desc_len;
1248 e1++;
1249 ce++;
1250 if (++pidx == q->size) {
1251 pidx = 0;
1252 gen ^= 1;
1253 e1 = q->entries;
1254 ce = q->centries;
1255 }
1256 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1257 &desc_mapping, &desc_len,
1258 nfrags, q);
1259
1260 if (likely(desc_len))
1261 write_tx_desc(e1, desc_mapping, desc_len, gen,
1262 nfrags == 0);
1263 }
1264
1265 ce->skb = NULL;
1266 dma_unmap_addr_set(ce, dma_addr, mapping);
1267 dma_unmap_len_set(ce, dma_len, skb_headlen(skb));
1268
1269 for (i = 0; nfrags--; i++) {
1270 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1271 e1++;
1272 ce++;
1273 if (++pidx == q->size) {
1274 pidx = 0;
1275 gen ^= 1;
1276 e1 = q->entries;
1277 ce = q->centries;
1278 }
1279
1280 mapping = pci_map_page(adapter->pdev, frag->page,
1281 frag->page_offset, frag->size,
1282 PCI_DMA_TODEVICE);
1283 desc_mapping = mapping;
1284 desc_len = frag->size;
1285
1286 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1287 &desc_mapping, &desc_len,
1288 nfrags, q);
1289 if (likely(desc_len))
1290 write_tx_desc(e1, desc_mapping, desc_len, gen,
1291 nfrags == 0);
1292 ce->skb = NULL;
1293 dma_unmap_addr_set(ce, dma_addr, mapping);
1294 dma_unmap_len_set(ce, dma_len, frag->size);
1295 }
1296 ce->skb = skb;
1297 wmb();
1298 e->flags = flags;
1299}
1300
1301/*
1302 * Clean up completed Tx buffers.
1303 */
1304static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1305{
1306 unsigned int reclaim = q->processed - q->cleaned;
1307
1308 if (reclaim) {
1309 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1310 q->processed, q->cleaned);
1311 free_cmdQ_buffers(sge, q, reclaim);
1312 q->cleaned += reclaim;
1313 }
1314}
1315
1316/*
1317 * Called from tasklet. Checks the scheduler for any
1318 * pending skbs that can be sent.
1319 */
1320static void restart_sched(unsigned long arg)
1321{
1322 struct sge *sge = (struct sge *) arg;
1323 struct adapter *adapter = sge->adapter;
1324 struct cmdQ *q = &sge->cmdQ[0];
1325 struct sk_buff *skb;
1326 unsigned int credits, queued_skb = 0;
1327
1328 spin_lock(&q->lock);
1329 reclaim_completed_tx(sge, q);
1330
1331 credits = q->size - q->in_use;
1332 pr_debug("restart_sched credits=%d\n", credits);
1333 while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1334 unsigned int genbit, pidx, count;
1335 count = 1 + skb_shinfo(skb)->nr_frags;
1336 count += compute_large_page_tx_descs(skb);
1337 q->in_use += count;
1338 genbit = q->genbit;
1339 pidx = q->pidx;
1340 q->pidx += count;
1341 if (q->pidx >= q->size) {
1342 q->pidx -= q->size;
1343 q->genbit ^= 1;
1344 }
1345 write_tx_descs(adapter, skb, pidx, genbit, q);
1346 credits = q->size - q->in_use;
1347 queued_skb = 1;
1348 }
1349
1350 if (queued_skb) {
1351 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1352 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1353 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1354 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1355 }
1356 }
1357 spin_unlock(&q->lock);
1358}
1359
1360/**
1361 * sge_rx - process an ingress ethernet packet
1362 * @sge: the sge structure
1363 * @fl: the free list that contains the packet buffer
1364 * @len: the packet length
1365 *
1366 * Process an ingress ethernet pakcet and deliver it to the stack.
1367 */
1368static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1369{
1370 struct sk_buff *skb;
1371 const struct cpl_rx_pkt *p;
1372 struct adapter *adapter = sge->adapter;
1373 struct sge_port_stats *st;
1374 struct net_device *dev;
1375
1376 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1377 if (unlikely(!skb)) {
1378 sge->stats.rx_drops++;
1379 return;
1380 }
1381
1382 p = (const struct cpl_rx_pkt *) skb->data;
1383 if (p->iff >= adapter->params.nports) {
1384 kfree_skb(skb);
1385 return;
1386 }
1387 __skb_pull(skb, sizeof(*p));
1388
1389 st = this_cpu_ptr(sge->port_stats[p->iff]);
1390 dev = adapter->port[p->iff].dev;
1391
1392 skb->protocol = eth_type_trans(skb, dev);
1393 if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff &&
1394 skb->protocol == htons(ETH_P_IP) &&
1395 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1396 ++st->rx_cso_good;
1397 skb->ip_summed = CHECKSUM_UNNECESSARY;
1398 } else
1399 skb_checksum_none_assert(skb);
1400
1401 if (p->vlan_valid) {
1402 st->vlan_xtract++;
1403 __vlan_hwaccel_put_tag(skb, ntohs(p->vlan));
1404 }
1405 netif_receive_skb(skb);
1406}
1407
1408/*
1409 * Returns true if a command queue has enough available descriptors that
1410 * we can resume Tx operation after temporarily disabling its packet queue.
1411 */
1412static inline int enough_free_Tx_descs(const struct cmdQ *q)
1413{
1414 unsigned int r = q->processed - q->cleaned;
1415
1416 return q->in_use - r < (q->size >> 1);
1417}
1418
1419/*
1420 * Called when sufficient space has become available in the SGE command queues
1421 * after the Tx packet schedulers have been suspended to restart the Tx path.
1422 */
1423static void restart_tx_queues(struct sge *sge)
1424{
1425 struct adapter *adap = sge->adapter;
1426 int i;
1427
1428 if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1429 return;
1430
1431 for_each_port(adap, i) {
1432 struct net_device *nd = adap->port[i].dev;
1433
1434 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1435 netif_running(nd)) {
1436 sge->stats.cmdQ_restarted[2]++;
1437 netif_wake_queue(nd);
1438 }
1439 }
1440}
1441
1442/*
1443 * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1444 * information.
1445 */
1446static unsigned int update_tx_info(struct adapter *adapter,
1447 unsigned int flags,
1448 unsigned int pr0)
1449{
1450 struct sge *sge = adapter->sge;
1451 struct cmdQ *cmdq = &sge->cmdQ[0];
1452
1453 cmdq->processed += pr0;
1454 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1455 freelQs_empty(sge);
1456 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1457 }
1458 if (flags & F_CMDQ0_ENABLE) {
1459 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1460
1461 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1462 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1463 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1464 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1465 }
1466 if (sge->tx_sched)
1467 tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1468
1469 flags &= ~F_CMDQ0_ENABLE;
1470 }
1471
1472 if (unlikely(sge->stopped_tx_queues != 0))
1473 restart_tx_queues(sge);
1474
1475 return flags;
1476}
1477
1478/*
1479 * Process SGE responses, up to the supplied budget. Returns the number of
1480 * responses processed. A negative budget is effectively unlimited.
1481 */
1482static int process_responses(struct adapter *adapter, int budget)
1483{
1484 struct sge *sge = adapter->sge;
1485 struct respQ *q = &sge->respQ;
1486 struct respQ_e *e = &q->entries[q->cidx];
1487 int done = 0;
1488 unsigned int flags = 0;
1489 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1490
1491 while (done < budget && e->GenerationBit == q->genbit) {
1492 flags |= e->Qsleeping;
1493
1494 cmdq_processed[0] += e->Cmdq0CreditReturn;
1495 cmdq_processed[1] += e->Cmdq1CreditReturn;
1496
1497 /* We batch updates to the TX side to avoid cacheline
1498 * ping-pong of TX state information on MP where the sender
1499 * might run on a different CPU than this function...
1500 */
1501 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1502 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1503 cmdq_processed[0] = 0;
1504 }
1505
1506 if (unlikely(cmdq_processed[1] > 16)) {
1507 sge->cmdQ[1].processed += cmdq_processed[1];
1508 cmdq_processed[1] = 0;
1509 }
1510
1511 if (likely(e->DataValid)) {
1512 struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1513
1514 BUG_ON(!e->Sop || !e->Eop);
1515 if (unlikely(e->Offload))
1516 unexpected_offload(adapter, fl);
1517 else
1518 sge_rx(sge, fl, e->BufferLength);
1519
1520 ++done;
1521
1522 /*
1523 * Note: this depends on each packet consuming a
1524 * single free-list buffer; cf. the BUG above.
1525 */
1526 if (++fl->cidx == fl->size)
1527 fl->cidx = 0;
1528 prefetch(fl->centries[fl->cidx].skb);
1529
1530 if (unlikely(--fl->credits <
1531 fl->size - SGE_FREEL_REFILL_THRESH))
1532 refill_free_list(sge, fl);
1533 } else
1534 sge->stats.pure_rsps++;
1535
1536 e++;
1537 if (unlikely(++q->cidx == q->size)) {
1538 q->cidx = 0;
1539 q->genbit ^= 1;
1540 e = q->entries;
1541 }
1542 prefetch(e);
1543
1544 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1545 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1546 q->credits = 0;
1547 }
1548 }
1549
1550 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1551 sge->cmdQ[1].processed += cmdq_processed[1];
1552
1553 return done;
1554}
1555
1556static inline int responses_pending(const struct adapter *adapter)
1557{
1558 const struct respQ *Q = &adapter->sge->respQ;
1559 const struct respQ_e *e = &Q->entries[Q->cidx];
1560
1561 return e->GenerationBit == Q->genbit;
1562}
1563
1564/*
1565 * A simpler version of process_responses() that handles only pure (i.e.,
1566 * non data-carrying) responses. Such respones are too light-weight to justify
1567 * calling a softirq when using NAPI, so we handle them specially in hard
1568 * interrupt context. The function is called with a pointer to a response,
1569 * which the caller must ensure is a valid pure response. Returns 1 if it
1570 * encounters a valid data-carrying response, 0 otherwise.
1571 */
1572static int process_pure_responses(struct adapter *adapter)
1573{
1574 struct sge *sge = adapter->sge;
1575 struct respQ *q = &sge->respQ;
1576 struct respQ_e *e = &q->entries[q->cidx];
1577 const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1578 unsigned int flags = 0;
1579 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1580
1581 prefetch(fl->centries[fl->cidx].skb);
1582 if (e->DataValid)
1583 return 1;
1584
1585 do {
1586 flags |= e->Qsleeping;
1587
1588 cmdq_processed[0] += e->Cmdq0CreditReturn;
1589 cmdq_processed[1] += e->Cmdq1CreditReturn;
1590
1591 e++;
1592 if (unlikely(++q->cidx == q->size)) {
1593 q->cidx = 0;
1594 q->genbit ^= 1;
1595 e = q->entries;
1596 }
1597 prefetch(e);
1598
1599 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1600 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1601 q->credits = 0;
1602 }
1603 sge->stats.pure_rsps++;
1604 } while (e->GenerationBit == q->genbit && !e->DataValid);
1605
1606 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1607 sge->cmdQ[1].processed += cmdq_processed[1];
1608
1609 return e->GenerationBit == q->genbit;
1610}
1611
1612/*
1613 * Handler for new data events when using NAPI. This does not need any locking
1614 * or protection from interrupts as data interrupts are off at this point and
1615 * other adapter interrupts do not interfere.
1616 */
1617int t1_poll(struct napi_struct *napi, int budget)
1618{
1619 struct adapter *adapter = container_of(napi, struct adapter, napi);
1620 int work_done = process_responses(adapter, budget);
1621
1622 if (likely(work_done < budget)) {
1623 napi_complete(napi);
1624 writel(adapter->sge->respQ.cidx,
1625 adapter->regs + A_SG_SLEEPING);
1626 }
1627 return work_done;
1628}
1629
1630irqreturn_t t1_interrupt(int irq, void *data)
1631{
1632 struct adapter *adapter = data;
1633 struct sge *sge = adapter->sge;
1634 int handled;
1635
1636 if (likely(responses_pending(adapter))) {
1637 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1638
1639 if (napi_schedule_prep(&adapter->napi)) {
1640 if (process_pure_responses(adapter))
1641 __napi_schedule(&adapter->napi);
1642 else {
1643 /* no data, no NAPI needed */
1644 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1645 /* undo schedule_prep */
1646 napi_enable(&adapter->napi);
1647 }
1648 }
1649 return IRQ_HANDLED;
1650 }
1651
1652 spin_lock(&adapter->async_lock);
1653 handled = t1_slow_intr_handler(adapter);
1654 spin_unlock(&adapter->async_lock);
1655
1656 if (!handled)
1657 sge->stats.unhandled_irqs++;
1658
1659 return IRQ_RETVAL(handled != 0);
1660}
1661
1662/*
1663 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1664 *
1665 * The code figures out how many entries the sk_buff will require in the
1666 * cmdQ and updates the cmdQ data structure with the state once the enqueue
1667 * has complete. Then, it doesn't access the global structure anymore, but
1668 * uses the corresponding fields on the stack. In conjunction with a spinlock
1669 * around that code, we can make the function reentrant without holding the
1670 * lock when we actually enqueue (which might be expensive, especially on
1671 * architectures with IO MMUs).
1672 *
1673 * This runs with softirqs disabled.
1674 */
1675static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1676 unsigned int qid, struct net_device *dev)
1677{
1678 struct sge *sge = adapter->sge;
1679 struct cmdQ *q = &sge->cmdQ[qid];
1680 unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1681
1682 if (!spin_trylock(&q->lock))
1683 return NETDEV_TX_LOCKED;
1684
1685 reclaim_completed_tx(sge, q);
1686
1687 pidx = q->pidx;
1688 credits = q->size - q->in_use;
1689 count = 1 + skb_shinfo(skb)->nr_frags;
1690 count += compute_large_page_tx_descs(skb);
1691
1692 /* Ethernet packet */
1693 if (unlikely(credits < count)) {
1694 if (!netif_queue_stopped(dev)) {
1695 netif_stop_queue(dev);
1696 set_bit(dev->if_port, &sge->stopped_tx_queues);
1697 sge->stats.cmdQ_full[2]++;
1698 pr_err("%s: Tx ring full while queue awake!\n",
1699 adapter->name);
1700 }
1701 spin_unlock(&q->lock);
1702 return NETDEV_TX_BUSY;
1703 }
1704
1705 if (unlikely(credits - count < q->stop_thres)) {
1706 netif_stop_queue(dev);
1707 set_bit(dev->if_port, &sge->stopped_tx_queues);
1708 sge->stats.cmdQ_full[2]++;
1709 }
1710
1711 /* T204 cmdQ0 skbs that are destined for a certain port have to go
1712 * through the scheduler.
1713 */
1714 if (sge->tx_sched && !qid && skb->dev) {
1715use_sched:
1716 use_sched_skb = 1;
1717 /* Note that the scheduler might return a different skb than
1718 * the one passed in.
1719 */
1720 skb = sched_skb(sge, skb, credits);
1721 if (!skb) {
1722 spin_unlock(&q->lock);
1723 return NETDEV_TX_OK;
1724 }
1725 pidx = q->pidx;
1726 count = 1 + skb_shinfo(skb)->nr_frags;
1727 count += compute_large_page_tx_descs(skb);
1728 }
1729
1730 q->in_use += count;
1731 genbit = q->genbit;
1732 pidx = q->pidx;
1733 q->pidx += count;
1734 if (q->pidx >= q->size) {
1735 q->pidx -= q->size;
1736 q->genbit ^= 1;
1737 }
1738 spin_unlock(&q->lock);
1739
1740 write_tx_descs(adapter, skb, pidx, genbit, q);
1741
1742 /*
1743 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring
1744 * the doorbell if the Q is asleep. There is a natural race, where
1745 * the hardware is going to sleep just after we checked, however,
1746 * then the interrupt handler will detect the outstanding TX packet
1747 * and ring the doorbell for us.
1748 */
1749 if (qid)
1750 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1751 else {
1752 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1753 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1754 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1755 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1756 }
1757 }
1758
1759 if (use_sched_skb) {
1760 if (spin_trylock(&q->lock)) {
1761 credits = q->size - q->in_use;
1762 skb = NULL;
1763 goto use_sched;
1764 }
1765 }
1766 return NETDEV_TX_OK;
1767}
1768
1769#define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1770
1771/*
1772 * eth_hdr_len - return the length of an Ethernet header
1773 * @data: pointer to the start of the Ethernet header
1774 *
1775 * Returns the length of an Ethernet header, including optional VLAN tag.
1776 */
1777static inline int eth_hdr_len(const void *data)
1778{
1779 const struct ethhdr *e = data;
1780
1781 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1782}
1783
1784/*
1785 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1786 */
1787netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1788{
1789 struct adapter *adapter = dev->ml_priv;
1790 struct sge *sge = adapter->sge;
1791 struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]);
1792 struct cpl_tx_pkt *cpl;
1793 struct sk_buff *orig_skb = skb;
1794 int ret;
1795
1796 if (skb->protocol == htons(ETH_P_CPL5))
1797 goto send;
1798
1799 /*
1800 * We are using a non-standard hard_header_len.
1801 * Allocate more header room in the rare cases it is not big enough.
1802 */
1803 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1804 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1805 ++st->tx_need_hdrroom;
1806 dev_kfree_skb_any(orig_skb);
1807 if (!skb)
1808 return NETDEV_TX_OK;
1809 }
1810
1811 if (skb_shinfo(skb)->gso_size) {
1812 int eth_type;
1813 struct cpl_tx_pkt_lso *hdr;
1814
1815 ++st->tx_tso;
1816
1817 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1818 CPL_ETH_II : CPL_ETH_II_VLAN;
1819
1820 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1821 hdr->opcode = CPL_TX_PKT_LSO;
1822 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1823 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1824 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1825 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1826 skb_shinfo(skb)->gso_size));
1827 hdr->len = htonl(skb->len - sizeof(*hdr));
1828 cpl = (struct cpl_tx_pkt *)hdr;
1829 } else {
1830 /*
1831 * Packets shorter than ETH_HLEN can break the MAC, drop them
1832 * early. Also, we may get oversized packets because some
1833 * parts of the kernel don't handle our unusual hard_header_len
1834 * right, drop those too.
1835 */
1836 if (unlikely(skb->len < ETH_HLEN ||
1837 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1838 pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1839 skb->len, eth_hdr_len(skb->data), dev->mtu);
1840 dev_kfree_skb_any(skb);
1841 return NETDEV_TX_OK;
1842 }
1843
1844 if (skb->ip_summed == CHECKSUM_PARTIAL &&
1845 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1846 if (unlikely(skb_checksum_help(skb))) {
1847 pr_debug("%s: unable to do udp checksum\n", dev->name);
1848 dev_kfree_skb_any(skb);
1849 return NETDEV_TX_OK;
1850 }
1851 }
1852
1853 /* Hmmm, assuming to catch the gratious arp... and we'll use
1854 * it to flush out stuck espi packets...
1855 */
1856 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1857 if (skb->protocol == htons(ETH_P_ARP) &&
1858 arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1859 adapter->sge->espibug_skb[dev->if_port] = skb;
1860 /* We want to re-use this skb later. We
1861 * simply bump the reference count and it
1862 * will not be freed...
1863 */
1864 skb = skb_get(skb);
1865 }
1866 }
1867
1868 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1869 cpl->opcode = CPL_TX_PKT;
1870 cpl->ip_csum_dis = 1; /* SW calculates IP csum */
1871 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1872 /* the length field isn't used so don't bother setting it */
1873
1874 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1875 }
1876 cpl->iff = dev->if_port;
1877
1878 if (vlan_tx_tag_present(skb)) {
1879 cpl->vlan_valid = 1;
1880 cpl->vlan = htons(vlan_tx_tag_get(skb));
1881 st->vlan_insert++;
1882 } else
1883 cpl->vlan_valid = 0;
1884
1885send:
1886 ret = t1_sge_tx(skb, adapter, 0, dev);
1887
1888 /* If transmit busy, and we reallocated skb's due to headroom limit,
1889 * then silently discard to avoid leak.
1890 */
1891 if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1892 dev_kfree_skb_any(skb);
1893 ret = NETDEV_TX_OK;
1894 }
1895 return ret;
1896}
1897
1898/*
1899 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled.
1900 */
1901static void sge_tx_reclaim_cb(unsigned long data)
1902{
1903 int i;
1904 struct sge *sge = (struct sge *)data;
1905
1906 for (i = 0; i < SGE_CMDQ_N; ++i) {
1907 struct cmdQ *q = &sge->cmdQ[i];
1908
1909 if (!spin_trylock(&q->lock))
1910 continue;
1911
1912 reclaim_completed_tx(sge, q);
1913 if (i == 0 && q->in_use) { /* flush pending credits */
1914 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1915 }
1916 spin_unlock(&q->lock);
1917 }
1918 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1919}
1920
1921/*
1922 * Propagate changes of the SGE coalescing parameters to the HW.
1923 */
1924int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1925{
1926 sge->fixed_intrtimer = p->rx_coalesce_usecs *
1927 core_ticks_per_usec(sge->adapter);
1928 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1929 return 0;
1930}
1931
1932/*
1933 * Allocates both RX and TX resources and configures the SGE. However,
1934 * the hardware is not enabled yet.
1935 */
1936int t1_sge_configure(struct sge *sge, struct sge_params *p)
1937{
1938 if (alloc_rx_resources(sge, p))
1939 return -ENOMEM;
1940 if (alloc_tx_resources(sge, p)) {
1941 free_rx_resources(sge);
1942 return -ENOMEM;
1943 }
1944 configure_sge(sge, p);
1945
1946 /*
1947 * Now that we have sized the free lists calculate the payload
1948 * capacity of the large buffers. Other parts of the driver use
1949 * this to set the max offload coalescing size so that RX packets
1950 * do not overflow our large buffers.
1951 */
1952 p->large_buf_capacity = jumbo_payload_capacity(sge);
1953 return 0;
1954}
1955
1956/*
1957 * Disables the DMA engine.
1958 */
1959void t1_sge_stop(struct sge *sge)
1960{
1961 int i;
1962 writel(0, sge->adapter->regs + A_SG_CONTROL);
1963 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1964
1965 if (is_T2(sge->adapter))
1966 del_timer_sync(&sge->espibug_timer);
1967
1968 del_timer_sync(&sge->tx_reclaim_timer);
1969 if (sge->tx_sched)
1970 tx_sched_stop(sge);
1971
1972 for (i = 0; i < MAX_NPORTS; i++)
1973 kfree_skb(sge->espibug_skb[i]);
1974}
1975
1976/*
1977 * Enables the DMA engine.
1978 */
1979void t1_sge_start(struct sge *sge)
1980{
1981 refill_free_list(sge, &sge->freelQ[0]);
1982 refill_free_list(sge, &sge->freelQ[1]);
1983
1984 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1985 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1986 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1987
1988 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1989
1990 if (is_T2(sge->adapter))
1991 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1992}
1993
1994/*
1995 * Callback for the T2 ESPI 'stuck packet feature' workaorund
1996 */
1997static void espibug_workaround_t204(unsigned long data)
1998{
1999 struct adapter *adapter = (struct adapter *)data;
2000 struct sge *sge = adapter->sge;
2001 unsigned int nports = adapter->params.nports;
2002 u32 seop[MAX_NPORTS];
2003
2004 if (adapter->open_device_map & PORT_MASK) {
2005 int i;
2006
2007 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
2008 return;
2009
2010 for (i = 0; i < nports; i++) {
2011 struct sk_buff *skb = sge->espibug_skb[i];
2012
2013 if (!netif_running(adapter->port[i].dev) ||
2014 netif_queue_stopped(adapter->port[i].dev) ||
2015 !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2016 continue;
2017
2018 if (!skb->cb[0]) {
2019 skb_copy_to_linear_data_offset(skb,
2020 sizeof(struct cpl_tx_pkt),
2021 ch_mac_addr,
2022 ETH_ALEN);
2023 skb_copy_to_linear_data_offset(skb,
2024 skb->len - 10,
2025 ch_mac_addr,
2026 ETH_ALEN);
2027 skb->cb[0] = 0xff;
2028 }
2029
2030 /* bump the reference count to avoid freeing of
2031 * the skb once the DMA has completed.
2032 */
2033 skb = skb_get(skb);
2034 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2035 }
2036 }
2037 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2038}
2039
2040static void espibug_workaround(unsigned long data)
2041{
2042 struct adapter *adapter = (struct adapter *)data;
2043 struct sge *sge = adapter->sge;
2044
2045 if (netif_running(adapter->port[0].dev)) {
2046 struct sk_buff *skb = sge->espibug_skb[0];
2047 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2048
2049 if ((seop & 0xfff0fff) == 0xfff && skb) {
2050 if (!skb->cb[0]) {
2051 skb_copy_to_linear_data_offset(skb,
2052 sizeof(struct cpl_tx_pkt),
2053 ch_mac_addr,
2054 ETH_ALEN);
2055 skb_copy_to_linear_data_offset(skb,
2056 skb->len - 10,
2057 ch_mac_addr,
2058 ETH_ALEN);
2059 skb->cb[0] = 0xff;
2060 }
2061
2062 /* bump the reference count to avoid freeing of the
2063 * skb once the DMA has completed.
2064 */
2065 skb = skb_get(skb);
2066 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2067 }
2068 }
2069 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2070}
2071
2072/*
2073 * Creates a t1_sge structure and returns suggested resource parameters.
2074 */
2075struct sge * __devinit t1_sge_create(struct adapter *adapter,
2076 struct sge_params *p)
2077{
2078 struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2079 int i;
2080
2081 if (!sge)
2082 return NULL;
2083
2084 sge->adapter = adapter;
2085 sge->netdev = adapter->port[0].dev;
2086 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2087 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2088
2089 for_each_port(adapter, i) {
2090 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2091 if (!sge->port_stats[i])
2092 goto nomem_port;
2093 }
2094
2095 init_timer(&sge->tx_reclaim_timer);
2096 sge->tx_reclaim_timer.data = (unsigned long)sge;
2097 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2098
2099 if (is_T2(sge->adapter)) {
2100 init_timer(&sge->espibug_timer);
2101
2102 if (adapter->params.nports > 1) {
2103 tx_sched_init(sge);
2104 sge->espibug_timer.function = espibug_workaround_t204;
2105 } else
2106 sge->espibug_timer.function = espibug_workaround;
2107 sge->espibug_timer.data = (unsigned long)sge->adapter;
2108
2109 sge->espibug_timeout = 1;
2110 /* for T204, every 10ms */
2111 if (adapter->params.nports > 1)
2112 sge->espibug_timeout = HZ/100;
2113 }
2114
2115
2116 p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2117 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2118 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2119 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2120 if (sge->tx_sched) {
2121 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2122 p->rx_coalesce_usecs = 15;
2123 else
2124 p->rx_coalesce_usecs = 50;
2125 } else
2126 p->rx_coalesce_usecs = 50;
2127
2128 p->coalesce_enable = 0;
2129 p->sample_interval_usecs = 0;
2130
2131 return sge;
2132nomem_port:
2133 while (i >= 0) {
2134 free_percpu(sge->port_stats[i]);
2135 --i;
2136 }
2137 kfree(sge);
2138 return NULL;
2139
2140}
diff --git a/drivers/net/chelsio/sge.h b/drivers/net/chelsio/sge.h
deleted file mode 100644
index e03980bcdd65..000000000000
--- a/drivers/net/chelsio/sge.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: sge.h *
4 * $Revision: 1.11 $ *
5 * $Date: 2005/06/21 22:10:55 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CXGB_SGE_H_
40#define _CXGB_SGE_H_
41
42#include <linux/types.h>
43#include <linux/interrupt.h>
44#include <asm/byteorder.h>
45
46struct sge_intr_counts {
47 unsigned int rx_drops; /* # of packets dropped due to no mem */
48 unsigned int pure_rsps; /* # of non-payload responses */
49 unsigned int unhandled_irqs; /* # of unhandled interrupts */
50 unsigned int respQ_empty; /* # times respQ empty */
51 unsigned int respQ_overflow; /* # respQ overflow (fatal) */
52 unsigned int freelistQ_empty; /* # times freelist empty */
53 unsigned int pkt_too_big; /* packet too large (fatal) */
54 unsigned int pkt_mismatch;
55 unsigned int cmdQ_full[3]; /* not HW IRQ, host cmdQ[] full */
56 unsigned int cmdQ_restarted[3];/* # of times cmdQ X was restarted */
57};
58
59struct sge_port_stats {
60 u64 rx_cso_good; /* # of successful RX csum offloads */
61 u64 tx_cso; /* # of TX checksum offloads */
62 u64 tx_tso; /* # of TSO requests */
63 u64 vlan_xtract; /* # of VLAN tag extractions */
64 u64 vlan_insert; /* # of VLAN tag insertions */
65 u64 tx_need_hdrroom; /* # of TX skbs in need of more header room */
66};
67
68struct sk_buff;
69struct net_device;
70struct adapter;
71struct sge_params;
72struct sge;
73
74struct sge *t1_sge_create(struct adapter *, struct sge_params *);
75int t1_sge_configure(struct sge *, struct sge_params *);
76int t1_sge_set_coalesce_params(struct sge *, struct sge_params *);
77void t1_sge_destroy(struct sge *);
78irqreturn_t t1_interrupt(int irq, void *cookie);
79int t1_poll(struct napi_struct *, int);
80
81netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev);
82void t1_vlan_mode(struct adapter *adapter, u32 features);
83void t1_sge_start(struct sge *);
84void t1_sge_stop(struct sge *);
85int t1_sge_intr_error_handler(struct sge *);
86void t1_sge_intr_enable(struct sge *);
87void t1_sge_intr_disable(struct sge *);
88void t1_sge_intr_clear(struct sge *);
89const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge);
90void t1_sge_get_port_stats(const struct sge *sge, int port, struct sge_port_stats *);
91unsigned int t1_sched_update_parms(struct sge *, unsigned int, unsigned int,
92 unsigned int);
93
94#endif /* _CXGB_SGE_H_ */
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
deleted file mode 100644
index 8a43c7e19701..000000000000
--- a/drivers/net/chelsio/subr.c
+++ /dev/null
@@ -1,1130 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: subr.c *
4 * $Revision: 1.27 $ *
5 * $Date: 2005/06/22 01:08:36 $ *
6 * Description: *
7 * Various subroutines (intr,pio,etc.) used by Chelsio 10G Ethernet driver. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40#include "common.h"
41#include "elmer0.h"
42#include "regs.h"
43#include "gmac.h"
44#include "cphy.h"
45#include "sge.h"
46#include "tp.h"
47#include "espi.h"
48
49/**
50 * t1_wait_op_done - wait until an operation is completed
51 * @adapter: the adapter performing the operation
52 * @reg: the register to check for completion
53 * @mask: a single-bit field within @reg that indicates completion
54 * @polarity: the value of the field when the operation is completed
55 * @attempts: number of check iterations
56 * @delay: delay in usecs between iterations
57 *
58 * Wait until an operation is completed by checking a bit in a register
59 * up to @attempts times. Returns %0 if the operation completes and %1
60 * otherwise.
61 */
62static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
63 int attempts, int delay)
64{
65 while (1) {
66 u32 val = readl(adapter->regs + reg) & mask;
67
68 if (!!val == polarity)
69 return 0;
70 if (--attempts == 0)
71 return 1;
72 if (delay)
73 udelay(delay);
74 }
75}
76
77#define TPI_ATTEMPTS 50
78
79/*
80 * Write a register over the TPI interface (unlocked and locked versions).
81 */
82int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
83{
84 int tpi_busy;
85
86 writel(addr, adapter->regs + A_TPI_ADDR);
87 writel(value, adapter->regs + A_TPI_WR_DATA);
88 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
89
90 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
91 TPI_ATTEMPTS, 3);
92 if (tpi_busy)
93 pr_alert("%s: TPI write to 0x%x failed\n",
94 adapter->name, addr);
95 return tpi_busy;
96}
97
98int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
99{
100 int ret;
101
102 spin_lock(&adapter->tpi_lock);
103 ret = __t1_tpi_write(adapter, addr, value);
104 spin_unlock(&adapter->tpi_lock);
105 return ret;
106}
107
108/*
109 * Read a register over the TPI interface (unlocked and locked versions).
110 */
111int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
112{
113 int tpi_busy;
114
115 writel(addr, adapter->regs + A_TPI_ADDR);
116 writel(0, adapter->regs + A_TPI_CSR);
117
118 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
119 TPI_ATTEMPTS, 3);
120 if (tpi_busy)
121 pr_alert("%s: TPI read from 0x%x failed\n",
122 adapter->name, addr);
123 else
124 *valp = readl(adapter->regs + A_TPI_RD_DATA);
125 return tpi_busy;
126}
127
128int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
129{
130 int ret;
131
132 spin_lock(&adapter->tpi_lock);
133 ret = __t1_tpi_read(adapter, addr, valp);
134 spin_unlock(&adapter->tpi_lock);
135 return ret;
136}
137
138/*
139 * Set a TPI parameter.
140 */
141static void t1_tpi_par(adapter_t *adapter, u32 value)
142{
143 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
144}
145
146/*
147 * Called when a port's link settings change to propagate the new values to the
148 * associated PHY and MAC. After performing the common tasks it invokes an
149 * OS-specific handler.
150 */
151void t1_link_changed(adapter_t *adapter, int port_id)
152{
153 int link_ok, speed, duplex, fc;
154 struct cphy *phy = adapter->port[port_id].phy;
155 struct link_config *lc = &adapter->port[port_id].link_config;
156
157 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
158
159 lc->speed = speed < 0 ? SPEED_INVALID : speed;
160 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
161 if (!(lc->requested_fc & PAUSE_AUTONEG))
162 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
163
164 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
165 /* Set MAC speed, duplex, and flow control to match PHY. */
166 struct cmac *mac = adapter->port[port_id].mac;
167
168 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
169 lc->fc = (unsigned char)fc;
170 }
171 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
172}
173
174static int t1_pci_intr_handler(adapter_t *adapter)
175{
176 u32 pcix_cause;
177
178 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
179
180 if (pcix_cause) {
181 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
182 pcix_cause);
183 t1_fatal_err(adapter); /* PCI errors are fatal */
184 }
185 return 0;
186}
187
188#ifdef CONFIG_CHELSIO_T1_1G
189#include "fpga_defs.h"
190
191/*
192 * PHY interrupt handler for FPGA boards.
193 */
194static int fpga_phy_intr_handler(adapter_t *adapter)
195{
196 int p;
197 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
198
199 for_each_port(adapter, p)
200 if (cause & (1 << p)) {
201 struct cphy *phy = adapter->port[p].phy;
202 int phy_cause = phy->ops->interrupt_handler(phy);
203
204 if (phy_cause & cphy_cause_link_change)
205 t1_link_changed(adapter, p);
206 }
207 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
208 return 0;
209}
210
211/*
212 * Slow path interrupt handler for FPGAs.
213 */
214static int fpga_slow_intr(adapter_t *adapter)
215{
216 u32 cause = readl(adapter->regs + A_PL_CAUSE);
217
218 cause &= ~F_PL_INTR_SGE_DATA;
219 if (cause & F_PL_INTR_SGE_ERR)
220 t1_sge_intr_error_handler(adapter->sge);
221
222 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
223 fpga_phy_intr_handler(adapter);
224
225 if (cause & FPGA_PCIX_INTERRUPT_TP) {
226 /*
227 * FPGA doesn't support MC4 interrupts and it requires
228 * this odd layer of indirection for MC5.
229 */
230 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
231
232 /* Clear TP interrupt */
233 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234 }
235 if (cause & FPGA_PCIX_INTERRUPT_PCIX)
236 t1_pci_intr_handler(adapter);
237
238 /* Clear the interrupts just processed. */
239 if (cause)
240 writel(cause, adapter->regs + A_PL_CAUSE);
241
242 return cause != 0;
243}
244#endif
245
246/*
247 * Wait until Elmer's MI1 interface is ready for new operations.
248 */
249static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
250{
251 int attempts = 100, busy;
252
253 do {
254 u32 val;
255
256 __t1_tpi_read(adapter, mi1_reg, &val);
257 busy = val & F_MI1_OP_BUSY;
258 if (busy)
259 udelay(10);
260 } while (busy && --attempts);
261 if (busy)
262 pr_alert("%s: MDIO operation timed out\n", adapter->name);
263 return busy;
264}
265
266/*
267 * MI1 MDIO initialization.
268 */
269static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
270{
271 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
272 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
273 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
274
275 if (!(bi->caps & SUPPORTED_10000baseT_Full))
276 val |= V_MI1_SOF(1);
277 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
278}
279
280#if defined(CONFIG_CHELSIO_T1_1G)
281/*
282 * Elmer MI1 MDIO read/write operations.
283 */
284static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
285 u16 reg_addr)
286{
287 struct adapter *adapter = dev->ml_priv;
288 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
289 unsigned int val;
290
291 spin_lock(&adapter->tpi_lock);
292 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
293 __t1_tpi_write(adapter,
294 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
295 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
296 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
297 spin_unlock(&adapter->tpi_lock);
298 return val;
299}
300
301static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
302 u16 reg_addr, u16 val)
303{
304 struct adapter *adapter = dev->ml_priv;
305 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
306
307 spin_lock(&adapter->tpi_lock);
308 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
309 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
310 __t1_tpi_write(adapter,
311 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
312 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
313 spin_unlock(&adapter->tpi_lock);
314 return 0;
315}
316
317static const struct mdio_ops mi1_mdio_ops = {
318 .init = mi1_mdio_init,
319 .read = mi1_mdio_read,
320 .write = mi1_mdio_write,
321 .mode_support = MDIO_SUPPORTS_C22
322};
323
324#endif
325
326static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
327 u16 reg_addr)
328{
329 struct adapter *adapter = dev->ml_priv;
330 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
331 unsigned int val;
332
333 spin_lock(&adapter->tpi_lock);
334
335 /* Write the address we want. */
336 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
337 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
338 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
339 MI1_OP_INDIRECT_ADDRESS);
340 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
341
342 /* Write the operation we want. */
343 __t1_tpi_write(adapter,
344 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
345 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
346
347 /* Read the data. */
348 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
349 spin_unlock(&adapter->tpi_lock);
350 return val;
351}
352
353static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
354 int mmd_addr, u16 reg_addr, u16 val)
355{
356 struct adapter *adapter = dev->ml_priv;
357 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
358
359 spin_lock(&adapter->tpi_lock);
360
361 /* Write the address we want. */
362 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
363 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
364 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
365 MI1_OP_INDIRECT_ADDRESS);
366 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
367
368 /* Write the data. */
369 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
370 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
371 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
372 spin_unlock(&adapter->tpi_lock);
373 return 0;
374}
375
376static const struct mdio_ops mi1_mdio_ext_ops = {
377 .init = mi1_mdio_init,
378 .read = mi1_mdio_ext_read,
379 .write = mi1_mdio_ext_write,
380 .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
381};
382
383enum {
384 CH_BRD_T110_1CU,
385 CH_BRD_N110_1F,
386 CH_BRD_N210_1F,
387 CH_BRD_T210_1F,
388 CH_BRD_T210_1CU,
389 CH_BRD_N204_4CU,
390};
391
392static const struct board_info t1_board[] = {
393 {
394 .board = CHBT_BOARD_CHT110,
395 .port_number = 1,
396 .caps = SUPPORTED_10000baseT_Full,
397 .chip_term = CHBT_TERM_T1,
398 .chip_mac = CHBT_MAC_PM3393,
399 .chip_phy = CHBT_PHY_MY3126,
400 .clock_core = 125000000,
401 .clock_mc3 = 150000000,
402 .clock_mc4 = 125000000,
403 .espi_nports = 1,
404 .clock_elmer0 = 44,
405 .mdio_mdien = 1,
406 .mdio_mdiinv = 1,
407 .mdio_mdc = 1,
408 .mdio_phybaseaddr = 1,
409 .gmac = &t1_pm3393_ops,
410 .gphy = &t1_my3126_ops,
411 .mdio_ops = &mi1_mdio_ext_ops,
412 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
413 },
414
415 {
416 .board = CHBT_BOARD_N110,
417 .port_number = 1,
418 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
419 .chip_term = CHBT_TERM_T1,
420 .chip_mac = CHBT_MAC_PM3393,
421 .chip_phy = CHBT_PHY_88X2010,
422 .clock_core = 125000000,
423 .espi_nports = 1,
424 .clock_elmer0 = 44,
425 .mdio_mdien = 0,
426 .mdio_mdiinv = 0,
427 .mdio_mdc = 1,
428 .mdio_phybaseaddr = 0,
429 .gmac = &t1_pm3393_ops,
430 .gphy = &t1_mv88x201x_ops,
431 .mdio_ops = &mi1_mdio_ext_ops,
432 .desc = "Chelsio N110 1x10GBaseX NIC",
433 },
434
435 {
436 .board = CHBT_BOARD_N210,
437 .port_number = 1,
438 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
439 .chip_term = CHBT_TERM_T2,
440 .chip_mac = CHBT_MAC_PM3393,
441 .chip_phy = CHBT_PHY_88X2010,
442 .clock_core = 125000000,
443 .espi_nports = 1,
444 .clock_elmer0 = 44,
445 .mdio_mdien = 0,
446 .mdio_mdiinv = 0,
447 .mdio_mdc = 1,
448 .mdio_phybaseaddr = 0,
449 .gmac = &t1_pm3393_ops,
450 .gphy = &t1_mv88x201x_ops,
451 .mdio_ops = &mi1_mdio_ext_ops,
452 .desc = "Chelsio N210 1x10GBaseX NIC",
453 },
454
455 {
456 .board = CHBT_BOARD_CHT210,
457 .port_number = 1,
458 .caps = SUPPORTED_10000baseT_Full,
459 .chip_term = CHBT_TERM_T2,
460 .chip_mac = CHBT_MAC_PM3393,
461 .chip_phy = CHBT_PHY_88X2010,
462 .clock_core = 125000000,
463 .clock_mc3 = 133000000,
464 .clock_mc4 = 125000000,
465 .espi_nports = 1,
466 .clock_elmer0 = 44,
467 .mdio_mdien = 0,
468 .mdio_mdiinv = 0,
469 .mdio_mdc = 1,
470 .mdio_phybaseaddr = 0,
471 .gmac = &t1_pm3393_ops,
472 .gphy = &t1_mv88x201x_ops,
473 .mdio_ops = &mi1_mdio_ext_ops,
474 .desc = "Chelsio T210 1x10GBaseX TOE",
475 },
476
477 {
478 .board = CHBT_BOARD_CHT210,
479 .port_number = 1,
480 .caps = SUPPORTED_10000baseT_Full,
481 .chip_term = CHBT_TERM_T2,
482 .chip_mac = CHBT_MAC_PM3393,
483 .chip_phy = CHBT_PHY_MY3126,
484 .clock_core = 125000000,
485 .clock_mc3 = 133000000,
486 .clock_mc4 = 125000000,
487 .espi_nports = 1,
488 .clock_elmer0 = 44,
489 .mdio_mdien = 1,
490 .mdio_mdiinv = 1,
491 .mdio_mdc = 1,
492 .mdio_phybaseaddr = 1,
493 .gmac = &t1_pm3393_ops,
494 .gphy = &t1_my3126_ops,
495 .mdio_ops = &mi1_mdio_ext_ops,
496 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
497 },
498
499#ifdef CONFIG_CHELSIO_T1_1G
500 {
501 .board = CHBT_BOARD_CHN204,
502 .port_number = 4,
503 .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
504 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
505 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
506 SUPPORTED_PAUSE | SUPPORTED_TP,
507 .chip_term = CHBT_TERM_T2,
508 .chip_mac = CHBT_MAC_VSC7321,
509 .chip_phy = CHBT_PHY_88E1111,
510 .clock_core = 100000000,
511 .espi_nports = 4,
512 .clock_elmer0 = 44,
513 .mdio_mdien = 0,
514 .mdio_mdiinv = 0,
515 .mdio_mdc = 0,
516 .mdio_phybaseaddr = 4,
517 .gmac = &t1_vsc7326_ops,
518 .gphy = &t1_mv88e1xxx_ops,
519 .mdio_ops = &mi1_mdio_ops,
520 .desc = "Chelsio N204 4x100/1000BaseT NIC",
521 },
522#endif
523
524};
525
526DEFINE_PCI_DEVICE_TABLE(t1_pci_tbl) = {
527 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
528 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
529 CH_DEVICE(7, 0, CH_BRD_N110_1F),
530 CH_DEVICE(10, 1, CH_BRD_N210_1F),
531 CH_DEVICE(11, 1, CH_BRD_T210_1F),
532 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
533 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
534 { 0 }
535};
536
537MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
538
539/*
540 * Return the board_info structure with a given index. Out-of-range indices
541 * return NULL.
542 */
543const struct board_info *t1_get_board_info(unsigned int board_id)
544{
545 return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
546}
547
548struct chelsio_vpd_t {
549 u32 format_version;
550 u8 serial_number[16];
551 u8 mac_base_address[6];
552 u8 pad[2]; /* make multiple-of-4 size requirement explicit */
553};
554
555#define EEPROMSIZE (8 * 1024)
556#define EEPROM_MAX_POLL 4
557
558/*
559 * Read SEEPROM. A zero is written to the flag register when the address is
560 * written to the Control register. The hardware device will set the flag to a
561 * one when 4B have been transferred to the Data register.
562 */
563int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
564{
565 int i = EEPROM_MAX_POLL;
566 u16 val;
567 u32 v;
568
569 if (addr >= EEPROMSIZE || (addr & 3))
570 return -EINVAL;
571
572 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
573 do {
574 udelay(50);
575 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
576 } while (!(val & F_VPD_OP_FLAG) && --i);
577
578 if (!(val & F_VPD_OP_FLAG)) {
579 pr_err("%s: reading EEPROM address 0x%x failed\n",
580 adapter->name, addr);
581 return -EIO;
582 }
583 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
584 *data = cpu_to_le32(v);
585 return 0;
586}
587
588static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
589{
590 int addr, ret = 0;
591
592 for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
593 ret = t1_seeprom_read(adapter, addr,
594 (__le32 *)((u8 *)vpd + addr));
595
596 return ret;
597}
598
599/*
600 * Read a port's MAC address from the VPD ROM.
601 */
602static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
603{
604 struct chelsio_vpd_t vpd;
605
606 if (t1_eeprom_vpd_get(adapter, &vpd))
607 return 1;
608 memcpy(mac_addr, vpd.mac_base_address, 5);
609 mac_addr[5] = vpd.mac_base_address[5] + index;
610 return 0;
611}
612
613/*
614 * Set up the MAC/PHY according to the requested link settings.
615 *
616 * If the PHY can auto-negotiate first decide what to advertise, then
617 * enable/disable auto-negotiation as desired and reset.
618 *
619 * If the PHY does not auto-negotiate we just reset it.
620 *
621 * If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
622 * otherwise do it later based on the outcome of auto-negotiation.
623 */
624int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
625{
626 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
627
628 if (lc->supported & SUPPORTED_Autoneg) {
629 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
630 if (fc) {
631 if (fc == ((PAUSE_RX | PAUSE_TX) &
632 (mac->adapter->params.nports < 2)))
633 lc->advertising |= ADVERTISED_PAUSE;
634 else {
635 lc->advertising |= ADVERTISED_ASYM_PAUSE;
636 if (fc == PAUSE_RX)
637 lc->advertising |= ADVERTISED_PAUSE;
638 }
639 }
640 phy->ops->advertise(phy, lc->advertising);
641
642 if (lc->autoneg == AUTONEG_DISABLE) {
643 lc->speed = lc->requested_speed;
644 lc->duplex = lc->requested_duplex;
645 lc->fc = (unsigned char)fc;
646 mac->ops->set_speed_duplex_fc(mac, lc->speed,
647 lc->duplex, fc);
648 /* Also disables autoneg */
649 phy->state = PHY_AUTONEG_RDY;
650 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
651 phy->ops->reset(phy, 0);
652 } else {
653 phy->state = PHY_AUTONEG_EN;
654 phy->ops->autoneg_enable(phy); /* also resets PHY */
655 }
656 } else {
657 phy->state = PHY_AUTONEG_RDY;
658 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
659 lc->fc = (unsigned char)fc;
660 phy->ops->reset(phy, 0);
661 }
662 return 0;
663}
664
665/*
666 * External interrupt handler for boards using elmer0.
667 */
668int t1_elmer0_ext_intr_handler(adapter_t *adapter)
669{
670 struct cphy *phy;
671 int phy_cause;
672 u32 cause;
673
674 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
675
676 switch (board_info(adapter)->board) {
677#ifdef CONFIG_CHELSIO_T1_1G
678 case CHBT_BOARD_CHT204:
679 case CHBT_BOARD_CHT204E:
680 case CHBT_BOARD_CHN204:
681 case CHBT_BOARD_CHT204V: {
682 int i, port_bit;
683 for_each_port(adapter, i) {
684 port_bit = i + 1;
685 if (!(cause & (1 << port_bit)))
686 continue;
687
688 phy = adapter->port[i].phy;
689 phy_cause = phy->ops->interrupt_handler(phy);
690 if (phy_cause & cphy_cause_link_change)
691 t1_link_changed(adapter, i);
692 }
693 break;
694 }
695 case CHBT_BOARD_CHT101:
696 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
697 phy = adapter->port[0].phy;
698 phy_cause = phy->ops->interrupt_handler(phy);
699 if (phy_cause & cphy_cause_link_change)
700 t1_link_changed(adapter, 0);
701 }
702 break;
703 case CHBT_BOARD_7500: {
704 int p;
705 /*
706 * Elmer0's interrupt cause isn't useful here because there is
707 * only one bit that can be set for all 4 ports. This means
708 * we are forced to check every PHY's interrupt status
709 * register to see who initiated the interrupt.
710 */
711 for_each_port(adapter, p) {
712 phy = adapter->port[p].phy;
713 phy_cause = phy->ops->interrupt_handler(phy);
714 if (phy_cause & cphy_cause_link_change)
715 t1_link_changed(adapter, p);
716 }
717 break;
718 }
719#endif
720 case CHBT_BOARD_CHT210:
721 case CHBT_BOARD_N210:
722 case CHBT_BOARD_N110:
723 if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
724 phy = adapter->port[0].phy;
725 phy_cause = phy->ops->interrupt_handler(phy);
726 if (phy_cause & cphy_cause_link_change)
727 t1_link_changed(adapter, 0);
728 }
729 break;
730 case CHBT_BOARD_8000:
731 case CHBT_BOARD_CHT110:
732 if (netif_msg_intr(adapter))
733 dev_dbg(&adapter->pdev->dev,
734 "External interrupt cause 0x%x\n", cause);
735 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
736 struct cmac *mac = adapter->port[0].mac;
737
738 mac->ops->interrupt_handler(mac);
739 }
740 if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
741 u32 mod_detect;
742
743 t1_tpi_read(adapter,
744 A_ELMER0_GPI_STAT, &mod_detect);
745 if (netif_msg_link(adapter))
746 dev_info(&adapter->pdev->dev, "XPAK %s\n",
747 mod_detect ? "removed" : "inserted");
748 }
749 break;
750 }
751 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
752 return 0;
753}
754
755/* Enables all interrupts. */
756void t1_interrupts_enable(adapter_t *adapter)
757{
758 unsigned int i;
759
760 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
761
762 t1_sge_intr_enable(adapter->sge);
763 t1_tp_intr_enable(adapter->tp);
764 if (adapter->espi) {
765 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
766 t1_espi_intr_enable(adapter->espi);
767 }
768
769 /* Enable MAC/PHY interrupts for each port. */
770 for_each_port(adapter, i) {
771 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
772 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
773 }
774
775 /* Enable PCIX & external chip interrupts on ASIC boards. */
776 if (t1_is_asic(adapter)) {
777 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
778
779 /* PCI-X interrupts */
780 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
781 0xffffffff);
782
783 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
784 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
785 writel(pl_intr, adapter->regs + A_PL_ENABLE);
786 }
787}
788
789/* Disables all interrupts. */
790void t1_interrupts_disable(adapter_t* adapter)
791{
792 unsigned int i;
793
794 t1_sge_intr_disable(adapter->sge);
795 t1_tp_intr_disable(adapter->tp);
796 if (adapter->espi)
797 t1_espi_intr_disable(adapter->espi);
798
799 /* Disable MAC/PHY interrupts for each port. */
800 for_each_port(adapter, i) {
801 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
802 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
803 }
804
805 /* Disable PCIX & external chip interrupts. */
806 if (t1_is_asic(adapter))
807 writel(0, adapter->regs + A_PL_ENABLE);
808
809 /* PCI-X interrupts */
810 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
811
812 adapter->slow_intr_mask = 0;
813}
814
815/* Clears all interrupts */
816void t1_interrupts_clear(adapter_t* adapter)
817{
818 unsigned int i;
819
820 t1_sge_intr_clear(adapter->sge);
821 t1_tp_intr_clear(adapter->tp);
822 if (adapter->espi)
823 t1_espi_intr_clear(adapter->espi);
824
825 /* Clear MAC/PHY interrupts for each port. */
826 for_each_port(adapter, i) {
827 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
828 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
829 }
830
831 /* Enable interrupts for external devices. */
832 if (t1_is_asic(adapter)) {
833 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
834
835 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
836 adapter->regs + A_PL_CAUSE);
837 }
838
839 /* PCI-X interrupts */
840 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
841}
842
843/*
844 * Slow path interrupt handler for ASICs.
845 */
846static int asic_slow_intr(adapter_t *adapter)
847{
848 u32 cause = readl(adapter->regs + A_PL_CAUSE);
849
850 cause &= adapter->slow_intr_mask;
851 if (!cause)
852 return 0;
853 if (cause & F_PL_INTR_SGE_ERR)
854 t1_sge_intr_error_handler(adapter->sge);
855 if (cause & F_PL_INTR_TP)
856 t1_tp_intr_handler(adapter->tp);
857 if (cause & F_PL_INTR_ESPI)
858 t1_espi_intr_handler(adapter->espi);
859 if (cause & F_PL_INTR_PCIX)
860 t1_pci_intr_handler(adapter);
861 if (cause & F_PL_INTR_EXT)
862 t1_elmer0_ext_intr(adapter);
863
864 /* Clear the interrupts just processed. */
865 writel(cause, adapter->regs + A_PL_CAUSE);
866 readl(adapter->regs + A_PL_CAUSE); /* flush writes */
867 return 1;
868}
869
870int t1_slow_intr_handler(adapter_t *adapter)
871{
872#ifdef CONFIG_CHELSIO_T1_1G
873 if (!t1_is_asic(adapter))
874 return fpga_slow_intr(adapter);
875#endif
876 return asic_slow_intr(adapter);
877}
878
879/* Power sequencing is a work-around for Intel's XPAKs. */
880static void power_sequence_xpak(adapter_t* adapter)
881{
882 u32 mod_detect;
883 u32 gpo;
884
885 /* Check for XPAK */
886 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
887 if (!(ELMER0_GP_BIT5 & mod_detect)) {
888 /* XPAK is present */
889 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
890 gpo |= ELMER0_GP_BIT18;
891 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
892 }
893}
894
895int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
896 struct adapter_params *p)
897{
898 p->chip_version = bi->chip_term;
899 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
900 if (p->chip_version == CHBT_TERM_T1 ||
901 p->chip_version == CHBT_TERM_T2 ||
902 p->chip_version == CHBT_TERM_FPGA) {
903 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
904
905 val = G_TP_PC_REV(val);
906 if (val == 2)
907 p->chip_revision = TERM_T1B;
908 else if (val == 3)
909 p->chip_revision = TERM_T2;
910 else
911 return -1;
912 } else
913 return -1;
914 return 0;
915}
916
917/*
918 * Enable board components other than the Chelsio chip, such as external MAC
919 * and PHY.
920 */
921static int board_init(adapter_t *adapter, const struct board_info *bi)
922{
923 switch (bi->board) {
924 case CHBT_BOARD_8000:
925 case CHBT_BOARD_N110:
926 case CHBT_BOARD_N210:
927 case CHBT_BOARD_CHT210:
928 t1_tpi_par(adapter, 0xf);
929 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
930 break;
931 case CHBT_BOARD_CHT110:
932 t1_tpi_par(adapter, 0xf);
933 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
934
935 /* TBD XXX Might not need. This fixes a problem
936 * described in the Intel SR XPAK errata.
937 */
938 power_sequence_xpak(adapter);
939 break;
940#ifdef CONFIG_CHELSIO_T1_1G
941 case CHBT_BOARD_CHT204E:
942 /* add config space write here */
943 case CHBT_BOARD_CHT204:
944 case CHBT_BOARD_CHT204V:
945 case CHBT_BOARD_CHN204:
946 t1_tpi_par(adapter, 0xf);
947 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
948 break;
949 case CHBT_BOARD_CHT101:
950 case CHBT_BOARD_7500:
951 t1_tpi_par(adapter, 0xf);
952 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
953 break;
954#endif
955 }
956 return 0;
957}
958
959/*
960 * Initialize and configure the Terminator HW modules. Note that external
961 * MAC and PHYs are initialized separately.
962 */
963int t1_init_hw_modules(adapter_t *adapter)
964{
965 int err = -EIO;
966 const struct board_info *bi = board_info(adapter);
967
968 if (!bi->clock_mc4) {
969 u32 val = readl(adapter->regs + A_MC4_CFG);
970
971 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
972 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
973 adapter->regs + A_MC5_CONFIG);
974 }
975
976 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
977 bi->espi_nports))
978 goto out_err;
979
980 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
981 goto out_err;
982
983 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
984 if (err)
985 goto out_err;
986
987 err = 0;
988out_err:
989 return err;
990}
991
992/*
993 * Determine a card's PCI mode.
994 */
995static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
996{
997 static const unsigned short speed_map[] = { 33, 66, 100, 133 };
998 u32 pci_mode;
999
1000 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1001 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1002 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1003 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1004}
1005
1006/*
1007 * Release the structures holding the SW per-Terminator-HW-module state.
1008 */
1009void t1_free_sw_modules(adapter_t *adapter)
1010{
1011 unsigned int i;
1012
1013 for_each_port(adapter, i) {
1014 struct cmac *mac = adapter->port[i].mac;
1015 struct cphy *phy = adapter->port[i].phy;
1016
1017 if (mac)
1018 mac->ops->destroy(mac);
1019 if (phy)
1020 phy->ops->destroy(phy);
1021 }
1022
1023 if (adapter->sge)
1024 t1_sge_destroy(adapter->sge);
1025 if (adapter->tp)
1026 t1_tp_destroy(adapter->tp);
1027 if (adapter->espi)
1028 t1_espi_destroy(adapter->espi);
1029}
1030
1031static void __devinit init_link_config(struct link_config *lc,
1032 const struct board_info *bi)
1033{
1034 lc->supported = bi->caps;
1035 lc->requested_speed = lc->speed = SPEED_INVALID;
1036 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1037 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1038 if (lc->supported & SUPPORTED_Autoneg) {
1039 lc->advertising = lc->supported;
1040 lc->autoneg = AUTONEG_ENABLE;
1041 lc->requested_fc |= PAUSE_AUTONEG;
1042 } else {
1043 lc->advertising = 0;
1044 lc->autoneg = AUTONEG_DISABLE;
1045 }
1046}
1047
1048/*
1049 * Allocate and initialize the data structures that hold the SW state of
1050 * the Terminator HW modules.
1051 */
1052int __devinit t1_init_sw_modules(adapter_t *adapter,
1053 const struct board_info *bi)
1054{
1055 unsigned int i;
1056
1057 adapter->params.brd_info = bi;
1058 adapter->params.nports = bi->port_number;
1059 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1060
1061 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1062 if (!adapter->sge) {
1063 pr_err("%s: SGE initialization failed\n",
1064 adapter->name);
1065 goto error;
1066 }
1067
1068 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1069 pr_err("%s: ESPI initialization failed\n",
1070 adapter->name);
1071 goto error;
1072 }
1073
1074 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1075 if (!adapter->tp) {
1076 pr_err("%s: TP initialization failed\n",
1077 adapter->name);
1078 goto error;
1079 }
1080
1081 board_init(adapter, bi);
1082 bi->mdio_ops->init(adapter, bi);
1083 if (bi->gphy->reset)
1084 bi->gphy->reset(adapter);
1085 if (bi->gmac->reset)
1086 bi->gmac->reset(adapter);
1087
1088 for_each_port(adapter, i) {
1089 u8 hw_addr[6];
1090 struct cmac *mac;
1091 int phy_addr = bi->mdio_phybaseaddr + i;
1092
1093 adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1094 phy_addr, bi->mdio_ops);
1095 if (!adapter->port[i].phy) {
1096 pr_err("%s: PHY %d initialization failed\n",
1097 adapter->name, i);
1098 goto error;
1099 }
1100
1101 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1102 if (!mac) {
1103 pr_err("%s: MAC %d initialization failed\n",
1104 adapter->name, i);
1105 goto error;
1106 }
1107
1108 /*
1109 * Get the port's MAC addresses either from the EEPROM if one
1110 * exists or the one hardcoded in the MAC.
1111 */
1112 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1113 mac->ops->macaddress_get(mac, hw_addr);
1114 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1115 pr_err("%s: could not read MAC address from VPD ROM\n",
1116 adapter->port[i].dev->name);
1117 goto error;
1118 }
1119 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1120 init_link_config(&adapter->port[i].link_config, bi);
1121 }
1122
1123 get_pci_mode(adapter, &adapter->params.pci);
1124 t1_interrupts_clear(adapter);
1125 return 0;
1126
1127error:
1128 t1_free_sw_modules(adapter);
1129 return -1;
1130}
diff --git a/drivers/net/chelsio/suni1x10gexp_regs.h b/drivers/net/chelsio/suni1x10gexp_regs.h
deleted file mode 100644
index d0f87d82566a..000000000000
--- a/drivers/net/chelsio/suni1x10gexp_regs.h
+++ /dev/null
@@ -1,1643 +0,0 @@
1/*****************************************************************************
2 * *
3 * File: suni1x10gexp_regs.h *
4 * $Revision: 1.9 $ *
5 * $Date: 2005/06/22 00:17:04 $ *
6 * Description: *
7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Maintainers: maintainers@chelsio.com *
25 * *
26 * Authors: PMC/SIERRA *
27 * *
28 * History: *
29 * *
30 ****************************************************************************/
31
32#ifndef _CXGB_SUNI1x10GEXP_REGS_H_
33#define _CXGB_SUNI1x10GEXP_REGS_H_
34
35/*
36** Space allocated for each Exact Match Filter
37** There are 8 filter configurations
38*/
39#define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
40
41#define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER )
42
43/*
44** Space allocated for VLAN-Id Filter
45** There are 8 filter configurations
46*/
47#define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
48
49#define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER )
50
51/*
52** Space allocated for each MSTAT Counter
53*/
54#define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
55
56#define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT )
57
58
59/******************************************************************************/
60/** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/
61/******************************************************************************/
62/* Refer to the Register Bit Masks bellow for the naming of each register and */
63/* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */
64/******************************************************************************/
65
66
67#define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
68#define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
69#define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
70#define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
71#define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
72#define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
73
74#define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
75#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007
76#define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008
77#define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009
78#define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A
79#define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B
80
81#define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C
82#define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
83#define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
84#define SUNI1x10GEXP_REG_FREE 0x000F
85
86#define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010
87#define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011
88
89#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100
90#define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101
91#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
92#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103
93#define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
94#define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107
95
96#define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
97#define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041
98#define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
99#define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
100#define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
101#define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
102#define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
103#define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
104#define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049
105#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
106#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
107#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId))
108#define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId))
109#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A
110#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B
111#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C
112#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
113#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
114#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
115#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050
116#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051
117#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052
118#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053
119#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054
120#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055
121#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056
122#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057
123#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058
124#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059
125#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A
126#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B
127#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C
128#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D
129#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E
130#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F
131#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060
132#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061
133#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062
134#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063
135#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064
136#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065
137#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066
138#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067
139#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068
140#define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069
141#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
142#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
143#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
144#define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
145#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
146#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F
147#define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
148
149#define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081
150#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084
151#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085
152#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086
153#define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087
154#define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
155#define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
156#define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A
157#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
158#define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
159#define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092
160
161#define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0
162#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1
163#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2
164#define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3
165#define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4
166#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5
167#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
168#define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
169#define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9
170#define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA
171#define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB
172#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC
173#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD
174#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE
175#define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF
176#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0
177#define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1
178#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2
179#define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3
180#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4
181#define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5
182#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6
183#define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7
184
185#define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
186#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
187#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
188#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103
189#define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104
190#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105
191#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
192#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
193#define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
194#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109
195#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A
196#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B
197#define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C
198#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
199#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
200#define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId))
201#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
202#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111
203#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112
204#define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113
205#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
206#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115
207#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116
208#define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117
209#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118
210#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119
211#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A
212#define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B
213#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C
214#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D
215#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E
216#define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F
217#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
218#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121
219#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122
220#define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123
221#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
222#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125
223#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126
224#define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127
225#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
226#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129
227#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A
228#define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B
229#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C
230#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D
231#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E
232#define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F
233#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
234#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131
235#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132
236#define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133
237#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134
238#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135
239#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136
240#define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137
241#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
242#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139
243#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A
244#define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B
245#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
246#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D
247#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E
248#define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F
249#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
250#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141
251#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142
252#define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143
253#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
254#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145
255#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146
256#define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147
257#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148
258#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149
259#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A
260#define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B
261#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
262#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D
263#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E
264#define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F
265#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
266#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151
267#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152
268#define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153
269#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
270#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155
271#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156
272#define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157
273#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
274#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159
275#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A
276#define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B
277#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C
278#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D
279#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E
280#define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F
281#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160
282#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161
283#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162
284#define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163
285#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164
286#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165
287#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166
288#define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167
289#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168
290#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169
291#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A
292#define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B
293#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C
294#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D
295#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E
296#define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F
297#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170
298#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171
299#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172
300#define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173
301#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174
302#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175
303#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176
304#define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177
305#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178
306#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179
307#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a
308#define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b
309#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c
310#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d
311#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e
312#define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f
313#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180
314#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181
315#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182
316#define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183
317#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184
318#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185
319#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186
320#define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187
321#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188
322#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189
323#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A
324#define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B
325#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C
326#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D
327#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E
328#define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F
329#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190
330#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191
331#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192
332#define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193
333#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
334#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195
335#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196
336#define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197
337#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198
338#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199
339#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A
340#define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B
341#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
342#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D
343#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E
344#define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F
345#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
346#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1
347#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2
348#define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3
349#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4
350#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5
351#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6
352#define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7
353#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
354#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9
355#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA
356#define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB
357#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC
358#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD
359#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE
360#define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF
361#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
362#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1
363#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2
364#define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3
365#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4
366#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5
367#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6
368#define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7
369#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
370#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9
371#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA
372#define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB
373#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
374#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD
375#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE
376#define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF
377#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0
378#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1
379#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2
380#define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3
381#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4
382#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5
383#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6
384#define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7
385#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8
386#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9
387#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA
388#define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB
389#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC
390#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD
391#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE
392#define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF
393#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0
394#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1
395#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2
396#define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3
397#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4
398#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5
399#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6
400#define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7
401#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8
402#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9
403#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA
404#define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB
405#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC
406#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD
407#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE
408#define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF
409#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0
410#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1
411#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2
412#define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3
413#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4
414#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5
415#define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6
416#define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51
417
418#define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200
419#define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201
420#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
421#define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
422#define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D
423#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E
424#define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F
425#define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210
426#define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211
427
428#define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240
429#define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241
430#define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242
431#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243
432#define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244
433#define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245
434
435#define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280
436#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
437#define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
438#define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284
439
440#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
441#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
442#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
443#define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303
444#define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304
445#define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305
446
447#define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
448#define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041
449#define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
450#define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
451#define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044
452#define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
453#define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046
454#define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
455#define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
456#define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
457#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D
458#define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E
459#define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051
460#define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052
461
462#define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080
463#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
464#define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
465#define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086
466
467#define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0
468#define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1
469#define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2
470#define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3
471#define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4
472#define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5
473#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
474#define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
475#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8
476#define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9
477#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA
478#define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB
479#define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC
480#define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD
481#define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE
482#define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF
483#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0
484#define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1
485#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2
486#define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3
487
488
489#define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200
490#define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201
491#define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202
492#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203
493#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204
494#define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205
495#define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206
496#define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207
497#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
498#define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
499#define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210
500
501#define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280
502#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
503#define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
504
505
506/*----------------------------------------*/
507#define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480
508
509/******************************************************************************/
510/* -- End register offset definitions -- */
511/******************************************************************************/
512
513/******************************************************************************/
514/** SUNI-1x10GE-XP REGISTER BIT MASKS **/
515/******************************************************************************/
516
517#define SUNI1x10GEXP_BITMSK_BITS_1 0x00001
518#define SUNI1x10GEXP_BITMSK_BITS_2 0x00003
519#define SUNI1x10GEXP_BITMSK_BITS_3 0x00007
520#define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f
521#define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f
522#define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f
523#define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f
524#define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff
525#define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff
526#define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff
527#define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff
528#define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff
529#define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff
530#define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff
531#define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff
532#define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff
533
534#define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15)
535#define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14)
536#define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13)
537#define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12)
538#define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11)
539#define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10)
540#define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9)
541#define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8)
542#define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7)
543#define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6)
544#define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5)
545#define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4)
546#define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3)
547#define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2)
548#define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1)
549
550#define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
551
552
553
554/*----------------------------------------------------------------------------
555 * Register 0x0001: S/UNI-1x10GE-XP Product Revision
556 * Bit 3-0 REVISION
557 *----------------------------------------------------------------------------*/
558#define SUNI1x10GEXP_BITMSK_REVISION 0x000F
559
560/*----------------------------------------------------------------------------
561 * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
562 * Bit 2 XAUI_ARESETB
563 * Bit 1 PL4_ARESETB
564 * Bit 0 DRESETB
565 *----------------------------------------------------------------------------*/
566#define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004
567#define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002
568#define SUNI1x10GEXP_BITMSK_DRESETB 0x0001
569
570/*----------------------------------------------------------------------------
571 * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
572 * Bit 11 PL4IO_OUTCLKSEL
573 * Bit 9 SYSPCSLB
574 * Bit 8 LINEPCSLB
575 * Bit 7 MSTAT_BYPASS
576 * Bit 6 RXXG_BYPASS
577 * Bit 5 TXXG_BYPASS
578 * Bit 4 SOP_PAD_EN
579 * Bit 1 LOS_INV
580 * Bit 0 OVERRIDE_LOS
581 *----------------------------------------------------------------------------*/
582#define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800
583#define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200
584#define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100
585#define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080
586#define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040
587#define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020
588#define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010
589#define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002
590#define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001
591
592/*----------------------------------------------------------------------------
593 * Register 0x0004: S/UNI-1x10GE-XP Device Status
594 * Bit 9 TOP_SXRA_EXPIRED
595 * Bit 8 TOP_MDIO_BUSY
596 * Bit 7 TOP_DTRB
597 * Bit 6 TOP_EXPIRED
598 * Bit 5 TOP_PAUSED
599 * Bit 4 TOP_PL4_ID_DOOL
600 * Bit 3 TOP_PL4_IS_DOOL
601 * Bit 2 TOP_PL4_ID_ROOL
602 * Bit 1 TOP_PL4_IS_ROOL
603 * Bit 0 TOP_PL4_OUT_ROOL
604 *----------------------------------------------------------------------------*/
605#define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
606#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100
607#define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080
608#define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
609#define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020
610#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
611#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
612#define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
613#define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002
614#define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
615
616/*----------------------------------------------------------------------------
617 * Register 0x0005: Global Performance Update and Clock Monitors
618 * Bit 15 TIP
619 * Bit 8 XAUI_REF_CLKA
620 * Bit 7 RXLANE3CLKA
621 * Bit 6 RXLANE2CLKA
622 * Bit 5 RXLANE1CLKA
623 * Bit 4 RXLANE0CLKA
624 * Bit 3 CSUCLKA
625 * Bit 2 TDCLKA
626 * Bit 1 RSCLKA
627 * Bit 0 RDCLKA
628 *----------------------------------------------------------------------------*/
629#define SUNI1x10GEXP_BITMSK_TIP 0x8000
630#define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100
631#define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080
632#define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040
633#define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020
634#define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010
635#define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008
636#define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004
637#define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002
638#define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001
639
640/*----------------------------------------------------------------------------
641 * Register 0x0006: MDIO Command
642 * Bit 4 MDIO_RDINC
643 * Bit 3 MDIO_RSTAT
644 * Bit 2 MDIO_LCTLD
645 * Bit 1 MDIO_LCTLA
646 * Bit 0 MDIO_SPRE
647 *----------------------------------------------------------------------------*/
648#define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010
649#define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008
650#define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004
651#define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002
652#define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001
653
654/*----------------------------------------------------------------------------
655 * Register 0x0007: MDIO Interrupt Enable
656 * Bit 0 MDIO_BUSY_EN
657 *----------------------------------------------------------------------------*/
658#define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001
659
660/*----------------------------------------------------------------------------
661 * Register 0x0008: MDIO Interrupt Status
662 * Bit 0 MDIO_BUSYI
663 *----------------------------------------------------------------------------*/
664#define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001
665
666/*----------------------------------------------------------------------------
667 * Register 0x0009: MMD PHY Address
668 * Bit 12-8 MDIO_DEVADR
669 * Bit 4-0 MDIO_PRTADR
670 *----------------------------------------------------------------------------*/
671#define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00
672#define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8
673#define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F
674#define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0
675
676/*----------------------------------------------------------------------------
677 * Register 0x000C: OAM Interface Control
678 * Bit 6 MDO_OD_ENB
679 * Bit 5 MDI_INV
680 * Bit 4 MDI_SEL
681 * Bit 3 RXOAMEN
682 * Bit 2 RXOAMCLKEN
683 * Bit 1 TXOAMEN
684 * Bit 0 TXOAMCLKEN
685 *----------------------------------------------------------------------------*/
686#define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040
687#define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020
688#define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010
689#define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008
690#define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004
691#define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002
692#define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001
693
694/*----------------------------------------------------------------------------
695 * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
696 * Bit 15 TOP_PL4IO_INT
697 * Bit 14 TOP_IRAM_INT
698 * Bit 13 TOP_ERAM_INT
699 * Bit 12 TOP_XAUI_INT
700 * Bit 11 TOP_MSTAT_INT
701 * Bit 10 TOP_RXXG_INT
702 * Bit 9 TOP_TXXG_INT
703 * Bit 8 TOP_XRF_INT
704 * Bit 7 TOP_XTEF_INT
705 * Bit 6 TOP_MDIO_BUSY_INT
706 * Bit 5 TOP_RXOAM_INT
707 * Bit 4 TOP_TXOAM_INT
708 * Bit 3 TOP_IFLX_INT
709 * Bit 2 TOP_EFLX_INT
710 * Bit 1 TOP_PL4ODP_INT
711 * Bit 0 TOP_PL4IDU_INT
712 *----------------------------------------------------------------------------*/
713#define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000
714#define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000
715#define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000
716#define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000
717#define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800
718#define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400
719#define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200
720#define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100
721#define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080
722#define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040
723#define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020
724#define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010
725#define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008
726#define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004
727#define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002
728#define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001
729
730/*----------------------------------------------------------------------------
731 * Register 0x000E:PM3393 Global interrupt enable
732 * Bit 15 TOP_INTE
733 *----------------------------------------------------------------------------*/
734#define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
735
736/*----------------------------------------------------------------------------
737 * Register 0x0010: XTEF Miscellaneous Control
738 * Bit 7 RF_VAL
739 * Bit 6 RF_OVERRIDE
740 * Bit 5 LF_VAL
741 * Bit 4 LF_OVERRIDE
742 *----------------------------------------------------------------------------*/
743#define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080
744#define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040
745#define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020
746#define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010
747#define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0
748
749/*----------------------------------------------------------------------------
750 * Register 0x0011: XRF Miscellaneous Control
751 * Bit 6-4 EN_IDLE_REP
752 *----------------------------------------------------------------------------*/
753#define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070
754
755/*----------------------------------------------------------------------------
756 * Register 0x0100: SERDES 3125 Configuration Register 1
757 * Bit 10 RXEQB_3
758 * Bit 8 RXEQB_2
759 * Bit 6 RXEQB_1
760 * Bit 4 RXEQB_0
761 *----------------------------------------------------------------------------*/
762#define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0
763#define SUNI1x10GEXP_BITOFF_RXEQB_3 10
764#define SUNI1x10GEXP_BITOFF_RXEQB_2 8
765#define SUNI1x10GEXP_BITOFF_RXEQB_1 6
766#define SUNI1x10GEXP_BITOFF_RXEQB_0 4
767
768/*----------------------------------------------------------------------------
769 * Register 0x0101: SERDES 3125 Configuration Register 2
770 * Bit 12 YSEL
771 * Bit 7 PRE_EMPH_3
772 * Bit 6 PRE_EMPH_2
773 * Bit 5 PRE_EMPH_1
774 * Bit 4 PRE_EMPH_0
775 *----------------------------------------------------------------------------*/
776#define SUNI1x10GEXP_BITMSK_YSEL 0x1000
777#define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0
778#define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080
779#define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040
780#define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020
781#define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010
782
783/*----------------------------------------------------------------------------
784 * Register 0x0102: SERDES 3125 Interrupt Enable Register
785 * Bit 3 LASIE
786 * Bit 2 SPLL_RAE
787 * Bit 1 MPLL_RAE
788 * Bit 0 PLL_LOCKE
789 *----------------------------------------------------------------------------*/
790#define SUNI1x10GEXP_BITMSK_LASIE 0x0008
791#define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004
792#define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002
793#define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001
794
795/*----------------------------------------------------------------------------
796 * Register 0x0103: SERDES 3125 Interrupt Visibility Register
797 * Bit 3 LASIV
798 * Bit 2 SPLL_RAV
799 * Bit 1 MPLL_RAV
800 * Bit 0 PLL_LOCKV
801 *----------------------------------------------------------------------------*/
802#define SUNI1x10GEXP_BITMSK_LASIV 0x0008
803#define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004
804#define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002
805#define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001
806
807/*----------------------------------------------------------------------------
808 * Register 0x0104: SERDES 3125 Interrupt Status Register
809 * Bit 3 LASII
810 * Bit 2 SPLL_RAI
811 * Bit 1 MPLL_RAI
812 * Bit 0 PLL_LOCKI
813 *----------------------------------------------------------------------------*/
814#define SUNI1x10GEXP_BITMSK_LASII 0x0008
815#define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004
816#define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002
817#define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001
818
819/*----------------------------------------------------------------------------
820 * Register 0x0107: SERDES 3125 Test Configuration
821 * Bit 12 DUALTX
822 * Bit 10 HC_1
823 * Bit 9 HC_0
824 *----------------------------------------------------------------------------*/
825#define SUNI1x10GEXP_BITMSK_DUALTX 0x1000
826#define SUNI1x10GEXP_BITMSK_HC 0x0600
827#define SUNI1x10GEXP_BITOFF_HC_0 9
828
829/*----------------------------------------------------------------------------
830 * Register 0x2040: RXXG Configuration 1
831 * Bit 15 RXXG_RXEN
832 * Bit 14 RXXG_ROCF
833 * Bit 13 RXXG_PAD_STRIP
834 * Bit 10 RXXG_PUREP
835 * Bit 9 RXXG_LONGP
836 * Bit 8 RXXG_PARF
837 * Bit 7 RXXG_FLCHK
838 * Bit 5 RXXG_PASS_CTRL
839 * Bit 3 RXXG_CRC_STRIP
840 * Bit 2-0 RXXG_MIFG
841 *----------------------------------------------------------------------------*/
842#define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
843#define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000
844#define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000
845#define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
846#define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200
847#define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100
848#define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
849#define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020
850#define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
851
852/*----------------------------------------------------------------------------
853 * Register 0x02041: RXXG Configuration 2
854 * Bit 7-0 RXXG_HDRSIZE
855 *----------------------------------------------------------------------------*/
856#define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF
857
858/*----------------------------------------------------------------------------
859 * Register 0x2042: RXXG Configuration 3
860 * Bit 15 RXXG_MIN_LERRE
861 * Bit 14 RXXG_MAX_LERRE
862 * Bit 12 RXXG_LINE_ERRE
863 * Bit 10 RXXG_RX_OVRE
864 * Bit 9 RXXG_ADR_FILTERE
865 * Bit 8 RXXG_ERR_FILTERE
866 * Bit 5 RXXG_PRMB_ERRE
867 *----------------------------------------------------------------------------*/
868#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000
869#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000
870#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000
871#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400
872#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200
873#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100
874#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
875
876/*----------------------------------------------------------------------------
877 * Register 0x2043: RXXG Interrupt
878 * Bit 15 RXXG_MIN_LERRI
879 * Bit 14 RXXG_MAX_LERRI
880 * Bit 12 RXXG_LINE_ERRI
881 * Bit 10 RXXG_RX_OVRI
882 * Bit 9 RXXG_ADR_FILTERI
883 * Bit 8 RXXG_ERR_FILTERI
884 * Bit 5 RXXG_PRMB_ERRE
885 *----------------------------------------------------------------------------*/
886#define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000
887#define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000
888#define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000
889#define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400
890#define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200
891#define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100
892#define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
893
894/*----------------------------------------------------------------------------
895 * Register 0x2049: RXXG Receive FIFO Threshold
896 * Bit 2-0 RXXG_CUT_THRU
897 *----------------------------------------------------------------------------*/
898#define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007
899#define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0
900
901/*----------------------------------------------------------------------------
902 * Register 0x2062H - 0x2069: RXXG Exact Match VID
903 * Bit 11-0 RXXG_VID_MATCH
904 *----------------------------------------------------------------------------*/
905#define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF
906#define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0
907
908/*----------------------------------------------------------------------------
909 * Register 0x206EH - 0x206F: RXXG Address Filter Control
910 * Bit 3 RXXG_FORWARD_ENABLE
911 * Bit 2 RXXG_VLAN_ENABLE
912 * Bit 1 RXXG_SRC_ADDR
913 * Bit 0 RXXG_MATCH_ENABLE
914 *----------------------------------------------------------------------------*/
915#define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008
916#define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004
917#define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002
918#define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001
919
920/*----------------------------------------------------------------------------
921 * Register 0x2070: RXXG Address Filter Control 2
922 * Bit 1 RXXG_PMODE
923 * Bit 0 RXXG_MHASH_EN
924 *----------------------------------------------------------------------------*/
925#define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002
926#define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
927
928/*----------------------------------------------------------------------------
929 * Register 0x2081: XRF Control Register 2
930 * Bit 6 EN_PKT_GEN
931 * Bit 4-2 PATT
932 *----------------------------------------------------------------------------*/
933#define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040
934#define SUNI1x10GEXP_BITMSK_PATT 0x001C
935#define SUNI1x10GEXP_BITOFF_PATT 2
936
937/*----------------------------------------------------------------------------
938 * Register 0x2088: XRF Interrupt Enable
939 * Bit 12-9 LANE_HICERE
940 * Bit 8-5 HS_SD_LANEE
941 * Bit 4 ALIGN_STATUS_ERRE
942 * Bit 3-0 LANE_SYNC_STAT_ERRE
943 *----------------------------------------------------------------------------*/
944#define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00
945#define SUNI1x10GEXP_BITOFF_LANE_HICERE 9
946#define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0
947#define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5
948#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010
949#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F
950#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0
951
952/*----------------------------------------------------------------------------
953 * Register 0x2089: XRF Interrupt Status
954 * Bit 12-9 LANE_HICERI
955 * Bit 8-5 HS_SD_LANEI
956 * Bit 4 ALIGN_STATUS_ERRI
957 * Bit 3-0 LANE_SYNC_STAT_ERRI
958 *----------------------------------------------------------------------------*/
959#define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00
960#define SUNI1x10GEXP_BITOFF_LANE_HICERI 9
961#define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0
962#define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5
963#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010
964#define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F
965#define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0
966
967/*----------------------------------------------------------------------------
968 * Register 0x208A: XRF Error Status
969 * Bit 8-5 HS_SD_LANE
970 * Bit 4 ALIGN_STATUS_ERR
971 * Bit 3-0 LANE_SYNC_STAT_ERR
972 *----------------------------------------------------------------------------*/
973#define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100
974#define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080
975#define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040
976#define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020
977#define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010
978#define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008
979#define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004
980#define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002
981#define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001
982
983/*----------------------------------------------------------------------------
984 * Register 0x208B: XRF Diagnostic Interrupt Enable
985 * Bit 7-4 LANE_OVERRUNE
986 * Bit 3-0 LANE_UNDERRUNE
987 *----------------------------------------------------------------------------*/
988#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0
989#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4
990#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F
991#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0
992
993/*----------------------------------------------------------------------------
994 * Register 0x208C: XRF Diagnostic Interrupt Status
995 * Bit 7-4 LANE_OVERRUNI
996 * Bit 3-0 LANE_UNDERRUNI
997 *----------------------------------------------------------------------------*/
998#define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0
999#define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4
1000#define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F
1001#define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0
1002
1003/*----------------------------------------------------------------------------
1004 * Register 0x20C0: RXOAM Configuration
1005 * Bit 15 RXOAM_BUSY
1006 * Bit 14-12 RXOAM_F2_SEL
1007 * Bit 10-8 RXOAM_F1_SEL
1008 * Bit 7-6 RXOAM_FILTER_CTRL
1009 * Bit 5-0 RXOAM_PX_EN
1010 *----------------------------------------------------------------------------*/
1011#define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000
1012#define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000
1013#define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12
1014#define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700
1015#define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8
1016#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0
1017#define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6
1018#define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F
1019#define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0
1020
1021/*----------------------------------------------------------------------------
1022 * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1023 * Bit 15-8 RXOAM_FX_MASK
1024 * Bit 7-0 RXOAM_FX_VAL
1025 *----------------------------------------------------------------------------*/
1026#define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00
1027#define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8
1028#define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF
1029#define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0
1030
1031/*----------------------------------------------------------------------------
1032 * Register 0x20C3: RXOAM Configuration Register 2
1033 * Bit 13 RXOAM_REC_BYTE_VAL
1034 * Bit 11-10 RXOAM_BYPASS_MODE
1035 * Bit 5-0 RXOAM_PX_CLEAR
1036 *----------------------------------------------------------------------------*/
1037#define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000
1038#define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00
1039#define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10
1040#define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F
1041#define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0
1042
1043/*----------------------------------------------------------------------------
1044 * Register 0x20C4: RXOAM HEC Configuration
1045 * Bit 15-8 RXOAM_COSET
1046 * Bit 2 RXOAM_HEC_ERR_PKT
1047 * Bit 0 RXOAM_HEC_EN
1048 *----------------------------------------------------------------------------*/
1049#define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00
1050#define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8
1051#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004
1052#define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001
1053
1054/*----------------------------------------------------------------------------
1055 * Register 0x20C7: RXOAM Interrupt Enable
1056 * Bit 10 RXOAM_FILTER_THRSHE
1057 * Bit 9 RXOAM_OAM_ERRE
1058 * Bit 8 RXOAM_HECE_THRSHE
1059 * Bit 7 RXOAM_SOPE
1060 * Bit 6 RXOAM_RFE
1061 * Bit 5 RXOAM_LFE
1062 * Bit 4 RXOAM_DV_ERRE
1063 * Bit 3 RXOAM_DATA_INVALIDE
1064 * Bit 2 RXOAM_FILTER_DROPE
1065 * Bit 1 RXOAM_HECE
1066 * Bit 0 RXOAM_OFLE
1067 *----------------------------------------------------------------------------*/
1068#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400
1069#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200
1070#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100
1071#define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080
1072#define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040
1073#define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020
1074#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010
1075#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008
1076#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004
1077#define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002
1078#define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001
1079
1080/*----------------------------------------------------------------------------
1081 * Register 0x20C8: RXOAM Interrupt Status
1082 * Bit 10 RXOAM_FILTER_THRSHI
1083 * Bit 9 RXOAM_OAM_ERRI
1084 * Bit 8 RXOAM_HECE_THRSHI
1085 * Bit 7 RXOAM_SOPI
1086 * Bit 6 RXOAM_RFI
1087 * Bit 5 RXOAM_LFI
1088 * Bit 4 RXOAM_DV_ERRI
1089 * Bit 3 RXOAM_DATA_INVALIDI
1090 * Bit 2 RXOAM_FILTER_DROPI
1091 * Bit 1 RXOAM_HECI
1092 * Bit 0 RXOAM_OFLI
1093 *----------------------------------------------------------------------------*/
1094#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400
1095#define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200
1096#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100
1097#define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080
1098#define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040
1099#define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020
1100#define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010
1101#define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008
1102#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004
1103#define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002
1104#define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001
1105
1106/*----------------------------------------------------------------------------
1107 * Register 0x20C9: RXOAM Status
1108 * Bit 10 RXOAM_FILTER_THRSHV
1109 * Bit 8 RXOAM_HECE_THRSHV
1110 * Bit 6 RXOAM_RFV
1111 * Bit 5 RXOAM_LFV
1112 *----------------------------------------------------------------------------*/
1113#define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400
1114#define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100
1115#define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040
1116#define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020
1117
1118/*----------------------------------------------------------------------------
1119 * Register 0x2100: MSTAT Control
1120 * Bit 2 MSTAT_WRITE
1121 * Bit 1 MSTAT_CLEAR
1122 * Bit 0 MSTAT_SNAP
1123 *----------------------------------------------------------------------------*/
1124#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004
1125#define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
1126#define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
1127
1128/*----------------------------------------------------------------------------
1129 * Register 0x2109: MSTAT Counter Write Address
1130 * Bit 5-0 MSTAT_WRITE_ADDRESS
1131 *----------------------------------------------------------------------------*/
1132#define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1133#define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1134
1135/*----------------------------------------------------------------------------
1136 * Register 0x2200: IFLX Global Configuration Register
1137 * Bit 15 IFLX_IRCU_ENABLE
1138 * Bit 14 IFLX_IDSWT_ENABLE
1139 * Bit 13-0 IFLX_IFD_CNT
1140 *----------------------------------------------------------------------------*/
1141#define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000
1142#define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000
1143#define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF
1144#define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0
1145
1146/*----------------------------------------------------------------------------
1147 * Register 0x2209: IFLX FIFO Overflow Enable
1148 * Bit 0 IFLX_OVFE
1149 *----------------------------------------------------------------------------*/
1150#define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1151
1152/*----------------------------------------------------------------------------
1153 * Register 0x220A: IFLX FIFO Overflow Interrupt
1154 * Bit 0 IFLX_OVFI
1155 *----------------------------------------------------------------------------*/
1156#define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1157
1158/*----------------------------------------------------------------------------
1159 * Register 0x220D: IFLX Indirect Channel Address
1160 * Bit 15 IFLX_BUSY
1161 * Bit 14 IFLX_RWB
1162 *----------------------------------------------------------------------------*/
1163#define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000
1164#define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000
1165
1166/*----------------------------------------------------------------------------
1167 * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1168 * Bit 9-0 IFLX_LOLIM
1169 *----------------------------------------------------------------------------*/
1170#define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF
1171#define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0
1172
1173/*----------------------------------------------------------------------------
1174 * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1175 * Bit 9-0 IFLX_HILIM
1176 *----------------------------------------------------------------------------*/
1177#define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF
1178#define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0
1179
1180/*----------------------------------------------------------------------------
1181 * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1182 * Bit 15 IFLX_FULL
1183 * Bit 14 IFLX_AFULL
1184 * Bit 13-0 IFLX_AFTH
1185 *----------------------------------------------------------------------------*/
1186#define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000
1187#define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000
1188#define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF
1189#define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0
1190
1191/*----------------------------------------------------------------------------
1192 * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1193 * Bit 15 IFLX_EMPTY
1194 * Bit 14 IFLX_AEMPTY
1195 * Bit 13-0 IFLX_AETH
1196 *----------------------------------------------------------------------------*/
1197#define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000
1198#define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000
1199#define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF
1200#define SUNI1x10GEXP_BITOFF_IFLX_AETH 0
1201
1202/*----------------------------------------------------------------------------
1203 * Register 0x2240: PL4MOS Configuration Register
1204 * Bit 3 PL4MOS_RE_INIT
1205 * Bit 2 PL4MOS_EN
1206 * Bit 1 PL4MOS_NO_STATUS
1207 *----------------------------------------------------------------------------*/
1208#define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008
1209#define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004
1210#define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002
1211
1212/*----------------------------------------------------------------------------
1213 * Register 0x2243: PL4MOS MaxBurst1 Register
1214 * Bit 11-0 PL4MOS_MAX_BURST1
1215 *----------------------------------------------------------------------------*/
1216#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF
1217#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0
1218
1219/*----------------------------------------------------------------------------
1220 * Register 0x2244: PL4MOS MaxBurst2 Register
1221 * Bit 11-0 PL4MOS_MAX_BURST2
1222 *----------------------------------------------------------------------------*/
1223#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF
1224#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0
1225
1226/*----------------------------------------------------------------------------
1227 * Register 0x2245: PL4MOS Transfer Size Register
1228 * Bit 7-0 PL4MOS_MAX_TRANSFER
1229 *----------------------------------------------------------------------------*/
1230#define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF
1231#define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0
1232
1233/*----------------------------------------------------------------------------
1234 * Register 0x2280: PL4ODP Configuration
1235 * Bit 15-12 PL4ODP_REPEAT_T
1236 * Bit 8 PL4ODP_SOP_RULE
1237 * Bit 1 PL4ODP_EN_PORTS
1238 * Bit 0 PL4ODP_EN_DFWD
1239 *----------------------------------------------------------------------------*/
1240#define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000
1241#define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12
1242#define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100
1243#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002
1244#define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001
1245
1246/*----------------------------------------------------------------------------
1247 * Register 0x2282: PL4ODP Interrupt Mask
1248 * Bit 0 PL4ODP_OUT_DISE
1249 *----------------------------------------------------------------------------*/
1250#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001
1251
1252
1253
1254#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080
1255#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040
1256#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008
1257#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004
1258#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002
1259
1260
1261/*----------------------------------------------------------------------------
1262 * Register 0x2283: PL4ODP Interrupt
1263 * Bit 0 PL4ODP_OUT_DISI
1264 *----------------------------------------------------------------------------*/
1265#define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001
1266
1267
1268
1269#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080
1270#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040
1271#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008
1272#define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004
1273#define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002
1274
1275/*----------------------------------------------------------------------------
1276 * Register 0x2300: PL4IO Lock Detect Status
1277 * Bit 15 PL4IO_OUT_ROOLV
1278 * Bit 12 PL4IO_IS_ROOLV
1279 * Bit 11 PL4IO_DIP2_ERRV
1280 * Bit 8 PL4IO_ID_ROOLV
1281 * Bit 4 PL4IO_IS_DOOLV
1282 * Bit 0 PL4IO_ID_DOOLV
1283 *----------------------------------------------------------------------------*/
1284#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000
1285#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000
1286#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800
1287#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100
1288#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010
1289#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001
1290
1291/*----------------------------------------------------------------------------
1292 * Register 0x2301: PL4IO Lock Detect Change
1293 * Bit 15 PL4IO_OUT_ROOLI
1294 * Bit 12 PL4IO_IS_ROOLI
1295 * Bit 11 PL4IO_DIP2_ERRI
1296 * Bit 8 PL4IO_ID_ROOLI
1297 * Bit 4 PL4IO_IS_DOOLI
1298 * Bit 0 PL4IO_ID_DOOLI
1299 *----------------------------------------------------------------------------*/
1300#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000
1301#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000
1302#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800
1303#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100
1304#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010
1305#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001
1306
1307/*----------------------------------------------------------------------------
1308 * Register 0x2302: PL4IO Lock Detect Mask
1309 * Bit 15 PL4IO_OUT_ROOLE
1310 * Bit 12 PL4IO_IS_ROOLE
1311 * Bit 11 PL4IO_DIP2_ERRE
1312 * Bit 8 PL4IO_ID_ROOLE
1313 * Bit 4 PL4IO_IS_DOOLE
1314 * Bit 0 PL4IO_ID_DOOLE
1315 *----------------------------------------------------------------------------*/
1316#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000
1317#define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000
1318#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800
1319#define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100
1320#define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010
1321#define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001
1322
1323/*----------------------------------------------------------------------------
1324 * Register 0x2303: PL4IO Lock Detect Limits
1325 * Bit 15-8 PL4IO_REF_LIMIT
1326 * Bit 7-0 PL4IO_TRAN_LIMIT
1327 *----------------------------------------------------------------------------*/
1328#define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00
1329#define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8
1330#define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF
1331#define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0
1332
1333/*----------------------------------------------------------------------------
1334 * Register 0x2304: PL4IO Calendar Repetitions
1335 * Bit 15-8 PL4IO_IN_MUL
1336 * Bit 7-0 PL4IO_OUT_MUL
1337 *----------------------------------------------------------------------------*/
1338#define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00
1339#define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8
1340#define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF
1341#define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0
1342
1343/*----------------------------------------------------------------------------
1344 * Register 0x2305: PL4IO Configuration
1345 * Bit 15 PL4IO_DIP2_ERR_CHK
1346 * Bit 11 PL4IO_ODAT_DIS
1347 * Bit 10 PL4IO_TRAIN_DIS
1348 * Bit 9 PL4IO_OSTAT_DIS
1349 * Bit 8 PL4IO_ISTAT_DIS
1350 * Bit 7 PL4IO_NO_ISTAT
1351 * Bit 6 PL4IO_STAT_OUTSEL
1352 * Bit 5 PL4IO_INSEL
1353 * Bit 4 PL4IO_DLSEL
1354 * Bit 1-0 PL4IO_OUTSEL
1355 *----------------------------------------------------------------------------*/
1356#define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000
1357#define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800
1358#define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400
1359#define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200
1360#define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100
1361#define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080
1362#define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040
1363#define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020
1364#define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010
1365#define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003
1366#define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0
1367
1368/*----------------------------------------------------------------------------
1369 * Register 0x3040: TXXG Configuration Register 1
1370 * Bit 15 TXXG_TXEN0
1371 * Bit 13 TXXG_HOSTPAUSE
1372 * Bit 12-7 TXXG_IPGT
1373 * Bit 5 TXXG_32BIT_ALIGN
1374 * Bit 4 TXXG_CRCEN
1375 * Bit 3 TXXG_FCTX
1376 * Bit 2 TXXG_FCRX
1377 * Bit 1 TXXG_PADEN
1378 * Bit 0 TXXG_SPRE
1379 *----------------------------------------------------------------------------*/
1380#define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
1381#define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000
1382#define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80
1383#define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7
1384#define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
1385#define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
1386#define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
1387#define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
1388#define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
1389#define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001
1390
1391/*----------------------------------------------------------------------------
1392 * Register 0x3041: TXXG Configuration Register 2
1393 * Bit 7-0 TXXG_HDRSIZE
1394 *----------------------------------------------------------------------------*/
1395#define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF
1396
1397/*----------------------------------------------------------------------------
1398 * Register 0x3042: TXXG Configuration Register 3
1399 * Bit 15 TXXG_FIFO_ERRE
1400 * Bit 14 TXXG_FIFO_UDRE
1401 * Bit 13 TXXG_MAX_LERRE
1402 * Bit 12 TXXG_MIN_LERRE
1403 * Bit 11 TXXG_XFERE
1404 *----------------------------------------------------------------------------*/
1405#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000
1406#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000
1407#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000
1408#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000
1409#define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800
1410
1411/*----------------------------------------------------------------------------
1412 * Register 0x3043: TXXG Interrupt
1413 * Bit 15 TXXG_FIFO_ERRI
1414 * Bit 14 TXXG_FIFO_UDRI
1415 * Bit 13 TXXG_MAX_LERRI
1416 * Bit 12 TXXG_MIN_LERRI
1417 * Bit 11 TXXG_XFERI
1418 *----------------------------------------------------------------------------*/
1419#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000
1420#define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000
1421#define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000
1422#define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000
1423#define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800
1424
1425/*----------------------------------------------------------------------------
1426 * Register 0x3044: TXXG Status Register
1427 * Bit 1 TXXG_TXACTIVE
1428 * Bit 0 TXXG_PAUSED
1429 *----------------------------------------------------------------------------*/
1430#define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002
1431#define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001
1432
1433/*----------------------------------------------------------------------------
1434 * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register
1435 * Bit 7-0 TXXG_TX_MINFR
1436 *----------------------------------------------------------------------------*/
1437#define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF
1438#define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0
1439
1440/*----------------------------------------------------------------------------
1441 * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1442 * Bit 7-0 TXXG_FC_PAUSE_QNTM
1443 *----------------------------------------------------------------------------*/
1444#define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF
1445#define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0
1446
1447/*----------------------------------------------------------------------------
1448 * Register 0x3080: XTEF Control
1449 * Bit 3-0 XTEF_FORCE_PARITY_ERR
1450 *----------------------------------------------------------------------------*/
1451#define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F
1452#define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0
1453
1454/*----------------------------------------------------------------------------
1455 * Register 0x3084: XTEF Interrupt Event Register
1456 * Bit 0 XTEF_LOST_SYNCI
1457 *----------------------------------------------------------------------------*/
1458#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001
1459
1460/*----------------------------------------------------------------------------
1461 * Register 0x3085: XTEF Interrupt Enable Register
1462 * Bit 0 XTEF_LOST_SYNCE
1463 *----------------------------------------------------------------------------*/
1464#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001
1465
1466/*----------------------------------------------------------------------------
1467 * Register 0x3086: XTEF Visibility Register
1468 * Bit 0 XTEF_LOST_SYNCV
1469 *----------------------------------------------------------------------------*/
1470#define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001
1471
1472/*----------------------------------------------------------------------------
1473 * Register 0x30C0: TXOAM OAM Configuration
1474 * Bit 15 TXOAM_HEC_EN
1475 * Bit 14 TXOAM_EMPTYCODE_EN
1476 * Bit 13 TXOAM_FORCE_IDLE
1477 * Bit 12 TXOAM_IGNORE_IDLE
1478 * Bit 11-6 TXOAM_PX_OVERWRITE
1479 * Bit 5-0 TXOAM_PX_SEL
1480 *----------------------------------------------------------------------------*/
1481#define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000
1482#define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000
1483#define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000
1484#define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000
1485#define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0
1486#define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6
1487#define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F
1488#define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0
1489
1490/*----------------------------------------------------------------------------
1491 * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1492 * Bit 15 TXOAM_MINIDIS
1493 * Bit 14 TXOAM_BUSY
1494 * Bit 13 TXOAM_TRANS_EN
1495 * Bit 10-0 TXOAM_MINIRATE
1496 *----------------------------------------------------------------------------*/
1497#define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000
1498#define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000
1499#define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000
1500#define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF
1501
1502/*----------------------------------------------------------------------------
1503 * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1504 * Bit 13-10 TXOAM_FTHRESH
1505 * Bit 9-6 TXOAM_MINIPOST
1506 * Bit 5-0 TXOAM_MINIPRE
1507 *----------------------------------------------------------------------------*/
1508#define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00
1509#define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10
1510#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0
1511#define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6
1512#define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F
1513
1514/*----------------------------------------------------------------------------
1515 * Register 0x30C6: TXOAM Interrupt Enable
1516 * Bit 2 TXOAM_SOP_ERRE
1517 * Bit 1 TXOAM_OFLE
1518 * Bit 0 TXOAM_ERRE
1519 *----------------------------------------------------------------------------*/
1520#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004
1521#define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002
1522#define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001
1523
1524/*----------------------------------------------------------------------------
1525 * Register 0x30C7: TXOAM Interrupt Status
1526 * Bit 2 TXOAM_SOP_ERRI
1527 * Bit 1 TXOAM_OFLI
1528 * Bit 0 TXOAM_ERRI
1529 *----------------------------------------------------------------------------*/
1530#define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004
1531#define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002
1532#define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001
1533
1534/*----------------------------------------------------------------------------
1535 * Register 0x30CF: TXOAM Coset
1536 * Bit 7-0 TXOAM_COSET
1537 *----------------------------------------------------------------------------*/
1538#define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF
1539
1540/*----------------------------------------------------------------------------
1541 * Register 0x3200: EFLX Global Configuration
1542 * Bit 15 EFLX_ERCU_EN
1543 * Bit 7 EFLX_EN_EDSWT
1544 *----------------------------------------------------------------------------*/
1545#define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000
1546#define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080
1547
1548/*----------------------------------------------------------------------------
1549 * Register 0x3201: EFLX ERCU Global Status
1550 * Bit 13 EFLX_OVF_ERR
1551 *----------------------------------------------------------------------------*/
1552#define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000
1553
1554/*----------------------------------------------------------------------------
1555 * Register 0x3202: EFLX Indirect Channel Address
1556 * Bit 15 EFLX_BUSY
1557 * Bit 14 EFLX_RDWRB
1558 *----------------------------------------------------------------------------*/
1559#define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000
1560#define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000
1561
1562/*----------------------------------------------------------------------------
1563 * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1564 *----------------------------------------------------------------------------*/
1565#define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF
1566#define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0
1567
1568/*----------------------------------------------------------------------------
1569 * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1570 *----------------------------------------------------------------------------*/
1571#define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF
1572#define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0
1573
1574/*----------------------------------------------------------------------------
1575 * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1576 * Bit 15 EFLX_FULL
1577 * Bit 14 EFLX_AFULL
1578 * Bit 13-0 EFLX_AFTH
1579 *----------------------------------------------------------------------------*/
1580#define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000
1581#define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000
1582#define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF
1583#define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0
1584
1585/*----------------------------------------------------------------------------
1586 * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1587 * Bit 15 EFLX_EMPTY
1588 * Bit 14 EFLX_AEMPTY
1589 * Bit 13-0 EFLX_AETH
1590 *----------------------------------------------------------------------------*/
1591#define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000
1592#define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000
1593#define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF
1594#define SUNI1x10GEXP_BITOFF_EFLX_AETH 0
1595
1596/*----------------------------------------------------------------------------
1597 * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1598 *----------------------------------------------------------------------------*/
1599#define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF
1600#define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0
1601
1602/*----------------------------------------------------------------------------
1603 * Register 0x320C: EFLX FIFO Overflow Error Enable
1604 * Bit 0 EFLX_OVFE
1605 *----------------------------------------------------------------------------*/
1606#define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001
1607
1608/*----------------------------------------------------------------------------
1609 * Register 0x320D: EFLX FIFO Overflow Error Indication
1610 * Bit 0 EFLX_OVFI
1611 *----------------------------------------------------------------------------*/
1612#define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001
1613
1614/*----------------------------------------------------------------------------
1615 * Register 0x3210: EFLX Channel Provision
1616 * Bit 0 EFLX_PROV
1617 *----------------------------------------------------------------------------*/
1618#define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001
1619
1620/*----------------------------------------------------------------------------
1621 * Register 0x3280: PL4IDU Configuration
1622 * Bit 2 PL4IDU_SYNCH_ON_TRAIN
1623 * Bit 1 PL4IDU_EN_PORTS
1624 * Bit 0 PL4IDU_EN_DFWD
1625 *----------------------------------------------------------------------------*/
1626#define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004
1627#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002
1628#define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001
1629
1630/*----------------------------------------------------------------------------
1631 * Register 0x3282: PL4IDU Interrupt Mask
1632 * Bit 1 PL4IDU_DIP4E
1633 *----------------------------------------------------------------------------*/
1634#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002
1635
1636/*----------------------------------------------------------------------------
1637 * Register 0x3283: PL4IDU Interrupt
1638 * Bit 1 PL4IDU_DIP4I
1639 *----------------------------------------------------------------------------*/
1640#define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002
1641
1642#endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */
1643
diff --git a/drivers/net/chelsio/tp.c b/drivers/net/chelsio/tp.c
deleted file mode 100644
index 8bed4a59e65f..000000000000
--- a/drivers/net/chelsio/tp.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
2#include "common.h"
3#include "regs.h"
4#include "tp.h"
5#ifdef CONFIG_CHELSIO_T1_1G
6#include "fpga_defs.h"
7#endif
8
9struct petp {
10 adapter_t *adapter;
11};
12
13/* Pause deadlock avoidance parameters */
14#define DROP_MSEC 16
15#define DROP_PKTS_CNT 1
16
17static void tp_init(adapter_t * ap, const struct tp_params *p,
18 unsigned int tp_clk)
19{
20 u32 val;
21
22 if (!t1_is_asic(ap))
23 return;
24
25 val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
26 F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
27 if (!p->pm_size)
28 val |= F_OFFLOAD_DISABLE;
29 else
30 val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM;
31 writel(val, ap->regs + A_TP_IN_CONFIG);
32 writel(F_TP_OUT_CSPI_CPL |
33 F_TP_OUT_ESPI_ETHERNET |
34 F_TP_OUT_ESPI_GENERATE_IP_CSUM |
35 F_TP_OUT_ESPI_GENERATE_TCP_CSUM, ap->regs + A_TP_OUT_CONFIG);
36 writel(V_IP_TTL(64) |
37 F_PATH_MTU /* IP DF bit */ |
38 V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
39 V_SYN_COOKIE_PARAMETER(29), ap->regs + A_TP_GLOBAL_CONFIG);
40 /*
41 * Enable pause frame deadlock prevention.
42 */
43 if (is_T2(ap) && ap->params.nports > 1) {
44 u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
45
46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
47 V_DROP_TICKS_CNT(drop_ticks) |
48 V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
49 ap->regs + A_TP_TX_DROP_CONFIG);
50 }
51}
52
53void t1_tp_destroy(struct petp *tp)
54{
55 kfree(tp);
56}
57
58struct petp *__devinit t1_tp_create(adapter_t * adapter, struct tp_params *p)
59{
60 struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
61
62 if (!tp)
63 return NULL;
64
65 tp->adapter = adapter;
66
67 return tp;
68}
69
70void t1_tp_intr_enable(struct petp *tp)
71{
72 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
73
74#ifdef CONFIG_CHELSIO_T1_1G
75 if (!t1_is_asic(tp->adapter)) {
76 /* FPGA */
77 writel(0xffffffff,
78 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
80 tp->adapter->regs + A_PL_ENABLE);
81 } else
82#endif
83 {
84 /* We don't use any TP interrupts */
85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
86 writel(tp_intr | F_PL_INTR_TP,
87 tp->adapter->regs + A_PL_ENABLE);
88 }
89}
90
91void t1_tp_intr_disable(struct petp *tp)
92{
93 u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
94
95#ifdef CONFIG_CHELSIO_T1_1G
96 if (!t1_is_asic(tp->adapter)) {
97 /* FPGA */
98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
99 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
100 tp->adapter->regs + A_PL_ENABLE);
101 } else
102#endif
103 {
104 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
105 writel(tp_intr & ~F_PL_INTR_TP,
106 tp->adapter->regs + A_PL_ENABLE);
107 }
108}
109
110void t1_tp_intr_clear(struct petp *tp)
111{
112#ifdef CONFIG_CHELSIO_T1_1G
113 if (!t1_is_asic(tp->adapter)) {
114 writel(0xffffffff,
115 tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
116 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
117 return;
118 }
119#endif
120 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
121 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
122}
123
124int t1_tp_intr_handler(struct petp *tp)
125{
126 u32 cause;
127
128#ifdef CONFIG_CHELSIO_T1_1G
129 /* FPGA doesn't support TP interrupts. */
130 if (!t1_is_asic(tp->adapter))
131 return 1;
132#endif
133
134 cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
135 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
136 return 0;
137}
138
139static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
140{
141 u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
142
143 if (enable)
144 val |= csum_bit;
145 else
146 val &= ~csum_bit;
147 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
148}
149
150void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
151{
152 set_csum_offload(tp, F_IP_CSUM, enable);
153}
154
155void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
156{
157 set_csum_offload(tp, F_TCP_CSUM, enable);
158}
159
160/*
161 * Initialize TP state. tp_params contains initial settings for some TP
162 * parameters, particularly the one-time PM and CM settings.
163 */
164int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
165{
166 adapter_t *adapter = tp->adapter;
167
168 tp_init(adapter, p, tp_clk);
169 writel(F_TP_RESET, adapter->regs + A_TP_RESET);
170 return 0;
171}
diff --git a/drivers/net/chelsio/tp.h b/drivers/net/chelsio/tp.h
deleted file mode 100644
index dfd8ce25106a..000000000000
--- a/drivers/net/chelsio/tp.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/* $Date: 2005/03/07 23:59:05 $ $RCSfile: tp.h,v $ $Revision: 1.20 $ */
2#ifndef CHELSIO_TP_H
3#define CHELSIO_TP_H
4
5#include "common.h"
6
7#define TP_MAX_RX_COALESCING_SIZE 16224U
8
9struct tp_mib_statistics {
10
11 /* IP */
12 u32 ipInReceive_hi;
13 u32 ipInReceive_lo;
14 u32 ipInHdrErrors_hi;
15 u32 ipInHdrErrors_lo;
16 u32 ipInAddrErrors_hi;
17 u32 ipInAddrErrors_lo;
18 u32 ipInUnknownProtos_hi;
19 u32 ipInUnknownProtos_lo;
20 u32 ipInDiscards_hi;
21 u32 ipInDiscards_lo;
22 u32 ipInDelivers_hi;
23 u32 ipInDelivers_lo;
24 u32 ipOutRequests_hi;
25 u32 ipOutRequests_lo;
26 u32 ipOutDiscards_hi;
27 u32 ipOutDiscards_lo;
28 u32 ipOutNoRoutes_hi;
29 u32 ipOutNoRoutes_lo;
30 u32 ipReasmTimeout;
31 u32 ipReasmReqds;
32 u32 ipReasmOKs;
33 u32 ipReasmFails;
34
35 u32 reserved[8];
36
37 /* TCP */
38 u32 tcpActiveOpens;
39 u32 tcpPassiveOpens;
40 u32 tcpAttemptFails;
41 u32 tcpEstabResets;
42 u32 tcpOutRsts;
43 u32 tcpCurrEstab;
44 u32 tcpInSegs_hi;
45 u32 tcpInSegs_lo;
46 u32 tcpOutSegs_hi;
47 u32 tcpOutSegs_lo;
48 u32 tcpRetransSeg_hi;
49 u32 tcpRetransSeg_lo;
50 u32 tcpInErrs_hi;
51 u32 tcpInErrs_lo;
52 u32 tcpRtoMin;
53 u32 tcpRtoMax;
54};
55
56struct petp;
57struct tp_params;
58
59struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p);
60void t1_tp_destroy(struct petp *tp);
61
62void t1_tp_intr_disable(struct petp *tp);
63void t1_tp_intr_enable(struct petp *tp);
64void t1_tp_intr_clear(struct petp *tp);
65int t1_tp_intr_handler(struct petp *tp);
66
67void t1_tp_get_mib_statistics(adapter_t *adap, struct tp_mib_statistics *tps);
68void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable);
69void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable);
70int t1_tp_set_coalescing_size(struct petp *tp, unsigned int size);
71int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk);
72#endif
diff --git a/drivers/net/chelsio/vsc7326.c b/drivers/net/chelsio/vsc7326.c
deleted file mode 100644
index b0cb388f5e12..000000000000
--- a/drivers/net/chelsio/vsc7326.c
+++ /dev/null
@@ -1,730 +0,0 @@
1/* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */
2
3/* Driver for Vitesse VSC7326 (Schaumburg) MAC */
4
5#include "gmac.h"
6#include "elmer0.h"
7#include "vsc7326_reg.h"
8
9/* Update fast changing statistics every 15 seconds */
10#define STATS_TICK_SECS 15
11/* 30 minutes for full statistics update */
12#define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)
13
14#define MAX_MTU 9600
15
16/* The egress WM value 0x01a01fff should be used only when the
17 * interface is down (MAC port disabled). This is a workaround
18 * for disabling the T2/MAC flow-control. When the interface is
19 * enabled, the WM value should be set to 0x014a03F0.
20 */
21#define WM_DISABLE 0x01a01fff
22#define WM_ENABLE 0x014a03F0
23
24struct init_table {
25 u32 addr;
26 u32 data;
27};
28
29struct _cmac_instance {
30 u32 index;
31 u32 ticks;
32};
33
34#define INITBLOCK_SLEEP 0xffffffff
35
36static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
37{
38 u32 status, vlo, vhi;
39 int i;
40
41 spin_lock_bh(&adapter->mac_lock);
42 t1_tpi_read(adapter, (addr << 2) + 4, &vlo);
43 i = 0;
44 do {
45 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
46 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
47 status = (vhi << 16) | vlo;
48 i++;
49 } while (((status & 1) == 0) && (i < 50));
50 if (i == 50)
51 pr_err("Invalid tpi read from MAC, breaking loop.\n");
52
53 t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
54 t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
55
56 *val = (vhi << 16) | vlo;
57
58 /* pr_err("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
59 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
60 ((addr&0x01fe)>>1), *val); */
61 spin_unlock_bh(&adapter->mac_lock);
62}
63
64static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
65{
66 spin_lock_bh(&adapter->mac_lock);
67 t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
68 t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
69 /* pr_err("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
70 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
71 ((addr&0x01fe)>>1), data); */
72 spin_unlock_bh(&adapter->mac_lock);
73}
74
75/* Hard reset the MAC. This wipes out *all* configuration. */
76static void vsc7326_full_reset(adapter_t* adapter)
77{
78 u32 val;
79 u32 result = 0xffff;
80
81 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
82 val &= ~1;
83 t1_tpi_write(adapter, A_ELMER0_GPO, val);
84 udelay(2);
85 val |= 0x1; /* Enable mac MAC itself */
86 val |= 0x800; /* Turn off the red LED */
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
88 mdelay(1);
89 vsc_write(adapter, REG_SW_RESET, 0x80000001);
90 do {
91 mdelay(1);
92 vsc_read(adapter, REG_SW_RESET, &result);
93 } while (result != 0x0);
94}
95
96static struct init_table vsc7326_reset[] = {
97 { REG_IFACE_MODE, 0x00000000 },
98 { REG_CRC_CFG, 0x00000020 },
99 { REG_PLL_CLK_SPEED, 0x00050c00 },
100 { REG_PLL_CLK_SPEED, 0x00050c00 },
101 { REG_MSCH, 0x00002f14 },
102 { REG_SPI4_MISC, 0x00040409 },
103 { REG_SPI4_DESKEW, 0x00080000 },
104 { REG_SPI4_ING_SETUP2, 0x08080004 },
105 { REG_SPI4_ING_SETUP0, 0x04111004 },
106 { REG_SPI4_EGR_SETUP0, 0x80001a04 },
107 { REG_SPI4_ING_SETUP1, 0x02010000 },
108 { REG_AGE_INC(0), 0x00000000 },
109 { REG_AGE_INC(1), 0x00000000 },
110 { REG_ING_CONTROL, 0x0a200011 },
111 { REG_EGR_CONTROL, 0xa0010091 },
112};
113
114static struct init_table vsc7326_portinit[4][22] = {
115 { /* Port 0 */
116 /* FIFO setup */
117 { REG_DBG(0), 0x000004f0 },
118 { REG_HDX(0), 0x00073101 },
119 { REG_TEST(0,0), 0x00000022 },
120 { REG_TEST(1,0), 0x00000022 },
121 { REG_TOP_BOTTOM(0,0), 0x003f0000 },
122 { REG_TOP_BOTTOM(1,0), 0x00120000 },
123 { REG_HIGH_LOW_WM(0,0), 0x07460757 },
124 { REG_HIGH_LOW_WM(1,0), WM_DISABLE },
125 { REG_CT_THRHLD(0,0), 0x00000000 },
126 { REG_CT_THRHLD(1,0), 0x00000000 },
127 { REG_BUCKE(0), 0x0002ffff },
128 { REG_BUCKI(0), 0x0002ffff },
129 { REG_TEST(0,0), 0x00000020 },
130 { REG_TEST(1,0), 0x00000020 },
131 /* Port config */
132 { REG_MAX_LEN(0), 0x00002710 },
133 { REG_PORT_FAIL(0), 0x00000002 },
134 { REG_NORMALIZER(0), 0x00000a64 },
135 { REG_DENORM(0), 0x00000010 },
136 { REG_STICK_BIT(0), 0x03baa370 },
137 { REG_DEV_SETUP(0), 0x00000083 },
138 { REG_DEV_SETUP(0), 0x00000082 },
139 { REG_MODE_CFG(0), 0x0200259f },
140 },
141 { /* Port 1 */
142 /* FIFO setup */
143 { REG_DBG(1), 0x000004f0 },
144 { REG_HDX(1), 0x00073101 },
145 { REG_TEST(0,1), 0x00000022 },
146 { REG_TEST(1,1), 0x00000022 },
147 { REG_TOP_BOTTOM(0,1), 0x007e003f },
148 { REG_TOP_BOTTOM(1,1), 0x00240012 },
149 { REG_HIGH_LOW_WM(0,1), 0x07460757 },
150 { REG_HIGH_LOW_WM(1,1), WM_DISABLE },
151 { REG_CT_THRHLD(0,1), 0x00000000 },
152 { REG_CT_THRHLD(1,1), 0x00000000 },
153 { REG_BUCKE(1), 0x0002ffff },
154 { REG_BUCKI(1), 0x0002ffff },
155 { REG_TEST(0,1), 0x00000020 },
156 { REG_TEST(1,1), 0x00000020 },
157 /* Port config */
158 { REG_MAX_LEN(1), 0x00002710 },
159 { REG_PORT_FAIL(1), 0x00000002 },
160 { REG_NORMALIZER(1), 0x00000a64 },
161 { REG_DENORM(1), 0x00000010 },
162 { REG_STICK_BIT(1), 0x03baa370 },
163 { REG_DEV_SETUP(1), 0x00000083 },
164 { REG_DEV_SETUP(1), 0x00000082 },
165 { REG_MODE_CFG(1), 0x0200259f },
166 },
167 { /* Port 2 */
168 /* FIFO setup */
169 { REG_DBG(2), 0x000004f0 },
170 { REG_HDX(2), 0x00073101 },
171 { REG_TEST(0,2), 0x00000022 },
172 { REG_TEST(1,2), 0x00000022 },
173 { REG_TOP_BOTTOM(0,2), 0x00bd007e },
174 { REG_TOP_BOTTOM(1,2), 0x00360024 },
175 { REG_HIGH_LOW_WM(0,2), 0x07460757 },
176 { REG_HIGH_LOW_WM(1,2), WM_DISABLE },
177 { REG_CT_THRHLD(0,2), 0x00000000 },
178 { REG_CT_THRHLD(1,2), 0x00000000 },
179 { REG_BUCKE(2), 0x0002ffff },
180 { REG_BUCKI(2), 0x0002ffff },
181 { REG_TEST(0,2), 0x00000020 },
182 { REG_TEST(1,2), 0x00000020 },
183 /* Port config */
184 { REG_MAX_LEN(2), 0x00002710 },
185 { REG_PORT_FAIL(2), 0x00000002 },
186 { REG_NORMALIZER(2), 0x00000a64 },
187 { REG_DENORM(2), 0x00000010 },
188 { REG_STICK_BIT(2), 0x03baa370 },
189 { REG_DEV_SETUP(2), 0x00000083 },
190 { REG_DEV_SETUP(2), 0x00000082 },
191 { REG_MODE_CFG(2), 0x0200259f },
192 },
193 { /* Port 3 */
194 /* FIFO setup */
195 { REG_DBG(3), 0x000004f0 },
196 { REG_HDX(3), 0x00073101 },
197 { REG_TEST(0,3), 0x00000022 },
198 { REG_TEST(1,3), 0x00000022 },
199 { REG_TOP_BOTTOM(0,3), 0x00fc00bd },
200 { REG_TOP_BOTTOM(1,3), 0x00480036 },
201 { REG_HIGH_LOW_WM(0,3), 0x07460757 },
202 { REG_HIGH_LOW_WM(1,3), WM_DISABLE },
203 { REG_CT_THRHLD(0,3), 0x00000000 },
204 { REG_CT_THRHLD(1,3), 0x00000000 },
205 { REG_BUCKE(3), 0x0002ffff },
206 { REG_BUCKI(3), 0x0002ffff },
207 { REG_TEST(0,3), 0x00000020 },
208 { REG_TEST(1,3), 0x00000020 },
209 /* Port config */
210 { REG_MAX_LEN(3), 0x00002710 },
211 { REG_PORT_FAIL(3), 0x00000002 },
212 { REG_NORMALIZER(3), 0x00000a64 },
213 { REG_DENORM(3), 0x00000010 },
214 { REG_STICK_BIT(3), 0x03baa370 },
215 { REG_DEV_SETUP(3), 0x00000083 },
216 { REG_DEV_SETUP(3), 0x00000082 },
217 { REG_MODE_CFG(3), 0x0200259f },
218 },
219};
220
221static void run_table(adapter_t *adapter, struct init_table *ib, int len)
222{
223 int i;
224
225 for (i = 0; i < len; i++) {
226 if (ib[i].addr == INITBLOCK_SLEEP) {
227 udelay( ib[i].data );
228 pr_err("sleep %d us\n",ib[i].data);
229 } else
230 vsc_write( adapter, ib[i].addr, ib[i].data );
231 }
232}
233
234static int bist_rd(adapter_t *adapter, int moduleid, int address)
235{
236 int data = 0;
237 u32 result = 0;
238
239 if ((address != 0x0) &&
240 (address != 0x1) &&
241 (address != 0x2) &&
242 (address != 0xd) &&
243 (address != 0xe))
244 pr_err("No bist address: 0x%x\n", address);
245
246 data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
247 ((moduleid & 0xff) << 0));
248 vsc_write(adapter, REG_RAM_BIST_CMD, data);
249
250 udelay(10);
251
252 vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
253 if ((result & (1 << 9)) != 0x0)
254 pr_err("Still in bist read: 0x%x\n", result);
255 else if ((result & (1 << 8)) != 0x0)
256 pr_err("bist read error: 0x%x\n", result);
257
258 return result & 0xff;
259}
260
261static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
262{
263 int data = 0;
264 u32 result = 0;
265
266 if ((address != 0x0) &&
267 (address != 0x1) &&
268 (address != 0x2) &&
269 (address != 0xd) &&
270 (address != 0xe))
271 pr_err("No bist address: 0x%x\n", address);
272
273 if (value > 255)
274 pr_err("Suspicious write out of range value: 0x%x\n", value);
275
276 data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
277 ((moduleid & 0xff) << 0));
278 vsc_write(adapter, REG_RAM_BIST_CMD, data);
279
280 udelay(5);
281
282 vsc_read(adapter, REG_RAM_BIST_CMD, &result);
283 if ((result & (1 << 27)) != 0x0)
284 pr_err("Still in bist write: 0x%x\n", result);
285 else if ((result & (1 << 26)) != 0x0)
286 pr_err("bist write error: 0x%x\n", result);
287
288 return 0;
289}
290
291static int run_bist(adapter_t *adapter, int moduleid)
292{
293 /*run bist*/
294 (void) bist_wr(adapter,moduleid, 0x00, 0x02);
295 (void) bist_wr(adapter,moduleid, 0x01, 0x01);
296
297 return 0;
298}
299
300static int check_bist(adapter_t *adapter, int moduleid)
301{
302 int result=0;
303 int column=0;
304 /*check bist*/
305 result = bist_rd(adapter,moduleid, 0x02);
306 column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
307 (bist_rd(adapter,moduleid, 0x0d)));
308 if ((result & 3) != 0x3)
309 pr_err("Result: 0x%x BIST error in ram %d, column: 0x%04x\n",
310 result, moduleid, column);
311 return 0;
312}
313
314static int enable_mem(adapter_t *adapter, int moduleid)
315{
316 /*enable mem*/
317 (void) bist_wr(adapter,moduleid, 0x00, 0x00);
318 return 0;
319}
320
321static int run_bist_all(adapter_t *adapter)
322{
323 int port = 0;
324 u32 val = 0;
325
326 vsc_write(adapter, REG_MEM_BIST, 0x5);
327 vsc_read(adapter, REG_MEM_BIST, &val);
328
329 for (port = 0; port < 12; port++)
330 vsc_write(adapter, REG_DEV_SETUP(port), 0x0);
331
332 udelay(300);
333 vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
334 udelay(300);
335
336 (void) run_bist(adapter,13);
337 (void) run_bist(adapter,14);
338 (void) run_bist(adapter,20);
339 (void) run_bist(adapter,21);
340 mdelay(200);
341 (void) check_bist(adapter,13);
342 (void) check_bist(adapter,14);
343 (void) check_bist(adapter,20);
344 (void) check_bist(adapter,21);
345 udelay(100);
346 (void) enable_mem(adapter,13);
347 (void) enable_mem(adapter,14);
348 (void) enable_mem(adapter,20);
349 (void) enable_mem(adapter,21);
350 udelay(300);
351 vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
352 udelay(300);
353 for (port = 0; port < 12; port++)
354 vsc_write(adapter, REG_DEV_SETUP(port), 0x1);
355
356 udelay(300);
357 vsc_write(adapter, REG_MEM_BIST, 0x0);
358 mdelay(10);
359 return 0;
360}
361
362static int mac_intr_handler(struct cmac *mac)
363{
364 return 0;
365}
366
367static int mac_intr_enable(struct cmac *mac)
368{
369 return 0;
370}
371
372static int mac_intr_disable(struct cmac *mac)
373{
374 return 0;
375}
376
377static int mac_intr_clear(struct cmac *mac)
378{
379 return 0;
380}
381
382/* Expect MAC address to be in network byte order. */
383static int mac_set_address(struct cmac* mac, u8 addr[6])
384{
385 u32 val;
386 int port = mac->instance->index;
387
388 vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port),
389 (addr[3] << 16) | (addr[4] << 8) | addr[5]);
390 vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port),
391 (addr[0] << 16) | (addr[1] << 8) | addr[2]);
392
393 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &val);
394 val &= ~0xf0000000;
395 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28));
396
397 vsc_write(mac->adapter, REG_ING_FFILT_MASK0,
398 0xffff0000 | (addr[4] << 8) | addr[5]);
399 vsc_write(mac->adapter, REG_ING_FFILT_MASK1,
400 0xffff0000 | (addr[2] << 8) | addr[3]);
401 vsc_write(mac->adapter, REG_ING_FFILT_MASK2,
402 0xffff0000 | (addr[0] << 8) | addr[1]);
403 return 0;
404}
405
406static int mac_get_address(struct cmac *mac, u8 addr[6])
407{
408 u32 addr_lo, addr_hi;
409 int port = mac->instance->index;
410
411 vsc_read(mac->adapter, REG_MAC_LOW_ADDR(port), &addr_lo);
412 vsc_read(mac->adapter, REG_MAC_HIGH_ADDR(port), &addr_hi);
413
414 addr[0] = (u8) (addr_hi >> 16);
415 addr[1] = (u8) (addr_hi >> 8);
416 addr[2] = (u8) addr_hi;
417 addr[3] = (u8) (addr_lo >> 16);
418 addr[4] = (u8) (addr_lo >> 8);
419 addr[5] = (u8) addr_lo;
420 return 0;
421}
422
423/* This is intended to reset a port, not the whole MAC */
424static int mac_reset(struct cmac *mac)
425{
426 int index = mac->instance->index;
427
428 run_table(mac->adapter, vsc7326_portinit[index],
429 ARRAY_SIZE(vsc7326_portinit[index]));
430
431 return 0;
432}
433
434static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
435{
436 u32 v;
437 int port = mac->instance->index;
438
439 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &v);
440 v |= 1 << 12;
441
442 if (t1_rx_mode_promisc(rm))
443 v &= ~(1 << (port + 16));
444 else
445 v |= 1 << (port + 16);
446
447 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v);
448 return 0;
449}
450
451static int mac_set_mtu(struct cmac *mac, int mtu)
452{
453 int port = mac->instance->index;
454
455 if (mtu > MAX_MTU)
456 return -EINVAL;
457
458 /* max_len includes header and FCS */
459 vsc_write(mac->adapter, REG_MAX_LEN(port), mtu + 14 + 4);
460 return 0;
461}
462
463static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
464 int fc)
465{
466 u32 v;
467 int enable, port = mac->instance->index;
468
469 if (speed >= 0 && speed != SPEED_10 && speed != SPEED_100 &&
470 speed != SPEED_1000)
471 return -1;
472 if (duplex > 0 && duplex != DUPLEX_FULL)
473 return -1;
474
475 if (speed >= 0) {
476 vsc_read(mac->adapter, REG_MODE_CFG(port), &v);
477 enable = v & 3; /* save tx/rx enables */
478 v &= ~0xf;
479 v |= 4; /* full duplex */
480 if (speed == SPEED_1000)
481 v |= 8; /* GigE */
482 enable |= v;
483 vsc_write(mac->adapter, REG_MODE_CFG(port), v);
484
485 if (speed == SPEED_1000)
486 v = 0x82;
487 else if (speed == SPEED_100)
488 v = 0x84;
489 else /* SPEED_10 */
490 v = 0x86;
491 vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */
492 vsc_write(mac->adapter, REG_DEV_SETUP(port), v);
493 vsc_read(mac->adapter, REG_DBG(port), &v);
494 v &= ~0xff00;
495 if (speed == SPEED_1000)
496 v |= 0x400;
497 else if (speed == SPEED_100)
498 v |= 0x2000;
499 else /* SPEED_10 */
500 v |= 0xff00;
501 vsc_write(mac->adapter, REG_DBG(port), v);
502
503 vsc_write(mac->adapter, REG_TX_IFG(port),
504 speed == SPEED_1000 ? 5 : 0x11);
505 if (duplex == DUPLEX_HALF)
506 enable = 0x0; /* 100 or 10 */
507 else if (speed == SPEED_1000)
508 enable = 0xc;
509 else /* SPEED_100 or 10 */
510 enable = 0x4;
511 enable |= 0x9 << 10; /* IFG1 */
512 enable |= 0x6 << 6; /* IFG2 */
513 enable |= 0x1 << 4; /* VLAN */
514 enable |= 0x3; /* RX/TX EN */
515 vsc_write(mac->adapter, REG_MODE_CFG(port), enable);
516
517 }
518
519 vsc_read(mac->adapter, REG_PAUSE_CFG(port), &v);
520 v &= 0xfff0ffff;
521 v |= 0x20000; /* xon/xoff */
522 if (fc & PAUSE_RX)
523 v |= 0x40000;
524 if (fc & PAUSE_TX)
525 v |= 0x80000;
526 if (fc == (PAUSE_RX | PAUSE_TX))
527 v |= 0x10000;
528 vsc_write(mac->adapter, REG_PAUSE_CFG(port), v);
529 return 0;
530}
531
532static int mac_enable(struct cmac *mac, int which)
533{
534 u32 val;
535 int port = mac->instance->index;
536
537 /* Write the correct WM value when the port is enabled. */
538 vsc_write(mac->adapter, REG_HIGH_LOW_WM(1,port), WM_ENABLE);
539
540 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
541 if (which & MAC_DIRECTION_RX)
542 val |= 0x2;
543 if (which & MAC_DIRECTION_TX)
544 val |= 1;
545 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
546 return 0;
547}
548
549static int mac_disable(struct cmac *mac, int which)
550{
551 u32 val;
552 int i, port = mac->instance->index;
553
554 /* Reset the port, this also writes the correct WM value */
555 mac_reset(mac);
556
557 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
558 if (which & MAC_DIRECTION_RX)
559 val &= ~0x2;
560 if (which & MAC_DIRECTION_TX)
561 val &= ~0x1;
562 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
563 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
564
565 /* Clear stats */
566 for (i = 0; i <= 0x3a; ++i)
567 vsc_write(mac->adapter, CRA(4, port, i), 0);
568
569 /* Clear software counters */
570 memset(&mac->stats, 0, sizeof(struct cmac_statistics));
571
572 return 0;
573}
574
575static void rmon_update(struct cmac *mac, unsigned int addr, u64 *stat)
576{
577 u32 v, lo;
578
579 vsc_read(mac->adapter, addr, &v);
580 lo = *stat;
581 *stat = *stat - lo + v;
582
583 if (v == 0)
584 return;
585
586 if (v < lo)
587 *stat += (1ULL << 32);
588}
589
590static void port_stats_update(struct cmac *mac)
591{
592 struct {
593 unsigned int reg;
594 unsigned int offset;
595 } hw_stats[] = {
596
597#define HW_STAT(reg, stat_name) \
598 { reg, (&((struct cmac_statistics *)NULL)->stat_name) - (u64 *)NULL }
599
600 /* Rx stats */
601 HW_STAT(RxUnicast, RxUnicastFramesOK),
602 HW_STAT(RxMulticast, RxMulticastFramesOK),
603 HW_STAT(RxBroadcast, RxBroadcastFramesOK),
604 HW_STAT(Crc, RxFCSErrors),
605 HW_STAT(RxAlignment, RxAlignErrors),
606 HW_STAT(RxOversize, RxFrameTooLongErrors),
607 HW_STAT(RxPause, RxPauseFrames),
608 HW_STAT(RxJabbers, RxJabberErrors),
609 HW_STAT(RxFragments, RxRuntErrors),
610 HW_STAT(RxUndersize, RxRuntErrors),
611 HW_STAT(RxSymbolCarrier, RxSymbolErrors),
612 HW_STAT(RxSize1519ToMax, RxJumboFramesOK),
613
614 /* Tx stats (skip collision stats as we are full-duplex only) */
615 HW_STAT(TxUnicast, TxUnicastFramesOK),
616 HW_STAT(TxMulticast, TxMulticastFramesOK),
617 HW_STAT(TxBroadcast, TxBroadcastFramesOK),
618 HW_STAT(TxPause, TxPauseFrames),
619 HW_STAT(TxUnderrun, TxUnderrun),
620 HW_STAT(TxSize1519ToMax, TxJumboFramesOK),
621 }, *p = hw_stats;
622 unsigned int port = mac->instance->index;
623 u64 *stats = (u64 *)&mac->stats;
624 unsigned int i;
625
626 for (i = 0; i < ARRAY_SIZE(hw_stats); i++)
627 rmon_update(mac, CRA(0x4, port, p->reg), stats + p->offset);
628
629 rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK);
630 rmon_update(mac, REG_RX_OK_BYTES(port), &mac->stats.RxOctetsOK);
631 rmon_update(mac, REG_RX_BAD_BYTES(port), &mac->stats.RxOctetsBad);
632}
633
634/*
635 * This function is called periodically to accumulate the current values of the
636 * RMON counters into the port statistics. Since the counters are only 32 bits
637 * some of them can overflow in less than a minute at GigE speeds, so this
638 * function should be called every 30 seconds or so.
639 *
640 * To cut down on reading costs we update only the octet counters at each tick
641 * and do a full update at major ticks, which can be every 30 minutes or more.
642 */
643static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
644 int flag)
645{
646 if (flag == MAC_STATS_UPDATE_FULL ||
647 mac->instance->ticks >= MAJOR_UPDATE_TICKS) {
648 port_stats_update(mac);
649 mac->instance->ticks = 0;
650 } else {
651 int port = mac->instance->index;
652
653 rmon_update(mac, REG_RX_OK_BYTES(port),
654 &mac->stats.RxOctetsOK);
655 rmon_update(mac, REG_RX_BAD_BYTES(port),
656 &mac->stats.RxOctetsBad);
657 rmon_update(mac, REG_TX_OK_BYTES(port),
658 &mac->stats.TxOctetsOK);
659 mac->instance->ticks++;
660 }
661 return &mac->stats;
662}
663
664static void mac_destroy(struct cmac *mac)
665{
666 kfree(mac);
667}
668
669static struct cmac_ops vsc7326_ops = {
670 .destroy = mac_destroy,
671 .reset = mac_reset,
672 .interrupt_handler = mac_intr_handler,
673 .interrupt_enable = mac_intr_enable,
674 .interrupt_disable = mac_intr_disable,
675 .interrupt_clear = mac_intr_clear,
676 .enable = mac_enable,
677 .disable = mac_disable,
678 .set_mtu = mac_set_mtu,
679 .set_rx_mode = mac_set_rx_mode,
680 .set_speed_duplex_fc = mac_set_speed_duplex_fc,
681 .statistics_update = mac_update_statistics,
682 .macaddress_get = mac_get_address,
683 .macaddress_set = mac_set_address,
684};
685
686static struct cmac *vsc7326_mac_create(adapter_t *adapter, int index)
687{
688 struct cmac *mac;
689 u32 val;
690 int i;
691
692 mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
693 if (!mac)
694 return NULL;
695
696 mac->ops = &vsc7326_ops;
697 mac->instance = (cmac_instance *)(mac + 1);
698 mac->adapter = adapter;
699
700 mac->instance->index = index;
701 mac->instance->ticks = 0;
702
703 i = 0;
704 do {
705 u32 vhi, vlo;
706
707 vhi = vlo = 0;
708 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
709 udelay(1);
710 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
711 udelay(5);
712 val = (vhi << 16) | vlo;
713 } while ((++i < 10000) && (val == 0xffffffff));
714
715 return mac;
716}
717
718static int vsc7326_mac_reset(adapter_t *adapter)
719{
720 vsc7326_full_reset(adapter);
721 (void) run_bist_all(adapter);
722 run_table(adapter, vsc7326_reset, ARRAY_SIZE(vsc7326_reset));
723 return 0;
724}
725
726const struct gmac t1_vsc7326_ops = {
727 .stats_update_period = STATS_TICK_SECS,
728 .create = vsc7326_mac_create,
729 .reset = vsc7326_mac_reset,
730};
diff --git a/drivers/net/chelsio/vsc7326_reg.h b/drivers/net/chelsio/vsc7326_reg.h
deleted file mode 100644
index 479edbcabe68..000000000000
--- a/drivers/net/chelsio/vsc7326_reg.h
+++ /dev/null
@@ -1,297 +0,0 @@
1/* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */
2#ifndef _VSC7321_REG_H_
3#define _VSC7321_REG_H_
4
5/* Register definitions for Vitesse VSC7321 (Meigs II) MAC
6 *
7 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
8 * PD0011-01-14-Meigs-II 2002-12-12
9 */
10
11/* Just 'cause it's in here doesn't mean it's used. */
12
13#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
14
15/* System and CPU comm's registers */
16#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
17#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
18#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
19#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
20#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
21#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
22#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
23#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
24#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
25#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
26#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */
27#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */
28#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */
29#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */
30#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */
31#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */
32#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */
33
34/* Aggregator registers */
35#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */
36#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */
37#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */
38#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */
39#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */
40#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */
41#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */
42#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */
43#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */
44#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */
45#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */
46#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */
47
48/* BIST registers */
49/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
50/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
51#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */
52#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */
53#define BIST_PORT_SELECT 0x00 /* BIST port select */
54#define BIST_COMMAND 0x01 /* BIST enable/disable */
55#define BIST_STATUS 0x02 /* BIST operation status */
56#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */
57#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */
58#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */
59#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */
60#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */
61#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */
62#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */
63#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */
64#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */
65
66/* FIFO registers
67 * ie = 0 for ingress, 1 for egress
68 * fn = FIFO number, 0-9
69 */
70#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */
71#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */
72#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */
73#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */
74#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */
75#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */
76#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */
77#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */
78#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */
79#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */
80
81/* Traffic shaper buckets
82 * ie = 0 for ingress, 1 for egress
83 * bn = bucket number 0-10 (yes, 11 buckets)
84 */
85/* OK, this one's kinda ugly. Some hardware designers are perverse. */
86#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
87#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b)
88
89#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */
90#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */
91#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */
92#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */
93#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */
94#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */
95#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
96#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */
97/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */
98#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */
99#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */
100#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */
101#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */
102#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */
103#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */
104#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */
105
106/* SPI4 interface */
107#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */
108#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */
109#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */
110#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */
111#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */
112#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */
113#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
114#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */
115#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */
116#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */
117#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */
118#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */
119#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */
120#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */
121#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */
122#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */
123#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */
124#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */
125#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */
126#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */
127
128#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */
129
130/* 10GbE MAC Block Registers */
131/* Note that those registers that are exactly the same for 10GbE as for
132 * tri-speed are only defined with the version that needs a port number.
133 * Pass 0xa in those cases.
134 *
135 * Also note that despite the presence of a MAC address register, this part
136 * does no ingress MAC address filtering. That register is used only for
137 * pause frame detection and generation.
138 */
139/* 10GbE specific, and different from tri-speed */
140#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */
141#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */
142#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */
143#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
144#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */
145#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */
146#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
147#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */
148#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */
149#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */
150#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */
151#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */
152#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */
153#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */
154#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */
155#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */
156#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */
157#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */
158#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */
159#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */
160#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */
161#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */
162#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */
163
164/* pn = port number 0-9 for tri-speed, 10 for 10GbE */
165/* Both tri-speed and 10GbE */
166#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */
167#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */
168#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */
169
170/* tri-speed only
171 * pn = port number, 0-9
172 */
173#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */
174#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */
175#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */
176#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */
177#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */
178#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */
179#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */
180#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */
181#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */
182#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */
183#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */
184#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */
185#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */
186#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */
187#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */
188#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */
189#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */
190#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */
191#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */
192#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */
193
194/* Statistics */
195/* CRA(0x4,pn,reg) */
196/* reg below */
197/* pn = port number, 0-a, a = 10GbE */
198
199enum {
200 RxInBytes = 0x00, // # Rx in octets
201 RxSymbolCarrier = 0x01, // Frames w/ symbol errors
202 RxPause = 0x02, // # pause frames received
203 RxUnsupOpcode = 0x03, // # control frames with unsupported opcode
204 RxOkBytes = 0x04, // # octets in good frames
205 RxBadBytes = 0x05, // # octets in bad frames
206 RxUnicast = 0x06, // # good unicast frames
207 RxMulticast = 0x07, // # good multicast frames
208 RxBroadcast = 0x08, // # good broadcast frames
209 Crc = 0x09, // # frames w/ bad CRC only
210 RxAlignment = 0x0a, // # frames w/ alignment err
211 RxUndersize = 0x0b, // # frames undersize
212 RxFragments = 0x0c, // # frames undersize w/ crc err
213 RxInRangeLengthError = 0x0d, // # frames with length error
214 RxOutOfRangeError = 0x0e, // # frames with illegal length field
215 RxOversize = 0x0f, // # frames oversize
216 RxJabbers = 0x10, // # frames oversize w/ crc err
217 RxSize64 = 0x11, // # frames 64 octets long
218 RxSize65To127 = 0x12, // # frames 65-127 octets
219 RxSize128To255 = 0x13, // # frames 128-255
220 RxSize256To511 = 0x14, // # frames 256-511
221 RxSize512To1023 = 0x15, // # frames 512-1023
222 RxSize1024To1518 = 0x16, // # frames 1024-1518
223 RxSize1519ToMax = 0x17, // # frames 1519-max
224
225 TxOutBytes = 0x18, // # octets tx
226 TxPause = 0x19, // # pause frames sent
227 TxOkBytes = 0x1a, // # octets tx OK
228 TxUnicast = 0x1b, // # frames unicast
229 TxMulticast = 0x1c, // # frames multicast
230 TxBroadcast = 0x1d, // # frames broadcast
231 TxMultipleColl = 0x1e, // # frames tx after multiple collisions
232 TxLateColl = 0x1f, // # late collisions detected
233 TxXcoll = 0x20, // # frames lost, excessive collisions
234 TxDefer = 0x21, // # frames deferred on first tx attempt
235 TxXdefer = 0x22, // # frames excessively deferred
236 TxCsense = 0x23, // carrier sense errors at frame end
237 TxSize64 = 0x24, // # frames 64 octets long
238 TxSize65To127 = 0x25, // # frames 65-127 octets
239 TxSize128To255 = 0x26, // # frames 128-255
240 TxSize256To511 = 0x27, // # frames 256-511
241 TxSize512To1023 = 0x28, // # frames 512-1023
242 TxSize1024To1518 = 0x29, // # frames 1024-1518
243 TxSize1519ToMax = 0x2a, // # frames 1519-max
244 TxSingleColl = 0x2b, // # frames tx after single collision
245 TxBackoff2 = 0x2c, // # frames tx ok after 2 backoffs/collisions
246 TxBackoff3 = 0x2d, // after 3 backoffs/collisions
247 TxBackoff4 = 0x2e, // after 4
248 TxBackoff5 = 0x2f, // after 5
249 TxBackoff6 = 0x30, // after 6
250 TxBackoff7 = 0x31, // after 7
251 TxBackoff8 = 0x32, // after 8
252 TxBackoff9 = 0x33, // after 9
253 TxBackoff10 = 0x34, // after 10
254 TxBackoff11 = 0x35, // after 11
255 TxBackoff12 = 0x36, // after 12
256 TxBackoff13 = 0x37, // after 13
257 TxBackoff14 = 0x38, // after 14
258 TxBackoff15 = 0x39, // after 15
259 TxUnderrun = 0x3a, // # frames dropped from underrun
260 // Hole. See REG_RX_XGMII_PROT_ERR below.
261 RxIpgShrink = 0x3c, // # of IPG shrinks detected
262 // Duplicate. See REG_STAT_STICKY10G below.
263 StatSticky1G = 0x3e, // tri-speed sticky bits
264 StatInit = 0x3f // Clear all statistics
265};
266
267#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */
268#define REG_STAT_STICKY10G CRA(0x4,0xa,StatSticky1G) /* 10GbE sticky bits */
269
270#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes)
271#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,RxBadBytes)
272#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes)
273
274/* MII-Management Block registers */
275/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If
276 * we hooked up to the one with separate directions, the middle 0x0 needs to
277 * change to 0x1. And the current errata states that MII-M 1 doesn't work.
278 */
279
280#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */
281#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */
282#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */
283#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */
284
285#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
286#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
287#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d)
288#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d)
289#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
290#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
291#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
292#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
293
294
295/* Whew. */
296
297#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 04:46:10 -0500