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authorBen Hutchings <bhutchings@solarflare.com>2009-05-19 09:21:07 -0400
committerDavid S. Miller <davem@davemloft.net>2009-05-20 23:51:56 -0400
commitaa22437e87469fdee94b5344780b4a3dbb87a154 (patch)
treec6f9ead382f355d907fcba2c6144d7f6784d3750 /drivers/net/chelsio
parent9f29f6de56462a363d3cc1d5f000961d622c5888 (diff)
chelsio: Use generic XENPAK LASI register definitions
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Acked-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/chelsio')
-rw-r--r--drivers/net/chelsio/mv88x201x.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/net/chelsio/mv88x201x.c b/drivers/net/chelsio/mv88x201x.c
index 29e0cba48d53..d50907bf2ebd 100644
--- a/drivers/net/chelsio/mv88x201x.c
+++ b/drivers/net/chelsio/mv88x201x.c
@@ -86,7 +86,8 @@ static int mv88x201x_reset(struct cphy *cphy, int wait)
86static int mv88x201x_interrupt_enable(struct cphy *cphy) 86static int mv88x201x_interrupt_enable(struct cphy *cphy)
87{ 87{
88 /* Enable PHY LASI interrupts. */ 88 /* Enable PHY LASI interrupts. */
89 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, 0x9002, 0x1); 89 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
90 MDIO_PMA_LASI_LSALARM);
90 91
91 /* Enable Marvell interrupts through Elmer0. */ 92 /* Enable Marvell interrupts through Elmer0. */
92 if (t1_is_asic(cphy->adapter)) { 93 if (t1_is_asic(cphy->adapter)) {
@@ -102,7 +103,7 @@ static int mv88x201x_interrupt_enable(struct cphy *cphy)
102static int mv88x201x_interrupt_disable(struct cphy *cphy) 103static int mv88x201x_interrupt_disable(struct cphy *cphy)
103{ 104{
104 /* Disable PHY LASI interrupts. */ 105 /* Disable PHY LASI interrupts. */
105 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, 0x9002, 0x0); 106 cphy_mdio_write(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0x0);
106 107
107 /* Disable Marvell interrupts through Elmer0. */ 108 /* Disable Marvell interrupts through Elmer0. */
108 if (t1_is_asic(cphy->adapter)) { 109 if (t1_is_asic(cphy->adapter)) {
@@ -122,9 +123,9 @@ static int mv88x201x_interrupt_clear(struct cphy *cphy)
122 123
123#ifdef MV88x2010_LINK_STATUS_BUGS 124#ifdef MV88x2010_LINK_STATUS_BUGS
124 /* Required to read twice before clear takes affect. */ 125 /* Required to read twice before clear takes affect. */
125 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9003, &val); 126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
126 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9004, &val); 127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9005, &val); 128 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
128 129
129 /* Read this register after the others above it else 130 /* Read this register after the others above it else
130 * the register doesn't clear correctly. 131 * the register doesn't clear correctly.
@@ -135,12 +136,12 @@ static int mv88x201x_interrupt_clear(struct cphy *cphy)
135 /* Clear link status. */ 136 /* Clear link status. */
136 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val); 137 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
137 /* Clear PHY LASI interrupts. */ 138 /* Clear PHY LASI interrupts. */
138 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9005, &val); 139 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
139 140
140#ifdef MV88x2010_LINK_STATUS_BUGS 141#ifdef MV88x2010_LINK_STATUS_BUGS
141 /* Do it again. */ 142 /* Do it again. */
142 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9003, &val); 143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
143 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, 0x9004, &val); 144 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
144#endif 145#endif
145 146
146 /* Clear Marvell interrupts through Elmer0. */ 147 /* Clear Marvell interrupts through Elmer0. */