[PATCH] chelsio: add 1G swcixw aupport

Add support for 1G versions of Chelsio devices.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

1 files changed, 33 insertions, 0 deletions

diff --git a/drivers/net/chelsio/tp.c b/drivers/net/chelsio/tp.c
index 04a7073e9d15..0ca0b6e19e43 100644
--- a/drivers/net/chelsio/tp.c
+++ b/drivers/net/chelsio/tp.c
@@ -2,6 +2,9 @@
 #include "common.h"
 #include "regs.h"
 #include "tp.h"
+#ifdef CONFIG_CHELSIO_T1_1G
+#include "fpga_defs.h"
+#endif
 
 struct petp {
         adapter_t *adapter;
@@ -70,6 +73,15 @@ void t1_tp_intr_enable(struct petp *tp)
 {
         u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
 
+#ifdef CONFIG_CHELSIO_T1_1G
+        if (!t1_is_asic(tp->adapter)) {
+                /* FPGA */
+                writel(0xffffffff,
+                       tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
+                writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
+                       tp->adapter->regs + A_PL_ENABLE);
+        } else
+#endif
         {
                 /* We don't use any TP interrupts */
                 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
@@ -82,6 +94,14 @@ void t1_tp_intr_disable(struct petp *tp)
 {
         u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
 
+#ifdef CONFIG_CHELSIO_T1_1G
+        if (!t1_is_asic(tp->adapter)) {
+                /* FPGA */
+                writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
+                writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
+                       tp->adapter->regs + A_PL_ENABLE);
+        } else
+#endif
         {
                 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
                 writel(tp_intr & ~F_PL_INTR_TP,
@@ -91,6 +111,14 @@ void t1_tp_intr_disable(struct petp *tp)
 
 void t1_tp_intr_clear(struct petp *tp)
 {
+#ifdef CONFIG_CHELSIO_T1_1G
+        if (!t1_is_asic(tp->adapter)) {
+                writel(0xffffffff,
+                       tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
+                writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
+                return;
+        }
+#endif
         writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
         writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
 }
@@ -99,6 +127,11 @@ int t1_tp_intr_handler(struct petp *tp)
 {
         u32 cause;
 
+#ifdef CONFIG_CHELSIO_T1_1G
+        /* FPGA doesn't support TP interrupts. */
+        if (!t1_is_asic(tp->adapter))
+                return 1;
+#endif
 
         cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
         writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);