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authorBen Hutchings <bhutchings@solarflare.com>2009-04-29 04:06:34 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-29 20:32:31 -0400
commit23c3320cb039debfb94b27e8e9bfe26dd47692c3 (patch)
treebfb9253e7a6bc4472050db8e9241ad85a99283ab /drivers/net/chelsio/subr.c
parent68e7f45e118f98b77cfa007aa2d97b5dac69fe6b (diff)
chelsio: Use generic MDIO definitions and mdio_mii_ioctl()
Compile-tested only. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/chelsio/subr.c')
-rw-r--r--drivers/net/chelsio/subr.c43
1 files changed, 23 insertions, 20 deletions
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
index 7adf30230c4f..2564312b3056 100644
--- a/drivers/net/chelsio/subr.c
+++ b/drivers/net/chelsio/subr.c
@@ -284,32 +284,29 @@ static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
284/* 284/*
285 * Elmer MI1 MDIO read/write operations. 285 * Elmer MI1 MDIO read/write operations.
286 */ 286 */
287static int mi1_mdio_read(adapter_t *adapter, int phy_addr, int mmd_addr, 287static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
288 int reg_addr, unsigned int *valp) 288 u16 reg_addr)
289{ 289{
290 struct adapter *adapter = dev->ml_priv;
290 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); 291 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
291 292 unsigned int val;
292 if (mmd_addr)
293 return -EINVAL;
294 293
295 spin_lock(&adapter->tpi_lock); 294 spin_lock(&adapter->tpi_lock);
296 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 295 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
297 __t1_tpi_write(adapter, 296 __t1_tpi_write(adapter,
298 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ); 297 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
299 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 298 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
300 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp); 299 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
301 spin_unlock(&adapter->tpi_lock); 300 spin_unlock(&adapter->tpi_lock);
302 return 0; 301 return val;
303} 302}
304 303
305static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr, 304static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
306 int reg_addr, unsigned int val) 305 u16 reg_addr, u16 val)
307{ 306{
307 struct adapter *adapter = dev->ml_priv;
308 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr); 308 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
309 309
310 if (mmd_addr)
311 return -EINVAL;
312
313 spin_lock(&adapter->tpi_lock); 310 spin_lock(&adapter->tpi_lock);
314 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr); 311 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
315 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val); 312 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
@@ -324,16 +321,19 @@ static int mi1_mdio_write(adapter_t *adapter, int phy_addr, int mmd_addr,
324static const struct mdio_ops mi1_mdio_ops = { 321static const struct mdio_ops mi1_mdio_ops = {
325 .init = mi1_mdio_init, 322 .init = mi1_mdio_init,
326 .read = mi1_mdio_read, 323 .read = mi1_mdio_read,
327 .write = mi1_mdio_write 324 .write = mi1_mdio_write,
325 .mode_support = MDIO_SUPPORTS_C22
328}; 326};
329#endif 327#endif
330 328
331#endif 329#endif
332 330
333static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, 331static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
334 int reg_addr, unsigned int *valp) 332 u16 reg_addr)
335{ 333{
334 struct adapter *adapter = dev->ml_priv;
336 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 335 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
336 unsigned int val;
337 337
338 spin_lock(&adapter->tpi_lock); 338 spin_lock(&adapter->tpi_lock);
339 339
@@ -350,14 +350,15 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
350 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP); 350 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
351 351
352 /* Read the data. */ 352 /* Read the data. */
353 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp); 353 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
354 spin_unlock(&adapter->tpi_lock); 354 spin_unlock(&adapter->tpi_lock);
355 return 0; 355 return val;
356} 356}
357 357
358static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, 358static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
359 int reg_addr, unsigned int val) 359 int mmd_addr, u16 reg_addr, u16 val)
360{ 360{
361 struct adapter *adapter = dev->ml_priv;
361 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr); 362 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
362 363
363 spin_lock(&adapter->tpi_lock); 364 spin_lock(&adapter->tpi_lock);
@@ -380,7 +381,8 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
380static const struct mdio_ops mi1_mdio_ext_ops = { 381static const struct mdio_ops mi1_mdio_ext_ops = {
381 .init = mi1_mdio_init, 382 .init = mi1_mdio_init,
382 .read = mi1_mdio_ext_read, 383 .read = mi1_mdio_ext_read,
383 .write = mi1_mdio_ext_write 384 .write = mi1_mdio_ext_write,
385 .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
384}; 386};
385 387
386enum { 388enum {
@@ -1140,6 +1142,7 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
1140 adapter->name, i); 1142 adapter->name, i);
1141 goto error; 1143 goto error;
1142 } 1144 }
1145 adapter->port[i].phy->mdio.dev = adapter->port[i].dev;
1143 1146
1144 adapter->port[i].mac = mac = bi->gmac->create(adapter, i); 1147 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1145 if (!mac) { 1148 if (!mac) {