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authorFrancois Romieu <romieu@fr.zoreil.com>2006-12-11 17:47:00 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-05 16:58:43 -0500
commit356bd1460d1e1c4e433e4114fdac02139bddf17c (patch)
tree677c17fddfb7c66f29134c33f64463f15fc43824 /drivers/net/chelsio/subr.c
parentb7d58394e65c7d90486026614a6ae26d82dd7756 (diff)
chelsio: spaces, tabs and friends
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Diffstat (limited to 'drivers/net/chelsio/subr.c')
-rw-r--r--drivers/net/chelsio/subr.c83
1 files changed, 41 insertions, 42 deletions
diff --git a/drivers/net/chelsio/subr.c b/drivers/net/chelsio/subr.c
index 38dbaf28d439..c2522cdfab37 100644
--- a/drivers/net/chelsio/subr.c
+++ b/drivers/net/chelsio/subr.c
@@ -223,13 +223,13 @@ static int fpga_slow_intr(adapter_t *adapter)
223 t1_sge_intr_error_handler(adapter->sge); 223 t1_sge_intr_error_handler(adapter->sge);
224 224
225 if (cause & FPGA_PCIX_INTERRUPT_GMAC) 225 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
226 fpga_phy_intr_handler(adapter); 226 fpga_phy_intr_handler(adapter);
227 227
228 if (cause & FPGA_PCIX_INTERRUPT_TP) { 228 if (cause & FPGA_PCIX_INTERRUPT_TP) {
229 /* 229 /*
230 * FPGA doesn't support MC4 interrupts and it requires 230 * FPGA doesn't support MC4 interrupts and it requires
231 * this odd layer of indirection for MC5. 231 * this odd layer of indirection for MC5.
232 */ 232 */
233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE); 233 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
234 234
235 /* Clear TP interrupt */ 235 /* Clear TP interrupt */
@@ -262,8 +262,7 @@ static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
262 udelay(10); 262 udelay(10);
263 } while (busy && --attempts); 263 } while (busy && --attempts);
264 if (busy) 264 if (busy)
265 CH_ALERT("%s: MDIO operation timed out\n", 265 CH_ALERT("%s: MDIO operation timed out\n", adapter->name);
266 adapter->name);
267 return busy; 266 return busy;
268} 267}
269 268
@@ -605,23 +604,23 @@ int t1_elmer0_ext_intr_handler(adapter_t *adapter)
605 604
606 switch (board_info(adapter)->board) { 605 switch (board_info(adapter)->board) {
607#ifdef CONFIG_CHELSIO_T1_1G 606#ifdef CONFIG_CHELSIO_T1_1G
608 case CHBT_BOARD_CHT204: 607 case CHBT_BOARD_CHT204:
609 case CHBT_BOARD_CHT204E: 608 case CHBT_BOARD_CHT204E:
610 case CHBT_BOARD_CHN204: 609 case CHBT_BOARD_CHN204:
611 case CHBT_BOARD_CHT204V: { 610 case CHBT_BOARD_CHT204V: {
612 int i, port_bit; 611 int i, port_bit;
613 for_each_port(adapter, i) { 612 for_each_port(adapter, i) {
614 port_bit = i + 1; 613 port_bit = i + 1;
615 if (!(cause & (1 << port_bit))) 614 if (!(cause & (1 << port_bit)))
616 continue; 615 continue;
617 616
618 phy = adapter->port[i].phy; 617 phy = adapter->port[i].phy;
619 phy_cause = phy->ops->interrupt_handler(phy); 618 phy_cause = phy->ops->interrupt_handler(phy);
620 if (phy_cause & cphy_cause_link_change) 619 if (phy_cause & cphy_cause_link_change)
621 t1_link_changed(adapter, i); 620 t1_link_changed(adapter, i);
622 } 621 }
623 break; 622 break;
624 } 623 }
625 case CHBT_BOARD_CHT101: 624 case CHBT_BOARD_CHT101:
626 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */ 625 if (cause & ELMER0_GP_BIT1) { /* Marvell 88E1111 interrupt */
627 phy = adapter->port[0].phy; 626 phy = adapter->port[0].phy;
@@ -632,13 +631,13 @@ int t1_elmer0_ext_intr_handler(adapter_t *adapter)
632 break; 631 break;
633 case CHBT_BOARD_7500: { 632 case CHBT_BOARD_7500: {
634 int p; 633 int p;
635 /* 634 /*
636 * Elmer0's interrupt cause isn't useful here because there is 635 * Elmer0's interrupt cause isn't useful here because there is
637 * only one bit that can be set for all 4 ports. This means 636 * only one bit that can be set for all 4 ports. This means
638 * we are forced to check every PHY's interrupt status 637 * we are forced to check every PHY's interrupt status
639 * register to see who initiated the interrupt. 638 * register to see who initiated the interrupt.
640 */ 639 */
641 for_each_port(adapter, p) { 640 for_each_port(adapter, p) {
642 phy = adapter->port[p].phy; 641 phy = adapter->port[p].phy;
643 phy_cause = phy->ops->interrupt_handler(phy); 642 phy_cause = phy->ops->interrupt_handler(phy);
644 if (phy_cause & cphy_cause_link_change) 643 if (phy_cause & cphy_cause_link_change)
@@ -659,7 +658,7 @@ int t1_elmer0_ext_intr_handler(adapter_t *adapter)
659 break; 658 break;
660 case CHBT_BOARD_8000: 659 case CHBT_BOARD_8000:
661 case CHBT_BOARD_CHT110: 660 case CHBT_BOARD_CHT110:
662 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n", 661 CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
663 cause); 662 cause);
664 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */ 663 if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
665 struct cmac *mac = adapter->port[0].mac; 664 struct cmac *mac = adapter->port[0].mac;
@@ -671,9 +670,9 @@ int t1_elmer0_ext_intr_handler(adapter_t *adapter)
671 670
672 t1_tpi_read(adapter, 671 t1_tpi_read(adapter,
673 A_ELMER0_GPI_STAT, &mod_detect); 672 A_ELMER0_GPI_STAT, &mod_detect);
674 CH_MSG(adapter, INFO, LINK, "XPAK %s\n", 673 CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
675 mod_detect ? "removed" : "inserted"); 674 mod_detect ? "removed" : "inserted");
676 } 675 }
677 break; 676 break;
678#ifdef CONFIG_CHELSIO_T1_COUGAR 677#ifdef CONFIG_CHELSIO_T1_COUGAR
679 case CHBT_BOARD_COUGAR: 678 case CHBT_BOARD_COUGAR:
@@ -757,7 +756,7 @@ void t1_interrupts_disable(adapter_t* adapter)
757 756
758 /* Disable PCIX & external chip interrupts. */ 757 /* Disable PCIX & external chip interrupts. */
759 if (t1_is_asic(adapter)) 758 if (t1_is_asic(adapter))
760 writel(0, adapter->regs + A_PL_ENABLE); 759 writel(0, adapter->regs + A_PL_ENABLE);
761 760
762 /* PCI-X interrupts */ 761 /* PCI-X interrupts */
763 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0); 762 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
@@ -832,11 +831,11 @@ int t1_slow_intr_handler(adapter_t *adapter)
832/* Power sequencing is a work-around for Intel's XPAKs. */ 831/* Power sequencing is a work-around for Intel's XPAKs. */
833static void power_sequence_xpak(adapter_t* adapter) 832static void power_sequence_xpak(adapter_t* adapter)
834{ 833{
835 u32 mod_detect; 834 u32 mod_detect;
836 u32 gpo; 835 u32 gpo;
837 836
838 /* Check for XPAK */ 837 /* Check for XPAK */
839 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect); 838 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
840 if (!(ELMER0_GP_BIT5 & mod_detect)) { 839 if (!(ELMER0_GP_BIT5 & mod_detect)) {
841 /* XPAK is present */ 840 /* XPAK is present */
842 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo); 841 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
@@ -879,31 +878,31 @@ static int board_init(adapter_t *adapter, const struct board_info *bi)
879 case CHBT_BOARD_N210: 878 case CHBT_BOARD_N210:
880 case CHBT_BOARD_CHT210: 879 case CHBT_BOARD_CHT210:
881 case CHBT_BOARD_COUGAR: 880 case CHBT_BOARD_COUGAR:
882 t1_tpi_par(adapter, 0xf); 881 t1_tpi_par(adapter, 0xf);
883 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800); 882 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
884 break; 883 break;
885 case CHBT_BOARD_CHT110: 884 case CHBT_BOARD_CHT110:
886 t1_tpi_par(adapter, 0xf); 885 t1_tpi_par(adapter, 0xf);
887 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800); 886 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
888 887
889 /* TBD XXX Might not need. This fixes a problem 888 /* TBD XXX Might not need. This fixes a problem
890 * described in the Intel SR XPAK errata. 889 * described in the Intel SR XPAK errata.
891 */ 890 */
892 power_sequence_xpak(adapter); 891 power_sequence_xpak(adapter);
893 break; 892 break;
894#ifdef CONFIG_CHELSIO_T1_1G 893#ifdef CONFIG_CHELSIO_T1_1G
895 case CHBT_BOARD_CHT204E: 894 case CHBT_BOARD_CHT204E:
896 /* add config space write here */ 895 /* add config space write here */
897 case CHBT_BOARD_CHT204: 896 case CHBT_BOARD_CHT204:
898 case CHBT_BOARD_CHT204V: 897 case CHBT_BOARD_CHT204V:
899 case CHBT_BOARD_CHN204: 898 case CHBT_BOARD_CHN204:
900 t1_tpi_par(adapter, 0xf); 899 t1_tpi_par(adapter, 0xf);
901 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804); 900 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
902 break; 901 break;
903 case CHBT_BOARD_CHT101: 902 case CHBT_BOARD_CHT101:
904 case CHBT_BOARD_7500: 903 case CHBT_BOARD_7500:
905 t1_tpi_par(adapter, 0xf); 904 t1_tpi_par(adapter, 0xf);
906 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804); 905 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
907 break; 906 break;
908#endif 907#endif
909 } 908 }
@@ -943,7 +942,7 @@ int t1_init_hw_modules(adapter_t *adapter)
943 goto out_err; 942 goto out_err;
944 943
945 err = 0; 944 err = 0;
946 out_err: 945out_err:
947 return err; 946 return err;
948} 947}
949 948
@@ -985,7 +984,7 @@ void t1_free_sw_modules(adapter_t *adapter)
985 if (adapter->espi) 984 if (adapter->espi)
986 t1_espi_destroy(adapter->espi); 985 t1_espi_destroy(adapter->espi);
987#ifdef CONFIG_CHELSIO_T1_COUGAR 986#ifdef CONFIG_CHELSIO_T1_COUGAR
988 if (adapter->cspi) 987 if (adapter->cspi)
989 t1_cspi_destroy(adapter->cspi); 988 t1_cspi_destroy(adapter->cspi);
990#endif 989#endif
991} 990}
@@ -1012,7 +1011,7 @@ static void __devinit init_link_config(struct link_config *lc,
1012 CH_ERR("%s: CSPI initialization failed\n", 1011 CH_ERR("%s: CSPI initialization failed\n",
1013 adapter->name); 1012 adapter->name);
1014 goto error; 1013 goto error;
1015 } 1014 }
1016#endif 1015#endif
1017 1016
1018/* 1017/*