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authorScott Bardone <sbardone@chelsio.com>2005-06-23 01:40:19 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-06-23 01:40:19 -0400
commit559fb51ba7e66fe298b8355fabde1275b7def35f (patch)
treee1de3eb86ea5e6ac8c5f27dc32140a0c2aacc51e /drivers/net/chelsio/sge.c
parenta5324343955997d1439f26518ddac567cd5d134b (diff)
Update Chelsio gige net driver.
- Use extern prefix for functions required. - Removed a lot of wrappers, including t1_read/write_reg_4. - Removed various macros, using native kernel calls now. - Enumerated various #defines. - Removed a lot of shared code which is not currently used in "NIC only" mode. - Removed dead code. Documentation/networking/cxgb.txt: - Updated release notes for version 2.1.1 drivers/net/chelsio/ch_ethtool.h - removed file, no longer using ETHTOOL namespace. drivers/net/chelsio/common.h - moved code from osdep.h to common.h - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/cphy.h - removed dead code. - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/cxgb2.c - use DMA_{32,64}BIT_MASK in include/linux/dma-mapping.h. - removed unused code. - use printk message for link info resembling drivers/net/mii.c. - no longer using the MODULE_xxx namespace. - no longer using "pci_" namespace. - no longer using ETHTOOL namespace. drivers/net/chelsio/cxgb2.h - removed file, merged into common.h drivers/net/chelsio/elmer0.h - removed dead code. - added various enums. - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/espi.c - removed various macros, using native kernel calls now. - removed a lot of wrappers, including t1_read/write_reg_4. drivers/net/chelsio/espi.h - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/gmac.h - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/mv88x201x.c - changes to sync with Chelsio TOT. drivers/net/chelsio/osdep.h - removed file, consolidation. osdep was used to translate wrapper functions since our code supports multiple OSs. removed wrappers. drivers/net/chelsio/pm3393.c - removed various macros, using native kernel calls now. - removed a lot of wrappers, including t1_read/write_reg_4. - removed unused code. drivers/net/chelsio/regs.h - added a few register entries for future and current feature support. - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/sge.c - rewrote large portion of scatter-gather engine to stabilize performance. - using u8/u16/u32 kernel types instead of __u8/__u16/__u32 compiler types. drivers/net/chelsio/sge.h - rewrote large portion of scatter-gather engine to stabilize performance. - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/subr.c - merged tp.c into subr.c - removed various macros, using native kernel calls now. - removed a lot of wrappers, including t1_read/write_reg_4. - removed unused code. drivers/net/chelsio/suni1x10gexp_regs.h - modified copyright and authorship of file. - added comment to #endif indicating which symbol it closes. drivers/net/chelsio/tp.c - removed file, merged into subr.c. drivers/net/chelsio/tp.h - removed file. include/linux/pci_ids.h - patched to include PCI_VENDOR_ID_CHELSIO 0x1425, removed define from our code.
Diffstat (limited to 'drivers/net/chelsio/sge.c')
-rw-r--r--drivers/net/chelsio/sge.c1859
1 files changed, 1046 insertions, 813 deletions
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index bcf8b1e939b0..53b41d99b00b 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -1,8 +1,8 @@
1/***************************************************************************** 1/*****************************************************************************
2 * * 2 * *
3 * File: sge.c * 3 * File: sge.c *
4 * $Revision: 1.13 $ * 4 * $Revision: 1.26 $ *
5 * $Date: 2005/03/23 07:41:27 $ * 5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: * 6 * Description: *
7 * DMA engine. * 7 * DMA engine. *
8 * part of the Chelsio 10Gb Ethernet Driver. * 8 * part of the Chelsio 10Gb Ethernet Driver. *
@@ -58,59 +58,62 @@
58#include "regs.h" 58#include "regs.h"
59#include "espi.h" 59#include "espi.h"
60 60
61
62#ifdef NETIF_F_TSO
61#include <linux/tcp.h> 63#include <linux/tcp.h>
64#endif
62 65
63#define SGE_CMDQ_N 2 66#define SGE_CMDQ_N 2
64#define SGE_FREELQ_N 2 67#define SGE_FREELQ_N 2
65#define SGE_CMDQ0_E_N 512 68#define SGE_CMDQ0_E_N 1024
66#define SGE_CMDQ1_E_N 128 69#define SGE_CMDQ1_E_N 128
67#define SGE_FREEL_SIZE 4096 70#define SGE_FREEL_SIZE 4096
68#define SGE_JUMBO_FREEL_SIZE 512 71#define SGE_JUMBO_FREEL_SIZE 512
69#define SGE_FREEL_REFILL_THRESH 16 72#define SGE_FREEL_REFILL_THRESH 16
70#define SGE_RESPQ_E_N 1024 73#define SGE_RESPQ_E_N 1024
71#define SGE_INTR_BUCKETSIZE 100 74#define SGE_INTRTIMER_NRES 1000
72#define SGE_INTR_LATBUCKETS 5 75#define SGE_RX_COPY_THRES 256
73#define SGE_INTR_MAXBUCKETS 11
74#define SGE_INTRTIMER0 1
75#define SGE_INTRTIMER1 50
76#define SGE_INTRTIMER_NRES 10000
77#define SGE_RX_COPY_THRESHOLD 256
78#define SGE_RX_SM_BUF_SIZE 1536 76#define SGE_RX_SM_BUF_SIZE 1536
79 77
80#define SGE_RESPQ_REPLENISH_THRES ((3 * SGE_RESPQ_E_N) / 4) 78# define SGE_RX_DROP_THRES 2
79
80#define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
81
82/*
83 * Period of the TX buffer reclaim timer. This timer does not need to run
84 * frequently as TX buffers are usually reclaimed by new TX packets.
85 */
86#define TX_RECLAIM_PERIOD (HZ / 4)
81 87
82#define SGE_RX_OFFSET 2
83#ifndef NET_IP_ALIGN 88#ifndef NET_IP_ALIGN
84# define NET_IP_ALIGN SGE_RX_OFFSET 89# define NET_IP_ALIGN 2
85#endif 90#endif
86 91
92#define M_CMD_LEN 0x7fffffff
93#define V_CMD_LEN(v) (v)
94#define G_CMD_LEN(v) ((v) & M_CMD_LEN)
95#define V_CMD_GEN1(v) ((v) << 31)
96#define V_CMD_GEN2(v) (v)
97#define F_CMD_DATAVALID (1 << 1)
98#define F_CMD_SOP (1 << 2)
99#define V_CMD_EOP(v) ((v) << 3)
100
87/* 101/*
88 * Memory Mapped HW Command, Freelist and Response Queue Descriptors 102 * Command queue, receive buffer list, and response queue descriptors.
89 */ 103 */
90#if defined(__BIG_ENDIAN_BITFIELD) 104#if defined(__BIG_ENDIAN_BITFIELD)
91struct cmdQ_e { 105struct cmdQ_e {
92 u32 AddrLow; 106 u32 addr_lo;
93 u32 GenerationBit : 1; 107 u32 len_gen;
94 u32 BufferLength : 31; 108 u32 flags;
95 u32 RespQueueSelector : 4; 109 u32 addr_hi;
96 u32 ResponseTokens : 12;
97 u32 CmdId : 8;
98 u32 Reserved : 3;
99 u32 TokenValid : 1;
100 u32 Eop : 1;
101 u32 Sop : 1;
102 u32 DataValid : 1;
103 u32 GenerationBit2 : 1;
104 u32 AddrHigh;
105}; 110};
106 111
107struct freelQ_e { 112struct freelQ_e {
108 u32 AddrLow; 113 u32 addr_lo;
109 u32 GenerationBit : 1; 114 u32 len_gen;
110 u32 BufferLength : 31; 115 u32 gen2;
111 u32 Reserved : 31; 116 u32 addr_hi;
112 u32 GenerationBit2 : 1;
113 u32 AddrHigh;
114}; 117};
115 118
116struct respQ_e { 119struct respQ_e {
@@ -128,31 +131,19 @@ struct respQ_e {
128 u32 GenerationBit : 1; 131 u32 GenerationBit : 1;
129 u32 BufferLength; 132 u32 BufferLength;
130}; 133};
131
132#elif defined(__LITTLE_ENDIAN_BITFIELD) 134#elif defined(__LITTLE_ENDIAN_BITFIELD)
133struct cmdQ_e { 135struct cmdQ_e {
134 u32 BufferLength : 31; 136 u32 len_gen;
135 u32 GenerationBit : 1; 137 u32 addr_lo;
136 u32 AddrLow; 138 u32 addr_hi;
137 u32 AddrHigh; 139 u32 flags;
138 u32 GenerationBit2 : 1;
139 u32 DataValid : 1;
140 u32 Sop : 1;
141 u32 Eop : 1;
142 u32 TokenValid : 1;
143 u32 Reserved : 3;
144 u32 CmdId : 8;
145 u32 ResponseTokens : 12;
146 u32 RespQueueSelector : 4;
147}; 140};
148 141
149struct freelQ_e { 142struct freelQ_e {
150 u32 BufferLength : 31; 143 u32 len_gen;
151 u32 GenerationBit : 1; 144 u32 addr_lo;
152 u32 AddrLow; 145 u32 addr_hi;
153 u32 AddrHigh; 146 u32 gen2;
154 u32 GenerationBit2 : 1;
155 u32 Reserved : 31;
156}; 147};
157 148
158struct respQ_e { 149struct respQ_e {
@@ -179,7 +170,6 @@ struct cmdQ_ce {
179 struct sk_buff *skb; 170 struct sk_buff *skb;
180 DECLARE_PCI_UNMAP_ADDR(dma_addr); 171 DECLARE_PCI_UNMAP_ADDR(dma_addr);
181 DECLARE_PCI_UNMAP_LEN(dma_len); 172 DECLARE_PCI_UNMAP_LEN(dma_len);
182 unsigned int single;
183}; 173};
184 174
185struct freelQ_ce { 175struct freelQ_ce {
@@ -189,44 +179,52 @@ struct freelQ_ce {
189}; 179};
190 180
191/* 181/*
192 * SW Command, Freelist and Response Queue 182 * SW command, freelist and response rings
193 */ 183 */
194struct cmdQ { 184struct cmdQ {
195 atomic_t asleep; /* HW DMA Fetch status */ 185 unsigned long status; /* HW DMA fetch status */
196 atomic_t credits; /* # available descriptors for TX */ 186 unsigned int in_use; /* # of in-use command descriptors */
197 atomic_t pio_pidx; /* Variable updated on Doorbell */ 187 unsigned int size; /* # of descriptors */
198 u16 entries_n; /* # descriptors for TX */ 188 unsigned int processed; /* total # of descs HW has processed */
199 u16 pidx; /* producer index (SW) */ 189 unsigned int cleaned; /* total # of descs SW has reclaimed */
200 u16 cidx; /* consumer index (HW) */ 190 unsigned int stop_thres; /* SW TX queue suspend threshold */
201 u8 genbit; /* current generation (=valid) bit */ 191 u16 pidx; /* producer index (SW) */
202 struct cmdQ_e *entries; /* HW command descriptor Q */ 192 u16 cidx; /* consumer index (HW) */
203 struct cmdQ_ce *centries; /* SW command context descriptor Q */ 193 u8 genbit; /* current generation (=valid) bit */
204 spinlock_t Qlock; /* Lock to protect cmdQ enqueuing */ 194 u8 sop; /* is next entry start of packet? */
205 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */ 195 struct cmdQ_e *entries; /* HW command descriptor Q */
196 struct cmdQ_ce *centries; /* SW command context descriptor Q */
197 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
198 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
206}; 199};
207 200
208struct freelQ { 201struct freelQ {
209 unsigned int credits; /* # of available RX buffers */ 202 unsigned int credits; /* # of available RX buffers */
210 unsigned int entries_n; /* free list capacity */ 203 unsigned int size; /* free list capacity */
211 u16 pidx; /* producer index (SW) */ 204 u16 pidx; /* producer index (SW) */
212 u16 cidx; /* consumer index (HW) */ 205 u16 cidx; /* consumer index (HW) */
213 u16 rx_buffer_size; /* Buffer size on this free list */ 206 u16 rx_buffer_size; /* Buffer size on this free list */
214 u16 dma_offset; /* DMA offset to align IP headers */ 207 u16 dma_offset; /* DMA offset to align IP headers */
215 u8 genbit; /* current generation (=valid) bit */ 208 u16 recycleq_idx; /* skb recycle q to use */
216 struct freelQ_e *entries; /* HW freelist descriptor Q */ 209 u8 genbit; /* current generation (=valid) bit */
217 struct freelQ_ce *centries; /* SW freelist conext descriptor Q */ 210 struct freelQ_e *entries; /* HW freelist descriptor Q */
218 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */ 211 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
212 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */
219}; 213};
220 214
221struct respQ { 215struct respQ {
222 u16 credits; /* # of available respQ descriptors */ 216 unsigned int credits; /* credits to be returned to SGE */
223 u16 credits_pend; /* # of not yet returned descriptors */ 217 unsigned int size; /* # of response Q descriptors */
224 u16 entries_n; /* # of response Q descriptors */ 218 u16 cidx; /* consumer index (SW) */
225 u16 pidx; /* producer index (HW) */ 219 u8 genbit; /* current generation(=valid) bit */
226 u16 cidx; /* consumer index (SW) */
227 u8 genbit; /* current generation(=valid) bit */
228 struct respQ_e *entries; /* HW response descriptor Q */ 220 struct respQ_e *entries; /* HW response descriptor Q */
229 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */ 221 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */
222};
223
224/* Bit flags for cmdQ.status */
225enum {
226 CMDQ_STAT_RUNNING = 1, /* fetch engine is running */
227 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
230}; 228};
231 229
232/* 230/*
@@ -239,134 +237,50 @@ struct respQ {
239 */ 237 */
240struct sge { 238struct sge {
241 struct adapter *adapter; /* adapter backpointer */ 239 struct adapter *adapter; /* adapter backpointer */
242 struct freelQ freelQ[SGE_FREELQ_N]; /* freelist Q(s) */ 240 struct net_device *netdev; /* netdevice backpointer */
243 struct respQ respQ; /* response Q instatiation */ 241 struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */
242 struct respQ respQ; /* response Q */
243 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */
244 unsigned int rx_pkt_pad; /* RX padding for L2 packets */ 244 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
245 unsigned int jumbo_fl; /* jumbo freelist Q index */ 245 unsigned int jumbo_fl; /* jumbo freelist Q index */
246 u32 intrtimer[SGE_INTR_MAXBUCKETS]; /* ! */ 246 unsigned int intrtimer_nres; /* no-resource interrupt timer */
247 u32 currIndex; /* current index into intrtimer[] */ 247 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
248 u32 intrtimer_nres; /* no resource interrupt timer value */ 248 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
249 u32 sge_control; /* shadow content of sge control reg */ 249 struct timer_list espibug_timer;
250 struct sge_intr_counts intr_cnt; 250 unsigned int espibug_timeout;
251 struct timer_list ptimer; 251 struct sk_buff *espibug_skb;
252 struct sk_buff *pskb; 252 u32 sge_control; /* shadow value of sge control reg */
253 u32 ptimeout; 253 struct sge_intr_counts stats;
254 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned; /* command Q(s)*/ 254 struct sge_port_stats port_stats[MAX_NPORTS];
255 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
255}; 256};
256 257
257static unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
258 unsigned int qid);
259
260/* 258/*
261 * PIO to indicate that memory mapped Q contains valid descriptor(s). 259 * PIO to indicate that memory mapped Q contains valid descriptor(s).
262 */ 260 */
263static inline void doorbell_pio(struct sge *sge, u32 val) 261static inline void doorbell_pio(struct adapter *adapter, u32 val)
264{ 262{
265 wmb(); 263 wmb();
266 t1_write_reg_4(sge->adapter, A_SG_DOORBELL, val); 264 writel(val, adapter->regs + A_SG_DOORBELL);
267}
268
269/*
270 * Disables the DMA engine.
271 */
272void t1_sge_stop(struct sge *sge)
273{
274 t1_write_reg_4(sge->adapter, A_SG_CONTROL, 0);
275 t1_read_reg_4(sge->adapter, A_SG_CONTROL); /* flush write */
276 if (is_T2(sge->adapter))
277 del_timer_sync(&sge->ptimer);
278}
279
280static u8 ch_mac_addr[ETH_ALEN] = {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
281static void t1_espi_workaround(void *data)
282{
283 struct adapter *adapter = (struct adapter *)data;
284 struct sge *sge = adapter->sge;
285
286 if (netif_running(adapter->port[0].dev) &&
287 atomic_read(&sge->cmdQ[0].asleep)) {
288
289 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
290
291 if ((seop & 0xfff0fff) == 0xfff && sge->pskb) {
292 struct sk_buff *skb = sge->pskb;
293 if (!skb->cb[0]) {
294 memcpy(skb->data+sizeof(struct cpl_tx_pkt), ch_mac_addr, ETH_ALEN);
295 memcpy(skb->data+skb->len-10, ch_mac_addr, ETH_ALEN);
296
297 skb->cb[0] = 0xff;
298 }
299 t1_sge_tx(skb, adapter,0);
300 }
301 }
302 mod_timer(&adapter->sge->ptimer, jiffies + sge->ptimeout);
303}
304
305/*
306 * Enables the DMA engine.
307 */
308void t1_sge_start(struct sge *sge)
309{
310 t1_write_reg_4(sge->adapter, A_SG_CONTROL, sge->sge_control);
311 t1_read_reg_4(sge->adapter, A_SG_CONTROL); /* flush write */
312 if (is_T2(sge->adapter)) {
313 init_timer(&sge->ptimer);
314 sge->ptimer.function = (void *)&t1_espi_workaround;
315 sge->ptimer.data = (unsigned long)sge->adapter;
316 sge->ptimer.expires = jiffies + sge->ptimeout;
317 add_timer(&sge->ptimer);
318 }
319}
320
321/*
322 * Creates a t1_sge structure and returns suggested resource parameters.
323 */
324struct sge * __devinit t1_sge_create(struct adapter *adapter,
325 struct sge_params *p)
326{
327 struct sge *sge = kmalloc(sizeof(*sge), GFP_KERNEL);
328
329 if (!sge)
330 return NULL;
331 memset(sge, 0, sizeof(*sge));
332
333 if (is_T2(adapter))
334 sge->ptimeout = 1; /* finest allowed */
335
336 sge->adapter = adapter;
337 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : SGE_RX_OFFSET;
338 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
339
340 p->cmdQ_size[0] = SGE_CMDQ0_E_N;
341 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
342 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
343 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
344 p->rx_coalesce_usecs = SGE_INTRTIMER1;
345 p->last_rx_coalesce_raw = SGE_INTRTIMER1 *
346 (board_info(sge->adapter)->clock_core / 1000000);
347 p->default_rx_coalesce_usecs = SGE_INTRTIMER1;
348 p->coalesce_enable = 0; /* Turn off adaptive algorithm by default */
349 p->sample_interval_usecs = 0;
350 return sge;
351} 265}
352 266
353/* 267/*
354 * Frees all RX buffers on the freelist Q. The caller must make sure that 268 * Frees all RX buffers on the freelist Q. The caller must make sure that
355 * the SGE is turned off before calling this function. 269 * the SGE is turned off before calling this function.
356 */ 270 */
357static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *Q) 271static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
358{ 272{
359 unsigned int cidx = Q->cidx, credits = Q->credits; 273 unsigned int cidx = q->cidx;
360 274
361 while (credits--) { 275 while (q->credits--) {
362 struct freelQ_ce *ce = &Q->centries[cidx]; 276 struct freelQ_ce *ce = &q->centries[cidx];
363 277
364 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), 278 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
365 pci_unmap_len(ce, dma_len), 279 pci_unmap_len(ce, dma_len),
366 PCI_DMA_FROMDEVICE); 280 PCI_DMA_FROMDEVICE);
367 dev_kfree_skb(ce->skb); 281 dev_kfree_skb(ce->skb);
368 ce->skb = NULL; 282 ce->skb = NULL;
369 if (++cidx == Q->entries_n) 283 if (++cidx == q->size)
370 cidx = 0; 284 cidx = 0;
371 } 285 }
372} 286}
@@ -380,29 +294,29 @@ static void free_rx_resources(struct sge *sge)
380 unsigned int size, i; 294 unsigned int size, i;
381 295
382 if (sge->respQ.entries) { 296 if (sge->respQ.entries) {
383 size = sizeof(struct respQ_e) * sge->respQ.entries_n; 297 size = sizeof(struct respQ_e) * sge->respQ.size;
384 pci_free_consistent(pdev, size, sge->respQ.entries, 298 pci_free_consistent(pdev, size, sge->respQ.entries,
385 sge->respQ.dma_addr); 299 sge->respQ.dma_addr);
386 } 300 }
387 301
388 for (i = 0; i < SGE_FREELQ_N; i++) { 302 for (i = 0; i < SGE_FREELQ_N; i++) {
389 struct freelQ *Q = &sge->freelQ[i]; 303 struct freelQ *q = &sge->freelQ[i];
390 304
391 if (Q->centries) { 305 if (q->centries) {
392 free_freelQ_buffers(pdev, Q); 306 free_freelQ_buffers(pdev, q);
393 kfree(Q->centries); 307 kfree(q->centries);
394 } 308 }
395 if (Q->entries) { 309 if (q->entries) {
396 size = sizeof(struct freelQ_e) * Q->entries_n; 310 size = sizeof(struct freelQ_e) * q->size;
397 pci_free_consistent(pdev, size, Q->entries, 311 pci_free_consistent(pdev, size, q->entries,
398 Q->dma_addr); 312 q->dma_addr);
399 } 313 }
400 } 314 }
401} 315}
402 316
403/* 317/*
404 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a 318 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
405 * response Q. 319 * response queue.
406 */ 320 */
407static int alloc_rx_resources(struct sge *sge, struct sge_params *p) 321static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
408{ 322{
@@ -410,21 +324,22 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
410 unsigned int size, i; 324 unsigned int size, i;
411 325
412 for (i = 0; i < SGE_FREELQ_N; i++) { 326 for (i = 0; i < SGE_FREELQ_N; i++) {
413 struct freelQ *Q = &sge->freelQ[i]; 327 struct freelQ *q = &sge->freelQ[i];
414 328
415 Q->genbit = 1; 329 q->genbit = 1;
416 Q->entries_n = p->freelQ_size[i]; 330 q->size = p->freelQ_size[i];
417 Q->dma_offset = SGE_RX_OFFSET - sge->rx_pkt_pad; 331 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
418 size = sizeof(struct freelQ_e) * Q->entries_n; 332 size = sizeof(struct freelQ_e) * q->size;
419 Q->entries = (struct freelQ_e *) 333 q->entries = (struct freelQ_e *)
420 pci_alloc_consistent(pdev, size, &Q->dma_addr); 334 pci_alloc_consistent(pdev, size, &q->dma_addr);
421 if (!Q->entries) 335 if (!q->entries)
422 goto err_no_mem; 336 goto err_no_mem;
423 memset(Q->entries, 0, size); 337 memset(q->entries, 0, size);
424 Q->centries = kcalloc(Q->entries_n, sizeof(struct freelQ_ce), 338 size = sizeof(struct freelQ_ce) * q->size;
425 GFP_KERNEL); 339 q->centries = kmalloc(size, GFP_KERNEL);
426 if (!Q->centries) 340 if (!q->centries)
427 goto err_no_mem; 341 goto err_no_mem;
342 memset(q->centries, 0, size);
428 } 343 }
429 344
430 /* 345 /*
@@ -440,10 +355,17 @@ static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
440 sge->freelQ[sge->jumbo_fl].rx_buffer_size = (16 * 1024) - 355 sge->freelQ[sge->jumbo_fl].rx_buffer_size = (16 * 1024) -
441 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 356 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
442 357
358 /*
359 * Setup which skb recycle Q should be used when recycling buffers from
360 * each free list.
361 */
362 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
363 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
364
443 sge->respQ.genbit = 1; 365 sge->respQ.genbit = 1;
444 sge->respQ.entries_n = SGE_RESPQ_E_N; 366 sge->respQ.size = SGE_RESPQ_E_N;
445 sge->respQ.credits = SGE_RESPQ_E_N; 367 sge->respQ.credits = 0;
446 size = sizeof(struct respQ_e) * sge->respQ.entries_n; 368 size = sizeof(struct respQ_e) * sge->respQ.size;
447 sge->respQ.entries = (struct respQ_e *) 369 sge->respQ.entries = (struct respQ_e *)
448 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr); 370 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
449 if (!sge->respQ.entries) 371 if (!sge->respQ.entries)
@@ -457,48 +379,37 @@ err_no_mem:
457} 379}
458 380
459/* 381/*
460 * Frees 'credits_pend' TX buffers and returns the credits to Q->credits. 382 * Reclaims n TX descriptors and frees the buffers associated with them.
461 *
462 * The adaptive algorithm receives the total size of the buffers freed
463 * accumulated in @*totpayload. No initialization of this argument here.
464 *
465 */ 383 */
466static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *Q, 384static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
467 unsigned int credits_pend, unsigned int *totpayload)
468{ 385{
386 struct cmdQ_ce *ce;
469 struct pci_dev *pdev = sge->adapter->pdev; 387 struct pci_dev *pdev = sge->adapter->pdev;
470 struct sk_buff *skb; 388 unsigned int cidx = q->cidx;
471 struct cmdQ_ce *ce, *cq = Q->centries;
472 unsigned int entries_n = Q->entries_n, cidx = Q->cidx,
473 i = credits_pend;
474
475 389
476 ce = &cq[cidx]; 390 q->in_use -= n;
477 while (i--) { 391 ce = &q->centries[cidx];
478 if (ce->single) 392 while (n--) {
393 if (q->sop)
479 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr), 394 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
480 pci_unmap_len(ce, dma_len), 395 pci_unmap_len(ce, dma_len),
481 PCI_DMA_TODEVICE); 396 PCI_DMA_TODEVICE);
482 else 397 else
483 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr), 398 pci_unmap_page(pdev, pci_unmap_addr(ce, dma_addr),
484 pci_unmap_len(ce, dma_len), 399 pci_unmap_len(ce, dma_len),
485 PCI_DMA_TODEVICE); 400 PCI_DMA_TODEVICE);
486 if (totpayload) 401 q->sop = 0;
487 *totpayload += pci_unmap_len(ce, dma_len); 402 if (ce->skb) {
488 403 dev_kfree_skb(ce->skb);
489 skb = ce->skb; 404 q->sop = 1;
490 if (skb) 405 }
491 dev_kfree_skb_irq(skb);
492
493 ce++; 406 ce++;
494 if (++cidx == entries_n) { 407 if (++cidx == q->size) {
495 cidx = 0; 408 cidx = 0;
496 ce = cq; 409 ce = q->centries;
497 } 410 }
498 } 411 }
499 412 q->cidx = cidx;
500 Q->cidx = cidx;
501 atomic_add(credits_pend, &Q->credits);
502} 413}
503 414
504/* 415/*
@@ -512,20 +423,17 @@ static void free_tx_resources(struct sge *sge)
512 unsigned int size, i; 423 unsigned int size, i;
513 424
514 for (i = 0; i < SGE_CMDQ_N; i++) { 425 for (i = 0; i < SGE_CMDQ_N; i++) {
515 struct cmdQ *Q = &sge->cmdQ[i]; 426 struct cmdQ *q = &sge->cmdQ[i];
516 427
517 if (Q->centries) { 428 if (q->centries) {
518 unsigned int pending = Q->entries_n - 429 if (q->in_use)
519 atomic_read(&Q->credits); 430 free_cmdQ_buffers(sge, q, q->in_use);
520 431 kfree(q->centries);
521 if (pending)
522 free_cmdQ_buffers(sge, Q, pending, NULL);
523 kfree(Q->centries);
524 } 432 }
525 if (Q->entries) { 433 if (q->entries) {
526 size = sizeof(struct cmdQ_e) * Q->entries_n; 434 size = sizeof(struct cmdQ_e) * q->size;
527 pci_free_consistent(pdev, size, Q->entries, 435 pci_free_consistent(pdev, size, q->entries,
528 Q->dma_addr); 436 q->dma_addr);
529 } 437 }
530 } 438 }
531} 439}
@@ -539,25 +447,38 @@ static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
539 unsigned int size, i; 447 unsigned int size, i;
540 448
541 for (i = 0; i < SGE_CMDQ_N; i++) { 449 for (i = 0; i < SGE_CMDQ_N; i++) {
542 struct cmdQ *Q = &sge->cmdQ[i]; 450 struct cmdQ *q = &sge->cmdQ[i];
543 451
544 Q->genbit = 1; 452 q->genbit = 1;
545 Q->entries_n = p->cmdQ_size[i]; 453 q->sop = 1;
546 atomic_set(&Q->credits, Q->entries_n); 454 q->size = p->cmdQ_size[i];
547 atomic_set(&Q->asleep, 1); 455 q->in_use = 0;
548 spin_lock_init(&Q->Qlock); 456 q->status = 0;
549 size = sizeof(struct cmdQ_e) * Q->entries_n; 457 q->processed = q->cleaned = 0;
550 Q->entries = (struct cmdQ_e *) 458 q->stop_thres = 0;
551 pci_alloc_consistent(pdev, size, &Q->dma_addr); 459 spin_lock_init(&q->lock);
552 if (!Q->entries) 460 size = sizeof(struct cmdQ_e) * q->size;
461 q->entries = (struct cmdQ_e *)
462 pci_alloc_consistent(pdev, size, &q->dma_addr);
463 if (!q->entries)
553 goto err_no_mem; 464 goto err_no_mem;
554 memset(Q->entries, 0, size); 465 memset(q->entries, 0, size);
555 Q->centries = kcalloc(Q->entries_n, sizeof(struct cmdQ_ce), 466 size = sizeof(struct cmdQ_ce) * q->size;
556 GFP_KERNEL); 467 q->centries = kmalloc(size, GFP_KERNEL);
557 if (!Q->centries) 468 if (!q->centries)
558 goto err_no_mem; 469 goto err_no_mem;
470 memset(q->centries, 0, size);
559 } 471 }
560 472
473 /*
474 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
475 * only. For queue 0 set the stop threshold so we can handle one more
476 * packet from each port, plus reserve an additional 24 entries for
477 * Ethernet packets only. Queue 1 never suspends nor do we reserve
478 * space for Ethernet packets.
479 */
480 sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
481 (MAX_SKB_FRAGS + 1);
561 return 0; 482 return 0;
562 483
563err_no_mem: 484err_no_mem:
@@ -569,9 +490,9 @@ static inline void setup_ring_params(struct adapter *adapter, u64 addr,
569 u32 size, int base_reg_lo, 490 u32 size, int base_reg_lo,
570 int base_reg_hi, int size_reg) 491 int base_reg_hi, int size_reg)
571{ 492{
572 t1_write_reg_4(adapter, base_reg_lo, (u32)addr); 493 writel((u32)addr, adapter->regs + base_reg_lo);
573 t1_write_reg_4(adapter, base_reg_hi, addr >> 32); 494 writel(addr >> 32, adapter->regs + base_reg_hi);
574 t1_write_reg_4(adapter, size_reg, size); 495 writel(size, adapter->regs + size_reg);
575} 496}
576 497
577/* 498/*
@@ -585,97 +506,52 @@ void t1_set_vlan_accel(struct adapter *adapter, int on_off)
585 if (on_off) 506 if (on_off)
586 sge->sge_control |= F_VLAN_XTRACT; 507 sge->sge_control |= F_VLAN_XTRACT;
587 if (adapter->open_device_map) { 508 if (adapter->open_device_map) {
588 t1_write_reg_4(adapter, A_SG_CONTROL, sge->sge_control); 509 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
589 t1_read_reg_4(adapter, A_SG_CONTROL); /* flush */ 510 readl(adapter->regs + A_SG_CONTROL); /* flush */
590 } 511 }
591} 512}
592 513
593/* 514/*
594 * Sets the interrupt latency timer when the adaptive Rx coalescing
595 * is turned off. Do nothing when it is turned on again.
596 *
597 * This routine relies on the fact that the caller has already set
598 * the adaptive policy in adapter->sge_params before calling it.
599*/
600int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
601{
602 if (!p->coalesce_enable) {
603 u32 newTimer = p->rx_coalesce_usecs *
604 (board_info(sge->adapter)->clock_core / 1000000);
605
606 t1_write_reg_4(sge->adapter, A_SG_INTRTIMER, newTimer);
607 }
608 return 0;
609}
610
611/*
612 * Programs the various SGE registers. However, the engine is not yet enabled, 515 * Programs the various SGE registers. However, the engine is not yet enabled,
613 * but sge->sge_control is setup and ready to go. 516 * but sge->sge_control is setup and ready to go.
614 */ 517 */
615static void configure_sge(struct sge *sge, struct sge_params *p) 518static void configure_sge(struct sge *sge, struct sge_params *p)
616{ 519{
617 struct adapter *ap = sge->adapter; 520 struct adapter *ap = sge->adapter;
618 int i; 521
619 522 writel(0, ap->regs + A_SG_CONTROL);
620 t1_write_reg_4(ap, A_SG_CONTROL, 0); 523 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
621 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].entries_n,
622 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE); 524 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
623 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].entries_n, 525 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
624 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE); 526 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
625 setup_ring_params(ap, sge->freelQ[0].dma_addr, 527 setup_ring_params(ap, sge->freelQ[0].dma_addr,
626 sge->freelQ[0].entries_n, A_SG_FL0BASELWR, 528 sge->freelQ[0].size, A_SG_FL0BASELWR,
627 A_SG_FL0BASEUPR, A_SG_FL0SIZE); 529 A_SG_FL0BASEUPR, A_SG_FL0SIZE);
628 setup_ring_params(ap, sge->freelQ[1].dma_addr, 530 setup_ring_params(ap, sge->freelQ[1].dma_addr,
629 sge->freelQ[1].entries_n, A_SG_FL1BASELWR, 531 sge->freelQ[1].size, A_SG_FL1BASELWR,
630 A_SG_FL1BASEUPR, A_SG_FL1SIZE); 532 A_SG_FL1BASEUPR, A_SG_FL1SIZE);
631 533
632 /* The threshold comparison uses <. */ 534 /* The threshold comparison uses <. */
633 t1_write_reg_4(ap, A_SG_FLTHRESHOLD, SGE_RX_SM_BUF_SIZE + 1); 535 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
634 536
635 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.entries_n, 537 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
636 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE); 538 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
637 t1_write_reg_4(ap, A_SG_RSPQUEUECREDIT, (u32)sge->respQ.entries_n); 539 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
638 540
639 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE | 541 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
640 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE | 542 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
641 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE | 543 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
544 F_DISABLE_FL0_GTS | F_DISABLE_FL1_GTS |
642 V_RX_PKT_OFFSET(sge->rx_pkt_pad); 545 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
643 546
644#if defined(__BIG_ENDIAN_BITFIELD) 547#if defined(__BIG_ENDIAN_BITFIELD)
645 sge->sge_control |= F_ENABLE_BIG_ENDIAN; 548 sge->sge_control |= F_ENABLE_BIG_ENDIAN;
646#endif 549#endif
647 550
648 /* 551 /* Initialize no-resource timer */
649 * Initialize the SGE Interrupt Timer arrray: 552 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
650 * intrtimer[0] = (SGE_INTRTIMER0) usec 553
651 * intrtimer[0<i<5] = (SGE_INTRTIMER0 + i*2) usec 554 t1_sge_set_coalesce_params(sge, p);
652 * intrtimer[4<i<10] = ((i - 3) * 6) usec
653 * intrtimer[10] = (SGE_INTRTIMER1) usec
654 *
655 */
656 sge->intrtimer[0] = board_info(sge->adapter)->clock_core / 1000000;
657 for (i = 1; i < SGE_INTR_LATBUCKETS; ++i) {
658 sge->intrtimer[i] = SGE_INTRTIMER0 + (2 * i);
659 sge->intrtimer[i] *= sge->intrtimer[0];
660 }
661 for (i = SGE_INTR_LATBUCKETS; i < SGE_INTR_MAXBUCKETS - 1; ++i) {
662 sge->intrtimer[i] = (i - 3) * 6;
663 sge->intrtimer[i] *= sge->intrtimer[0];
664 }
665 sge->intrtimer[SGE_INTR_MAXBUCKETS - 1] =
666 sge->intrtimer[0] * SGE_INTRTIMER1;
667 /* Initialize resource timer */
668 sge->intrtimer_nres = sge->intrtimer[0] * SGE_INTRTIMER_NRES;
669 /* Finally finish initialization of intrtimer[0] */
670 sge->intrtimer[0] *= SGE_INTRTIMER0;
671 /* Initialize for a throughput oriented workload */
672 sge->currIndex = SGE_INTR_MAXBUCKETS - 1;
673
674 if (p->coalesce_enable)
675 t1_write_reg_4(ap, A_SG_INTRTIMER,
676 sge->intrtimer[sge->currIndex]);
677 else
678 t1_sge_set_coalesce_params(sge, p);
679} 555}
680 556
681/* 557/*
@@ -684,31 +560,8 @@ static void configure_sge(struct sge *sge, struct sge_params *p)
684static inline unsigned int jumbo_payload_capacity(const struct sge *sge) 560static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
685{ 561{
686 return sge->freelQ[sge->jumbo_fl].rx_buffer_size - 562 return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
687 sizeof(struct cpl_rx_data) - SGE_RX_OFFSET + sge->rx_pkt_pad; 563 sge->freelQ[sge->jumbo_fl].dma_offset -
688} 564 sizeof(struct cpl_rx_data);
689
690/*
691 * Allocates both RX and TX resources and configures the SGE. However,
692 * the hardware is not enabled yet.
693 */
694int t1_sge_configure(struct sge *sge, struct sge_params *p)
695{
696 if (alloc_rx_resources(sge, p))
697 return -ENOMEM;
698 if (alloc_tx_resources(sge, p)) {
699 free_rx_resources(sge);
700 return -ENOMEM;
701 }
702 configure_sge(sge, p);
703
704 /*
705 * Now that we have sized the free lists calculate the payload
706 * capacity of the large buffers. Other parts of the driver use
707 * this to set the max offload coalescing size so that RX packets
708 * do not overflow our large buffers.
709 */
710 p->large_buf_capacity = jumbo_payload_capacity(sge);
711 return 0;
712} 565}
713 566
714/* 567/*
@@ -716,8 +569,9 @@ int t1_sge_configure(struct sge *sge, struct sge_params *p)
716 */ 569 */
717void t1_sge_destroy(struct sge *sge) 570void t1_sge_destroy(struct sge *sge)
718{ 571{
719 if (sge->pskb) 572 if (sge->espibug_skb)
720 dev_kfree_skb(sge->pskb); 573 kfree_skb(sge->espibug_skb);
574
721 free_tx_resources(sge); 575 free_tx_resources(sge);
722 free_rx_resources(sge); 576 free_rx_resources(sge);
723 kfree(sge); 577 kfree(sge);
@@ -735,75 +589,75 @@ void t1_sge_destroy(struct sge *sge)
735 * we specify a RX_OFFSET in order to make sure that the IP header is 4B 589 * we specify a RX_OFFSET in order to make sure that the IP header is 4B
736 * aligned. 590 * aligned.
737 */ 591 */
738static void refill_free_list(struct sge *sge, struct freelQ *Q) 592static void refill_free_list(struct sge *sge, struct freelQ *q)
739{ 593{
740 struct pci_dev *pdev = sge->adapter->pdev; 594 struct pci_dev *pdev = sge->adapter->pdev;
741 struct freelQ_ce *ce = &Q->centries[Q->pidx]; 595 struct freelQ_ce *ce = &q->centries[q->pidx];
742 struct freelQ_e *e = &Q->entries[Q->pidx]; 596 struct freelQ_e *e = &q->entries[q->pidx];
743 unsigned int dma_len = Q->rx_buffer_size - Q->dma_offset; 597 unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
744 598
745 599
746 while (Q->credits < Q->entries_n) { 600 while (q->credits < q->size) {
747 if (e->GenerationBit != Q->genbit) { 601 struct sk_buff *skb;
748 struct sk_buff *skb; 602 dma_addr_t mapping;
749 dma_addr_t mapping;
750 603
751 skb = alloc_skb(Q->rx_buffer_size, GFP_ATOMIC); 604 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
752 if (!skb) 605 if (!skb)
753 break; 606 break;
754 if (Q->dma_offset) 607
755 skb_reserve(skb, Q->dma_offset); 608 skb_reserve(skb, q->dma_offset);
756 mapping = pci_map_single(pdev, skb->data, dma_len, 609 mapping = pci_map_single(pdev, skb->data, dma_len,
757 PCI_DMA_FROMDEVICE); 610 PCI_DMA_FROMDEVICE);
758 ce->skb = skb; 611 ce->skb = skb;
759 pci_unmap_addr_set(ce, dma_addr, mapping); 612 pci_unmap_addr_set(ce, dma_addr, mapping);
760 pci_unmap_len_set(ce, dma_len, dma_len); 613 pci_unmap_len_set(ce, dma_len, dma_len);
761 e->AddrLow = (u32)mapping; 614 e->addr_lo = (u32)mapping;
762 e->AddrHigh = (u64)mapping >> 32; 615 e->addr_hi = (u64)mapping >> 32;
763 e->BufferLength = dma_len; 616 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
764 e->GenerationBit = e->GenerationBit2 = Q->genbit; 617 wmb();
765 } 618 e->gen2 = V_CMD_GEN2(q->genbit);
766 619
767 e++; 620 e++;
768 ce++; 621 ce++;
769 if (++Q->pidx == Q->entries_n) { 622 if (++q->pidx == q->size) {
770 Q->pidx = 0; 623 q->pidx = 0;
771 Q->genbit ^= 1; 624 q->genbit ^= 1;
772 ce = Q->centries; 625 ce = q->centries;
773 e = Q->entries; 626 e = q->entries;
774 } 627 }
775 Q->credits++; 628 q->credits++;
776 } 629 }
777 630
778} 631}
779 632
780/* 633/*
781 * Calls refill_free_list for both freelist Qs. If we cannot 634 * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
782 * fill at least 1/4 of both Qs, we go into 'few interrupt mode' in order 635 * of both rings, we go into 'few interrupt mode' in order to give the system
783 * to give the system time to free up resources. 636 * time to free up resources.
784 */ 637 */
785static void freelQs_empty(struct sge *sge) 638static void freelQs_empty(struct sge *sge)
786{ 639{
787 u32 irq_reg = t1_read_reg_4(sge->adapter, A_SG_INT_ENABLE); 640 struct adapter *adapter = sge->adapter;
641 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
788 u32 irqholdoff_reg; 642 u32 irqholdoff_reg;
789 643
790 refill_free_list(sge, &sge->freelQ[0]); 644 refill_free_list(sge, &sge->freelQ[0]);
791 refill_free_list(sge, &sge->freelQ[1]); 645 refill_free_list(sge, &sge->freelQ[1]);
792 646
793 if (sge->freelQ[0].credits > (sge->freelQ[0].entries_n >> 2) && 647 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
794 sge->freelQ[1].credits > (sge->freelQ[1].entries_n >> 2)) { 648 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
795 irq_reg |= F_FL_EXHAUSTED; 649 irq_reg |= F_FL_EXHAUSTED;
796 irqholdoff_reg = sge->intrtimer[sge->currIndex]; 650 irqholdoff_reg = sge->fixed_intrtimer;
797 } else { 651 } else {
798 /* Clear the F_FL_EXHAUSTED interrupts for now */ 652 /* Clear the F_FL_EXHAUSTED interrupts for now */
799 irq_reg &= ~F_FL_EXHAUSTED; 653 irq_reg &= ~F_FL_EXHAUSTED;
800 irqholdoff_reg = sge->intrtimer_nres; 654 irqholdoff_reg = sge->intrtimer_nres;
801 } 655 }
802 t1_write_reg_4(sge->adapter, A_SG_INTRTIMER, irqholdoff_reg); 656 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
803 t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, irq_reg); 657 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
804 658
805 /* We reenable the Qs to force a freelist GTS interrupt later */ 659 /* We reenable the Qs to force a freelist GTS interrupt later */
806 doorbell_pio(sge, F_FL0_ENABLE | F_FL1_ENABLE); 660 doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
807} 661}
808 662
809#define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA) 663#define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
@@ -816,10 +670,10 @@ static void freelQs_empty(struct sge *sge)
816 */ 670 */
817void t1_sge_intr_disable(struct sge *sge) 671void t1_sge_intr_disable(struct sge *sge)
818{ 672{
819 u32 val = t1_read_reg_4(sge->adapter, A_PL_ENABLE); 673 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
820 674
821 t1_write_reg_4(sge->adapter, A_PL_ENABLE, val & ~SGE_PL_INTR_MASK); 675 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
822 t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, 0); 676 writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
823} 677}
824 678
825/* 679/*
@@ -828,12 +682,12 @@ void t1_sge_intr_disable(struct sge *sge)
828void t1_sge_intr_enable(struct sge *sge) 682void t1_sge_intr_enable(struct sge *sge)
829{ 683{
830 u32 en = SGE_INT_ENABLE; 684 u32 en = SGE_INT_ENABLE;
831 u32 val = t1_read_reg_4(sge->adapter, A_PL_ENABLE); 685 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
832 686
833 if (sge->adapter->flags & TSO_CAPABLE) 687 if (sge->adapter->flags & TSO_CAPABLE)
834 en &= ~F_PACKET_TOO_BIG; 688 en &= ~F_PACKET_TOO_BIG;
835 t1_write_reg_4(sge->adapter, A_SG_INT_ENABLE, en); 689 writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
836 t1_write_reg_4(sge->adapter, A_PL_ENABLE, val | SGE_PL_INTR_MASK); 690 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
837} 691}
838 692
839/* 693/*
@@ -841,8 +695,8 @@ void t1_sge_intr_enable(struct sge *sge)
841 */ 695 */
842void t1_sge_intr_clear(struct sge *sge) 696void t1_sge_intr_clear(struct sge *sge)
843{ 697{
844 t1_write_reg_4(sge->adapter, A_PL_CAUSE, SGE_PL_INTR_MASK); 698 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
845 t1_write_reg_4(sge->adapter, A_SG_INT_CAUSE, 0xffffffff); 699 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
846} 700}
847 701
848/* 702/*
@@ -851,464 +705,673 @@ void t1_sge_intr_clear(struct sge *sge)
851int t1_sge_intr_error_handler(struct sge *sge) 705int t1_sge_intr_error_handler(struct sge *sge)
852{ 706{
853 struct adapter *adapter = sge->adapter; 707 struct adapter *adapter = sge->adapter;
854 u32 cause = t1_read_reg_4(adapter, A_SG_INT_CAUSE); 708 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
855 709
856 if (adapter->flags & TSO_CAPABLE) 710 if (adapter->flags & TSO_CAPABLE)
857 cause &= ~F_PACKET_TOO_BIG; 711 cause &= ~F_PACKET_TOO_BIG;
858 if (cause & F_RESPQ_EXHAUSTED) 712 if (cause & F_RESPQ_EXHAUSTED)
859 sge->intr_cnt.respQ_empty++; 713 sge->stats.respQ_empty++;
860 if (cause & F_RESPQ_OVERFLOW) { 714 if (cause & F_RESPQ_OVERFLOW) {
861 sge->intr_cnt.respQ_overflow++; 715 sge->stats.respQ_overflow++;
862 CH_ALERT("%s: SGE response queue overflow\n", 716 CH_ALERT("%s: SGE response queue overflow\n",
863 adapter->name); 717 adapter->name);
864 } 718 }
865 if (cause & F_FL_EXHAUSTED) { 719 if (cause & F_FL_EXHAUSTED) {
866 sge->intr_cnt.freelistQ_empty++; 720 sge->stats.freelistQ_empty++;
867 freelQs_empty(sge); 721 freelQs_empty(sge);
868 } 722 }
869 if (cause & F_PACKET_TOO_BIG) { 723 if (cause & F_PACKET_TOO_BIG) {
870 sge->intr_cnt.pkt_too_big++; 724 sge->stats.pkt_too_big++;
871 CH_ALERT("%s: SGE max packet size exceeded\n", 725 CH_ALERT("%s: SGE max packet size exceeded\n",
872 adapter->name); 726 adapter->name);
873 } 727 }
874 if (cause & F_PACKET_MISMATCH) { 728 if (cause & F_PACKET_MISMATCH) {
875 sge->intr_cnt.pkt_mismatch++; 729 sge->stats.pkt_mismatch++;
876 CH_ALERT("%s: SGE packet mismatch\n", adapter->name); 730 CH_ALERT("%s: SGE packet mismatch\n", adapter->name);
877 } 731 }
878 if (cause & SGE_INT_FATAL) 732 if (cause & SGE_INT_FATAL)
879 t1_fatal_err(adapter); 733 t1_fatal_err(adapter);
880 734
881 t1_write_reg_4(adapter, A_SG_INT_CAUSE, cause); 735 writel(cause, adapter->regs + A_SG_INT_CAUSE);
882 return 0; 736 return 0;
883} 737}
884 738
885/* 739const struct sge_intr_counts *t1_sge_get_intr_counts(struct sge *sge)
886 * The following code is copied from 2.6, where the skb_pull is doing the 740{
887 * right thing and only pulls ETH_HLEN. 741 return &sge->stats;
742}
743
744const struct sge_port_stats *t1_sge_get_port_stats(struct sge *sge, int port)
745{
746 return &sge->port_stats[port];
747}
748
749/**
750 * recycle_fl_buf - recycle a free list buffer
751 * @fl: the free list
752 * @idx: index of buffer to recycle
888 * 753 *
889 * Determine the packet's protocol ID. The rule here is that we 754 * Recycles the specified buffer on the given free list by adding it at
890 * assume 802.3 if the type field is short enough to be a length. 755 * the next available slot on the list.
891 * This is normal practice and works for any 'now in use' protocol.
892 */ 756 */
893static unsigned short sge_eth_type_trans(struct sk_buff *skb, 757static void recycle_fl_buf(struct freelQ *fl, int idx)
894 struct net_device *dev)
895{ 758{
896 struct ethhdr *eth; 759 struct freelQ_e *from = &fl->entries[idx];
897 unsigned char *rawp; 760 struct freelQ_e *to = &fl->entries[fl->pidx];
898 761
899 skb->mac.raw = skb->data; 762 fl->centries[fl->pidx] = fl->centries[idx];
900 skb_pull(skb, ETH_HLEN); 763 to->addr_lo = from->addr_lo;
901 eth = (struct ethhdr *)skb->mac.raw; 764 to->addr_hi = from->addr_hi;
765 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
766 wmb();
767 to->gen2 = V_CMD_GEN2(fl->genbit);
768 fl->credits++;
902 769
903 if (*eth->h_dest&1) { 770 if (++fl->pidx == fl->size) {
904 if(memcmp(eth->h_dest, dev->broadcast, ETH_ALEN) == 0) 771 fl->pidx = 0;
905 skb->pkt_type = PACKET_BROADCAST; 772 fl->genbit ^= 1;
906 else
907 skb->pkt_type = PACKET_MULTICAST;
908 } 773 }
774}
909 775
910 /* 776/**
911 * This ALLMULTI check should be redundant by 1.4 777 * get_packet - return the next ingress packet buffer
912 * so don't forget to remove it. 778 * @pdev: the PCI device that received the packet
913 * 779 * @fl: the SGE free list holding the packet
914 * Seems, you forgot to remove it. All silly devices 780 * @len: the actual packet length, excluding any SGE padding
915 * seems to set IFF_PROMISC. 781 * @dma_pad: padding at beginning of buffer left by SGE DMA
916 */ 782 * @skb_pad: padding to be used if the packet is copied
783 * @copy_thres: length threshold under which a packet should be copied
784 * @drop_thres: # of remaining buffers before we start dropping packets
785 *
786 * Get the next packet from a free list and complete setup of the
787 * sk_buff. If the packet is small we make a copy and recycle the
788 * original buffer, otherwise we use the original buffer itself. If a
789 * positive drop threshold is supplied packets are dropped and their
790 * buffers recycled if (a) the number of remaining buffers is under the
791 * threshold and the packet is too big to copy, or (b) the packet should
792 * be copied but there is no memory for the copy.
793 */
794static inline struct sk_buff *get_packet(struct pci_dev *pdev,
795 struct freelQ *fl, unsigned int len,
796 int dma_pad, int skb_pad,
797 unsigned int copy_thres,
798 unsigned int drop_thres)
799{
800 struct sk_buff *skb;
801 struct freelQ_ce *ce = &fl->centries[fl->cidx];
802
803 if (len < copy_thres) {
804 skb = alloc_skb(len + skb_pad, GFP_ATOMIC);
805 if (likely(skb != NULL)) {
806 skb_reserve(skb, skb_pad);
807 skb_put(skb, len);
808 pci_dma_sync_single_for_cpu(pdev,
809 pci_unmap_addr(ce, dma_addr),
810 pci_unmap_len(ce, dma_len),
811 PCI_DMA_FROMDEVICE);
812 memcpy(skb->data, ce->skb->data + dma_pad, len);
813 pci_dma_sync_single_for_device(pdev,
814 pci_unmap_addr(ce, dma_addr),
815 pci_unmap_len(ce, dma_len),
816 PCI_DMA_FROMDEVICE);
817 } else if (!drop_thres)
818 goto use_orig_buf;
917 819
918 else if (1 /*dev->flags&IFF_PROMISC*/) 820 recycle_fl_buf(fl, fl->cidx);
919 { 821 return skb;
920 if(memcmp(eth->h_dest,dev->dev_addr, ETH_ALEN))
921 skb->pkt_type=PACKET_OTHERHOST;
922 } 822 }
923 823
924 if (ntohs(eth->h_proto) >= 1536) 824 if (fl->credits < drop_thres) {
925 return eth->h_proto; 825 recycle_fl_buf(fl, fl->cidx);
926 826 return NULL;
927 rawp = skb->data; 827 }
928 828
929 /* 829use_orig_buf:
930 * This is a magic hack to spot IPX packets. Older Novell breaks 830 pci_unmap_single(pdev, pci_unmap_addr(ce, dma_addr),
931 * the protocol design and runs IPX over 802.3 without an 802.2 LLC 831 pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
932 * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This 832 skb = ce->skb;
933 * won't work for fault tolerant netware but does for the rest. 833 skb_reserve(skb, dma_pad);
934 */ 834 skb_put(skb, len);
935 if (*(unsigned short *)rawp == 0xFFFF) 835 return skb;
936 return htons(ETH_P_802_3); 836}
937 837
938 /* 838/**
939 * Real 802.2 LLC 839 * unexpected_offload - handle an unexpected offload packet
940 */ 840 * @adapter: the adapter
941 return htons(ETH_P_802_2); 841 * @fl: the free list that received the packet
842 *
843 * Called when we receive an unexpected offload packet (e.g., the TOE
844 * function is disabled or the card is a NIC). Prints a message and
845 * recycles the buffer.
846 */
847static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
848{
849 struct freelQ_ce *ce = &fl->centries[fl->cidx];
850 struct sk_buff *skb = ce->skb;
851
852 pci_dma_sync_single_for_cpu(adapter->pdev, pci_unmap_addr(ce, dma_addr),
853 pci_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
854 CH_ERR("%s: unexpected offload packet, cmd %u\n",
855 adapter->name, *skb->data);
856 recycle_fl_buf(fl, fl->cidx);
942} 857}
943 858
944/* 859/*
945 * Prepare the received buffer and pass it up the stack. If it is small enough 860 * Write the command descriptors to transmit the given skb starting at
946 * and allocation doesn't fail, we use a new sk_buff and copy the content. 861 * descriptor pidx with the given generation.
947 */ 862 */
948static unsigned int t1_sge_rx(struct sge *sge, struct freelQ *Q, 863static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
949 unsigned int len, unsigned int offload) 864 unsigned int pidx, unsigned int gen,
865 struct cmdQ *q)
950{ 866{
951 struct sk_buff *skb; 867 dma_addr_t mapping;
952 struct adapter *adapter = sge->adapter; 868 struct cmdQ_e *e, *e1;
953 struct freelQ_ce *ce = &Q->centries[Q->cidx]; 869 struct cmdQ_ce *ce;
870 unsigned int i, flags, nfrags = skb_shinfo(skb)->nr_frags;
871
872 mapping = pci_map_single(adapter->pdev, skb->data,
873 skb->len - skb->data_len, PCI_DMA_TODEVICE);
874 ce = &q->centries[pidx];
875 ce->skb = NULL;
876 pci_unmap_addr_set(ce, dma_addr, mapping);
877 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len);
954 878
955 if (len <= SGE_RX_COPY_THRESHOLD && 879 flags = F_CMD_DATAVALID | F_CMD_SOP | V_CMD_EOP(nfrags == 0) |
956 (skb = alloc_skb(len + NET_IP_ALIGN, GFP_ATOMIC))) { 880 V_CMD_GEN2(gen);
957 struct freelQ_e *e; 881 e = &q->entries[pidx];
958 char *src = ce->skb->data; 882 e->addr_lo = (u32)mapping;
883 e->addr_hi = (u64)mapping >> 32;
884 e->len_gen = V_CMD_LEN(skb->len - skb->data_len) | V_CMD_GEN1(gen);
885 for (e1 = e, i = 0; nfrags--; i++) {
886 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
959 887
960 pci_dma_sync_single_for_cpu(adapter->pdev, 888 ce++;
961 pci_unmap_addr(ce, dma_addr), 889 e1++;
962 pci_unmap_len(ce, dma_len), 890 if (++pidx == q->size) {
963 PCI_DMA_FROMDEVICE); 891 pidx = 0;
964 if (!offload) { 892 gen ^= 1;
965 skb_reserve(skb, NET_IP_ALIGN); 893 ce = q->centries;
966 src += sge->rx_pkt_pad; 894 e1 = q->entries;
967 } 895 }
968 memcpy(skb->data, src, len);
969 896
970 /* Reuse the entry. */ 897 mapping = pci_map_page(adapter->pdev, frag->page,
971 e = &Q->entries[Q->cidx]; 898 frag->page_offset, frag->size,
972 e->GenerationBit ^= 1; 899 PCI_DMA_TODEVICE);
973 e->GenerationBit2 ^= 1; 900 ce->skb = NULL;
974 } else { 901 pci_unmap_addr_set(ce, dma_addr, mapping);
975 pci_unmap_single(adapter->pdev, pci_unmap_addr(ce, dma_addr), 902 pci_unmap_len_set(ce, dma_len, frag->size);
976 pci_unmap_len(ce, dma_len), 903
977 PCI_DMA_FROMDEVICE); 904 e1->addr_lo = (u32)mapping;
978 skb = ce->skb; 905 e1->addr_hi = (u64)mapping >> 32;
979 if (!offload && sge->rx_pkt_pad) 906 e1->len_gen = V_CMD_LEN(frag->size) | V_CMD_GEN1(gen);
980 __skb_pull(skb, sge->rx_pkt_pad); 907 e1->flags = F_CMD_DATAVALID | V_CMD_EOP(nfrags == 0) |
908 V_CMD_GEN2(gen);
981 } 909 }
982 910
983 skb_put(skb, len); 911 ce->skb = skb;
912 wmb();
913 e->flags = flags;
914}
984 915
916/*
917 * Clean up completed Tx buffers.
918 */
919static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
920{
921 unsigned int reclaim = q->processed - q->cleaned;
985 922
986 if (unlikely(offload)) { 923 if (reclaim) {
987 { 924 free_cmdQ_buffers(sge, q, reclaim);
988 printk(KERN_ERR 925 q->cleaned += reclaim;
989 "%s: unexpected offloaded packet, cmd %u\n",
990 adapter->name, *skb->data);
991 dev_kfree_skb_any(skb);
992 }
993 } else {
994 struct cpl_rx_pkt *p = (struct cpl_rx_pkt *)skb->data;
995
996 skb_pull(skb, sizeof(*p));
997 skb->dev = adapter->port[p->iff].dev;
998 skb->dev->last_rx = jiffies;
999 skb->protocol = sge_eth_type_trans(skb, skb->dev);
1000 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
1001 skb->protocol == htons(ETH_P_IP) &&
1002 (skb->data[9] == IPPROTO_TCP ||
1003 skb->data[9] == IPPROTO_UDP))
1004 skb->ip_summed = CHECKSUM_UNNECESSARY;
1005 else
1006 skb->ip_summed = CHECKSUM_NONE;
1007 if (adapter->vlan_grp && p->vlan_valid)
1008 vlan_hwaccel_rx(skb, adapter->vlan_grp,
1009 ntohs(p->vlan));
1010 else
1011 netif_rx(skb);
1012 } 926 }
927}
1013 928
1014 if (++Q->cidx == Q->entries_n) 929#ifndef SET_ETHTOOL_OPS
1015 Q->cidx = 0; 930# define __netif_rx_complete(dev) netif_rx_complete(dev)
931#endif
1016 932
1017 if (unlikely(--Q->credits < Q->entries_n - SGE_FREEL_REFILL_THRESH)) 933/*
1018 refill_free_list(sge, Q); 934 * We cannot use the standard netif_rx_schedule_prep() because we have multiple
1019 return 1; 935 * ports plus the TOE all multiplexing onto a single response queue, therefore
936 * accepting new responses cannot depend on the state of any particular port.
937 * So define our own equivalent that omits the netif_running() test.
938 */
939static inline int napi_schedule_prep(struct net_device *dev)
940{
941 return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
1020} 942}
1021 943
1022 944
1023/* 945/**
1024 * Adaptive interrupt timer logic to keep the CPU utilization to 946 * sge_rx - process an ingress ethernet packet
1025 * manageable levels. Basically, as the Average Packet Size (APS) 947 * @sge: the sge structure
1026 * gets higher, the interrupt latency setting gets longer. Every 948 * @fl: the free list that contains the packet buffer
1027 * SGE_INTR_BUCKETSIZE (of 100B) causes a bump of 2usec to the 949 * @len: the packet length
1028 * base value of SGE_INTRTIMER0. At large values of payload the
1029 * latency hits the ceiling value of SGE_INTRTIMER1 stored at
1030 * index SGE_INTR_MAXBUCKETS-1 in sge->intrtimer[].
1031 * 950 *
1032 * sge->currIndex caches the last index to save unneeded PIOs. 951 * Process an ingress ethernet pakcet and deliver it to the stack.
1033 */ 952 */
1034static inline void update_intr_timer(struct sge *sge, unsigned int avg_payload) 953static int sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1035{ 954{
1036 unsigned int newIndex; 955 struct sk_buff *skb;
956 struct cpl_rx_pkt *p;
957 struct adapter *adapter = sge->adapter;
1037 958
1038 newIndex = avg_payload / SGE_INTR_BUCKETSIZE; 959 sge->stats.ethernet_pkts++;
1039 if (newIndex > SGE_INTR_MAXBUCKETS - 1) { 960 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad,
1040 newIndex = SGE_INTR_MAXBUCKETS - 1; 961 sge->rx_pkt_pad, 2, SGE_RX_COPY_THRES,
1041 } 962 SGE_RX_DROP_THRES);
1042 /* Save a PIO with this check....maybe */ 963 if (!skb) {
1043 if (newIndex != sge->currIndex) { 964 sge->port_stats[0].rx_drops++; /* charge only port 0 for now */
1044 t1_write_reg_4(sge->adapter, A_SG_INTRTIMER, 965 return 0;
1045 sge->intrtimer[newIndex]);
1046 sge->currIndex = newIndex;
1047 sge->adapter->params.sge.last_rx_coalesce_raw =
1048 sge->intrtimer[newIndex];
1049 } 966 }
967
968 p = (struct cpl_rx_pkt *)skb->data;
969 skb_pull(skb, sizeof(*p));
970 skb->dev = adapter->port[p->iff].dev;
971 skb->dev->last_rx = jiffies;
972 skb->protocol = eth_type_trans(skb, skb->dev);
973 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
974 skb->protocol == htons(ETH_P_IP) &&
975 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
976 sge->port_stats[p->iff].rx_cso_good++;
977 skb->ip_summed = CHECKSUM_UNNECESSARY;
978 } else
979 skb->ip_summed = CHECKSUM_NONE;
980
981 if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
982 sge->port_stats[p->iff].vlan_xtract++;
983 if (adapter->params.sge.polling)
984 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
985 ntohs(p->vlan));
986 else
987 vlan_hwaccel_rx(skb, adapter->vlan_grp,
988 ntohs(p->vlan));
989 } else if (adapter->params.sge.polling)
990 netif_receive_skb(skb);
991 else
992 netif_rx(skb);
993 return 0;
1050} 994}
1051 995
1052/* 996/*
1053 * Returns true if command queue q_num has enough available descriptors that 997 * Returns true if a command queue has enough available descriptors that
1054 * we can resume Tx operation after temporarily disabling its packet queue. 998 * we can resume Tx operation after temporarily disabling its packet queue.
1055 */ 999 */
1056static inline int enough_free_Tx_descs(struct sge *sge, int q_num) 1000static inline int enough_free_Tx_descs(const struct cmdQ *q)
1057{ 1001{
1058 return atomic_read(&sge->cmdQ[q_num].credits) > 1002 unsigned int r = q->processed - q->cleaned;
1059 (sge->cmdQ[q_num].entries_n >> 2); 1003
1004 return q->in_use - r < (q->size >> 1);
1060} 1005}
1061 1006
1062/* 1007/*
1063 * Main interrupt handler, optimized assuming that we took a 'DATA' 1008 * Called when sufficient space has become available in the SGE command queues
1064 * interrupt. 1009 * after the Tx packet schedulers have been suspended to restart the Tx path.
1065 *
1066 * 1. Clear the interrupt
1067 * 2. Loop while we find valid descriptors and process them; accumulate
1068 * information that can be processed after the loop
1069 * 3. Tell the SGE at which index we stopped processing descriptors
1070 * 4. Bookkeeping; free TX buffers, ring doorbell if there are any
1071 * outstanding TX buffers waiting, replenish RX buffers, potentially
1072 * reenable upper layers if they were turned off due to lack of TX
1073 * resources which are available again.
1074 * 5. If we took an interrupt, but no valid respQ descriptors was found we
1075 * let the slow_intr_handler run and do error handling.
1076 */ 1010 */
1077irqreturn_t t1_interrupt(int irq, void *cookie, struct pt_regs *regs) 1011static void restart_tx_queues(struct sge *sge)
1078{ 1012{
1079 struct net_device *netdev; 1013 struct adapter *adap = sge->adapter;
1080 struct adapter *adapter = cookie;
1081 struct sge *sge = adapter->sge;
1082 struct respQ *Q = &sge->respQ;
1083 unsigned int credits = Q->credits, flags = 0, ret = 0;
1084 unsigned int tot_rxpayload = 0, tot_txpayload = 0, n_rx = 0, n_tx = 0;
1085 unsigned int credits_pend[SGE_CMDQ_N] = { 0, 0 };
1086 1014
1087 struct respQ_e *e = &Q->entries[Q->cidx]; 1015 if (enough_free_Tx_descs(&sge->cmdQ[0])) {
1088 prefetch(e); 1016 int i;
1017
1018 for_each_port(adap, i) {
1019 struct net_device *nd = adap->port[i].dev;
1020
1021 if (test_and_clear_bit(nd->if_port,
1022 &sge->stopped_tx_queues) &&
1023 netif_running(nd)) {
1024 sge->stats.cmdQ_restarted[3]++;
1025 netif_wake_queue(nd);
1026 }
1027 }
1028 }
1029}
1030
1031/*
1032 * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1033 * information.
1034 */
1035static unsigned int update_tx_info(struct adapter *adapter,
1036 unsigned int flags,
1037 unsigned int pr0)
1038{
1039 struct sge *sge = adapter->sge;
1040 struct cmdQ *cmdq = &sge->cmdQ[0];
1089 1041
1090 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_SGE_DATA); 1042 cmdq->processed += pr0;
1091 1043
1044 if (flags & F_CMDQ0_ENABLE) {
1045 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1046
1047 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1048 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1049 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1050 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1051 }
1052 flags &= ~F_CMDQ0_ENABLE;
1053 }
1054
1055 if (unlikely(sge->stopped_tx_queues != 0))
1056 restart_tx_queues(sge);
1092 1057
1093 while (e->GenerationBit == Q->genbit) { 1058 return flags;
1094 if (--credits < SGE_RESPQ_REPLENISH_THRES) { 1059}
1095 u32 n = Q->entries_n - credits - 1;
1096 1060
1097 t1_write_reg_4(adapter, A_SG_RSPQUEUECREDIT, n); 1061/*
1098 credits += n; 1062 * Process SGE responses, up to the supplied budget. Returns the number of
1063 * responses processed. A negative budget is effectively unlimited.
1064 */
1065static int process_responses(struct adapter *adapter, int budget)
1066{
1067 struct sge *sge = adapter->sge;
1068 struct respQ *q = &sge->respQ;
1069 struct respQ_e *e = &q->entries[q->cidx];
1070 int budget_left = budget;
1071 unsigned int flags = 0;
1072 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1073
1074
1075 while (likely(budget_left && e->GenerationBit == q->genbit)) {
1076 flags |= e->Qsleeping;
1077
1078 cmdq_processed[0] += e->Cmdq0CreditReturn;
1079 cmdq_processed[1] += e->Cmdq1CreditReturn;
1080
1081 /* We batch updates to the TX side to avoid cacheline
1082 * ping-pong of TX state information on MP where the sender
1083 * might run on a different CPU than this function...
1084 */
1085 if (unlikely(flags & F_CMDQ0_ENABLE || cmdq_processed[0] > 64)) {
1086 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1087 cmdq_processed[0] = 0;
1088 }
1089 if (unlikely(cmdq_processed[1] > 16)) {
1090 sge->cmdQ[1].processed += cmdq_processed[1];
1091 cmdq_processed[1] = 0;
1099 } 1092 }
1100 if (likely(e->DataValid)) { 1093 if (likely(e->DataValid)) {
1101 if (!e->Sop || !e->Eop) 1094 struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1095
1096 if (unlikely(!e->Sop || !e->Eop))
1102 BUG(); 1097 BUG();
1103 t1_sge_rx(sge, &sge->freelQ[e->FreelistQid], 1098 if (unlikely(e->Offload))
1104 e->BufferLength, e->Offload); 1099 unexpected_offload(adapter, fl);
1105 tot_rxpayload += e->BufferLength; 1100 else
1106 ++n_rx; 1101 sge_rx(sge, fl, e->BufferLength);
1107 } 1102
1108 flags |= e->Qsleeping; 1103 /*
1109 credits_pend[0] += e->Cmdq0CreditReturn; 1104 * Note: this depends on each packet consuming a
1110 credits_pend[1] += e->Cmdq1CreditReturn; 1105 * single free-list buffer; cf. the BUG above.
1106 */
1107 if (++fl->cidx == fl->size)
1108 fl->cidx = 0;
1109 if (unlikely(--fl->credits <
1110 fl->size - SGE_FREEL_REFILL_THRESH))
1111 refill_free_list(sge, fl);
1112 } else
1113 sge->stats.pure_rsps++;
1111 1114
1112#ifdef CONFIG_SMP
1113 /*
1114 * If enough cmdQ0 buffers have finished DMAing free them so
1115 * anyone that may be waiting for their release can continue.
1116 * We do this only on MP systems to allow other CPUs to proceed
1117 * promptly. UP systems can wait for the free_cmdQ_buffers()
1118 * calls after this loop as the sole CPU is currently busy in
1119 * this loop.
1120 */
1121 if (unlikely(credits_pend[0] > SGE_FREEL_REFILL_THRESH)) {
1122 free_cmdQ_buffers(sge, &sge->cmdQ[0], credits_pend[0],
1123 &tot_txpayload);
1124 n_tx += credits_pend[0];
1125 credits_pend[0] = 0;
1126 }
1127#endif
1128 ret++;
1129 e++; 1115 e++;
1130 if (unlikely(++Q->cidx == Q->entries_n)) { 1116 if (unlikely(++q->cidx == q->size)) {
1131 Q->cidx = 0; 1117 q->cidx = 0;
1132 Q->genbit ^= 1; 1118 q->genbit ^= 1;
1133 e = Q->entries; 1119 e = q->entries;
1120 }
1121 prefetch(e);
1122
1123 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1124 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1125 q->credits = 0;
1134 } 1126 }
1127 --budget_left;
1135 } 1128 }
1136 1129
1137 Q->credits = credits; 1130 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1138 t1_write_reg_4(adapter, A_SG_SLEEPING, Q->cidx); 1131 sge->cmdQ[1].processed += cmdq_processed[1];
1139 1132
1140 if (credits_pend[0]) 1133 budget -= budget_left;
1141 free_cmdQ_buffers(sge, &sge->cmdQ[0], credits_pend[0], &tot_txpayload); 1134 return budget;
1142 if (credits_pend[1]) 1135}
1143 free_cmdQ_buffers(sge, &sge->cmdQ[1], credits_pend[1], &tot_txpayload);
1144 1136
1145 /* Do any coalescing and interrupt latency timer adjustments */ 1137/*
1146 if (adapter->params.sge.coalesce_enable) { 1138 * A simpler version of process_responses() that handles only pure (i.e.,
1147 unsigned int avg_txpayload = 0, avg_rxpayload = 0; 1139 * non data-carrying) responses. Such respones are too light-weight to justify
1140 * calling a softirq when using NAPI, so we handle them specially in hard
1141 * interrupt context. The function is called with a pointer to a response,
1142 * which the caller must ensure is a valid pure response. Returns 1 if it
1143 * encounters a valid data-carrying response, 0 otherwise.
1144 */
1145static int process_pure_responses(struct adapter *adapter, struct respQ_e *e)
1146{
1147 struct sge *sge = adapter->sge;
1148 struct respQ *q = &sge->respQ;
1149 unsigned int flags = 0;
1150 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1148 1151
1149 n_tx += credits_pend[0] + credits_pend[1]; 1152 do {
1153 flags |= e->Qsleeping;
1150 1154
1151 /* 1155 cmdq_processed[0] += e->Cmdq0CreditReturn;
1152 * Choose larger avg. payload size to increase 1156 cmdq_processed[1] += e->Cmdq1CreditReturn;
1153 * throughput and reduce [CPU util., intr/s.] 1157
1154 * 1158 e++;
1155 * Throughput behavior favored in mixed-mode. 1159 if (unlikely(++q->cidx == q->size)) {
1156 */ 1160 q->cidx = 0;
1157 if (n_tx) 1161 q->genbit ^= 1;
1158 avg_txpayload = tot_txpayload/n_tx; 1162 e = q->entries;
1159 if (n_rx)
1160 avg_rxpayload = tot_rxpayload/n_rx;
1161
1162 if (n_tx && avg_txpayload > avg_rxpayload){
1163 update_intr_timer(sge, avg_txpayload);
1164 } else if (n_rx) {
1165 update_intr_timer(sge, avg_rxpayload);
1166 } 1163 }
1167 } 1164 prefetch(e);
1168
1169 if (flags & F_CMDQ0_ENABLE) {
1170 struct cmdQ *cmdQ = &sge->cmdQ[0];
1171 1165
1172 atomic_set(&cmdQ->asleep, 1); 1166 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1173 if (atomic_read(&cmdQ->pio_pidx) != cmdQ->pidx) { 1167 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1174 doorbell_pio(sge, F_CMDQ0_ENABLE); 1168 q->credits = 0;
1175 atomic_set(&cmdQ->pio_pidx, cmdQ->pidx);
1176 } 1169 }
1177 } 1170 sge->stats.pure_rsps++;
1178 if (unlikely(flags & (F_FL0_ENABLE | F_FL1_ENABLE))) 1171 } while (e->GenerationBit == q->genbit && !e->DataValid);
1179 freelQs_empty(sge);
1180 1172
1181 netdev = adapter->port[0].dev; 1173 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1182 if (unlikely(netif_queue_stopped(netdev) && netif_carrier_ok(netdev) && 1174 sge->cmdQ[1].processed += cmdq_processed[1];
1183 enough_free_Tx_descs(sge, 0) &&
1184 enough_free_Tx_descs(sge, 1))) {
1185 netif_wake_queue(netdev);
1186 }
1187 if (unlikely(!ret))
1188 ret = t1_slow_intr_handler(adapter);
1189 1175
1190 return IRQ_RETVAL(ret != 0); 1176 return e->GenerationBit == q->genbit;
1191} 1177}
1192 1178
1193/* 1179/*
1194 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it. 1180 * Handler for new data events when using NAPI. This does not need any locking
1195 * 1181 * or protection from interrupts as data interrupts are off at this point and
1196 * The code figures out how many entries the sk_buff will require in the 1182 * other adapter interrupts do not interfere.
1197 * cmdQ and updates the cmdQ data structure with the state once the enqueue
1198 * has complete. Then, it doesn't access the global structure anymore, but
1199 * uses the corresponding fields on the stack. In conjuction with a spinlock
1200 * around that code, we can make the function reentrant without holding the
1201 * lock when we actually enqueue (which might be expensive, especially on
1202 * architectures with IO MMUs).
1203 */ 1183 */
1204static unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter, 1184static int t1_poll(struct net_device *dev, int *budget)
1205 unsigned int qid)
1206{ 1185{
1207 struct sge *sge = adapter->sge; 1186 struct adapter *adapter = dev->priv;
1208 struct cmdQ *Q = &sge->cmdQ[qid]; 1187 int effective_budget = min(*budget, dev->quota);
1209 struct cmdQ_e *e; 1188
1210 struct cmdQ_ce *ce; 1189 int work_done = process_responses(adapter, effective_budget);
1211 dma_addr_t mapping; 1190 *budget -= work_done;
1212 unsigned int credits, pidx, genbit; 1191 dev->quota -= work_done;
1213 1192
1214 unsigned int count = 1 + skb_shinfo(skb)->nr_frags; 1193 if (work_done >= effective_budget)
1194 return 1;
1195
1196 __netif_rx_complete(dev);
1215 1197
1216 /* 1198 /*
1217 * Coming from the timer 1199 * Because we don't atomically flush the following write it is
1200 * possible that in very rare cases it can reach the device in a way
1201 * that races with a new response being written plus an error interrupt
1202 * causing the NAPI interrupt handler below to return unhandled status
1203 * to the OS. To protect against this would require flushing the write
1204 * and doing both the write and the flush with interrupts off. Way too
1205 * expensive and unjustifiable given the rarity of the race.
1218 */ 1206 */
1219 if ((skb == sge->pskb)) { 1207 writel(adapter->sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1220 /* 1208 return 0;
1221 * Quit if any cmdQ activities 1209}
1222 */
1223 if (!spin_trylock(&Q->Qlock))
1224 return 0;
1225 if (atomic_read(&Q->credits) != Q->entries_n) {
1226 spin_unlock(&Q->Qlock);
1227 return 0;
1228 }
1229 }
1230 else
1231 spin_lock(&Q->Qlock);
1232
1233 genbit = Q->genbit;
1234 pidx = Q->pidx;
1235 credits = atomic_read(&Q->credits);
1236
1237 credits -= count;
1238 atomic_sub(count, &Q->credits);
1239 Q->pidx += count;
1240 if (Q->pidx >= Q->entries_n) {
1241 Q->pidx -= Q->entries_n;
1242 Q->genbit ^= 1;
1243 }
1244 1210
1245 if (unlikely(credits < (MAX_SKB_FRAGS + 1))) { 1211/*
1246 sge->intr_cnt.cmdQ_full[qid]++; 1212 * Returns true if the device is already scheduled for polling.
1247 netif_stop_queue(adapter->port[0].dev); 1213 */
1248 } 1214static inline int napi_is_scheduled(struct net_device *dev)
1249 spin_unlock(&Q->Qlock); 1215{
1216 return test_bit(__LINK_STATE_RX_SCHED, &dev->state);
1217}
1250 1218
1251 mapping = pci_map_single(adapter->pdev, skb->data, 1219/*
1252 skb->len - skb->data_len, PCI_DMA_TODEVICE); 1220 * NAPI version of the main interrupt handler.
1253 ce = &Q->centries[pidx]; 1221 */
1254 ce->skb = NULL; 1222static irqreturn_t t1_interrupt_napi(int irq, void *data, struct pt_regs *regs)
1255 pci_unmap_addr_set(ce, dma_addr, mapping); 1223{
1256 pci_unmap_len_set(ce, dma_len, skb->len - skb->data_len); 1224 int handled;
1257 ce->single = 1; 1225 struct adapter *adapter = data;
1226 struct sge *sge = adapter->sge;
1227 struct respQ *q = &adapter->sge->respQ;
1258 1228
1259 e = &Q->entries[pidx]; 1229 /*
1260 e->Sop = 1; 1230 * Clear the SGE_DATA interrupt first thing. Normally the NAPI
1261 e->DataValid = 1; 1231 * handler has control of the response queue and the interrupt handler
1262 e->BufferLength = skb->len - skb->data_len; 1232 * can look at the queue reliably only once it knows NAPI is off.
1263 e->AddrHigh = (u64)mapping >> 32; 1233 * We can't wait that long to clear the SGE_DATA interrupt because we
1264 e->AddrLow = (u32)mapping; 1234 * could race with t1_poll rearming the SGE interrupt, so we need to
1235 * clear the interrupt speculatively and really early on.
1236 */
1237 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1238
1239 spin_lock(&adapter->async_lock);
1240 if (!napi_is_scheduled(sge->netdev)) {
1241 struct respQ_e *e = &q->entries[q->cidx];
1242
1243 if (e->GenerationBit == q->genbit) {
1244 if (e->DataValid ||
1245 process_pure_responses(adapter, e)) {
1246 if (likely(napi_schedule_prep(sge->netdev)))
1247 __netif_rx_schedule(sge->netdev);
1248 else
1249 printk(KERN_CRIT
1250 "NAPI schedule failure!\n");
1251 } else
1252 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1253 handled = 1;
1254 goto unlock;
1255 } else
1256 writel(q->cidx, adapter->regs + A_SG_SLEEPING);
1257 } else
1258 if (readl(adapter->regs + A_PL_CAUSE) & F_PL_INTR_SGE_DATA)
1259 printk(KERN_ERR "data interrupt while NAPI running\n");
1260
1261 handled = t1_slow_intr_handler(adapter);
1262 if (!handled)
1263 sge->stats.unhandled_irqs++;
1264 unlock:
1265 spin_unlock(&adapter->async_lock);
1266 return IRQ_RETVAL(handled != 0);
1267}
1265 1268
1266 if (--count > 0) { 1269/*
1267 unsigned int i; 1270 * Main interrupt handler, optimized assuming that we took a 'DATA'
1271 * interrupt.
1272 *
1273 * 1. Clear the interrupt
1274 * 2. Loop while we find valid descriptors and process them; accumulate
1275 * information that can be processed after the loop
1276 * 3. Tell the SGE at which index we stopped processing descriptors
1277 * 4. Bookkeeping; free TX buffers, ring doorbell if there are any
1278 * outstanding TX buffers waiting, replenish RX buffers, potentially
1279 * reenable upper layers if they were turned off due to lack of TX
1280 * resources which are available again.
1281 * 5. If we took an interrupt, but no valid respQ descriptors was found we
1282 * let the slow_intr_handler run and do error handling.
1283 */
1284static irqreturn_t t1_interrupt(int irq, void *cookie, struct pt_regs *regs)
1285{
1286 int work_done;
1287 struct respQ_e *e;
1288 struct adapter *adapter = cookie;
1289 struct respQ *Q = &adapter->sge->respQ;
1268 1290
1269 e->Eop = 0; 1291 spin_lock(&adapter->async_lock);
1270 wmb(); 1292 e = &Q->entries[Q->cidx];
1271 e->GenerationBit = e->GenerationBit2 = genbit; 1293 prefetch(e);
1272 1294
1273 for (i = 0; i < count; i++) { 1295 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1274 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1275 1296
1276 ce++; e++; 1297 if (likely(e->GenerationBit == Q->genbit))
1277 if (++pidx == Q->entries_n) { 1298 work_done = process_responses(adapter, -1);
1278 pidx = 0; 1299 else
1279 genbit ^= 1; 1300 work_done = t1_slow_intr_handler(adapter);
1280 ce = Q->centries;
1281 e = Q->entries;
1282 }
1283 1301
1284 mapping = pci_map_page(adapter->pdev, frag->page, 1302 /*
1285 frag->page_offset, 1303 * The unconditional clearing of the PL_CAUSE above may have raced
1286 frag->size, 1304 * with DMA completion and the corresponding generation of a response
1287 PCI_DMA_TODEVICE); 1305 * to cause us to miss the resulting data interrupt. The next write
1288 ce->skb = NULL; 1306 * is also unconditional to recover the missed interrupt and render
1289 pci_unmap_addr_set(ce, dma_addr, mapping); 1307 * this race harmless.
1290 pci_unmap_len_set(ce, dma_len, frag->size); 1308 */
1291 ce->single = 0; 1309 writel(Q->cidx, adapter->regs + A_SG_SLEEPING);
1292 1310
1293 e->Sop = 0; 1311 if (!work_done)
1294 e->DataValid = 1; 1312 adapter->sge->stats.unhandled_irqs++;
1295 e->BufferLength = frag->size; 1313 spin_unlock(&adapter->async_lock);
1296 e->AddrHigh = (u64)mapping >> 32; 1314 return IRQ_RETVAL(work_done != 0);
1297 e->AddrLow = (u32)mapping; 1315}
1298 1316
1299 if (i < count - 1) { 1317intr_handler_t t1_select_intr_handler(adapter_t *adapter)
1300 e->Eop = 0; 1318{
1301 wmb(); 1319 return adapter->params.sge.polling ? t1_interrupt_napi : t1_interrupt;
1302 e->GenerationBit = e->GenerationBit2 = genbit; 1320}
1303 } 1321
1322/*
1323 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1324 *
1325 * The code figures out how many entries the sk_buff will require in the
1326 * cmdQ and updates the cmdQ data structure with the state once the enqueue
1327 * has complete. Then, it doesn't access the global structure anymore, but
1328 * uses the corresponding fields on the stack. In conjuction with a spinlock
1329 * around that code, we can make the function reentrant without holding the
1330 * lock when we actually enqueue (which might be expensive, especially on
1331 * architectures with IO MMUs).
1332 *
1333 * This runs with softirqs disabled.
1334 */
1335unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1336 unsigned int qid, struct net_device *dev)
1337{
1338 struct sge *sge = adapter->sge;
1339 struct cmdQ *q = &sge->cmdQ[qid];
1340 unsigned int credits, pidx, genbit, count;
1341
1342 spin_lock(&q->lock);
1343 reclaim_completed_tx(sge, q);
1344
1345 pidx = q->pidx;
1346 credits = q->size - q->in_use;
1347 count = 1 + skb_shinfo(skb)->nr_frags;
1348
1349 { /* Ethernet packet */
1350 if (unlikely(credits < count)) {
1351 netif_stop_queue(dev);
1352 set_bit(dev->if_port, &sge->stopped_tx_queues);
1353 sge->stats.cmdQ_full[3]++;
1354 spin_unlock(&q->lock);
1355 CH_ERR("%s: Tx ring full while queue awake!\n",
1356 adapter->name);
1357 return 1;
1304 } 1358 }
1359 if (unlikely(credits - count < q->stop_thres)) {
1360 sge->stats.cmdQ_full[3]++;
1361 netif_stop_queue(dev);
1362 set_bit(dev->if_port, &sge->stopped_tx_queues);
1363 }
1364 }
1365 q->in_use += count;
1366 genbit = q->genbit;
1367 q->pidx += count;
1368 if (q->pidx >= q->size) {
1369 q->pidx -= q->size;
1370 q->genbit ^= 1;
1305 } 1371 }
1372 spin_unlock(&q->lock);
1306 1373
1307 if (skb != sge->pskb) 1374 write_tx_descs(adapter, skb, pidx, genbit, q);
1308 ce->skb = skb;
1309 e->Eop = 1;
1310 wmb();
1311 e->GenerationBit = e->GenerationBit2 = genbit;
1312 1375
1313 /* 1376 /*
1314 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring 1377 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring
@@ -1317,12 +1380,14 @@ static unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1317 * then the interrupt handler will detect the outstanding TX packet 1380 * then the interrupt handler will detect the outstanding TX packet
1318 * and ring the doorbell for us. 1381 * and ring the doorbell for us.
1319 */ 1382 */
1320 if (qid) { 1383 if (qid)
1321 doorbell_pio(sge, F_CMDQ1_ENABLE); 1384 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1322 } else if (atomic_read(&Q->asleep)) { 1385 else {
1323 atomic_set(&Q->asleep, 0); 1386 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1324 doorbell_pio(sge, F_CMDQ0_ENABLE); 1387 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1325 atomic_set(&Q->pio_pidx, Q->pidx); 1388 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1389 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1390 }
1326 } 1391 }
1327 return 0; 1392 return 0;
1328} 1393}
@@ -1330,37 +1395,35 @@ static unsigned int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1330#define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14)) 1395#define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1331 1396
1332/* 1397/*
1398 * eth_hdr_len - return the length of an Ethernet header
1399 * @data: pointer to the start of the Ethernet header
1400 *
1401 * Returns the length of an Ethernet header, including optional VLAN tag.
1402 */
1403static inline int eth_hdr_len(const void *data)
1404{
1405 const struct ethhdr *e = data;
1406
1407 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1408}
1409
1410/*
1333 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx. 1411 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1334 */ 1412 */
1335int t1_start_xmit(struct sk_buff *skb, struct net_device *dev) 1413int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1336{ 1414{
1337 struct adapter *adapter = dev->priv; 1415 struct adapter *adapter = dev->priv;
1416 struct sge_port_stats *st = &adapter->sge->port_stats[dev->if_port];
1417 struct sge *sge = adapter->sge;
1338 struct cpl_tx_pkt *cpl; 1418 struct cpl_tx_pkt *cpl;
1339 struct ethhdr *eth;
1340 size_t max_len;
1341
1342 /*
1343 * We are using a non-standard hard_header_len and some kernel
1344 * components, such as pktgen, do not handle it right. Complain
1345 * when this happens but try to fix things up.
1346 */
1347 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1348 struct sk_buff *orig_skb = skb;
1349
1350 if (net_ratelimit())
1351 printk(KERN_ERR
1352 "%s: Tx packet has inadequate headroom\n",
1353 dev->name);
1354 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1355 dev_kfree_skb_any(orig_skb);
1356 if (!skb)
1357 return -ENOMEM;
1358 }
1359 1419
1420#ifdef NETIF_F_TSO
1360 if (skb_shinfo(skb)->tso_size) { 1421 if (skb_shinfo(skb)->tso_size) {
1361 int eth_type; 1422 int eth_type;
1362 struct cpl_tx_pkt_lso *hdr; 1423 struct cpl_tx_pkt_lso *hdr;
1363 1424
1425 st->tso++;
1426
1364 eth_type = skb->nh.raw - skb->data == ETH_HLEN ? 1427 eth_type = skb->nh.raw - skb->data == ETH_HLEN ?
1365 CPL_ETH_II : CPL_ETH_II_VLAN; 1428 CPL_ETH_II : CPL_ETH_II_VLAN;
1366 1429
@@ -1373,40 +1436,72 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1373 skb_shinfo(skb)->tso_size)); 1436 skb_shinfo(skb)->tso_size));
1374 hdr->len = htonl(skb->len - sizeof(*hdr)); 1437 hdr->len = htonl(skb->len - sizeof(*hdr));
1375 cpl = (struct cpl_tx_pkt *)hdr; 1438 cpl = (struct cpl_tx_pkt *)hdr;
1439 sge->stats.tx_lso_pkts++;
1376 } else 1440 } else
1441#endif
1377 { 1442 {
1378 /* 1443 /*
1379 * An Ethernet packet must have at least space for 1444 * Packets shorter than ETH_HLEN can break the MAC, drop them
1380 * the DIX Ethernet header and be no greater than 1445 * early. Also, we may get oversized packets because some
1381 * the device set MTU. Otherwise trash the packet. 1446 * parts of the kernel don't handle our unusual hard_header_len
1447 * right, drop those too.
1382 */ 1448 */
1383 if (skb->len < ETH_HLEN) 1449 if (unlikely(skb->len < ETH_HLEN ||
1384 goto t1_start_xmit_fail2; 1450 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1385 eth = (struct ethhdr *)skb->data; 1451 dev_kfree_skb_any(skb);
1386 if (eth->h_proto == htons(ETH_P_8021Q)) 1452 return NET_XMIT_SUCCESS;
1387 max_len = dev->mtu + VLAN_ETH_HLEN; 1453 }
1388 else 1454
1389 max_len = dev->mtu + ETH_HLEN; 1455 /*
1390 if (skb->len > max_len) 1456 * We are using a non-standard hard_header_len and some kernel
1391 goto t1_start_xmit_fail2; 1457 * components, such as pktgen, do not handle it right.
1458 * Complain when this happens but try to fix things up.
1459 */
1460 if (unlikely(skb_headroom(skb) <
1461 dev->hard_header_len - ETH_HLEN)) {
1462 struct sk_buff *orig_skb = skb;
1463
1464 if (net_ratelimit())
1465 printk(KERN_ERR "%s: inadequate headroom in "
1466 "Tx packet\n", dev->name);
1467 skb = skb_realloc_headroom(skb, sizeof(*cpl));
1468 dev_kfree_skb_any(orig_skb);
1469 if (!skb)
1470 return -ENOMEM;
1471 }
1392 1472
1393 if (!(adapter->flags & UDP_CSUM_CAPABLE) && 1473 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1394 skb->ip_summed == CHECKSUM_HW && 1474 skb->ip_summed == CHECKSUM_HW &&
1395 skb->nh.iph->protocol == IPPROTO_UDP && 1475 skb->nh.iph->protocol == IPPROTO_UDP)
1396 skb_checksum_help(skb, 0)) 1476 if (unlikely(skb_checksum_help(skb, 0))) {
1397 goto t1_start_xmit_fail3; 1477 dev_kfree_skb_any(skb);
1398 1478 return -ENOMEM;
1479 }
1399 1480
1400 if (!adapter->sge->pskb) { 1481 /* Hmmm, assuming to catch the gratious arp... and we'll use
1482 * it to flush out stuck espi packets...
1483 */
1484 if (unlikely(!adapter->sge->espibug_skb)) {
1401 if (skb->protocol == htons(ETH_P_ARP) && 1485 if (skb->protocol == htons(ETH_P_ARP) &&
1402 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) 1486 skb->nh.arph->ar_op == htons(ARPOP_REQUEST)) {
1403 adapter->sge->pskb = skb; 1487 adapter->sge->espibug_skb = skb;
1488 /* We want to re-use this skb later. We
1489 * simply bump the reference count and it
1490 * will not be freed...
1491 */
1492 skb = skb_get(skb);
1493 }
1404 } 1494 }
1405 cpl = (struct cpl_tx_pkt *)skb_push(skb, sizeof(*cpl)); 1495
1496 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1406 cpl->opcode = CPL_TX_PKT; 1497 cpl->opcode = CPL_TX_PKT;
1407 cpl->ip_csum_dis = 1; /* SW calculates IP csum */ 1498 cpl->ip_csum_dis = 1; /* SW calculates IP csum */
1408 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_HW ? 0 : 1; 1499 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_HW ? 0 : 1;
1409 /* the length field isn't used so don't bother setting it */ 1500 /* the length field isn't used so don't bother setting it */
1501
1502 st->tx_cso += (skb->ip_summed == CHECKSUM_HW);
1503 sge->stats.tx_do_cksum += (skb->ip_summed == CHECKSUM_HW);
1504 sge->stats.tx_reg_pkts++;
1410 } 1505 }
1411 cpl->iff = dev->if_port; 1506 cpl->iff = dev->if_port;
1412 1507
@@ -1414,38 +1509,176 @@ int t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1414 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) { 1509 if (adapter->vlan_grp && vlan_tx_tag_present(skb)) {
1415 cpl->vlan_valid = 1; 1510 cpl->vlan_valid = 1;
1416 cpl->vlan = htons(vlan_tx_tag_get(skb)); 1511 cpl->vlan = htons(vlan_tx_tag_get(skb));
1512 st->vlan_insert++;
1417 } else 1513 } else
1418#endif 1514#endif
1419 cpl->vlan_valid = 0; 1515 cpl->vlan_valid = 0;
1420 1516
1421 dev->trans_start = jiffies; 1517 dev->trans_start = jiffies;
1422 return t1_sge_tx(skb, adapter, 0); 1518 return t1_sge_tx(skb, adapter, 0, dev);
1519}
1423 1520
1424t1_start_xmit_fail3: 1521/*
1425 printk(KERN_INFO "%s: Unable to complete checksum\n", dev->name); 1522 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled.
1426 goto t1_start_xmit_fail1; 1523 */
1524static void sge_tx_reclaim_cb(unsigned long data)
1525{
1526 int i;
1527 struct sge *sge = (struct sge *)data;
1528
1529 for (i = 0; i < SGE_CMDQ_N; ++i) {
1530 struct cmdQ *q = &sge->cmdQ[i];
1531
1532 if (!spin_trylock(&q->lock))
1533 continue;
1427 1534
1428t1_start_xmit_fail2: 1535 reclaim_completed_tx(sge, q);
1429 printk(KERN_INFO "%s: Invalid packet length %d, dropping\n", 1536 if (i == 0 && q->in_use) /* flush pending credits */
1430 dev->name, skb->len); 1537 writel(F_CMDQ0_ENABLE,
1538 sge->adapter->regs + A_SG_DOORBELL);
1431 1539
1432t1_start_xmit_fail1: 1540 spin_unlock(&q->lock);
1433 dev_kfree_skb_any(skb); 1541 }
1542 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1543}
1544
1545/*
1546 * Propagate changes of the SGE coalescing parameters to the HW.
1547 */
1548int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1549{
1550 sge->netdev->poll = t1_poll;
1551 sge->fixed_intrtimer = p->rx_coalesce_usecs *
1552 core_ticks_per_usec(sge->adapter);
1553 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1434 return 0; 1554 return 0;
1435} 1555}
1436 1556
1437void t1_sge_set_ptimeout(adapter_t *adapter, u32 val) 1557/*
1558 * Allocates both RX and TX resources and configures the SGE. However,
1559 * the hardware is not enabled yet.
1560 */
1561int t1_sge_configure(struct sge *sge, struct sge_params *p)
1438{ 1562{
1439 struct sge *sge = adapter->sge; 1563 if (alloc_rx_resources(sge, p))
1564 return -ENOMEM;
1565 if (alloc_tx_resources(sge, p)) {
1566 free_rx_resources(sge);
1567 return -ENOMEM;
1568 }
1569 configure_sge(sge, p);
1570
1571 /*
1572 * Now that we have sized the free lists calculate the payload
1573 * capacity of the large buffers. Other parts of the driver use
1574 * this to set the max offload coalescing size so that RX packets
1575 * do not overflow our large buffers.
1576 */
1577 p->large_buf_capacity = jumbo_payload_capacity(sge);
1578 return 0;
1579}
1440 1580
1441 if (is_T2(adapter)) 1581/*
1442 sge->ptimeout = max((u32)((HZ * val) / 1000), (u32)1); 1582 * Disables the DMA engine.
1583 */
1584void t1_sge_stop(struct sge *sge)
1585{
1586 writel(0, sge->adapter->regs + A_SG_CONTROL);
1587 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1588 if (is_T2(sge->adapter))
1589 del_timer_sync(&sge->espibug_timer);
1590 del_timer_sync(&sge->tx_reclaim_timer);
1443} 1591}
1444 1592
1445u32 t1_sge_get_ptimeout(adapter_t *adapter) 1593/*
1594 * Enables the DMA engine.
1595 */
1596void t1_sge_start(struct sge *sge)
1446{ 1597{
1598 refill_free_list(sge, &sge->freelQ[0]);
1599 refill_free_list(sge, &sge->freelQ[1]);
1600
1601 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1602 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1603 (void) readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1604
1605 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1606
1607 if (is_T2(sge->adapter))
1608 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1609}
1610
1611/*
1612 * Callback for the T2 ESPI 'stuck packet feature' workaorund
1613 */
1614static void espibug_workaround(void *data)
1615{
1616 struct adapter *adapter = (struct adapter *)data;
1447 struct sge *sge = adapter->sge; 1617 struct sge *sge = adapter->sge;
1448 1618
1449 return (is_T2(adapter) ? ((sge->ptimeout * 1000) / HZ) : 0); 1619 if (netif_running(adapter->port[0].dev)) {
1620 struct sk_buff *skb = sge->espibug_skb;
1621
1622 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
1623
1624 if ((seop & 0xfff0fff) == 0xfff && skb) {
1625 if (!skb->cb[0]) {
1626 u8 ch_mac_addr[ETH_ALEN] =
1627 {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
1628 memcpy(skb->data + sizeof(struct cpl_tx_pkt),
1629 ch_mac_addr, ETH_ALEN);
1630 memcpy(skb->data + skb->len - 10, ch_mac_addr,
1631 ETH_ALEN);
1632 skb->cb[0] = 0xff;
1633 }
1634
1635 /* bump the reference count to avoid freeing of the
1636 * skb once the DMA has completed.
1637 */
1638 skb = skb_get(skb);
1639 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
1640 }
1641 }
1642 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1450} 1643}
1451 1644
1645/*
1646 * Creates a t1_sge structure and returns suggested resource parameters.
1647 */
1648struct sge * __devinit t1_sge_create(struct adapter *adapter,
1649 struct sge_params *p)
1650{
1651 struct sge *sge = kmalloc(sizeof(*sge), GFP_KERNEL);
1652
1653 if (!sge)
1654 return NULL;
1655 memset(sge, 0, sizeof(*sge));
1656
1657 sge->adapter = adapter;
1658 sge->netdev = adapter->port[0].dev;
1659 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
1660 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
1661
1662 init_timer(&sge->tx_reclaim_timer);
1663 sge->tx_reclaim_timer.data = (unsigned long)sge;
1664 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
1665
1666 if (is_T2(sge->adapter)) {
1667 init_timer(&sge->espibug_timer);
1668 sge->espibug_timer.function = (void *)&espibug_workaround;
1669 sge->espibug_timer.data = (unsigned long)sge->adapter;
1670 sge->espibug_timeout = 1;
1671 }
1672
1673
1674 p->cmdQ_size[0] = SGE_CMDQ0_E_N;
1675 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
1676 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
1677 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
1678 p->rx_coalesce_usecs = 50;
1679 p->coalesce_enable = 0;
1680 p->sample_interval_usecs = 0;
1681 p->polling = 0;
1682
1683 return sge;
1684}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 19:45:54 -0500