diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2006-12-01 19:36:16 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-12-02 00:24:49 -0500 |
commit | f1d3d38af75789f1b82969b83b69cab540609789 (patch) | |
tree | 47d31e8a55fb65cf33797197b92a332630cfc3ef /drivers/net/chelsio/regs.h | |
parent | 415294ecbb32ddbd0a7a2b7bae0b60fedfa09cc4 (diff) |
[PATCH] chelsio: add support for other 10G boards
Add support for other versions of the 10G Chelsio boards.
This is basically a port of the vendor driver with the
TOE features removed.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/chelsio/regs.h')
-rw-r--r-- | drivers/net/chelsio/regs.h | 1718 |
1 files changed, 1709 insertions, 9 deletions
diff --git a/drivers/net/chelsio/regs.h b/drivers/net/chelsio/regs.h index b90e11f40d1f..c80bf4d6d0a6 100644 --- a/drivers/net/chelsio/regs.h +++ b/drivers/net/chelsio/regs.h | |||
@@ -71,6 +71,10 @@ | |||
71 | #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) | 71 | #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) |
72 | #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) | 72 | #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) |
73 | 73 | ||
74 | #define S_DISABLE_CMDQ0_GTS 8 | ||
75 | #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) | ||
76 | #define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U) | ||
77 | |||
74 | #define S_DISABLE_CMDQ1_GTS 9 | 78 | #define S_DISABLE_CMDQ1_GTS 9 |
75 | #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) | 79 | #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) |
76 | #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) | 80 | #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) |
@@ -87,12 +91,18 @@ | |||
87 | #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) | 91 | #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) |
88 | #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) | 92 | #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) |
89 | 93 | ||
94 | #define S_FL_SELECTION_CRITERIA 13 | ||
95 | #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA) | ||
96 | #define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U) | ||
97 | |||
90 | #define S_ISCSI_COALESCE 14 | 98 | #define S_ISCSI_COALESCE 14 |
91 | #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) | 99 | #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) |
92 | #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) | 100 | #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) |
93 | 101 | ||
94 | #define S_RX_PKT_OFFSET 15 | 102 | #define S_RX_PKT_OFFSET 15 |
103 | #define M_RX_PKT_OFFSET 0x7 | ||
95 | #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) | 104 | #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) |
105 | #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET) | ||
96 | 106 | ||
97 | #define S_VLAN_XTRACT 18 | 107 | #define S_VLAN_XTRACT 18 |
98 | #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) | 108 | #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) |
@@ -108,16 +118,114 @@ | |||
108 | #define A_SG_FL1BASELWR 0x20 | 118 | #define A_SG_FL1BASELWR 0x20 |
109 | #define A_SG_FL1BASEUPR 0x24 | 119 | #define A_SG_FL1BASEUPR 0x24 |
110 | #define A_SG_CMD0SIZE 0x28 | 120 | #define A_SG_CMD0SIZE 0x28 |
121 | |||
122 | #define S_CMDQ0_SIZE 0 | ||
123 | #define M_CMDQ0_SIZE 0x1ffff | ||
124 | #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE) | ||
125 | #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE) | ||
126 | |||
111 | #define A_SG_FL0SIZE 0x2c | 127 | #define A_SG_FL0SIZE 0x2c |
128 | |||
129 | #define S_FL0_SIZE 0 | ||
130 | #define M_FL0_SIZE 0x1ffff | ||
131 | #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE) | ||
132 | #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE) | ||
133 | |||
112 | #define A_SG_RSPSIZE 0x30 | 134 | #define A_SG_RSPSIZE 0x30 |
135 | |||
136 | #define S_RESPQ_SIZE 0 | ||
137 | #define M_RESPQ_SIZE 0x1ffff | ||
138 | #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE) | ||
139 | #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE) | ||
140 | |||
113 | #define A_SG_RSPBASELWR 0x34 | 141 | #define A_SG_RSPBASELWR 0x34 |
114 | #define A_SG_RSPBASEUPR 0x38 | 142 | #define A_SG_RSPBASEUPR 0x38 |
115 | #define A_SG_FLTHRESHOLD 0x3c | 143 | #define A_SG_FLTHRESHOLD 0x3c |
144 | |||
145 | #define S_FL_THRESHOLD 0 | ||
146 | #define M_FL_THRESHOLD 0xffff | ||
147 | #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD) | ||
148 | #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD) | ||
149 | |||
116 | #define A_SG_RSPQUEUECREDIT 0x40 | 150 | #define A_SG_RSPQUEUECREDIT 0x40 |
151 | |||
152 | #define S_RESPQ_CREDIT 0 | ||
153 | #define M_RESPQ_CREDIT 0x1ffff | ||
154 | #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT) | ||
155 | #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT) | ||
156 | |||
117 | #define A_SG_SLEEPING 0x48 | 157 | #define A_SG_SLEEPING 0x48 |
158 | |||
159 | #define S_SLEEPING 0 | ||
160 | #define M_SLEEPING 0xffff | ||
161 | #define V_SLEEPING(x) ((x) << S_SLEEPING) | ||
162 | #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING) | ||
163 | |||
118 | #define A_SG_INTRTIMER 0x4c | 164 | #define A_SG_INTRTIMER 0x4c |
165 | |||
166 | #define S_INTERRUPT_TIMER_COUNT 0 | ||
167 | #define M_INTERRUPT_TIMER_COUNT 0xffffff | ||
168 | #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT) | ||
169 | #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT) | ||
170 | |||
171 | #define A_SG_CMD0PTR 0x50 | ||
172 | |||
173 | #define S_CMDQ0_POINTER 0 | ||
174 | #define M_CMDQ0_POINTER 0xffff | ||
175 | #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER) | ||
176 | #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER) | ||
177 | |||
178 | #define S_CURRENT_GENERATION_BIT 16 | ||
179 | #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT) | ||
180 | #define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U) | ||
181 | |||
182 | #define A_SG_CMD1PTR 0x54 | ||
183 | |||
184 | #define S_CMDQ1_POINTER 0 | ||
185 | #define M_CMDQ1_POINTER 0xffff | ||
186 | #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER) | ||
187 | #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER) | ||
188 | |||
189 | #define A_SG_FL0PTR 0x58 | ||
190 | |||
191 | #define S_FL0_POINTER 0 | ||
192 | #define M_FL0_POINTER 0xffff | ||
193 | #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER) | ||
194 | #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER) | ||
195 | |||
196 | #define A_SG_FL1PTR 0x5c | ||
197 | |||
198 | #define S_FL1_POINTER 0 | ||
199 | #define M_FL1_POINTER 0xffff | ||
200 | #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER) | ||
201 | #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER) | ||
202 | |||
203 | #define A_SG_VERSION 0x6c | ||
204 | |||
205 | #define S_DAY 0 | ||
206 | #define M_DAY 0x1f | ||
207 | #define V_DAY(x) ((x) << S_DAY) | ||
208 | #define G_DAY(x) (((x) >> S_DAY) & M_DAY) | ||
209 | |||
210 | #define S_MONTH 5 | ||
211 | #define M_MONTH 0xf | ||
212 | #define V_MONTH(x) ((x) << S_MONTH) | ||
213 | #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH) | ||
214 | |||
119 | #define A_SG_CMD1SIZE 0xb0 | 215 | #define A_SG_CMD1SIZE 0xb0 |
216 | |||
217 | #define S_CMDQ1_SIZE 0 | ||
218 | #define M_CMDQ1_SIZE 0x1ffff | ||
219 | #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE) | ||
220 | #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE) | ||
221 | |||
120 | #define A_SG_FL1SIZE 0xb4 | 222 | #define A_SG_FL1SIZE 0xb4 |
223 | |||
224 | #define S_FL1_SIZE 0 | ||
225 | #define M_FL1_SIZE 0x1ffff | ||
226 | #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE) | ||
227 | #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE) | ||
228 | |||
121 | #define A_SG_INT_ENABLE 0xb8 | 229 | #define A_SG_INT_ENABLE 0xb8 |
122 | 230 | ||
123 | #define S_RESPQ_EXHAUSTED 0 | 231 | #define S_RESPQ_EXHAUSTED 0 |
@@ -144,21 +252,369 @@ | |||
144 | #define A_SG_RESPACCUTIMER 0xc0 | 252 | #define A_SG_RESPACCUTIMER 0xc0 |
145 | 253 | ||
146 | /* MC3 registers */ | 254 | /* MC3 registers */ |
255 | #define A_MC3_CFG 0x100 | ||
256 | |||
257 | #define S_CLK_ENABLE 0 | ||
258 | #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE) | ||
259 | #define F_CLK_ENABLE V_CLK_ENABLE(1U) | ||
147 | 260 | ||
148 | #define S_READY 1 | 261 | #define S_READY 1 |
149 | #define V_READY(x) ((x) << S_READY) | 262 | #define V_READY(x) ((x) << S_READY) |
150 | #define F_READY V_READY(1U) | 263 | #define F_READY V_READY(1U) |
151 | 264 | ||
152 | /* MC4 registers */ | 265 | #define S_READ_TO_WRITE_DELAY 2 |
266 | #define M_READ_TO_WRITE_DELAY 0x7 | ||
267 | #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY) | ||
268 | #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY) | ||
269 | |||
270 | #define S_WRITE_TO_READ_DELAY 5 | ||
271 | #define M_WRITE_TO_READ_DELAY 0x7 | ||
272 | #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY) | ||
273 | #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY) | ||
153 | 274 | ||
275 | #define S_MC3_BANK_CYCLE 8 | ||
276 | #define M_MC3_BANK_CYCLE 0xf | ||
277 | #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE) | ||
278 | #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE) | ||
279 | |||
280 | #define S_REFRESH_CYCLE 12 | ||
281 | #define M_REFRESH_CYCLE 0xf | ||
282 | #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE) | ||
283 | #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE) | ||
284 | |||
285 | #define S_PRECHARGE_CYCLE 16 | ||
286 | #define M_PRECHARGE_CYCLE 0x3 | ||
287 | #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE) | ||
288 | #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE) | ||
289 | |||
290 | #define S_ACTIVE_TO_READ_WRITE_DELAY 18 | ||
291 | #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY) | ||
292 | #define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U) | ||
293 | |||
294 | #define S_ACTIVE_TO_PRECHARGE_DELAY 19 | ||
295 | #define M_ACTIVE_TO_PRECHARGE_DELAY 0x7 | ||
296 | #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY) | ||
297 | #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY) | ||
298 | |||
299 | #define S_WRITE_RECOVERY_DELAY 22 | ||
300 | #define M_WRITE_RECOVERY_DELAY 0x3 | ||
301 | #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY) | ||
302 | #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY) | ||
303 | |||
304 | #define S_DENSITY 24 | ||
305 | #define M_DENSITY 0x3 | ||
306 | #define V_DENSITY(x) ((x) << S_DENSITY) | ||
307 | #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY) | ||
308 | |||
309 | #define S_ORGANIZATION 26 | ||
310 | #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION) | ||
311 | #define F_ORGANIZATION V_ORGANIZATION(1U) | ||
312 | |||
313 | #define S_BANKS 27 | ||
314 | #define V_BANKS(x) ((x) << S_BANKS) | ||
315 | #define F_BANKS V_BANKS(1U) | ||
316 | |||
317 | #define S_UNREGISTERED 28 | ||
318 | #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED) | ||
319 | #define F_UNREGISTERED V_UNREGISTERED(1U) | ||
320 | |||
321 | #define S_MC3_WIDTH 29 | ||
322 | #define M_MC3_WIDTH 0x3 | ||
323 | #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH) | ||
324 | #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH) | ||
325 | |||
326 | #define S_MC3_SLOW 31 | ||
327 | #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW) | ||
328 | #define F_MC3_SLOW V_MC3_SLOW(1U) | ||
329 | |||
330 | #define A_MC3_MODE 0x104 | ||
331 | |||
332 | #define S_MC3_MODE 0 | ||
333 | #define M_MC3_MODE 0x3fff | ||
334 | #define V_MC3_MODE(x) ((x) << S_MC3_MODE) | ||
335 | #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE) | ||
336 | |||
337 | #define S_BUSY 31 | ||
338 | #define V_BUSY(x) ((x) << S_BUSY) | ||
339 | #define F_BUSY V_BUSY(1U) | ||
340 | |||
341 | #define A_MC3_EXT_MODE 0x108 | ||
342 | |||
343 | #define S_MC3_EXTENDED_MODE 0 | ||
344 | #define M_MC3_EXTENDED_MODE 0x3fff | ||
345 | #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE) | ||
346 | #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE) | ||
347 | |||
348 | #define A_MC3_PRECHARG 0x10c | ||
349 | #define A_MC3_REFRESH 0x110 | ||
350 | |||
351 | #define S_REFRESH_ENABLE 0 | ||
352 | #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE) | ||
353 | #define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U) | ||
354 | |||
355 | #define S_REFRESH_DIVISOR 1 | ||
356 | #define M_REFRESH_DIVISOR 0x3fff | ||
357 | #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR) | ||
358 | #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR) | ||
359 | |||
360 | #define A_MC3_STROBE 0x114 | ||
361 | |||
362 | #define S_MASTER_DLL_RESET 0 | ||
363 | #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET) | ||
364 | #define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U) | ||
365 | |||
366 | #define S_MASTER_DLL_TAP_COUNT 1 | ||
367 | #define M_MASTER_DLL_TAP_COUNT 0xff | ||
368 | #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT) | ||
369 | #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT) | ||
370 | |||
371 | #define S_MASTER_DLL_LOCKED 9 | ||
372 | #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED) | ||
373 | #define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U) | ||
374 | |||
375 | #define S_MASTER_DLL_MAX_TAP_COUNT 10 | ||
376 | #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT) | ||
377 | #define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U) | ||
378 | |||
379 | #define S_MASTER_DLL_TAP_COUNT_OFFSET 11 | ||
380 | #define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f | ||
381 | #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET) | ||
382 | #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET) | ||
383 | |||
384 | #define S_SLAVE_DLL_RESET 11 | ||
385 | #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET) | ||
386 | #define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U) | ||
387 | |||
388 | #define S_SLAVE_DLL_DELTA 12 | ||
389 | #define M_SLAVE_DLL_DELTA 0xf | ||
390 | #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA) | ||
391 | #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA) | ||
392 | |||
393 | #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17 | ||
394 | #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f | ||
395 | #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) | ||
396 | #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) | ||
397 | |||
398 | #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23 | ||
399 | #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE) | ||
400 | #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U) | ||
401 | |||
402 | #define S_SLAVE_DELAY_LINE_TAP_COUNT 24 | ||
403 | #define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f | ||
404 | #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT) | ||
405 | #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT) | ||
406 | |||
407 | #define A_MC3_ECC_CNTL 0x118 | ||
408 | |||
409 | #define S_ECC_GENERATION_ENABLE 0 | ||
410 | #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE) | ||
411 | #define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U) | ||
412 | |||
413 | #define S_ECC_CHECK_ENABLE 1 | ||
414 | #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE) | ||
415 | #define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U) | ||
416 | |||
417 | #define S_CORRECTABLE_ERROR_COUNT 2 | ||
418 | #define M_CORRECTABLE_ERROR_COUNT 0xff | ||
419 | #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT) | ||
420 | #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT) | ||
421 | |||
422 | #define S_UNCORRECTABLE_ERROR_COUNT 10 | ||
423 | #define M_UNCORRECTABLE_ERROR_COUNT 0xff | ||
424 | #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT) | ||
425 | #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT) | ||
426 | |||
427 | #define A_MC3_CE_ADDR 0x11c | ||
428 | |||
429 | #define S_MC3_CE_ADDR 4 | ||
430 | #define M_MC3_CE_ADDR 0xfffffff | ||
431 | #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR) | ||
432 | #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR) | ||
433 | |||
434 | #define A_MC3_CE_DATA0 0x120 | ||
435 | #define A_MC3_CE_DATA1 0x124 | ||
436 | #define A_MC3_CE_DATA2 0x128 | ||
437 | #define A_MC3_CE_DATA3 0x12c | ||
438 | #define A_MC3_CE_DATA4 0x130 | ||
439 | #define A_MC3_UE_ADDR 0x134 | ||
440 | |||
441 | #define S_MC3_UE_ADDR 4 | ||
442 | #define M_MC3_UE_ADDR 0xfffffff | ||
443 | #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR) | ||
444 | #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR) | ||
445 | |||
446 | #define A_MC3_UE_DATA0 0x138 | ||
447 | #define A_MC3_UE_DATA1 0x13c | ||
448 | #define A_MC3_UE_DATA2 0x140 | ||
449 | #define A_MC3_UE_DATA3 0x144 | ||
450 | #define A_MC3_UE_DATA4 0x148 | ||
451 | #define A_MC3_BD_ADDR 0x14c | ||
452 | #define A_MC3_BD_DATA0 0x150 | ||
453 | #define A_MC3_BD_DATA1 0x154 | ||
454 | #define A_MC3_BD_DATA2 0x158 | ||
455 | #define A_MC3_BD_DATA3 0x15c | ||
456 | #define A_MC3_BD_DATA4 0x160 | ||
457 | #define A_MC3_BD_OP 0x164 | ||
458 | |||
459 | #define S_BACK_DOOR_OPERATION 0 | ||
460 | #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION) | ||
461 | #define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U) | ||
462 | |||
463 | #define A_MC3_BIST_ADDR_BEG 0x168 | ||
464 | #define A_MC3_BIST_ADDR_END 0x16c | ||
465 | #define A_MC3_BIST_DATA 0x170 | ||
466 | #define A_MC3_BIST_OP 0x174 | ||
467 | |||
468 | #define S_OP 0 | ||
469 | #define V_OP(x) ((x) << S_OP) | ||
470 | #define F_OP V_OP(1U) | ||
471 | |||
472 | #define S_DATA_PATTERN 1 | ||
473 | #define M_DATA_PATTERN 0x3 | ||
474 | #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN) | ||
475 | #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN) | ||
476 | |||
477 | #define S_CONTINUOUS 3 | ||
478 | #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS) | ||
479 | #define F_CONTINUOUS V_CONTINUOUS(1U) | ||
480 | |||
481 | #define A_MC3_INT_ENABLE 0x178 | ||
482 | |||
483 | #define S_MC3_CORR_ERR 0 | ||
484 | #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR) | ||
485 | #define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U) | ||
486 | |||
487 | #define S_MC3_UNCORR_ERR 1 | ||
488 | #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR) | ||
489 | #define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U) | ||
490 | |||
491 | #define S_MC3_PARITY_ERR 2 | ||
492 | #define M_MC3_PARITY_ERR 0xff | ||
493 | #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR) | ||
494 | #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR) | ||
495 | |||
496 | #define S_MC3_ADDR_ERR 10 | ||
497 | #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR) | ||
498 | #define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U) | ||
499 | |||
500 | #define A_MC3_INT_CAUSE 0x17c | ||
501 | |||
502 | /* MC4 registers */ | ||
154 | #define A_MC4_CFG 0x180 | 503 | #define A_MC4_CFG 0x180 |
504 | |||
505 | #define S_POWER_UP 0 | ||
506 | #define V_POWER_UP(x) ((x) << S_POWER_UP) | ||
507 | #define F_POWER_UP V_POWER_UP(1U) | ||
508 | |||
509 | #define S_MC4_BANK_CYCLE 8 | ||
510 | #define M_MC4_BANK_CYCLE 0x7 | ||
511 | #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE) | ||
512 | #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE) | ||
513 | |||
514 | #define S_MC4_NARROW 24 | ||
515 | #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW) | ||
516 | #define F_MC4_NARROW V_MC4_NARROW(1U) | ||
517 | |||
155 | #define S_MC4_SLOW 25 | 518 | #define S_MC4_SLOW 25 |
156 | #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) | 519 | #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) |
157 | #define F_MC4_SLOW V_MC4_SLOW(1U) | 520 | #define F_MC4_SLOW V_MC4_SLOW(1U) |
158 | 521 | ||
159 | /* TPI registers */ | 522 | #define S_MC4A_WIDTH 24 |
523 | #define M_MC4A_WIDTH 0x3 | ||
524 | #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH) | ||
525 | #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH) | ||
526 | |||
527 | #define S_MC4A_SLOW 26 | ||
528 | #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW) | ||
529 | #define F_MC4A_SLOW V_MC4A_SLOW(1U) | ||
530 | |||
531 | #define A_MC4_MODE 0x184 | ||
532 | |||
533 | #define S_MC4_MODE 0 | ||
534 | #define M_MC4_MODE 0x7fff | ||
535 | #define V_MC4_MODE(x) ((x) << S_MC4_MODE) | ||
536 | #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE) | ||
537 | |||
538 | #define A_MC4_EXT_MODE 0x188 | ||
539 | |||
540 | #define S_MC4_EXTENDED_MODE 0 | ||
541 | #define M_MC4_EXTENDED_MODE 0x7fff | ||
542 | #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE) | ||
543 | #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE) | ||
544 | |||
545 | #define A_MC4_REFRESH 0x190 | ||
546 | #define A_MC4_STROBE 0x194 | ||
547 | #define A_MC4_ECC_CNTL 0x198 | ||
548 | #define A_MC4_CE_ADDR 0x19c | ||
549 | |||
550 | #define S_MC4_CE_ADDR 4 | ||
551 | #define M_MC4_CE_ADDR 0xffffff | ||
552 | #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR) | ||
553 | #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR) | ||
554 | |||
555 | #define A_MC4_CE_DATA0 0x1a0 | ||
556 | #define A_MC4_CE_DATA1 0x1a4 | ||
557 | #define A_MC4_CE_DATA2 0x1a8 | ||
558 | #define A_MC4_CE_DATA3 0x1ac | ||
559 | #define A_MC4_CE_DATA4 0x1b0 | ||
560 | #define A_MC4_UE_ADDR 0x1b4 | ||
561 | |||
562 | #define S_MC4_UE_ADDR 4 | ||
563 | #define M_MC4_UE_ADDR 0xffffff | ||
564 | #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR) | ||
565 | #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR) | ||
566 | |||
567 | #define A_MC4_UE_DATA0 0x1b8 | ||
568 | #define A_MC4_UE_DATA1 0x1bc | ||
569 | #define A_MC4_UE_DATA2 0x1c0 | ||
570 | #define A_MC4_UE_DATA3 0x1c4 | ||
571 | #define A_MC4_UE_DATA4 0x1c8 | ||
572 | #define A_MC4_BD_ADDR 0x1cc | ||
573 | |||
574 | #define S_MC4_BACK_DOOR_ADDR 0 | ||
575 | #define M_MC4_BACK_DOOR_ADDR 0xfffffff | ||
576 | #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR) | ||
577 | #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR) | ||
578 | |||
579 | #define A_MC4_BD_DATA0 0x1d0 | ||
580 | #define A_MC4_BD_DATA1 0x1d4 | ||
581 | #define A_MC4_BD_DATA2 0x1d8 | ||
582 | #define A_MC4_BD_DATA3 0x1dc | ||
583 | #define A_MC4_BD_DATA4 0x1e0 | ||
584 | #define A_MC4_BD_OP 0x1e4 | ||
585 | |||
586 | #define S_OPERATION 0 | ||
587 | #define V_OPERATION(x) ((x) << S_OPERATION) | ||
588 | #define F_OPERATION V_OPERATION(1U) | ||
589 | |||
590 | #define A_MC4_BIST_ADDR_BEG 0x1e8 | ||
591 | #define A_MC4_BIST_ADDR_END 0x1ec | ||
592 | #define A_MC4_BIST_DATA 0x1f0 | ||
593 | #define A_MC4_BIST_OP 0x1f4 | ||
594 | #define A_MC4_INT_ENABLE 0x1f8 | ||
595 | |||
596 | #define S_MC4_CORR_ERR 0 | ||
597 | #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR) | ||
598 | #define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U) | ||
599 | |||
600 | #define S_MC4_UNCORR_ERR 1 | ||
601 | #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR) | ||
602 | #define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U) | ||
603 | |||
604 | #define S_MC4_ADDR_ERR 2 | ||
605 | #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR) | ||
606 | #define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U) | ||
607 | |||
608 | #define A_MC4_INT_CAUSE 0x1fc | ||
160 | 609 | ||
610 | /* TPI registers */ | ||
161 | #define A_TPI_ADDR 0x280 | 611 | #define A_TPI_ADDR 0x280 |
612 | |||
613 | #define S_TPI_ADDRESS 0 | ||
614 | #define M_TPI_ADDRESS 0xffffff | ||
615 | #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS) | ||
616 | #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS) | ||
617 | |||
162 | #define A_TPI_WR_DATA 0x284 | 618 | #define A_TPI_WR_DATA 0x284 |
163 | #define A_TPI_RD_DATA 0x288 | 619 | #define A_TPI_RD_DATA 0x288 |
164 | #define A_TPI_CSR 0x28c | 620 | #define A_TPI_CSR 0x28c |
@@ -171,6 +627,10 @@ | |||
171 | #define V_TPIRDY(x) ((x) << S_TPIRDY) | 627 | #define V_TPIRDY(x) ((x) << S_TPIRDY) |
172 | #define F_TPIRDY V_TPIRDY(1U) | 628 | #define F_TPIRDY V_TPIRDY(1U) |
173 | 629 | ||
630 | #define S_INT_DIR 31 | ||
631 | #define V_INT_DIR(x) ((x) << S_INT_DIR) | ||
632 | #define F_INT_DIR V_INT_DIR(1U) | ||
633 | |||
174 | #define A_TPI_PAR 0x29c | 634 | #define A_TPI_PAR 0x29c |
175 | 635 | ||
176 | #define S_TPIPAR 0 | 636 | #define S_TPIPAR 0 |
@@ -178,14 +638,26 @@ | |||
178 | #define V_TPIPAR(x) ((x) << S_TPIPAR) | 638 | #define V_TPIPAR(x) ((x) << S_TPIPAR) |
179 | #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) | 639 | #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) |
180 | 640 | ||
181 | /* TP registers */ | ||
182 | 641 | ||
642 | /* TP registers */ | ||
183 | #define A_TP_IN_CONFIG 0x300 | 643 | #define A_TP_IN_CONFIG 0x300 |
184 | 644 | ||
645 | #define S_TP_IN_CSPI_TUNNEL 0 | ||
646 | #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL) | ||
647 | #define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U) | ||
648 | |||
649 | #define S_TP_IN_CSPI_ETHERNET 1 | ||
650 | #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET) | ||
651 | #define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U) | ||
652 | |||
185 | #define S_TP_IN_CSPI_CPL 3 | 653 | #define S_TP_IN_CSPI_CPL 3 |
186 | #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) | 654 | #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) |
187 | #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) | 655 | #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) |
188 | 656 | ||
657 | #define S_TP_IN_CSPI_POS 4 | ||
658 | #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS) | ||
659 | #define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U) | ||
660 | |||
189 | #define S_TP_IN_CSPI_CHECK_IP_CSUM 5 | 661 | #define S_TP_IN_CSPI_CHECK_IP_CSUM 5 |
190 | #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) | 662 | #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) |
191 | #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) | 663 | #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) |
@@ -194,10 +666,22 @@ | |||
194 | #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) | 666 | #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) |
195 | #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) | 667 | #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) |
196 | 668 | ||
669 | #define S_TP_IN_ESPI_TUNNEL 7 | ||
670 | #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL) | ||
671 | #define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U) | ||
672 | |||
197 | #define S_TP_IN_ESPI_ETHERNET 8 | 673 | #define S_TP_IN_ESPI_ETHERNET 8 |
198 | #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) | 674 | #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) |
199 | #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) | 675 | #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) |
200 | 676 | ||
677 | #define S_TP_IN_ESPI_CPL 10 | ||
678 | #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL) | ||
679 | #define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U) | ||
680 | |||
681 | #define S_TP_IN_ESPI_POS 11 | ||
682 | #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS) | ||
683 | #define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U) | ||
684 | |||
201 | #define S_TP_IN_ESPI_CHECK_IP_CSUM 12 | 685 | #define S_TP_IN_ESPI_CHECK_IP_CSUM 12 |
202 | #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) | 686 | #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) |
203 | #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) | 687 | #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) |
@@ -212,14 +696,42 @@ | |||
212 | 696 | ||
213 | #define A_TP_OUT_CONFIG 0x304 | 697 | #define A_TP_OUT_CONFIG 0x304 |
214 | 698 | ||
699 | #define S_TP_OUT_C_ETH 0 | ||
700 | #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH) | ||
701 | #define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U) | ||
702 | |||
215 | #define S_TP_OUT_CSPI_CPL 2 | 703 | #define S_TP_OUT_CSPI_CPL 2 |
216 | #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) | 704 | #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) |
217 | #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) | 705 | #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) |
218 | 706 | ||
707 | #define S_TP_OUT_CSPI_POS 3 | ||
708 | #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS) | ||
709 | #define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U) | ||
710 | |||
711 | #define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4 | ||
712 | #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM) | ||
713 | #define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U) | ||
714 | |||
715 | #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5 | ||
716 | #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM) | ||
717 | #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U) | ||
718 | |||
219 | #define S_TP_OUT_ESPI_ETHERNET 6 | 719 | #define S_TP_OUT_ESPI_ETHERNET 6 |
220 | #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) | 720 | #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) |
221 | #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) | 721 | #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) |
222 | 722 | ||
723 | #define S_TP_OUT_ESPI_TAG_ETHERNET 7 | ||
724 | #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET) | ||
725 | #define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U) | ||
726 | |||
727 | #define S_TP_OUT_ESPI_CPL 8 | ||
728 | #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL) | ||
729 | #define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U) | ||
730 | |||
731 | #define S_TP_OUT_ESPI_POS 9 | ||
732 | #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS) | ||
733 | #define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U) | ||
734 | |||
223 | #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 | 735 | #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 |
224 | #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) | 736 | #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) |
225 | #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) | 737 | #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) |
@@ -233,6 +745,16 @@ | |||
233 | #define S_IP_TTL 0 | 745 | #define S_IP_TTL 0 |
234 | #define M_IP_TTL 0xff | 746 | #define M_IP_TTL 0xff |
235 | #define V_IP_TTL(x) ((x) << S_IP_TTL) | 747 | #define V_IP_TTL(x) ((x) << S_IP_TTL) |
748 | #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL) | ||
749 | |||
750 | #define S_TCAM_SERVER_REGION_USAGE 8 | ||
751 | #define M_TCAM_SERVER_REGION_USAGE 0x3 | ||
752 | #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE) | ||
753 | #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE) | ||
754 | |||
755 | #define S_QOS_MAPPING 10 | ||
756 | #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING) | ||
757 | #define F_QOS_MAPPING V_QOS_MAPPING(1U) | ||
236 | 758 | ||
237 | #define S_TCP_CSUM 11 | 759 | #define S_TCP_CSUM 11 |
238 | #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) | 760 | #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) |
@@ -246,31 +768,476 @@ | |||
246 | #define V_IP_CSUM(x) ((x) << S_IP_CSUM) | 768 | #define V_IP_CSUM(x) ((x) << S_IP_CSUM) |
247 | #define F_IP_CSUM V_IP_CSUM(1U) | 769 | #define F_IP_CSUM V_IP_CSUM(1U) |
248 | 770 | ||
771 | #define S_IP_ID_SPLIT 14 | ||
772 | #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT) | ||
773 | #define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U) | ||
774 | |||
249 | #define S_PATH_MTU 15 | 775 | #define S_PATH_MTU 15 |
250 | #define V_PATH_MTU(x) ((x) << S_PATH_MTU) | 776 | #define V_PATH_MTU(x) ((x) << S_PATH_MTU) |
251 | #define F_PATH_MTU V_PATH_MTU(1U) | 777 | #define F_PATH_MTU V_PATH_MTU(1U) |
252 | 778 | ||
253 | #define S_5TUPLE_LOOKUP 17 | 779 | #define S_5TUPLE_LOOKUP 17 |
780 | #define M_5TUPLE_LOOKUP 0x3 | ||
254 | #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) | 781 | #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) |
782 | #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP) | ||
783 | |||
784 | #define S_IP_FRAGMENT_DROP 19 | ||
785 | #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP) | ||
786 | #define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U) | ||
787 | |||
788 | #define S_PING_DROP 20 | ||
789 | #define V_PING_DROP(x) ((x) << S_PING_DROP) | ||
790 | #define F_PING_DROP V_PING_DROP(1U) | ||
791 | |||
792 | #define S_PROTECT_MODE 21 | ||
793 | #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE) | ||
794 | #define F_PROTECT_MODE V_PROTECT_MODE(1U) | ||
795 | |||
796 | #define S_SYN_COOKIE_ALGORITHM 22 | ||
797 | #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM) | ||
798 | #define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U) | ||
799 | |||
800 | #define S_ATTACK_FILTER 23 | ||
801 | #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER) | ||
802 | #define F_ATTACK_FILTER V_ATTACK_FILTER(1U) | ||
803 | |||
804 | #define S_INTERFACE_TYPE 24 | ||
805 | #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE) | ||
806 | #define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U) | ||
807 | |||
808 | #define S_DISABLE_RX_FLOW_CONTROL 25 | ||
809 | #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL) | ||
810 | #define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U) | ||
255 | 811 | ||
256 | #define S_SYN_COOKIE_PARAMETER 26 | 812 | #define S_SYN_COOKIE_PARAMETER 26 |
813 | #define M_SYN_COOKIE_PARAMETER 0x3f | ||
257 | #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) | 814 | #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) |
815 | #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER) | ||
816 | |||
817 | #define A_TP_GLOBAL_RX_CREDITS 0x30c | ||
818 | #define A_TP_CM_SIZE 0x310 | ||
819 | #define A_TP_CM_MM_BASE 0x314 | ||
820 | |||
821 | #define S_CM_MEMMGR_BASE 0 | ||
822 | #define M_CM_MEMMGR_BASE 0xfffffff | ||
823 | #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE) | ||
824 | #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE) | ||
825 | |||
826 | #define A_TP_CM_TIMER_BASE 0x318 | ||
827 | |||
828 | #define S_CM_TIMER_BASE 0 | ||
829 | #define M_CM_TIMER_BASE 0xfffffff | ||
830 | #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE) | ||
831 | #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE) | ||
832 | |||
833 | #define A_TP_PM_SIZE 0x31c | ||
834 | #define A_TP_PM_TX_BASE 0x320 | ||
835 | #define A_TP_PM_DEFRAG_BASE 0x324 | ||
836 | #define A_TP_PM_RX_BASE 0x328 | ||
837 | #define A_TP_PM_RX_PG_SIZE 0x32c | ||
838 | #define A_TP_PM_RX_MAX_PGS 0x330 | ||
839 | #define A_TP_PM_TX_PG_SIZE 0x334 | ||
840 | #define A_TP_PM_TX_MAX_PGS 0x338 | ||
841 | #define A_TP_TCP_OPTIONS 0x340 | ||
842 | |||
843 | #define S_TIMESTAMP 0 | ||
844 | #define M_TIMESTAMP 0x3 | ||
845 | #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP) | ||
846 | #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP) | ||
847 | |||
848 | #define S_WINDOW_SCALE 2 | ||
849 | #define M_WINDOW_SCALE 0x3 | ||
850 | #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE) | ||
851 | #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE) | ||
852 | |||
853 | #define S_SACK 4 | ||
854 | #define M_SACK 0x3 | ||
855 | #define V_SACK(x) ((x) << S_SACK) | ||
856 | #define G_SACK(x) (((x) >> S_SACK) & M_SACK) | ||
857 | |||
858 | #define S_ECN 6 | ||
859 | #define M_ECN 0x3 | ||
860 | #define V_ECN(x) ((x) << S_ECN) | ||
861 | #define G_ECN(x) (((x) >> S_ECN) & M_ECN) | ||
862 | |||
863 | #define S_SACK_ALGORITHM 8 | ||
864 | #define M_SACK_ALGORITHM 0x3 | ||
865 | #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM) | ||
866 | #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM) | ||
867 | |||
868 | #define S_MSS 10 | ||
869 | #define V_MSS(x) ((x) << S_MSS) | ||
870 | #define F_MSS V_MSS(1U) | ||
871 | |||
872 | #define S_DEFAULT_PEER_MSS 16 | ||
873 | #define M_DEFAULT_PEER_MSS 0xffff | ||
874 | #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS) | ||
875 | #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS) | ||
876 | |||
877 | #define A_TP_DACK_CONFIG 0x344 | ||
878 | |||
879 | #define S_DACK_MODE 0 | ||
880 | #define V_DACK_MODE(x) ((x) << S_DACK_MODE) | ||
881 | #define F_DACK_MODE V_DACK_MODE(1U) | ||
882 | |||
883 | #define S_DACK_AUTO_MGMT 1 | ||
884 | #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT) | ||
885 | #define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U) | ||
886 | |||
887 | #define S_DACK_AUTO_CAREFUL 2 | ||
888 | #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL) | ||
889 | #define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U) | ||
890 | |||
891 | #define S_DACK_MSS_SELECTOR 3 | ||
892 | #define M_DACK_MSS_SELECTOR 0x3 | ||
893 | #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR) | ||
894 | #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR) | ||
895 | |||
896 | #define S_DACK_BYTE_THRESHOLD 5 | ||
897 | #define M_DACK_BYTE_THRESHOLD 0xfffff | ||
898 | #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD) | ||
899 | #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD) | ||
258 | 900 | ||
259 | #define A_TP_PC_CONFIG 0x348 | 901 | #define A_TP_PC_CONFIG 0x348 |
902 | |||
903 | #define S_TP_ACCESS_LATENCY 0 | ||
904 | #define M_TP_ACCESS_LATENCY 0xf | ||
905 | #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY) | ||
906 | #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY) | ||
907 | |||
908 | #define S_HELD_FIN_DISABLE 4 | ||
909 | #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE) | ||
910 | #define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U) | ||
911 | |||
912 | #define S_DDP_FC_ENABLE 5 | ||
913 | #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE) | ||
914 | #define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U) | ||
915 | |||
916 | #define S_RDMA_ERR_ENABLE 6 | ||
917 | #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE) | ||
918 | #define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U) | ||
919 | |||
920 | #define S_FAST_PDU_DELIVERY 7 | ||
921 | #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY) | ||
922 | #define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U) | ||
923 | |||
924 | #define S_CLEAR_FIN 8 | ||
925 | #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN) | ||
926 | #define F_CLEAR_FIN V_CLEAR_FIN(1U) | ||
927 | |||
260 | #define S_DIS_TX_FILL_WIN_PUSH 12 | 928 | #define S_DIS_TX_FILL_WIN_PUSH 12 |
261 | #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) | 929 | #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) |
262 | #define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) | 930 | #define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) |
263 | 931 | ||
264 | #define S_TP_PC_REV 30 | 932 | #define S_TP_PC_REV 30 |
265 | #define M_TP_PC_REV 0x3 | 933 | #define M_TP_PC_REV 0x3 |
934 | #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV) | ||
266 | #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) | 935 | #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) |
936 | |||
937 | #define A_TP_BACKOFF0 0x350 | ||
938 | |||
939 | #define S_ELEMENT0 0 | ||
940 | #define M_ELEMENT0 0xff | ||
941 | #define V_ELEMENT0(x) ((x) << S_ELEMENT0) | ||
942 | #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0) | ||
943 | |||
944 | #define S_ELEMENT1 8 | ||
945 | #define M_ELEMENT1 0xff | ||
946 | #define V_ELEMENT1(x) ((x) << S_ELEMENT1) | ||
947 | #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1) | ||
948 | |||
949 | #define S_ELEMENT2 16 | ||
950 | #define M_ELEMENT2 0xff | ||
951 | #define V_ELEMENT2(x) ((x) << S_ELEMENT2) | ||
952 | #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2) | ||
953 | |||
954 | #define S_ELEMENT3 24 | ||
955 | #define M_ELEMENT3 0xff | ||
956 | #define V_ELEMENT3(x) ((x) << S_ELEMENT3) | ||
957 | #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3) | ||
958 | |||
959 | #define A_TP_BACKOFF1 0x354 | ||
960 | #define A_TP_BACKOFF2 0x358 | ||
961 | #define A_TP_BACKOFF3 0x35c | ||
962 | #define A_TP_PARA_REG0 0x360 | ||
963 | |||
964 | #define S_VAR_MULT 0 | ||
965 | #define M_VAR_MULT 0xf | ||
966 | #define V_VAR_MULT(x) ((x) << S_VAR_MULT) | ||
967 | #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT) | ||
968 | |||
969 | #define S_VAR_GAIN 4 | ||
970 | #define M_VAR_GAIN 0xf | ||
971 | #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN) | ||
972 | #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN) | ||
973 | |||
974 | #define S_SRTT_GAIN 8 | ||
975 | #define M_SRTT_GAIN 0xf | ||
976 | #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN) | ||
977 | #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN) | ||
978 | |||
979 | #define S_RTTVAR_INIT 12 | ||
980 | #define M_RTTVAR_INIT 0xf | ||
981 | #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT) | ||
982 | #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT) | ||
983 | |||
984 | #define S_DUP_THRESH 20 | ||
985 | #define M_DUP_THRESH 0xf | ||
986 | #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH) | ||
987 | #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH) | ||
988 | |||
989 | #define S_INIT_CONG_WIN 24 | ||
990 | #define M_INIT_CONG_WIN 0x7 | ||
991 | #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN) | ||
992 | #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN) | ||
993 | |||
994 | #define A_TP_PARA_REG1 0x364 | ||
995 | |||
996 | #define S_INITIAL_SLOW_START_THRESHOLD 0 | ||
997 | #define M_INITIAL_SLOW_START_THRESHOLD 0xffff | ||
998 | #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD) | ||
999 | #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD) | ||
1000 | |||
1001 | #define S_RECEIVE_BUFFER_SIZE 16 | ||
1002 | #define M_RECEIVE_BUFFER_SIZE 0xffff | ||
1003 | #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE) | ||
1004 | #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE) | ||
1005 | |||
1006 | #define A_TP_PARA_REG2 0x368 | ||
1007 | |||
1008 | #define S_RX_COALESCE_SIZE 0 | ||
1009 | #define M_RX_COALESCE_SIZE 0xffff | ||
1010 | #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE) | ||
1011 | #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE) | ||
1012 | |||
1013 | #define S_MAX_RX_SIZE 16 | ||
1014 | #define M_MAX_RX_SIZE 0xffff | ||
1015 | #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE) | ||
1016 | #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE) | ||
1017 | |||
1018 | #define A_TP_PARA_REG3 0x36c | ||
1019 | |||
1020 | #define S_RX_COALESCING_PSH_DELIVER 0 | ||
1021 | #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER) | ||
1022 | #define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U) | ||
1023 | |||
1024 | #define S_RX_COALESCING_ENABLE 1 | ||
1025 | #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE) | ||
1026 | #define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U) | ||
1027 | |||
1028 | #define S_TAHOE_ENABLE 2 | ||
1029 | #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE) | ||
1030 | #define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U) | ||
1031 | |||
1032 | #define S_MAX_REORDER_FRAGMENTS 12 | ||
1033 | #define M_MAX_REORDER_FRAGMENTS 0x7 | ||
1034 | #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS) | ||
1035 | #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS) | ||
1036 | |||
1037 | #define A_TP_TIMER_RESOLUTION 0x390 | ||
1038 | |||
1039 | #define S_DELAYED_ACK_TIMER_RESOLUTION 0 | ||
1040 | #define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f | ||
1041 | #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION) | ||
1042 | #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION) | ||
1043 | |||
1044 | #define S_GENERIC_TIMER_RESOLUTION 16 | ||
1045 | #define M_GENERIC_TIMER_RESOLUTION 0x3f | ||
1046 | #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION) | ||
1047 | #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION) | ||
1048 | |||
1049 | #define A_TP_2MSL 0x394 | ||
1050 | |||
1051 | #define S_2MSL 0 | ||
1052 | #define M_2MSL 0x3fffffff | ||
1053 | #define V_2MSL(x) ((x) << S_2MSL) | ||
1054 | #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL) | ||
1055 | |||
1056 | #define A_TP_RXT_MIN 0x398 | ||
1057 | |||
1058 | #define S_RETRANSMIT_TIMER_MIN 0 | ||
1059 | #define M_RETRANSMIT_TIMER_MIN 0xffff | ||
1060 | #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN) | ||
1061 | #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN) | ||
1062 | |||
1063 | #define A_TP_RXT_MAX 0x39c | ||
1064 | |||
1065 | #define S_RETRANSMIT_TIMER_MAX 0 | ||
1066 | #define M_RETRANSMIT_TIMER_MAX 0x3fffffff | ||
1067 | #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX) | ||
1068 | #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX) | ||
1069 | |||
1070 | #define A_TP_PERS_MIN 0x3a0 | ||
1071 | |||
1072 | #define S_PERSIST_TIMER_MIN 0 | ||
1073 | #define M_PERSIST_TIMER_MIN 0xffff | ||
1074 | #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN) | ||
1075 | #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN) | ||
1076 | |||
1077 | #define A_TP_PERS_MAX 0x3a4 | ||
1078 | |||
1079 | #define S_PERSIST_TIMER_MAX 0 | ||
1080 | #define M_PERSIST_TIMER_MAX 0x3fffffff | ||
1081 | #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX) | ||
1082 | #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX) | ||
1083 | |||
1084 | #define A_TP_KEEP_IDLE 0x3ac | ||
1085 | |||
1086 | #define S_KEEP_ALIVE_IDLE_TIME 0 | ||
1087 | #define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff | ||
1088 | #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME) | ||
1089 | #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME) | ||
1090 | |||
1091 | #define A_TP_KEEP_INTVL 0x3b0 | ||
1092 | |||
1093 | #define S_KEEP_ALIVE_INTERVAL_TIME 0 | ||
1094 | #define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff | ||
1095 | #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME) | ||
1096 | #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME) | ||
1097 | |||
1098 | #define A_TP_INIT_SRTT 0x3b4 | ||
1099 | |||
1100 | #define S_INITIAL_SRTT 0 | ||
1101 | #define M_INITIAL_SRTT 0xffff | ||
1102 | #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT) | ||
1103 | #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT) | ||
1104 | |||
1105 | #define A_TP_DACK_TIME 0x3b8 | ||
1106 | |||
1107 | #define S_DELAYED_ACK_TIME 0 | ||
1108 | #define M_DELAYED_ACK_TIME 0x7ff | ||
1109 | #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME) | ||
1110 | #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME) | ||
1111 | |||
1112 | #define A_TP_FINWAIT2_TIME 0x3bc | ||
1113 | |||
1114 | #define S_FINWAIT2_TIME 0 | ||
1115 | #define M_FINWAIT2_TIME 0x3fffffff | ||
1116 | #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME) | ||
1117 | #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME) | ||
1118 | |||
1119 | #define A_TP_FAST_FINWAIT2_TIME 0x3c0 | ||
1120 | |||
1121 | #define S_FAST_FINWAIT2_TIME 0 | ||
1122 | #define M_FAST_FINWAIT2_TIME 0x3fffffff | ||
1123 | #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME) | ||
1124 | #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME) | ||
1125 | |||
1126 | #define A_TP_SHIFT_CNT 0x3c4 | ||
1127 | |||
1128 | #define S_KEEPALIVE_MAX 0 | ||
1129 | #define M_KEEPALIVE_MAX 0xff | ||
1130 | #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX) | ||
1131 | #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX) | ||
1132 | |||
1133 | #define S_WINDOWPROBE_MAX 8 | ||
1134 | #define M_WINDOWPROBE_MAX 0xff | ||
1135 | #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX) | ||
1136 | #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX) | ||
1137 | |||
1138 | #define S_RETRANSMISSION_MAX 16 | ||
1139 | #define M_RETRANSMISSION_MAX 0xff | ||
1140 | #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX) | ||
1141 | #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX) | ||
1142 | |||
1143 | #define S_SYN_MAX 24 | ||
1144 | #define M_SYN_MAX 0xff | ||
1145 | #define V_SYN_MAX(x) ((x) << S_SYN_MAX) | ||
1146 | #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX) | ||
1147 | |||
1148 | #define A_TP_QOS_REG0 0x3e0 | ||
1149 | |||
1150 | #define S_L3_VALUE 0 | ||
1151 | #define M_L3_VALUE 0x3f | ||
1152 | #define V_L3_VALUE(x) ((x) << S_L3_VALUE) | ||
1153 | #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE) | ||
1154 | |||
1155 | #define A_TP_QOS_REG1 0x3e4 | ||
1156 | #define A_TP_QOS_REG2 0x3e8 | ||
1157 | #define A_TP_QOS_REG3 0x3ec | ||
1158 | #define A_TP_QOS_REG4 0x3f0 | ||
1159 | #define A_TP_QOS_REG5 0x3f4 | ||
1160 | #define A_TP_QOS_REG6 0x3f8 | ||
1161 | #define A_TP_QOS_REG7 0x3fc | ||
1162 | #define A_TP_MTU_REG0 0x404 | ||
1163 | #define A_TP_MTU_REG1 0x408 | ||
1164 | #define A_TP_MTU_REG2 0x40c | ||
1165 | #define A_TP_MTU_REG3 0x410 | ||
1166 | #define A_TP_MTU_REG4 0x414 | ||
1167 | #define A_TP_MTU_REG5 0x418 | ||
1168 | #define A_TP_MTU_REG6 0x41c | ||
1169 | #define A_TP_MTU_REG7 0x420 | ||
267 | #define A_TP_RESET 0x44c | 1170 | #define A_TP_RESET 0x44c |
1171 | |||
268 | #define S_TP_RESET 0 | 1172 | #define S_TP_RESET 0 |
269 | #define V_TP_RESET(x) ((x) << S_TP_RESET) | 1173 | #define V_TP_RESET(x) ((x) << S_TP_RESET) |
270 | #define F_TP_RESET V_TP_RESET(1U) | 1174 | #define F_TP_RESET V_TP_RESET(1U) |
271 | 1175 | ||
1176 | #define S_CM_MEMMGR_INIT 1 | ||
1177 | #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT) | ||
1178 | #define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U) | ||
1179 | |||
1180 | #define A_TP_MIB_INDEX 0x450 | ||
1181 | #define A_TP_MIB_DATA 0x454 | ||
1182 | #define A_TP_SYNC_TIME_HI 0x458 | ||
1183 | #define A_TP_SYNC_TIME_LO 0x45c | ||
1184 | #define A_TP_CM_MM_RX_FLST_BASE 0x460 | ||
1185 | |||
1186 | #define S_CM_MEMMGR_RX_FREE_LIST_BASE 0 | ||
1187 | #define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff | ||
1188 | #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE) | ||
1189 | #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE) | ||
1190 | |||
1191 | #define A_TP_CM_MM_TX_FLST_BASE 0x464 | ||
1192 | |||
1193 | #define S_CM_MEMMGR_TX_FREE_LIST_BASE 0 | ||
1194 | #define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff | ||
1195 | #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE) | ||
1196 | #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE) | ||
1197 | |||
1198 | #define A_TP_CM_MM_P_FLST_BASE 0x468 | ||
1199 | |||
1200 | #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0 | ||
1201 | #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff | ||
1202 | #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) | ||
1203 | #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) | ||
1204 | |||
1205 | #define A_TP_CM_MM_MAX_P 0x46c | ||
1206 | |||
1207 | #define S_CM_MEMMGR_MAX_PSTRUCT 0 | ||
1208 | #define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff | ||
1209 | #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT) | ||
1210 | #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT) | ||
1211 | |||
272 | #define A_TP_INT_ENABLE 0x470 | 1212 | #define A_TP_INT_ENABLE 0x470 |
1213 | |||
1214 | #define S_TX_FREE_LIST_EMPTY 0 | ||
1215 | #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY) | ||
1216 | #define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U) | ||
1217 | |||
1218 | #define S_RX_FREE_LIST_EMPTY 1 | ||
1219 | #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY) | ||
1220 | #define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U) | ||
1221 | |||
273 | #define A_TP_INT_CAUSE 0x474 | 1222 | #define A_TP_INT_CAUSE 0x474 |
1223 | #define A_TP_TIMER_SEPARATOR 0x4a4 | ||
1224 | |||
1225 | #define S_DISABLE_PAST_TIMER_INSERTION 0 | ||
1226 | #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION) | ||
1227 | #define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U) | ||
1228 | |||
1229 | #define S_MODULATION_TIMER_SEPARATOR 1 | ||
1230 | #define M_MODULATION_TIMER_SEPARATOR 0x7fff | ||
1231 | #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR) | ||
1232 | #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR) | ||
1233 | |||
1234 | #define S_GLOBAL_TIMER_SEPARATOR 16 | ||
1235 | #define M_GLOBAL_TIMER_SEPARATOR 0xffff | ||
1236 | #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR) | ||
1237 | #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR) | ||
1238 | |||
1239 | #define A_TP_CM_FC_MODE 0x4b0 | ||
1240 | #define A_TP_PC_CONGESTION_CNTL 0x4b4 | ||
274 | #define A_TP_TX_DROP_CONFIG 0x4b8 | 1241 | #define A_TP_TX_DROP_CONFIG 0x4b8 |
275 | 1242 | ||
276 | #define S_ENABLE_TX_DROP 31 | 1243 | #define S_ENABLE_TX_DROP 31 |
@@ -282,12 +1249,108 @@ | |||
282 | #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) | 1249 | #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) |
283 | 1250 | ||
284 | #define S_DROP_TICKS_CNT 4 | 1251 | #define S_DROP_TICKS_CNT 4 |
1252 | #define M_DROP_TICKS_CNT 0x3ffffff | ||
285 | #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) | 1253 | #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) |
1254 | #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT) | ||
286 | 1255 | ||
287 | #define S_NUM_PKTS_DROPPED 0 | 1256 | #define S_NUM_PKTS_DROPPED 0 |
1257 | #define M_NUM_PKTS_DROPPED 0xf | ||
288 | #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) | 1258 | #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) |
1259 | #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED) | ||
1260 | |||
1261 | #define A_TP_TX_DROP_COUNT 0x4bc | ||
1262 | |||
1263 | /* RAT registers */ | ||
1264 | #define A_RAT_ROUTE_CONTROL 0x580 | ||
1265 | |||
1266 | #define S_USE_ROUTE_TABLE 0 | ||
1267 | #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE) | ||
1268 | #define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U) | ||
1269 | |||
1270 | #define S_ENABLE_CSPI 1 | ||
1271 | #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI) | ||
1272 | #define F_ENABLE_CSPI V_ENABLE_CSPI(1U) | ||
1273 | |||
1274 | #define S_ENABLE_PCIX 2 | ||
1275 | #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX) | ||
1276 | #define F_ENABLE_PCIX V_ENABLE_PCIX(1U) | ||
1277 | |||
1278 | #define A_RAT_ROUTE_TABLE_INDEX 0x584 | ||
1279 | |||
1280 | #define S_ROUTE_TABLE_INDEX 0 | ||
1281 | #define M_ROUTE_TABLE_INDEX 0xf | ||
1282 | #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX) | ||
1283 | #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX) | ||
1284 | |||
1285 | #define A_RAT_ROUTE_TABLE_DATA 0x588 | ||
1286 | #define A_RAT_NO_ROUTE 0x58c | ||
1287 | |||
1288 | #define S_CPL_OPCODE 0 | ||
1289 | #define M_CPL_OPCODE 0xff | ||
1290 | #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) | ||
1291 | #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE) | ||
1292 | |||
1293 | #define A_RAT_INTR_ENABLE 0x590 | ||
1294 | |||
1295 | #define S_ZEROROUTEERROR 0 | ||
1296 | #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR) | ||
1297 | #define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U) | ||
1298 | |||
1299 | #define S_CSPIFRAMINGERROR 1 | ||
1300 | #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR) | ||
1301 | #define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U) | ||
1302 | |||
1303 | #define S_SGEFRAMINGERROR 2 | ||
1304 | #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR) | ||
1305 | #define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U) | ||
1306 | |||
1307 | #define S_TPFRAMINGERROR 3 | ||
1308 | #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR) | ||
1309 | #define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U) | ||
1310 | |||
1311 | #define A_RAT_INTR_CAUSE 0x594 | ||
289 | 1312 | ||
290 | /* CSPI registers */ | 1313 | /* CSPI registers */ |
1314 | #define A_CSPI_RX_AE_WM 0x810 | ||
1315 | #define A_CSPI_RX_AF_WM 0x814 | ||
1316 | #define A_CSPI_CALENDAR_LEN 0x818 | ||
1317 | |||
1318 | #define S_CALENDARLENGTH 0 | ||
1319 | #define M_CALENDARLENGTH 0xffff | ||
1320 | #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH) | ||
1321 | #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH) | ||
1322 | |||
1323 | #define A_CSPI_FIFO_STATUS_ENABLE 0x820 | ||
1324 | |||
1325 | #define S_FIFOSTATUSENABLE 0 | ||
1326 | #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE) | ||
1327 | #define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U) | ||
1328 | |||
1329 | #define A_CSPI_MAXBURST1_MAXBURST2 0x828 | ||
1330 | |||
1331 | #define S_MAXBURST1 0 | ||
1332 | #define M_MAXBURST1 0xffff | ||
1333 | #define V_MAXBURST1(x) ((x) << S_MAXBURST1) | ||
1334 | #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1) | ||
1335 | |||
1336 | #define S_MAXBURST2 16 | ||
1337 | #define M_MAXBURST2 0xffff | ||
1338 | #define V_MAXBURST2(x) ((x) << S_MAXBURST2) | ||
1339 | #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2) | ||
1340 | |||
1341 | #define A_CSPI_TRAIN 0x82c | ||
1342 | |||
1343 | #define S_CSPI_TRAIN_ALPHA 0 | ||
1344 | #define M_CSPI_TRAIN_ALPHA 0xffff | ||
1345 | #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA) | ||
1346 | #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA) | ||
1347 | |||
1348 | #define S_CSPI_TRAIN_DATA_MAXT 16 | ||
1349 | #define M_CSPI_TRAIN_DATA_MAXT 0xffff | ||
1350 | #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT) | ||
1351 | #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT) | ||
1352 | |||
1353 | #define A_CSPI_INTR_STATUS 0x848 | ||
291 | 1354 | ||
292 | #define S_DIP4ERR 0 | 1355 | #define S_DIP4ERR 0 |
293 | #define V_DIP4ERR(x) ((x) << S_DIP4ERR) | 1356 | #define V_DIP4ERR(x) ((x) << S_DIP4ERR) |
@@ -309,22 +1372,63 @@ | |||
309 | #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) | 1372 | #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) |
310 | #define F_RAMPARITYERR V_RAMPARITYERR(1U) | 1373 | #define F_RAMPARITYERR V_RAMPARITYERR(1U) |
311 | 1374 | ||
312 | /* ESPI registers */ | 1375 | #define A_CSPI_INTR_ENABLE 0x84c |
313 | 1376 | ||
1377 | /* ESPI registers */ | ||
314 | #define A_ESPI_SCH_TOKEN0 0x880 | 1378 | #define A_ESPI_SCH_TOKEN0 0x880 |
1379 | |||
1380 | #define S_SCHTOKEN0 0 | ||
1381 | #define M_SCHTOKEN0 0xffff | ||
1382 | #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0) | ||
1383 | #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0) | ||
1384 | |||
315 | #define A_ESPI_SCH_TOKEN1 0x884 | 1385 | #define A_ESPI_SCH_TOKEN1 0x884 |
1386 | |||
1387 | #define S_SCHTOKEN1 0 | ||
1388 | #define M_SCHTOKEN1 0xffff | ||
1389 | #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1) | ||
1390 | #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1) | ||
1391 | |||
316 | #define A_ESPI_SCH_TOKEN2 0x888 | 1392 | #define A_ESPI_SCH_TOKEN2 0x888 |
1393 | |||
1394 | #define S_SCHTOKEN2 0 | ||
1395 | #define M_SCHTOKEN2 0xffff | ||
1396 | #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2) | ||
1397 | #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2) | ||
1398 | |||
317 | #define A_ESPI_SCH_TOKEN3 0x88c | 1399 | #define A_ESPI_SCH_TOKEN3 0x88c |
1400 | |||
1401 | #define S_SCHTOKEN3 0 | ||
1402 | #define M_SCHTOKEN3 0xffff | ||
1403 | #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3) | ||
1404 | #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3) | ||
1405 | |||
318 | #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 | 1406 | #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 |
1407 | |||
1408 | #define S_ALMOSTEMPTY 0 | ||
1409 | #define M_ALMOSTEMPTY 0xffff | ||
1410 | #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY) | ||
1411 | #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY) | ||
1412 | |||
319 | #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 | 1413 | #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 |
1414 | |||
1415 | #define S_ALMOSTFULL 0 | ||
1416 | #define M_ALMOSTFULL 0xffff | ||
1417 | #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL) | ||
1418 | #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL) | ||
1419 | |||
320 | #define A_ESPI_CALENDAR_LENGTH 0x898 | 1420 | #define A_ESPI_CALENDAR_LENGTH 0x898 |
321 | #define A_PORT_CONFIG 0x89c | 1421 | #define A_PORT_CONFIG 0x89c |
322 | 1422 | ||
323 | #define S_RX_NPORTS 0 | 1423 | #define S_RX_NPORTS 0 |
1424 | #define M_RX_NPORTS 0xff | ||
324 | #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) | 1425 | #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) |
1426 | #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS) | ||
325 | 1427 | ||
326 | #define S_TX_NPORTS 8 | 1428 | #define S_TX_NPORTS 8 |
1429 | #define M_TX_NPORTS 0xff | ||
327 | #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) | 1430 | #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) |
1431 | #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS) | ||
328 | 1432 | ||
329 | #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 | 1433 | #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 |
330 | 1434 | ||
@@ -332,12 +1436,124 @@ | |||
332 | #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) | 1436 | #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) |
333 | #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) | 1437 | #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) |
334 | 1438 | ||
1439 | #define S_TXDROPENABLE 1 | ||
1440 | #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE) | ||
1441 | #define F_TXDROPENABLE V_TXDROPENABLE(1U) | ||
1442 | |||
1443 | #define S_RXENDIANMODE 2 | ||
1444 | #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE) | ||
1445 | #define F_RXENDIANMODE V_RXENDIANMODE(1U) | ||
1446 | |||
1447 | #define S_TXENDIANMODE 3 | ||
1448 | #define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE) | ||
1449 | #define F_TXENDIANMODE V_TXENDIANMODE(1U) | ||
1450 | |||
335 | #define S_INTEL1010MODE 4 | 1451 | #define S_INTEL1010MODE 4 |
336 | #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) | 1452 | #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) |
337 | #define F_INTEL1010MODE V_INTEL1010MODE(1U) | 1453 | #define F_INTEL1010MODE V_INTEL1010MODE(1U) |
338 | 1454 | ||
339 | #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 | 1455 | #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 |
340 | #define A_ESPI_TRAIN 0x8ac | 1456 | #define A_ESPI_TRAIN 0x8ac |
1457 | |||
1458 | #define S_MAXTRAINALPHA 0 | ||
1459 | #define M_MAXTRAINALPHA 0xffff | ||
1460 | #define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA) | ||
1461 | #define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA) | ||
1462 | |||
1463 | #define S_MAXTRAINDATA 16 | ||
1464 | #define M_MAXTRAINDATA 0xffff | ||
1465 | #define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA) | ||
1466 | #define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA) | ||
1467 | |||
1468 | #define A_RAM_STATUS 0x8b0 | ||
1469 | |||
1470 | #define S_RXFIFOPARITYERROR 0 | ||
1471 | #define M_RXFIFOPARITYERROR 0x3ff | ||
1472 | #define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR) | ||
1473 | #define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR) | ||
1474 | |||
1475 | #define S_TXFIFOPARITYERROR 10 | ||
1476 | #define M_TXFIFOPARITYERROR 0x3ff | ||
1477 | #define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR) | ||
1478 | #define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR) | ||
1479 | |||
1480 | #define S_RXFIFOOVERFLOW 20 | ||
1481 | #define M_RXFIFOOVERFLOW 0x3ff | ||
1482 | #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW) | ||
1483 | #define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW) | ||
1484 | |||
1485 | #define A_TX_DROP_COUNT0 0x8b4 | ||
1486 | |||
1487 | #define S_TXPORT0DROPCNT 0 | ||
1488 | #define M_TXPORT0DROPCNT 0xffff | ||
1489 | #define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT) | ||
1490 | #define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT) | ||
1491 | |||
1492 | #define S_TXPORT1DROPCNT 16 | ||
1493 | #define M_TXPORT1DROPCNT 0xffff | ||
1494 | #define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT) | ||
1495 | #define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT) | ||
1496 | |||
1497 | #define A_TX_DROP_COUNT1 0x8b8 | ||
1498 | |||
1499 | #define S_TXPORT2DROPCNT 0 | ||
1500 | #define M_TXPORT2DROPCNT 0xffff | ||
1501 | #define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT) | ||
1502 | #define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT) | ||
1503 | |||
1504 | #define S_TXPORT3DROPCNT 16 | ||
1505 | #define M_TXPORT3DROPCNT 0xffff | ||
1506 | #define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT) | ||
1507 | #define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT) | ||
1508 | |||
1509 | #define A_RX_DROP_COUNT0 0x8bc | ||
1510 | |||
1511 | #define S_RXPORT0DROPCNT 0 | ||
1512 | #define M_RXPORT0DROPCNT 0xffff | ||
1513 | #define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT) | ||
1514 | #define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT) | ||
1515 | |||
1516 | #define S_RXPORT1DROPCNT 16 | ||
1517 | #define M_RXPORT1DROPCNT 0xffff | ||
1518 | #define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT) | ||
1519 | #define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT) | ||
1520 | |||
1521 | #define A_RX_DROP_COUNT1 0x8c0 | ||
1522 | |||
1523 | #define S_RXPORT2DROPCNT 0 | ||
1524 | #define M_RXPORT2DROPCNT 0xffff | ||
1525 | #define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT) | ||
1526 | #define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT) | ||
1527 | |||
1528 | #define S_RXPORT3DROPCNT 16 | ||
1529 | #define M_RXPORT3DROPCNT 0xffff | ||
1530 | #define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT) | ||
1531 | #define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT) | ||
1532 | |||
1533 | #define A_DIP4_ERROR_COUNT 0x8c4 | ||
1534 | |||
1535 | #define S_DIP4ERRORCNT 0 | ||
1536 | #define M_DIP4ERRORCNT 0xfff | ||
1537 | #define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT) | ||
1538 | #define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT) | ||
1539 | |||
1540 | #define S_DIP4ERRORCNTSHADOW 12 | ||
1541 | #define M_DIP4ERRORCNTSHADOW 0xfff | ||
1542 | #define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW) | ||
1543 | #define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW) | ||
1544 | |||
1545 | #define S_TRICN_RX_TRAIN_ERR 24 | ||
1546 | #define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR) | ||
1547 | #define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U) | ||
1548 | |||
1549 | #define S_TRICN_RX_TRAINING 25 | ||
1550 | #define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING) | ||
1551 | #define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U) | ||
1552 | |||
1553 | #define S_TRICN_RX_TRAIN_OK 26 | ||
1554 | #define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK) | ||
1555 | #define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U) | ||
1556 | |||
341 | #define A_ESPI_INTR_STATUS 0x8c8 | 1557 | #define A_ESPI_INTR_STATUS 0x8c8 |
342 | 1558 | ||
343 | #define S_DIP2PARITYERR 5 | 1559 | #define S_DIP2PARITYERR 5 |
@@ -347,19 +1563,56 @@ | |||
347 | #define A_ESPI_INTR_ENABLE 0x8cc | 1563 | #define A_ESPI_INTR_ENABLE 0x8cc |
348 | #define A_RX_DROP_THRESHOLD 0x8d0 | 1564 | #define A_RX_DROP_THRESHOLD 0x8d0 |
349 | #define A_ESPI_RX_RESET 0x8ec | 1565 | #define A_ESPI_RX_RESET 0x8ec |
1566 | |||
1567 | #define S_ESPI_RX_LNK_RST 0 | ||
1568 | #define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST) | ||
1569 | #define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U) | ||
1570 | |||
1571 | #define S_ESPI_RX_CORE_RST 1 | ||
1572 | #define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST) | ||
1573 | #define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U) | ||
1574 | |||
1575 | #define S_RX_CLK_STATUS 2 | ||
1576 | #define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS) | ||
1577 | #define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U) | ||
1578 | |||
350 | #define A_ESPI_MISC_CONTROL 0x8f0 | 1579 | #define A_ESPI_MISC_CONTROL 0x8f0 |
351 | 1580 | ||
352 | #define S_OUT_OF_SYNC_COUNT 0 | 1581 | #define S_OUT_OF_SYNC_COUNT 0 |
1582 | #define M_OUT_OF_SYNC_COUNT 0xf | ||
353 | #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) | 1583 | #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) |
1584 | #define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT) | ||
1585 | |||
1586 | #define S_DIP2_COUNT_MODE_ENABLE 4 | ||
1587 | #define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE) | ||
1588 | #define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U) | ||
354 | 1589 | ||
355 | #define S_DIP2_PARITY_ERR_THRES 5 | 1590 | #define S_DIP2_PARITY_ERR_THRES 5 |
1591 | #define M_DIP2_PARITY_ERR_THRES 0xf | ||
356 | #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) | 1592 | #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) |
1593 | #define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES) | ||
357 | 1594 | ||
358 | #define S_DIP4_THRES 9 | 1595 | #define S_DIP4_THRES 9 |
1596 | #define M_DIP4_THRES 0xfff | ||
359 | #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) | 1597 | #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) |
1598 | #define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES) | ||
1599 | |||
1600 | #define S_DIP4_THRES_ENABLE 21 | ||
1601 | #define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE) | ||
1602 | #define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U) | ||
1603 | |||
1604 | #define S_FORCE_DISABLE_STATUS 22 | ||
1605 | #define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS) | ||
1606 | #define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U) | ||
1607 | |||
1608 | #define S_DYNAMIC_DESKEW 23 | ||
1609 | #define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW) | ||
1610 | #define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U) | ||
360 | 1611 | ||
361 | #define S_MONITORED_PORT_NUM 25 | 1612 | #define S_MONITORED_PORT_NUM 25 |
1613 | #define M_MONITORED_PORT_NUM 0x3 | ||
362 | #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) | 1614 | #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) |
1615 | #define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM) | ||
363 | 1616 | ||
364 | #define S_MONITORED_DIRECTION 27 | 1617 | #define S_MONITORED_DIRECTION 27 |
365 | #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) | 1618 | #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) |
@@ -370,33 +1623,125 @@ | |||
370 | #define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) | 1623 | #define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) |
371 | 1624 | ||
372 | #define A_ESPI_DIP2_ERR_COUNT 0x8f4 | 1625 | #define A_ESPI_DIP2_ERR_COUNT 0x8f4 |
1626 | |||
1627 | #define S_DIP2_ERR_CNT 0 | ||
1628 | #define M_DIP2_ERR_CNT 0xf | ||
1629 | #define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT) | ||
1630 | #define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT) | ||
1631 | |||
373 | #define A_ESPI_CMD_ADDR 0x8f8 | 1632 | #define A_ESPI_CMD_ADDR 0x8f8 |
374 | 1633 | ||
375 | #define S_WRITE_DATA 0 | 1634 | #define S_WRITE_DATA 0 |
1635 | #define M_WRITE_DATA 0xff | ||
376 | #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) | 1636 | #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) |
1637 | #define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA) | ||
377 | 1638 | ||
378 | #define S_REGISTER_OFFSET 8 | 1639 | #define S_REGISTER_OFFSET 8 |
1640 | #define M_REGISTER_OFFSET 0xf | ||
379 | #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) | 1641 | #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) |
1642 | #define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET) | ||
380 | 1643 | ||
381 | #define S_CHANNEL_ADDR 12 | 1644 | #define S_CHANNEL_ADDR 12 |
1645 | #define M_CHANNEL_ADDR 0xf | ||
382 | #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) | 1646 | #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) |
1647 | #define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR) | ||
383 | 1648 | ||
384 | #define S_MODULE_ADDR 16 | 1649 | #define S_MODULE_ADDR 16 |
1650 | #define M_MODULE_ADDR 0x3 | ||
385 | #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) | 1651 | #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) |
1652 | #define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR) | ||
386 | 1653 | ||
387 | #define S_BUNDLE_ADDR 20 | 1654 | #define S_BUNDLE_ADDR 20 |
1655 | #define M_BUNDLE_ADDR 0x3 | ||
388 | #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) | 1656 | #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) |
1657 | #define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR) | ||
389 | 1658 | ||
390 | #define S_SPI4_COMMAND 24 | 1659 | #define S_SPI4_COMMAND 24 |
1660 | #define M_SPI4_COMMAND 0xff | ||
391 | #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) | 1661 | #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) |
1662 | #define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND) | ||
392 | 1663 | ||
393 | #define A_ESPI_GOSTAT 0x8fc | 1664 | #define A_ESPI_GOSTAT 0x8fc |
1665 | |||
1666 | #define S_READ_DATA 0 | ||
1667 | #define M_READ_DATA 0xff | ||
1668 | #define V_READ_DATA(x) ((x) << S_READ_DATA) | ||
1669 | #define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA) | ||
1670 | |||
394 | #define S_ESPI_CMD_BUSY 8 | 1671 | #define S_ESPI_CMD_BUSY 8 |
395 | #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) | 1672 | #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) |
396 | #define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) | 1673 | #define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) |
397 | 1674 | ||
398 | /* PL registers */ | 1675 | #define S_ERROR_ACK 9 |
1676 | #define V_ERROR_ACK(x) ((x) << S_ERROR_ACK) | ||
1677 | #define F_ERROR_ACK V_ERROR_ACK(1U) | ||
1678 | |||
1679 | #define S_UNMAPPED_ERR 10 | ||
1680 | #define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR) | ||
1681 | #define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U) | ||
1682 | |||
1683 | #define S_TRANSACTION_TIMER 16 | ||
1684 | #define M_TRANSACTION_TIMER 0xff | ||
1685 | #define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER) | ||
1686 | #define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER) | ||
1687 | |||
1688 | |||
1689 | /* ULP registers */ | ||
1690 | #define A_ULP_ULIMIT 0x980 | ||
1691 | #define A_ULP_TAGMASK 0x984 | ||
1692 | #define A_ULP_HREG_INDEX 0x988 | ||
1693 | #define A_ULP_HREG_DATA 0x98c | ||
1694 | #define A_ULP_INT_ENABLE 0x990 | ||
1695 | #define A_ULP_INT_CAUSE 0x994 | ||
399 | 1696 | ||
1697 | #define S_HREG_PAR_ERR 0 | ||
1698 | #define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR) | ||
1699 | #define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U) | ||
1700 | |||
1701 | #define S_EGRS_DATA_PAR_ERR 1 | ||
1702 | #define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR) | ||
1703 | #define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U) | ||
1704 | |||
1705 | #define S_INGRS_DATA_PAR_ERR 2 | ||
1706 | #define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR) | ||
1707 | #define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U) | ||
1708 | |||
1709 | #define S_PM_INTR 3 | ||
1710 | #define V_PM_INTR(x) ((x) << S_PM_INTR) | ||
1711 | #define F_PM_INTR V_PM_INTR(1U) | ||
1712 | |||
1713 | #define S_PM_E2C_SYNC_ERR 4 | ||
1714 | #define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR) | ||
1715 | #define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U) | ||
1716 | |||
1717 | #define S_PM_C2E_SYNC_ERR 5 | ||
1718 | #define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR) | ||
1719 | #define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U) | ||
1720 | |||
1721 | #define S_PM_E2C_EMPTY_ERR 6 | ||
1722 | #define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR) | ||
1723 | #define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U) | ||
1724 | |||
1725 | #define S_PM_C2E_EMPTY_ERR 7 | ||
1726 | #define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR) | ||
1727 | #define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U) | ||
1728 | |||
1729 | #define S_PM_PAR_ERR 8 | ||
1730 | #define M_PM_PAR_ERR 0xffff | ||
1731 | #define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR) | ||
1732 | #define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR) | ||
1733 | |||
1734 | #define S_PM_E2C_WRT_FULL 24 | ||
1735 | #define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL) | ||
1736 | #define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U) | ||
1737 | |||
1738 | #define S_PM_C2E_WRT_FULL 25 | ||
1739 | #define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL) | ||
1740 | #define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U) | ||
1741 | |||
1742 | #define A_ULP_PIO_CTRL 0x998 | ||
1743 | |||
1744 | /* PL registers */ | ||
400 | #define A_PL_ENABLE 0xa00 | 1745 | #define A_PL_ENABLE 0xa00 |
401 | 1746 | ||
402 | #define S_PL_INTR_SGE_ERR 0 | 1747 | #define S_PL_INTR_SGE_ERR 0 |
@@ -407,14 +1752,38 @@ | |||
407 | #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) | 1752 | #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) |
408 | #define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) | 1753 | #define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) |
409 | 1754 | ||
1755 | #define S_PL_INTR_MC3 2 | ||
1756 | #define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3) | ||
1757 | #define F_PL_INTR_MC3 V_PL_INTR_MC3(1U) | ||
1758 | |||
1759 | #define S_PL_INTR_MC4 3 | ||
1760 | #define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4) | ||
1761 | #define F_PL_INTR_MC4 V_PL_INTR_MC4(1U) | ||
1762 | |||
1763 | #define S_PL_INTR_MC5 4 | ||
1764 | #define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5) | ||
1765 | #define F_PL_INTR_MC5 V_PL_INTR_MC5(1U) | ||
1766 | |||
1767 | #define S_PL_INTR_RAT 5 | ||
1768 | #define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT) | ||
1769 | #define F_PL_INTR_RAT V_PL_INTR_RAT(1U) | ||
1770 | |||
410 | #define S_PL_INTR_TP 6 | 1771 | #define S_PL_INTR_TP 6 |
411 | #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) | 1772 | #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) |
412 | #define F_PL_INTR_TP V_PL_INTR_TP(1U) | 1773 | #define F_PL_INTR_TP V_PL_INTR_TP(1U) |
413 | 1774 | ||
1775 | #define S_PL_INTR_ULP 7 | ||
1776 | #define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP) | ||
1777 | #define F_PL_INTR_ULP V_PL_INTR_ULP(1U) | ||
1778 | |||
414 | #define S_PL_INTR_ESPI 8 | 1779 | #define S_PL_INTR_ESPI 8 |
415 | #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) | 1780 | #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) |
416 | #define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) | 1781 | #define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) |
417 | 1782 | ||
1783 | #define S_PL_INTR_CSPI 9 | ||
1784 | #define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI) | ||
1785 | #define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U) | ||
1786 | |||
418 | #define S_PL_INTR_PCIX 10 | 1787 | #define S_PL_INTR_PCIX 10 |
419 | #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) | 1788 | #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) |
420 | #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) | 1789 | #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) |
@@ -426,43 +1795,374 @@ | |||
426 | #define A_PL_CAUSE 0xa04 | 1795 | #define A_PL_CAUSE 0xa04 |
427 | 1796 | ||
428 | /* MC5 registers */ | 1797 | /* MC5 registers */ |
429 | |||
430 | #define A_MC5_CONFIG 0xc04 | 1798 | #define A_MC5_CONFIG 0xc04 |
431 | 1799 | ||
1800 | #define S_MODE 0 | ||
1801 | #define V_MODE(x) ((x) << S_MODE) | ||
1802 | #define F_MODE V_MODE(1U) | ||
1803 | |||
432 | #define S_TCAM_RESET 1 | 1804 | #define S_TCAM_RESET 1 |
433 | #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) | 1805 | #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) |
434 | #define F_TCAM_RESET V_TCAM_RESET(1U) | 1806 | #define F_TCAM_RESET V_TCAM_RESET(1U) |
435 | 1807 | ||
1808 | #define S_TCAM_READY 2 | ||
1809 | #define V_TCAM_READY(x) ((x) << S_TCAM_READY) | ||
1810 | #define F_TCAM_READY V_TCAM_READY(1U) | ||
1811 | |||
1812 | #define S_DBGI_ENABLE 4 | ||
1813 | #define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE) | ||
1814 | #define F_DBGI_ENABLE V_DBGI_ENABLE(1U) | ||
1815 | |||
436 | #define S_M_BUS_ENABLE 5 | 1816 | #define S_M_BUS_ENABLE 5 |
437 | #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) | 1817 | #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) |
438 | #define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) | 1818 | #define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) |
439 | 1819 | ||
440 | /* PCICFG registers */ | 1820 | #define S_PARITY_ENABLE 6 |
1821 | #define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE) | ||
1822 | #define F_PARITY_ENABLE V_PARITY_ENABLE(1U) | ||
1823 | |||
1824 | #define S_SYN_ISSUE_MODE 7 | ||
1825 | #define M_SYN_ISSUE_MODE 0x3 | ||
1826 | #define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE) | ||
1827 | #define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE) | ||
1828 | |||
1829 | #define S_BUILD 16 | ||
1830 | #define V_BUILD(x) ((x) << S_BUILD) | ||
1831 | #define F_BUILD V_BUILD(1U) | ||
1832 | |||
1833 | #define S_COMPRESSION_ENABLE 17 | ||
1834 | #define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE) | ||
1835 | #define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U) | ||
1836 | |||
1837 | #define S_NUM_LIP 18 | ||
1838 | #define M_NUM_LIP 0x3f | ||
1839 | #define V_NUM_LIP(x) ((x) << S_NUM_LIP) | ||
1840 | #define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP) | ||
1841 | |||
1842 | #define S_TCAM_PART_CNT 24 | ||
1843 | #define M_TCAM_PART_CNT 0x3 | ||
1844 | #define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT) | ||
1845 | #define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT) | ||
1846 | |||
1847 | #define S_TCAM_PART_TYPE 26 | ||
1848 | #define M_TCAM_PART_TYPE 0x3 | ||
1849 | #define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE) | ||
1850 | #define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE) | ||
1851 | |||
1852 | #define S_TCAM_PART_SIZE 28 | ||
1853 | #define M_TCAM_PART_SIZE 0x3 | ||
1854 | #define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE) | ||
1855 | #define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE) | ||
1856 | |||
1857 | #define S_TCAM_PART_TYPE_HI 30 | ||
1858 | #define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI) | ||
1859 | #define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U) | ||
1860 | |||
1861 | #define A_MC5_SIZE 0xc08 | ||
1862 | |||
1863 | #define S_SIZE 0 | ||
1864 | #define M_SIZE 0x3fffff | ||
1865 | #define V_SIZE(x) ((x) << S_SIZE) | ||
1866 | #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE) | ||
1867 | |||
1868 | #define A_MC5_ROUTING_TABLE_INDEX 0xc0c | ||
441 | 1869 | ||
1870 | #define S_START_OF_ROUTING_TABLE 0 | ||
1871 | #define M_START_OF_ROUTING_TABLE 0x3fffff | ||
1872 | #define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE) | ||
1873 | #define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE) | ||
1874 | |||
1875 | #define A_MC5_SERVER_INDEX 0xc14 | ||
1876 | |||
1877 | #define S_START_OF_SERVER_INDEX 0 | ||
1878 | #define M_START_OF_SERVER_INDEX 0x3fffff | ||
1879 | #define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX) | ||
1880 | #define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX) | ||
1881 | |||
1882 | #define A_MC5_LIP_RAM_ADDR 0xc18 | ||
1883 | |||
1884 | #define S_LOCAL_IP_RAM_ADDR 0 | ||
1885 | #define M_LOCAL_IP_RAM_ADDR 0x3f | ||
1886 | #define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR) | ||
1887 | #define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR) | ||
1888 | |||
1889 | #define S_RAM_WRITE_ENABLE 8 | ||
1890 | #define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE) | ||
1891 | #define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U) | ||
1892 | |||
1893 | #define A_MC5_LIP_RAM_DATA 0xc1c | ||
1894 | #define A_MC5_RSP_LATENCY 0xc20 | ||
1895 | |||
1896 | #define S_SEARCH_RESPONSE_LATENCY 0 | ||
1897 | #define M_SEARCH_RESPONSE_LATENCY 0x1f | ||
1898 | #define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY) | ||
1899 | #define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY) | ||
1900 | |||
1901 | #define S_LEARN_RESPONSE_LATENCY 8 | ||
1902 | #define M_LEARN_RESPONSE_LATENCY 0x1f | ||
1903 | #define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY) | ||
1904 | #define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY) | ||
1905 | |||
1906 | #define A_MC5_PARITY_LATENCY 0xc24 | ||
1907 | |||
1908 | #define S_SRCHLAT 0 | ||
1909 | #define M_SRCHLAT 0x1f | ||
1910 | #define V_SRCHLAT(x) ((x) << S_SRCHLAT) | ||
1911 | #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) | ||
1912 | |||
1913 | #define S_PARLAT 8 | ||
1914 | #define M_PARLAT 0x1f | ||
1915 | #define V_PARLAT(x) ((x) << S_PARLAT) | ||
1916 | #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) | ||
1917 | |||
1918 | #define A_MC5_WR_LRN_VERIFY 0xc28 | ||
1919 | |||
1920 | #define S_POVEREN 0 | ||
1921 | #define V_POVEREN(x) ((x) << S_POVEREN) | ||
1922 | #define F_POVEREN V_POVEREN(1U) | ||
1923 | |||
1924 | #define S_LRNVEREN 1 | ||
1925 | #define V_LRNVEREN(x) ((x) << S_LRNVEREN) | ||
1926 | #define F_LRNVEREN V_LRNVEREN(1U) | ||
1927 | |||
1928 | #define S_VWVEREN 2 | ||
1929 | #define V_VWVEREN(x) ((x) << S_VWVEREN) | ||
1930 | #define F_VWVEREN V_VWVEREN(1U) | ||
1931 | |||
1932 | #define A_MC5_PART_ID_INDEX 0xc2c | ||
1933 | |||
1934 | #define S_IDINDEX 0 | ||
1935 | #define M_IDINDEX 0xf | ||
1936 | #define V_IDINDEX(x) ((x) << S_IDINDEX) | ||
1937 | #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) | ||
1938 | |||
1939 | #define A_MC5_RESET_MAX 0xc30 | ||
1940 | |||
1941 | #define S_RSTMAX 0 | ||
1942 | #define M_RSTMAX 0x1ff | ||
1943 | #define V_RSTMAX(x) ((x) << S_RSTMAX) | ||
1944 | #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) | ||
1945 | |||
1946 | #define A_MC5_INT_ENABLE 0xc40 | ||
1947 | |||
1948 | #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0 | ||
1949 | #define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR) | ||
1950 | #define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U) | ||
1951 | |||
1952 | #define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1 | ||
1953 | #define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR) | ||
1954 | #define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U) | ||
1955 | |||
1956 | #define S_MC5_INT_HIT_IN_RT_REGION_ERR 2 | ||
1957 | #define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR) | ||
1958 | #define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U) | ||
1959 | |||
1960 | #define S_MC5_INT_MISS_ERR 3 | ||
1961 | #define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR) | ||
1962 | #define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U) | ||
1963 | |||
1964 | #define S_MC5_INT_LIP0_ERR 4 | ||
1965 | #define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR) | ||
1966 | #define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U) | ||
1967 | |||
1968 | #define S_MC5_INT_LIP_MISS_ERR 5 | ||
1969 | #define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR) | ||
1970 | #define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U) | ||
1971 | |||
1972 | #define S_MC5_INT_PARITY_ERR 6 | ||
1973 | #define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR) | ||
1974 | #define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U) | ||
1975 | |||
1976 | #define S_MC5_INT_ACTIVE_REGION_FULL 7 | ||
1977 | #define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL) | ||
1978 | #define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U) | ||
1979 | |||
1980 | #define S_MC5_INT_NFA_SRCH_ERR 8 | ||
1981 | #define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR) | ||
1982 | #define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U) | ||
1983 | |||
1984 | #define S_MC5_INT_SYN_COOKIE 9 | ||
1985 | #define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE) | ||
1986 | #define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U) | ||
1987 | |||
1988 | #define S_MC5_INT_SYN_COOKIE_BAD 10 | ||
1989 | #define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD) | ||
1990 | #define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U) | ||
1991 | |||
1992 | #define S_MC5_INT_SYN_COOKIE_OFF 11 | ||
1993 | #define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF) | ||
1994 | #define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U) | ||
1995 | |||
1996 | #define S_MC5_INT_UNKNOWN_CMD 15 | ||
1997 | #define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD) | ||
1998 | #define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U) | ||
1999 | |||
2000 | #define S_MC5_INT_REQUESTQ_PARITY_ERR 16 | ||
2001 | #define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR) | ||
2002 | #define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U) | ||
2003 | |||
2004 | #define S_MC5_INT_DISPATCHQ_PARITY_ERR 17 | ||
2005 | #define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR) | ||
2006 | #define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U) | ||
2007 | |||
2008 | #define S_MC5_INT_DEL_ACT_EMPTY 18 | ||
2009 | #define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY) | ||
2010 | #define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U) | ||
2011 | |||
2012 | #define A_MC5_INT_CAUSE 0xc44 | ||
2013 | #define A_MC5_INT_TID 0xc48 | ||
2014 | #define A_MC5_INT_PTID 0xc4c | ||
2015 | #define A_MC5_DBGI_CONFIG 0xc74 | ||
2016 | #define A_MC5_DBGI_REQ_CMD 0xc78 | ||
2017 | |||
2018 | #define S_CMDMODE 0 | ||
2019 | #define M_CMDMODE 0x7 | ||
2020 | #define V_CMDMODE(x) ((x) << S_CMDMODE) | ||
2021 | #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) | ||
2022 | |||
2023 | #define S_SADRSEL 4 | ||
2024 | #define V_SADRSEL(x) ((x) << S_SADRSEL) | ||
2025 | #define F_SADRSEL V_SADRSEL(1U) | ||
2026 | |||
2027 | #define S_WRITE_BURST_SIZE 22 | ||
2028 | #define M_WRITE_BURST_SIZE 0x3ff | ||
2029 | #define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE) | ||
2030 | #define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE) | ||
2031 | |||
2032 | #define A_MC5_DBGI_REQ_ADDR0 0xc7c | ||
2033 | #define A_MC5_DBGI_REQ_ADDR1 0xc80 | ||
2034 | #define A_MC5_DBGI_REQ_ADDR2 0xc84 | ||
2035 | #define A_MC5_DBGI_REQ_DATA0 0xc88 | ||
2036 | #define A_MC5_DBGI_REQ_DATA1 0xc8c | ||
2037 | #define A_MC5_DBGI_REQ_DATA2 0xc90 | ||
2038 | #define A_MC5_DBGI_REQ_DATA3 0xc94 | ||
2039 | #define A_MC5_DBGI_REQ_DATA4 0xc98 | ||
2040 | #define A_MC5_DBGI_REQ_MASK0 0xc9c | ||
2041 | #define A_MC5_DBGI_REQ_MASK1 0xca0 | ||
2042 | #define A_MC5_DBGI_REQ_MASK2 0xca4 | ||
2043 | #define A_MC5_DBGI_REQ_MASK3 0xca8 | ||
2044 | #define A_MC5_DBGI_REQ_MASK4 0xcac | ||
2045 | #define A_MC5_DBGI_RSP_STATUS 0xcb0 | ||
2046 | |||
2047 | #define S_DBGI_RSP_VALID 0 | ||
2048 | #define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID) | ||
2049 | #define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U) | ||
2050 | |||
2051 | #define S_DBGI_RSP_HIT 1 | ||
2052 | #define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT) | ||
2053 | #define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U) | ||
2054 | |||
2055 | #define S_DBGI_RSP_ERR 2 | ||
2056 | #define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR) | ||
2057 | #define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U) | ||
2058 | |||
2059 | #define S_DBGI_RSP_ERR_REASON 8 | ||
2060 | #define M_DBGI_RSP_ERR_REASON 0x7 | ||
2061 | #define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON) | ||
2062 | #define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON) | ||
2063 | |||
2064 | #define A_MC5_DBGI_RSP_DATA0 0xcb4 | ||
2065 | #define A_MC5_DBGI_RSP_DATA1 0xcb8 | ||
2066 | #define A_MC5_DBGI_RSP_DATA2 0xcbc | ||
2067 | #define A_MC5_DBGI_RSP_DATA3 0xcc0 | ||
2068 | #define A_MC5_DBGI_RSP_DATA4 0xcc4 | ||
2069 | #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8 | ||
2070 | #define A_MC5_POPEN_DATA_WR_CMD 0xccc | ||
2071 | #define A_MC5_POPEN_MASK_WR_CMD 0xcd0 | ||
2072 | #define A_MC5_AOPEN_SRCH_CMD 0xcd4 | ||
2073 | #define A_MC5_AOPEN_LRN_CMD 0xcd8 | ||
2074 | #define A_MC5_SYN_SRCH_CMD 0xcdc | ||
2075 | #define A_MC5_SYN_LRN_CMD 0xce0 | ||
2076 | #define A_MC5_ACK_SRCH_CMD 0xce4 | ||
2077 | #define A_MC5_ACK_LRN_CMD 0xce8 | ||
2078 | #define A_MC5_ILOOKUP_CMD 0xcec | ||
2079 | #define A_MC5_ELOOKUP_CMD 0xcf0 | ||
2080 | #define A_MC5_DATA_WRITE_CMD 0xcf4 | ||
2081 | #define A_MC5_DATA_READ_CMD 0xcf8 | ||
2082 | #define A_MC5_MASK_WRITE_CMD 0xcfc | ||
2083 | |||
2084 | /* PCICFG registers */ | ||
442 | #define A_PCICFG_PM_CSR 0x44 | 2085 | #define A_PCICFG_PM_CSR 0x44 |
443 | #define A_PCICFG_VPD_ADDR 0x4a | 2086 | #define A_PCICFG_VPD_ADDR 0x4a |
444 | 2087 | ||
2088 | #define S_VPD_ADDR 0 | ||
2089 | #define M_VPD_ADDR 0x7fff | ||
2090 | #define V_VPD_ADDR(x) ((x) << S_VPD_ADDR) | ||
2091 | #define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR) | ||
2092 | |||
445 | #define S_VPD_OP_FLAG 15 | 2093 | #define S_VPD_OP_FLAG 15 |
446 | #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) | 2094 | #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) |
447 | #define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) | 2095 | #define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) |
448 | 2096 | ||
449 | #define A_PCICFG_VPD_DATA 0x4c | 2097 | #define A_PCICFG_VPD_DATA 0x4c |
450 | 2098 | #define A_PCICFG_PCIX_CMD 0x60 | |
451 | #define A_PCICFG_INTR_ENABLE 0xf4 | 2099 | #define A_PCICFG_INTR_ENABLE 0xf4 |
452 | #define A_PCICFG_INTR_CAUSE 0xf8 | ||
453 | 2100 | ||
2101 | #define S_MASTER_PARITY_ERR 0 | ||
2102 | #define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR) | ||
2103 | #define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U) | ||
2104 | |||
2105 | #define S_SIG_TARGET_ABORT 1 | ||
2106 | #define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT) | ||
2107 | #define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U) | ||
2108 | |||
2109 | #define S_RCV_TARGET_ABORT 2 | ||
2110 | #define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT) | ||
2111 | #define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U) | ||
2112 | |||
2113 | #define S_RCV_MASTER_ABORT 3 | ||
2114 | #define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT) | ||
2115 | #define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U) | ||
2116 | |||
2117 | #define S_SIG_SYS_ERR 4 | ||
2118 | #define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR) | ||
2119 | #define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U) | ||
2120 | |||
2121 | #define S_DET_PARITY_ERR 5 | ||
2122 | #define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR) | ||
2123 | #define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U) | ||
2124 | |||
2125 | #define S_PIO_PARITY_ERR 6 | ||
2126 | #define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR) | ||
2127 | #define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U) | ||
2128 | |||
2129 | #define S_WF_PARITY_ERR 7 | ||
2130 | #define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR) | ||
2131 | #define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U) | ||
2132 | |||
2133 | #define S_RF_PARITY_ERR 8 | ||
2134 | #define M_RF_PARITY_ERR 0x3 | ||
2135 | #define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR) | ||
2136 | #define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR) | ||
2137 | |||
2138 | #define S_CF_PARITY_ERR 10 | ||
2139 | #define M_CF_PARITY_ERR 0x3 | ||
2140 | #define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR) | ||
2141 | #define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR) | ||
2142 | |||
2143 | #define A_PCICFG_INTR_CAUSE 0xf8 | ||
454 | #define A_PCICFG_MODE 0xfc | 2144 | #define A_PCICFG_MODE 0xfc |
455 | 2145 | ||
456 | #define S_PCI_MODE_64BIT 0 | 2146 | #define S_PCI_MODE_64BIT 0 |
457 | #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) | 2147 | #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) |
458 | #define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) | 2148 | #define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) |
459 | 2149 | ||
2150 | #define S_PCI_MODE_66MHZ 1 | ||
2151 | #define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ) | ||
2152 | #define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U) | ||
2153 | |||
2154 | #define S_PCI_MODE_PCIX_INITPAT 2 | ||
2155 | #define M_PCI_MODE_PCIX_INITPAT 0x7 | ||
2156 | #define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT) | ||
2157 | #define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT) | ||
2158 | |||
460 | #define S_PCI_MODE_PCIX 5 | 2159 | #define S_PCI_MODE_PCIX 5 |
461 | #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) | 2160 | #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) |
462 | #define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) | 2161 | #define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) |
463 | 2162 | ||
464 | #define S_PCI_MODE_CLK 6 | 2163 | #define S_PCI_MODE_CLK 6 |
465 | #define M_PCI_MODE_CLK 0x3 | 2164 | #define M_PCI_MODE_CLK 0x3 |
2165 | #define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK) | ||
466 | #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) | 2166 | #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) |
467 | 2167 | ||
468 | #endif /* _CXGB_REGS_H_ */ | 2168 | #endif /* _CXGB_REGS_H_ */ |