diff options
author | Francois Romieu <romieu@fr.zoreil.com> | 2006-12-11 17:47:00 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-02-05 16:58:43 -0500 |
commit | 356bd1460d1e1c4e433e4114fdac02139bddf17c (patch) | |
tree | 677c17fddfb7c66f29134c33f64463f15fc43824 /drivers/net/chelsio/elmer0.h | |
parent | b7d58394e65c7d90486026614a6ae26d82dd7756 (diff) |
chelsio: spaces, tabs and friends
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Diffstat (limited to 'drivers/net/chelsio/elmer0.h')
-rw-r--r-- | drivers/net/chelsio/elmer0.h | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/net/chelsio/elmer0.h b/drivers/net/chelsio/elmer0.h index 9ebecaa97d31..eef655c827d9 100644 --- a/drivers/net/chelsio/elmer0.h +++ b/drivers/net/chelsio/elmer0.h | |||
@@ -46,14 +46,14 @@ enum { | |||
46 | }; | 46 | }; |
47 | 47 | ||
48 | /* ELMER0 registers */ | 48 | /* ELMER0 registers */ |
49 | #define A_ELMER0_VERSION 0x100000 | 49 | #define A_ELMER0_VERSION 0x100000 |
50 | #define A_ELMER0_PHY_CFG 0x100004 | 50 | #define A_ELMER0_PHY_CFG 0x100004 |
51 | #define A_ELMER0_INT_ENABLE 0x100008 | 51 | #define A_ELMER0_INT_ENABLE 0x100008 |
52 | #define A_ELMER0_INT_CAUSE 0x10000c | 52 | #define A_ELMER0_INT_CAUSE 0x10000c |
53 | #define A_ELMER0_GPI_CFG 0x100010 | 53 | #define A_ELMER0_GPI_CFG 0x100010 |
54 | #define A_ELMER0_GPI_STAT 0x100014 | 54 | #define A_ELMER0_GPI_STAT 0x100014 |
55 | #define A_ELMER0_GPO 0x100018 | 55 | #define A_ELMER0_GPO 0x100018 |
56 | #define A_ELMER0_PORT0_MI1_CFG 0x400000 | 56 | #define A_ELMER0_PORT0_MI1_CFG 0x400000 |
57 | 57 | ||
58 | #define S_MI1_MDI_ENABLE 0 | 58 | #define S_MI1_MDI_ENABLE 0 |
59 | #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) | 59 | #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) |
@@ -111,18 +111,18 @@ enum { | |||
111 | #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) | 111 | #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) |
112 | #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) | 112 | #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) |
113 | 113 | ||
114 | #define A_ELMER0_PORT1_MI1_CFG 0x500000 | 114 | #define A_ELMER0_PORT1_MI1_CFG 0x500000 |
115 | #define A_ELMER0_PORT1_MI1_ADDR 0x500004 | 115 | #define A_ELMER0_PORT1_MI1_ADDR 0x500004 |
116 | #define A_ELMER0_PORT1_MI1_DATA 0x500008 | 116 | #define A_ELMER0_PORT1_MI1_DATA 0x500008 |
117 | #define A_ELMER0_PORT1_MI1_OP 0x50000c | 117 | #define A_ELMER0_PORT1_MI1_OP 0x50000c |
118 | #define A_ELMER0_PORT2_MI1_CFG 0x600000 | 118 | #define A_ELMER0_PORT2_MI1_CFG 0x600000 |
119 | #define A_ELMER0_PORT2_MI1_ADDR 0x600004 | 119 | #define A_ELMER0_PORT2_MI1_ADDR 0x600004 |
120 | #define A_ELMER0_PORT2_MI1_DATA 0x600008 | 120 | #define A_ELMER0_PORT2_MI1_DATA 0x600008 |
121 | #define A_ELMER0_PORT2_MI1_OP 0x60000c | 121 | #define A_ELMER0_PORT2_MI1_OP 0x60000c |
122 | #define A_ELMER0_PORT3_MI1_CFG 0x700000 | 122 | #define A_ELMER0_PORT3_MI1_CFG 0x700000 |
123 | #define A_ELMER0_PORT3_MI1_ADDR 0x700004 | 123 | #define A_ELMER0_PORT3_MI1_ADDR 0x700004 |
124 | #define A_ELMER0_PORT3_MI1_DATA 0x700008 | 124 | #define A_ELMER0_PORT3_MI1_DATA 0x700008 |
125 | #define A_ELMER0_PORT3_MI1_OP 0x70000c | 125 | #define A_ELMER0_PORT3_MI1_OP 0x70000c |
126 | 126 | ||
127 | /* Simple bit definition for GPI and GP0 registers. */ | 127 | /* Simple bit definition for GPI and GP0 registers. */ |
128 | #define ELMER0_GP_BIT0 0x0001 | 128 | #define ELMER0_GP_BIT0 0x0001 |