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authorChristoph Lameter <christoph@graphe.net>2005-03-30 16:34:31 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-05-15 19:15:02 -0400
commit8199d3a79c224bbe5943fa08684e1f93a17881b0 (patch)
tree77726ddade7ca4282bc12315abcb01fdf241be74 /drivers/net/chelsio/cpl5_cmd.h
parent88d7bd8cb9eb8d64bf7997600b0d64f7834047c5 (diff)
[PATCH] A new 10GB Ethernet Driver by Chelsio Communications
A Linux driver for the Chelsio 10Gb Ethernet Network Controller by Chelsio (http://www.chelsio.com). This driver supports the Chelsio N210 NIC and is backward compatible with the Chelsio N110 model 10Gb NICs. It supports AMD64, EM64T and x86 systems. Signed-off-by: Tina Yang <tinay@chelsio.com> Signed-off-by: Scott Bardone <sbardone@chelsio.com> Signed-off-by: Christoph Lameter <christoph@lameter.com> Adrian said: - my3126.c is unused (because t1_my3126_ops isn't used anywhere) - what are the EXTRA_CFLAGS in drivers/net/chelsio/Makefile for? - $(cxgb-y) in drivers/net/chelsio/Makefile seems to be unneeded - completely unused global functions: - espi.c: t1_espi_get_intr_counts - sge.c: t1_sge_get_intr_counts - the following functions can be made static: - sge.c: t1_espi_workaround - sge.c: t1_sge_tx - subr.c: __t1_tpi_read - subr.c: __t1_tpi_write - subr.c: t1_wait_op_done shemminger said: The performance recommendations in cxgb.txt are common to all fast devices, and should be in one file rather than just for this device. I would rather see ip-sysctl.txt updated or a new file on tuning recommendations started. Some of them have consequences that aren't documented well. For example, turning off TCP timestamps risks data corruption from sequence wrap. A new driver shouldn't need so may #ifdef's unless you want to putit on older vendor versions of 2.4 Some accessor and wrapper functions like: t1_pci_read_config_4 adapter_name t1_malloc are just annoying noise. Why have useless dead code like: /* Interrupt handler */ +static int pm3393_interrupt_handler(struct cmac *cmac) +{ + u32 master_intr_status; +/* + 1. Read master interrupt register. + 2. Read BLOCK's interrupt status registers. + 3. Handle BLOCK interrupts. +*/ Jeff said: step 1: kill all the OS wrappers. And do you really need hooks for multiple MACs, when only one MAC is really supported? Typically these hooks are at a higher level anyway -- struct net_device. From: Christoph Lameter <christoph@lameter Driver modified as suggested by Pekka Enberg, Stephen Hemminger and Andrian Bunk. Reduces the size of the driver to ~260k. - clean up tabs - removed my3126.c - removed 85% of suni1x10gexp_regs.h - removed 80% of regs.h - removed various calls, renamed variables/functions. - removed system specific and other wrappers (usleep, msleep) - removed dead code - dropped redundant casts in osdep.h - dropped redundant check of kfree - dropped weird code (MODVERSIONS stuff) - reduced number of #ifdefs - use kcalloc now instead of kmalloc - Add information about known issues with the driver - Add information about authors Signed-off-by: Scott Bardone <sbardone@chelsio.com> Signed-off-by: Christoph Lameter <christoph@lameter.com> Signed-off-by: Andrew Morton <akpm@osdl.org> diff -puN /dev/null Documentation/networking/cxgb.txt
Diffstat (limited to 'drivers/net/chelsio/cpl5_cmd.h')
-rw-r--r--drivers/net/chelsio/cpl5_cmd.h145
1 files changed, 145 insertions, 0 deletions
diff --git a/drivers/net/chelsio/cpl5_cmd.h b/drivers/net/chelsio/cpl5_cmd.h
new file mode 100644
index 000000000000..45e9248979f1
--- /dev/null
+++ b/drivers/net/chelsio/cpl5_cmd.h
@@ -0,0 +1,145 @@
1/*****************************************************************************
2 * *
3 * File: cpl5_cmd.h *
4 * $Revision: 1.4 $ *
5 * $Date: 2005/03/23 07:15:58 $ *
6 * Description: *
7 * part of the Chelsio 10Gb Ethernet Driver. *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License, version 2, as *
11 * published by the Free Software Foundation. *
12 * *
13 * You should have received a copy of the GNU General Public License along *
14 * with this program; if not, write to the Free Software Foundation, Inc., *
15 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
16 * *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
20 * *
21 * http://www.chelsio.com *
22 * *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
24 * All rights reserved. *
25 * *
26 * Maintainers: maintainers@chelsio.com *
27 * *
28 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
29 * Tina Yang <tainay@chelsio.com> *
30 * Felix Marti <felix@chelsio.com> *
31 * Scott Bardone <sbardone@chelsio.com> *
32 * Kurt Ottaway <kottaway@chelsio.com> *
33 * Frank DiMambro <frank@chelsio.com> *
34 * *
35 * History: *
36 * *
37 ****************************************************************************/
38
39#ifndef _CPL5_CMD_H
40#define _CPL5_CMD_H
41
42#include <asm/byteorder.h>
43
44#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
45#error "Adjust your <asm/byteorder.h> defines"
46#endif
47
48enum CPL_opcode {
49 CPL_RX_PKT = 0xAD,
50 CPL_TX_PKT = 0xB2,
51 CPL_TX_PKT_LSO = 0xB6,
52};
53
54enum { /* TX_PKT_LSO ethernet types */
55 CPL_ETH_II,
56 CPL_ETH_II_VLAN,
57 CPL_ETH_802_3,
58 CPL_ETH_802_3_VLAN
59};
60
61struct cpl_rx_data {
62 __u32 rsvd0;
63 __u32 len;
64 __u32 seq;
65 __u16 urg;
66 __u8 rsvd1;
67 __u8 status;
68};
69
70/*
71 * We want this header's alignment to be no more stringent than 2-byte aligned.
72 * All fields are u8 or u16 except for the length. However that field is not
73 * used so we break it into 2 16-bit parts to easily meet our alignment needs.
74 */
75struct cpl_tx_pkt {
76 __u8 opcode;
77#if defined(__LITTLE_ENDIAN_BITFIELD)
78 __u8 iff:4;
79 __u8 ip_csum_dis:1;
80 __u8 l4_csum_dis:1;
81 __u8 vlan_valid:1;
82 __u8 rsvd:1;
83#else
84 __u8 rsvd:1;
85 __u8 vlan_valid:1;
86 __u8 l4_csum_dis:1;
87 __u8 ip_csum_dis:1;
88 __u8 iff:4;
89#endif
90 __u16 vlan;
91 __u16 len_hi;
92 __u16 len_lo;
93};
94
95struct cpl_tx_pkt_lso {
96 __u8 opcode;
97#if defined(__LITTLE_ENDIAN_BITFIELD)
98 __u8 iff:4;
99 __u8 ip_csum_dis:1;
100 __u8 l4_csum_dis:1;
101 __u8 vlan_valid:1;
102 __u8 rsvd:1;
103#else
104 __u8 rsvd:1;
105 __u8 vlan_valid:1;
106 __u8 l4_csum_dis:1;
107 __u8 ip_csum_dis:1;
108 __u8 iff:4;
109#endif
110 __u16 vlan;
111 __u32 len;
112
113 __u32 rsvd2;
114 __u8 rsvd3;
115#if defined(__LITTLE_ENDIAN_BITFIELD)
116 __u8 tcp_hdr_words:4;
117 __u8 ip_hdr_words:4;
118#else
119 __u8 ip_hdr_words:4;
120 __u8 tcp_hdr_words:4;
121#endif
122 __u16 eth_type_mss;
123};
124
125struct cpl_rx_pkt {
126 __u8 opcode;
127#if defined(__LITTLE_ENDIAN_BITFIELD)
128 __u8 iff:4;
129 __u8 csum_valid:1;
130 __u8 bad_pkt:1;
131 __u8 vlan_valid:1;
132 __u8 rsvd:1;
133#else
134 __u8 rsvd:1;
135 __u8 vlan_valid:1;
136 __u8 bad_pkt:1;
137 __u8 csum_valid:1;
138 __u8 iff:4;
139#endif
140 __u16 csum;
141 __u16 vlan;
142 __u16 len;
143};
144
145#endif