diff options
| author | H. Peter Anvin <hpa@linux.intel.com> | 2009-02-23 17:05:56 -0500 |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2009-02-23 17:05:56 -0500 |
| commit | dc731ca60954310be0993e8992d450c7089fd13d (patch) | |
| tree | 6a997916f963d9e6dfa76fc5564296f57c3f909e /drivers/net/cassini.c | |
| parent | ec5b3d32437571b8a742069a4cfd04edb6b6eda5 (diff) | |
| parent | 20f4d6c3a2a23c5d7d9cc7f42fbb943ca7a03d1f (diff) | |
Merge branch 'x86/urgent' into x86/mce2
Diffstat (limited to 'drivers/net/cassini.c')
| -rw-r--r-- | drivers/net/cassini.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c index 840b3d1a22f5..bbbc3bb08aa5 100644 --- a/drivers/net/cassini.c +++ b/drivers/net/cassini.c | |||
| @@ -806,7 +806,7 @@ static int cas_reset_mii_phy(struct cas *cp) | |||
| 806 | 806 | ||
| 807 | cas_phy_write(cp, MII_BMCR, BMCR_RESET); | 807 | cas_phy_write(cp, MII_BMCR, BMCR_RESET); |
| 808 | udelay(100); | 808 | udelay(100); |
| 809 | while (limit--) { | 809 | while (--limit) { |
| 810 | val = cas_phy_read(cp, MII_BMCR); | 810 | val = cas_phy_read(cp, MII_BMCR); |
| 811 | if ((val & BMCR_RESET) == 0) | 811 | if ((val & BMCR_RESET) == 0) |
| 812 | break; | 812 | break; |
| @@ -979,7 +979,7 @@ static void cas_phy_init(struct cas *cp) | |||
| 979 | writel(val, cp->regs + REG_PCS_MII_CTRL); | 979 | writel(val, cp->regs + REG_PCS_MII_CTRL); |
| 980 | 980 | ||
| 981 | limit = STOP_TRIES; | 981 | limit = STOP_TRIES; |
| 982 | while (limit-- > 0) { | 982 | while (--limit > 0) { |
| 983 | udelay(10); | 983 | udelay(10); |
| 984 | if ((readl(cp->regs + REG_PCS_MII_CTRL) & | 984 | if ((readl(cp->regs + REG_PCS_MII_CTRL) & |
| 985 | PCS_MII_RESET) == 0) | 985 | PCS_MII_RESET) == 0) |