aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/cassini.c
diff options
context:
space:
mode:
authorJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
committerJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
commitd4ab4e6a23f805abb8fc3cc34525eec3788aeca1 (patch)
treeeefd82c155bc27469a85667d759cd90facf4a6e3 /drivers/net/cassini.c
parentc0fa797ae6cd02ff87c0bfe0d509368a3b45640e (diff)
parent96fd2d57b8252e16dfacf8941f7a74a6119197f5 (diff)
Merge branch 'master'; commit 'v2.6.39-rc3' into next
Diffstat (limited to 'drivers/net/cassini.c')
-rw-r--r--drivers/net/cassini.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index 3437613f0454..143a28c666af 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -51,7 +51,7 @@
51 * TX has 4 queues. currently these queues are used in a round-robin 51 * TX has 4 queues. currently these queues are used in a round-robin
52 * fashion for load balancing. They can also be used for QoS. for that 52 * fashion for load balancing. They can also be used for QoS. for that
53 * to work, however, QoS information needs to be exposed down to the driver 53 * to work, however, QoS information needs to be exposed down to the driver
54 * level so that subqueues get targetted to particular transmit rings. 54 * level so that subqueues get targeted to particular transmit rings.
55 * alternatively, the queues can be configured via use of the all-purpose 55 * alternatively, the queues can be configured via use of the all-purpose
56 * ioctl. 56 * ioctl.
57 * 57 *
@@ -5165,7 +5165,7 @@ err_out_free_res:
5165 pci_release_regions(pdev); 5165 pci_release_regions(pdev);
5166 5166
5167err_write_cacheline: 5167err_write_cacheline:
5168 /* Try to restore it in case the error occured after we 5168 /* Try to restore it in case the error occurred after we
5169 * set it. 5169 * set it.
5170 */ 5170 */
5171 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); 5171 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);