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authorholt@sgi.com <holt@sgi.com>2011-08-16 13:32:20 -0400
committerDavid S. Miller <davem@davemloft.net>2011-08-17 23:36:38 -0400
commit61e271ee64f1da6f69e56419ecf2ca7330884564 (patch)
treea6490f207c0485c55f6f7942fde8a013a733229b /drivers/net/can
parent12732c308340ad786d540b3a85f7b164189f2108 (diff)
flexcan: Abstract off read/write for big/little endian.
Make flexcan driver handle register reads in the appropriate endianess. This was a basic search and replace and then define some inlines. Signed-off-by: Robin Holt <holt@sgi.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Acked-by: Wolfgang Grandegger <wg@grandegger.com> Cc: U Bhaskar-B22300 <B22300@freescale.com> Cc: socketcan-core@lists.berlios.de Cc: netdev@vger.kernel.org Cc: PPC list <linuxppc-dev@lists.ozlabs.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/can')
-rw-r--r--drivers/net/can/flexcan.c140
1 files changed, 83 insertions, 57 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 586b2cdcee90..68cbe5243493 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -190,6 +190,31 @@ static struct can_bittiming_const flexcan_bittiming_const = {
190}; 190};
191 191
192/* 192/*
193 * Abstract off the read/write for arm versus ppc.
194 */
195#if defined(__BIG_ENDIAN)
196static inline u32 flexcan_read(void __iomem *addr)
197{
198 return in_be32(addr);
199}
200
201static inline void flexcan_write(u32 val, void __iomem *addr)
202{
203 out_be32(addr, val);
204}
205#else
206static inline u32 flexcan_read(void __iomem *addr)
207{
208 return readl(addr);
209}
210
211static inline void flexcan_write(u32 val, void __iomem *addr)
212{
213 writel(val, addr);
214}
215#endif
216
217/*
193 * Swtich transceiver on or off 218 * Swtich transceiver on or off
194 */ 219 */
195static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on) 220static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
@@ -210,9 +235,9 @@ static inline void flexcan_chip_enable(struct flexcan_priv *priv)
210 struct flexcan_regs __iomem *regs = priv->base; 235 struct flexcan_regs __iomem *regs = priv->base;
211 u32 reg; 236 u32 reg;
212 237
213 reg = readl(&regs->mcr); 238 reg = flexcan_read(&regs->mcr);
214 reg &= ~FLEXCAN_MCR_MDIS; 239 reg &= ~FLEXCAN_MCR_MDIS;
215 writel(reg, &regs->mcr); 240 flexcan_write(reg, &regs->mcr);
216 241
217 udelay(10); 242 udelay(10);
218} 243}
@@ -222,9 +247,9 @@ static inline void flexcan_chip_disable(struct flexcan_priv *priv)
222 struct flexcan_regs __iomem *regs = priv->base; 247 struct flexcan_regs __iomem *regs = priv->base;
223 u32 reg; 248 u32 reg;
224 249
225 reg = readl(&regs->mcr); 250 reg = flexcan_read(&regs->mcr);
226 reg |= FLEXCAN_MCR_MDIS; 251 reg |= FLEXCAN_MCR_MDIS;
227 writel(reg, &regs->mcr); 252 flexcan_write(reg, &regs->mcr);
228} 253}
229 254
230static int flexcan_get_berr_counter(const struct net_device *dev, 255static int flexcan_get_berr_counter(const struct net_device *dev,
@@ -232,7 +257,7 @@ static int flexcan_get_berr_counter(const struct net_device *dev,
232{ 257{
233 const struct flexcan_priv *priv = netdev_priv(dev); 258 const struct flexcan_priv *priv = netdev_priv(dev);
234 struct flexcan_regs __iomem *regs = priv->base; 259 struct flexcan_regs __iomem *regs = priv->base;
235 u32 reg = readl(&regs->ecr); 260 u32 reg = flexcan_read(&regs->ecr);
236 261
237 bec->txerr = (reg >> 0) & 0xff; 262 bec->txerr = (reg >> 0) & 0xff;
238 bec->rxerr = (reg >> 8) & 0xff; 263 bec->rxerr = (reg >> 8) & 0xff;
@@ -266,15 +291,15 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
266 291
267 if (cf->can_dlc > 0) { 292 if (cf->can_dlc > 0) {
268 u32 data = be32_to_cpup((__be32 *)&cf->data[0]); 293 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
269 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); 294 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
270 } 295 }
271 if (cf->can_dlc > 3) { 296 if (cf->can_dlc > 3) {
272 u32 data = be32_to_cpup((__be32 *)&cf->data[4]); 297 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
273 writel(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); 298 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
274 } 299 }
275 300
276 writel(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id); 301 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
277 writel(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); 302 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
278 303
279 kfree_skb(skb); 304 kfree_skb(skb);
280 305
@@ -462,8 +487,8 @@ static void flexcan_read_fifo(const struct net_device *dev,
462 struct flexcan_mb __iomem *mb = &regs->cantxfg[0]; 487 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
463 u32 reg_ctrl, reg_id; 488 u32 reg_ctrl, reg_id;
464 489
465 reg_ctrl = readl(&mb->can_ctrl); 490 reg_ctrl = flexcan_read(&mb->can_ctrl);
466 reg_id = readl(&mb->can_id); 491 reg_id = flexcan_read(&mb->can_id);
467 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 492 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
468 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 493 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
469 else 494 else
@@ -473,12 +498,12 @@ static void flexcan_read_fifo(const struct net_device *dev,
473 cf->can_id |= CAN_RTR_FLAG; 498 cf->can_id |= CAN_RTR_FLAG;
474 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); 499 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
475 500
476 *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0])); 501 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
477 *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1])); 502 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
478 503
479 /* mark as read */ 504 /* mark as read */
480 writel(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1); 505 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
481 readl(&regs->timer); 506 flexcan_read(&regs->timer);
482} 507}
483 508
484static int flexcan_read_frame(struct net_device *dev) 509static int flexcan_read_frame(struct net_device *dev)
@@ -514,17 +539,17 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
514 * The error bits are cleared on read, 539 * The error bits are cleared on read,
515 * use saved value from irq handler. 540 * use saved value from irq handler.
516 */ 541 */
517 reg_esr = readl(&regs->esr) | priv->reg_esr; 542 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
518 543
519 /* handle state changes */ 544 /* handle state changes */
520 work_done += flexcan_poll_state(dev, reg_esr); 545 work_done += flexcan_poll_state(dev, reg_esr);
521 546
522 /* handle RX-FIFO */ 547 /* handle RX-FIFO */
523 reg_iflag1 = readl(&regs->iflag1); 548 reg_iflag1 = flexcan_read(&regs->iflag1);
524 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && 549 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
525 work_done < quota) { 550 work_done < quota) {
526 work_done += flexcan_read_frame(dev); 551 work_done += flexcan_read_frame(dev);
527 reg_iflag1 = readl(&regs->iflag1); 552 reg_iflag1 = flexcan_read(&regs->iflag1);
528 } 553 }
529 554
530 /* report bus errors */ 555 /* report bus errors */
@@ -534,8 +559,8 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
534 if (work_done < quota) { 559 if (work_done < quota) {
535 napi_complete(napi); 560 napi_complete(napi);
536 /* enable IRQs */ 561 /* enable IRQs */
537 writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1); 562 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
538 writel(priv->reg_ctrl_default, &regs->ctrl); 563 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
539 } 564 }
540 565
541 return work_done; 566 return work_done;
@@ -549,9 +574,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
549 struct flexcan_regs __iomem *regs = priv->base; 574 struct flexcan_regs __iomem *regs = priv->base;
550 u32 reg_iflag1, reg_esr; 575 u32 reg_iflag1, reg_esr;
551 576
552 reg_iflag1 = readl(&regs->iflag1); 577 reg_iflag1 = flexcan_read(&regs->iflag1);
553 reg_esr = readl(&regs->esr); 578 reg_esr = flexcan_read(&regs->esr);
554 writel(FLEXCAN_ESR_ERR_INT, &regs->esr); /* ACK err IRQ */ 579 flexcan_write(FLEXCAN_ESR_ERR_INT, &regs->esr); /* ACK err IRQ */
555 580
556 /* 581 /*
557 * schedule NAPI in case of: 582 * schedule NAPI in case of:
@@ -567,16 +592,16 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
567 * save them for later use. 592 * save them for later use.
568 */ 593 */
569 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; 594 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
570 writel(FLEXCAN_IFLAG_DEFAULT & ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, 595 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
571 &regs->imask1); 596 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
572 writel(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 597 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
573 &regs->ctrl); 598 &regs->ctrl);
574 napi_schedule(&priv->napi); 599 napi_schedule(&priv->napi);
575 } 600 }
576 601
577 /* FIFO overflow */ 602 /* FIFO overflow */
578 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 603 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
579 writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1); 604 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
580 dev->stats.rx_over_errors++; 605 dev->stats.rx_over_errors++;
581 dev->stats.rx_errors++; 606 dev->stats.rx_errors++;
582 } 607 }
@@ -585,7 +610,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
585 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { 610 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
586 /* tx_bytes is incremented in flexcan_start_xmit */ 611 /* tx_bytes is incremented in flexcan_start_xmit */
587 stats->tx_packets++; 612 stats->tx_packets++;
588 writel((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1); 613 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
589 netif_wake_queue(dev); 614 netif_wake_queue(dev);
590 } 615 }
591 616
@@ -599,7 +624,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
599 struct flexcan_regs __iomem *regs = priv->base; 624 struct flexcan_regs __iomem *regs = priv->base;
600 u32 reg; 625 u32 reg;
601 626
602 reg = readl(&regs->ctrl); 627 reg = flexcan_read(&regs->ctrl);
603 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 628 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
604 FLEXCAN_CTRL_RJW(0x3) | 629 FLEXCAN_CTRL_RJW(0x3) |
605 FLEXCAN_CTRL_PSEG1(0x7) | 630 FLEXCAN_CTRL_PSEG1(0x7) |
@@ -623,11 +648,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
623 reg |= FLEXCAN_CTRL_SMP; 648 reg |= FLEXCAN_CTRL_SMP;
624 649
625 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg); 650 dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg);
626 writel(reg, &regs->ctrl); 651 flexcan_write(reg, &regs->ctrl);
627 652
628 /* print chip status */ 653 /* print chip status */
629 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 654 dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
630 readl(&regs->mcr), readl(&regs->ctrl)); 655 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
631} 656}
632 657
633/* 658/*
@@ -648,10 +673,10 @@ static int flexcan_chip_start(struct net_device *dev)
648 flexcan_chip_enable(priv); 673 flexcan_chip_enable(priv);
649 674
650 /* soft reset */ 675 /* soft reset */
651 writel(FLEXCAN_MCR_SOFTRST, &regs->mcr); 676 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
652 udelay(10); 677 udelay(10);
653 678
654 reg_mcr = readl(&regs->mcr); 679 reg_mcr = flexcan_read(&regs->mcr);
655 if (reg_mcr & FLEXCAN_MCR_SOFTRST) { 680 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
656 dev_err(dev->dev.parent, 681 dev_err(dev->dev.parent,
657 "Failed to softreset can module (mcr=0x%08x)\n", 682 "Failed to softreset can module (mcr=0x%08x)\n",
@@ -673,12 +698,12 @@ static int flexcan_chip_start(struct net_device *dev)
673 * choose format C 698 * choose format C
674 * 699 *
675 */ 700 */
676 reg_mcr = readl(&regs->mcr); 701 reg_mcr = flexcan_read(&regs->mcr);
677 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | 702 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
678 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | 703 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
679 FLEXCAN_MCR_IDAM_C; 704 FLEXCAN_MCR_IDAM_C;
680 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr); 705 dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
681 writel(reg_mcr, &regs->mcr); 706 flexcan_write(reg_mcr, &regs->mcr);
682 707
683 /* 708 /*
684 * CTRL 709 * CTRL
@@ -696,7 +721,7 @@ static int flexcan_chip_start(struct net_device *dev)
696 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any 721 * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
697 * warning or bus passive interrupts. 722 * warning or bus passive interrupts.
698 */ 723 */
699 reg_ctrl = readl(&regs->ctrl); 724 reg_ctrl = flexcan_read(&regs->ctrl);
700 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 725 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
701 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 726 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
702 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK; 727 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
@@ -704,38 +729,39 @@ static int flexcan_chip_start(struct net_device *dev)
704 /* save for later use */ 729 /* save for later use */
705 priv->reg_ctrl_default = reg_ctrl; 730 priv->reg_ctrl_default = reg_ctrl;
706 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 731 dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
707 writel(reg_ctrl, &regs->ctrl); 732 flexcan_write(reg_ctrl, &regs->ctrl);
708 733
709 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) { 734 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
710 writel(0, &regs->cantxfg[i].can_ctrl); 735 flexcan_write(0, &regs->cantxfg[i].can_ctrl);
711 writel(0, &regs->cantxfg[i].can_id); 736 flexcan_write(0, &regs->cantxfg[i].can_id);
712 writel(0, &regs->cantxfg[i].data[0]); 737 flexcan_write(0, &regs->cantxfg[i].data[0]);
713 writel(0, &regs->cantxfg[i].data[1]); 738 flexcan_write(0, &regs->cantxfg[i].data[1]);
714 739
715 /* put MB into rx queue */ 740 /* put MB into rx queue */
716 writel(FLEXCAN_MB_CNT_CODE(0x4), &regs->cantxfg[i].can_ctrl); 741 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
742 &regs->cantxfg[i].can_ctrl);
717 } 743 }
718 744
719 /* acceptance mask/acceptance code (accept everything) */ 745 /* acceptance mask/acceptance code (accept everything) */
720 writel(0x0, &regs->rxgmask); 746 flexcan_write(0x0, &regs->rxgmask);
721 writel(0x0, &regs->rx14mask); 747 flexcan_write(0x0, &regs->rx14mask);
722 writel(0x0, &regs->rx15mask); 748 flexcan_write(0x0, &regs->rx15mask);
723 749
724 flexcan_transceiver_switch(priv, 1); 750 flexcan_transceiver_switch(priv, 1);
725 751
726 /* synchronize with the can bus */ 752 /* synchronize with the can bus */
727 reg_mcr = readl(&regs->mcr); 753 reg_mcr = flexcan_read(&regs->mcr);
728 reg_mcr &= ~FLEXCAN_MCR_HALT; 754 reg_mcr &= ~FLEXCAN_MCR_HALT;
729 writel(reg_mcr, &regs->mcr); 755 flexcan_write(reg_mcr, &regs->mcr);
730 756
731 priv->can.state = CAN_STATE_ERROR_ACTIVE; 757 priv->can.state = CAN_STATE_ERROR_ACTIVE;
732 758
733 /* enable FIFO interrupts */ 759 /* enable FIFO interrupts */
734 writel(FLEXCAN_IFLAG_DEFAULT, &regs->imask1); 760 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
735 761
736 /* print chip status */ 762 /* print chip status */
737 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n", 763 dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n",
738 __func__, readl(&regs->mcr), readl(&regs->ctrl)); 764 __func__, flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
739 765
740 return 0; 766 return 0;
741 767
@@ -757,12 +783,12 @@ static void flexcan_chip_stop(struct net_device *dev)
757 u32 reg; 783 u32 reg;
758 784
759 /* Disable all interrupts */ 785 /* Disable all interrupts */
760 writel(0, &regs->imask1); 786 flexcan_write(0, &regs->imask1);
761 787
762 /* Disable + halt module */ 788 /* Disable + halt module */
763 reg = readl(&regs->mcr); 789 reg = flexcan_read(&regs->mcr);
764 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; 790 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
765 writel(reg, &regs->mcr); 791 flexcan_write(reg, &regs->mcr);
766 792
767 flexcan_transceiver_switch(priv, 0); 793 flexcan_transceiver_switch(priv, 0);
768 priv->can.state = CAN_STATE_STOPPED; 794 priv->can.state = CAN_STATE_STOPPED;
@@ -854,24 +880,24 @@ static int __devinit register_flexcandev(struct net_device *dev)
854 880
855 /* select "bus clock", chip must be disabled */ 881 /* select "bus clock", chip must be disabled */
856 flexcan_chip_disable(priv); 882 flexcan_chip_disable(priv);
857 reg = readl(&regs->ctrl); 883 reg = flexcan_read(&regs->ctrl);
858 reg |= FLEXCAN_CTRL_CLK_SRC; 884 reg |= FLEXCAN_CTRL_CLK_SRC;
859 writel(reg, &regs->ctrl); 885 flexcan_write(reg, &regs->ctrl);
860 886
861 flexcan_chip_enable(priv); 887 flexcan_chip_enable(priv);
862 888
863 /* set freeze, halt and activate FIFO, restrict register access */ 889 /* set freeze, halt and activate FIFO, restrict register access */
864 reg = readl(&regs->mcr); 890 reg = flexcan_read(&regs->mcr);
865 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | 891 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
866 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 892 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
867 writel(reg, &regs->mcr); 893 flexcan_write(reg, &regs->mcr);
868 894
869 /* 895 /*
870 * Currently we only support newer versions of this core 896 * Currently we only support newer versions of this core
871 * featuring a RX FIFO. Older cores found on some Coldfire 897 * featuring a RX FIFO. Older cores found on some Coldfire
872 * derivates are not yet supported. 898 * derivates are not yet supported.
873 */ 899 */
874 reg = readl(&regs->mcr); 900 reg = flexcan_read(&regs->mcr);
875 if (!(reg & FLEXCAN_MCR_FEN)) { 901 if (!(reg & FLEXCAN_MCR_FEN)) {
876 dev_err(dev->dev.parent, 902 dev_err(dev->dev.parent,
877 "Could not enable RX FIFO, unsupported core\n"); 903 "Could not enable RX FIFO, unsupported core\n");