diff options
author | Tomoya <tomoya-linux@dsn.okisemi.com> | 2010-11-17 09:06:25 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-11-18 15:07:30 -0500 |
commit | 0a80410dc53cf68e56456bef1ca66949b87412f9 (patch) | |
tree | 94211a5b8a110b3942a01405cfd1d4217f9f9dc1 /drivers/net/can | |
parent | 086b5650dcdaae7c4aa60a5d0724f775e733610e (diff) |
can: EG20T PCH: use BIT(X)
Replace bit assignment value to BIT(X).
For easy to readable/identifiable, replace all bit assigned macros to BIT(X)
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/can')
-rw-r--r-- | drivers/net/can/pch_can.c | 73 |
1 files changed, 37 insertions, 36 deletions
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c index c523e3dd5d10..238622a04bc1 100644 --- a/drivers/net/can/pch_can.c +++ b/drivers/net/can/pch_can.c | |||
@@ -38,50 +38,51 @@ | |||
38 | 38 | ||
39 | #define PCH_ENABLE 1 /* The enable flag */ | 39 | #define PCH_ENABLE 1 /* The enable flag */ |
40 | #define PCH_DISABLE 0 /* The disable flag */ | 40 | #define PCH_DISABLE 0 /* The disable flag */ |
41 | #define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */ | 41 | #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */ |
42 | #define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */ | 42 | #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */ |
43 | #define PCH_CTRL_IE_SIE_EIE 0x000e | 43 | #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1)) |
44 | #define PCH_CTRL_CCE 0x0040 | 44 | #define PCH_CTRL_CCE BIT(6) |
45 | #define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */ | 45 | #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */ |
46 | #define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */ | 46 | #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */ |
47 | #define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */ | 47 | #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */ |
48 | |||
48 | #define PCH_CMASK_RX_TX_SET 0x00f3 | 49 | #define PCH_CMASK_RX_TX_SET 0x00f3 |
49 | #define PCH_CMASK_RX_TX_GET 0x0073 | 50 | #define PCH_CMASK_RX_TX_GET 0x0073 |
50 | #define PCH_CMASK_ALL 0xff | 51 | #define PCH_CMASK_ALL 0xff |
51 | #define PCH_CMASK_RDWR 0x80 | 52 | #define PCH_CMASK_NEWDAT BIT(2) |
52 | #define PCH_CMASK_ARB 0x20 | 53 | #define PCH_CMASK_CLRINTPND BIT(3) |
53 | #define PCH_CMASK_CTRL 0x10 | 54 | #define PCH_CMASK_CTRL BIT(4) |
54 | #define PCH_CMASK_MASK 0x40 | 55 | #define PCH_CMASK_ARB BIT(5) |
55 | #define PCH_CMASK_NEWDAT 0x04 | 56 | #define PCH_CMASK_MASK BIT(6) |
56 | #define PCH_CMASK_CLRINTPND 0x08 | 57 | #define PCH_CMASK_RDWR BIT(7) |
57 | #define PCH_IF_MCONT_NEWDAT 0x8000 | 58 | #define PCH_IF_MCONT_NEWDAT BIT(15) |
58 | #define PCH_IF_MCONT_INTPND 0x2000 | 59 | #define PCH_IF_MCONT_MSGLOST BIT(14) |
59 | #define PCH_IF_MCONT_UMASK 0x1000 | 60 | #define PCH_IF_MCONT_INTPND BIT(13) |
60 | #define PCH_IF_MCONT_TXIE 0x0800 | 61 | #define PCH_IF_MCONT_UMASK BIT(12) |
61 | #define PCH_IF_MCONT_RXIE 0x0400 | 62 | #define PCH_IF_MCONT_TXIE BIT(11) |
62 | #define PCH_IF_MCONT_RMTEN 0x0200 | 63 | #define PCH_IF_MCONT_RXIE BIT(10) |
63 | #define PCH_IF_MCONT_TXRQXT 0x0100 | 64 | #define PCH_IF_MCONT_RMTEN BIT(9) |
64 | #define PCH_IF_MCONT_EOB 0x0080 | 65 | #define PCH_IF_MCONT_TXRQXT BIT(8) |
65 | #define PCH_IF_MCONT_DLC 0x000f | 66 | #define PCH_IF_MCONT_EOB BIT(7) |
66 | #define PCH_IF_MCONT_MSGLOST 0x4000 | 67 | #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3)) |
67 | #define PCH_MASK2_MDIR_MXTD 0xc000 | 68 | #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15)) |
68 | #define PCH_ID2_DIR 0x2000 | 69 | #define PCH_ID2_DIR BIT(13) |
69 | #define PCH_ID2_XTD 0x4000 | 70 | #define PCH_ID2_XTD BIT(14) |
70 | #define PCH_ID_MSGVAL 0x8000 | 71 | #define PCH_ID_MSGVAL BIT(15) |
71 | #define PCH_IF_CREQ_BUSY 0x8000 | 72 | #define PCH_IF_CREQ_BUSY BIT(15) |
72 | 73 | ||
73 | #define PCH_STATUS_INT 0x8000 | 74 | #define PCH_STATUS_INT 0x8000 |
74 | #define PCH_REC 0x00007f00 | 75 | #define PCH_REC 0x00007f00 |
75 | #define PCH_TEC 0x000000ff | 76 | #define PCH_TEC 0x000000ff |
76 | 77 | ||
77 | #define PCH_RX_OK 0x00000010 | 78 | #define PCH_TX_OK BIT(3) |
78 | #define PCH_TX_OK 0x00000008 | 79 | #define PCH_RX_OK BIT(4) |
79 | #define PCH_BUS_OFF 0x00000080 | 80 | #define PCH_EPASSIV BIT(5) |
80 | #define PCH_EWARN 0x00000040 | 81 | #define PCH_EWARN BIT(6) |
81 | #define PCH_EPASSIV 0x00000020 | 82 | #define PCH_BUS_OFF BIT(7) |
82 | #define PCH_LEC0 0x00000001 | 83 | #define PCH_LEC0 BIT(0) |
83 | #define PCH_LEC1 0x00000002 | 84 | #define PCH_LEC1 BIT(1) |
84 | #define PCH_LEC2 0x00000004 | 85 | #define PCH_LEC2 BIT(2) |
85 | #define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2) | 86 | #define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2) |
86 | #define PCH_STUF_ERR PCH_LEC0 | 87 | #define PCH_STUF_ERR PCH_LEC0 |
87 | #define PCH_FORM_ERR PCH_LEC1 | 88 | #define PCH_FORM_ERR PCH_LEC1 |