net/can/mscan: replace hardcoded values with defines

Not all hardcoded values have been replaced as this made the code quite
unreadable. IMHO this compromise serves the purpose of readability.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>

2 files changed, 15 insertions, 5 deletions

diff --git a/drivers/net/can/mscan/mscan.c b/drivers/net/can/mscan/mscan.c
index 20d1991b9094..263d1a9f0880 100644
--- a/drivers/net/can/mscan/mscan.c
+++ b/drivers/net/can/mscan/mscan.c
@@ -211,18 +211,23 @@ static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         rtr = frame->can_id & CAN_RTR_FLAG;
 
+        /* RTR is always the lowest bit of interest, then IDs follow */
         if (frame->can_id & CAN_EFF_FLAG) {
-                can_id = (frame->can_id & CAN_EFF_MASK) << 1;
+                can_id = (frame->can_id & CAN_EFF_MASK)
+                         << (MSCAN_EFF_RTR_SHIFT + 1);
                 if (rtr)
-                        can_id |= 1;
+                        can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
                 out_be16(&regs->tx.idr3_2, can_id);
 
                 can_id >>= 16;
-                can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) | (3 << 3);
+                /* EFF_FLAGS are inbetween the IDs :( */
+                can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
+                         | MSCAN_EFF_FLAGS;
         } else {
-                can_id = (frame->can_id & CAN_SFF_MASK) << 5;
+                can_id = (frame->can_id & CAN_SFF_MASK)
+                         << (MSCAN_SFF_RTR_SHIFT + 1);
                 if (rtr)
-                        can_id |= 1 << 4;
+                        can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
         }
         out_be16(&regs->tx.idr1_0, can_id);
 
diff --git a/drivers/net/can/mscan/mscan.h b/drivers/net/can/mscan/mscan.h
index 20180007fe3d..00fc4aaf1ed8 100644
--- a/drivers/net/can/mscan/mscan.h
+++ b/drivers/net/can/mscan/mscan.h
@@ -131,6 +131,11 @@
 /* MSCAN Miscellaneous Register (CANMISC) bits */
 #define MSCAN_BOHOLD            0x01
 
+/* MSCAN Identifier Register (IDR) bits */
+#define MSCAN_SFF_RTR_SHIFT     4
+#define MSCAN_EFF_RTR_SHIFT     0
+#define MSCAN_EFF_FLAGS         0x18    /* IDE + SRR */
+
 #ifdef MSCAN_FOR_MPC5200
 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
 #define _MSCAN_RESERVED_DSR_SIZE        2