diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 03:37:16 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:31:42 -0500 |
commit | 052a38e096dece43e38a19a896ae7ad019415bc1 (patch) | |
tree | 127b34c6948872a535bfc13e102d852515c44679 /drivers/net/bnx2x_reg.h | |
parent | c2c8b03e200bdda3ba23d27f5c33bac784dced01 (diff) |
bnx2x: Using registers name
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
-rw-r--r-- | drivers/net/bnx2x_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 08e703dc2b46..360a2564aa98 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -5239,6 +5239,7 @@ | |||
5239 | #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 | 5239 | #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 |
5240 | #define HW_LOCK_RESOURCE_SPIO 2 | 5240 | #define HW_LOCK_RESOURCE_SPIO 2 |
5241 | #define HW_LOCK_RESOURCE_UNDI 5 | 5241 | #define HW_LOCK_RESOURCE_UNDI 5 |
5242 | #define PRS_FLAG_OVERETH_IPV4 1 | ||
5242 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) | 5243 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) |
5243 | #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) | 5244 | #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) |
5244 | #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) | 5245 | #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) |
@@ -5861,6 +5862,10 @@ Theotherbitsarereservedandshouldbezero*/ | |||
5861 | #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 | 5862 | #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 |
5862 | 5863 | ||
5863 | 5864 | ||
5865 | #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 | ||
5866 | #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 | ||
5867 | #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 | ||
5868 | |||
5864 | #define MDIO_PMA_REG_7101_RESET 0xc000 | 5869 | #define MDIO_PMA_REG_7101_RESET 0xc000 |
5865 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 | 5870 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 |
5866 | #define MDIO_PMA_REG_7101_VER1 0xc026 | 5871 | #define MDIO_PMA_REG_7101_VER1 0xc026 |
@@ -5917,6 +5922,8 @@ Theotherbitsarereservedandshouldbezero*/ | |||
5917 | #define MDIO_AN_REG_CL37_FC_LD 0xffe4 | 5922 | #define MDIO_AN_REG_CL37_FC_LD 0xffe4 |
5918 | #define MDIO_AN_REG_CL37_FC_LP 0xffe5 | 5923 | #define MDIO_AN_REG_CL37_FC_LP 0xffe5 |
5919 | 5924 | ||
5925 | #define MDIO_AN_REG_8073_2_5G 0x8329 | ||
5926 | |||
5920 | 5927 | ||
5921 | #define IGU_FUNC_BASE 0x0400 | 5928 | #define IGU_FUNC_BASE 0x0400 |
5922 | 5929 | ||