bnx2x: Supporting BCM8727 PHY

Adding support for BCM8727 - a dual port SFP+ PHY. That includes verification of
the optic module vendor and part number - the list of approved modules resides
on the nvram and the module is verified by the FW. Since not all users would
like to use this verification feature, it can be disabled. The default behavior
is to issue a warning if the module is not approved, but still allow using it -
but it is also possible to disable the link if the module is not approved.

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 17 insertions, 9 deletions

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 6d77730b6b4d..d771168ec20a 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -5845,25 +5845,33 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_ROM_VER2           0xca1a
 #define MDIO_PMA_REG_EDC_FFE_MAIN       0xca1b
 #define MDIO_PMA_REG_PLL_BANDWIDTH      0xca1d
-#define MDIO_PMA_REG_GEN_CTRL2          0xca1e
+#define MDIO_PMA_REG_PLL_CTRL           0xca1e
 #define MDIO_PMA_REG_MISC_CTRL0         0xca23
 #define MDIO_PMA_REG_LRM_MODE           0xca3f
 #define MDIO_PMA_REG_CDR_BANDWIDTH      0xca46
 #define MDIO_PMA_REG_MISC_CTRL1         0xca85
 
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL         0x8000
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK     0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE          0x0000
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE      0x0004
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS   0x0008
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED        0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT     0x8002
-#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR     0x8003
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL          0x8000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK      0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE           0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE       0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS    0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED         0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT      0x8002
+#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR      0x8003
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF     0xc820
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
 #define MDIO_PMA_REG_8726_TX_CTRL1              0xca01
 #define MDIO_PMA_REG_8726_TX_CTRL2              0xca05
 
+#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR   0x8005
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF     0x8007
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8727_MISC_CTRL             0x8309
+#define MDIO_PMA_REG_8727_TX_CTRL1              0xca02
+#define MDIO_PMA_REG_8727_TX_CTRL2              0xca05
+#define MDIO_PMA_REG_8727_PCS_OPT_CTRL          0xc808
+#define MDIO_PMA_REG_8727_GPIO_CTRL             0xc80e
 
 #define MDIO_PMA_REG_8073_CHIP_REV                      0xc801
 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS             0xc820