bnx2x: Fix CL73 autoneg issues

- Advertise 1G KX4 in CL73 when 1G speed capability is enabled
- Add flow-control negotiation over CL73
- External loopback test on Serdes should be done in FORCE mode, since in
CL73 it is unable to link up with the same core using AUTONEG
- Fix bnx2x_set_led function to support CL73 link leds

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 14 insertions, 4 deletions

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index aa76cbada5e2..b80fde44c85d 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -4772,18 +4772,28 @@
 #define PCI_ID_VAL2                                     0x438
 
 
-#define MDIO_REG_BANK_CL73_IEEEB0                       0x0
-#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL                0x0
+#define MDIO_REG_BANK_CL73_IEEEB0       0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL        0x0
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN     0x0200
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN          0x1000
 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST       0x8000
 
-#define MDIO_REG_BANK_CL73_IEEEB1                       0x10
-#define MDIO_CL73_IEEEB1_AN_ADV2                                0x01
+#define MDIO_REG_BANK_CL73_IEEEB1       0x10
+#define MDIO_CL73_IEEEB1_AN_ADV1                0x00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE                  0x0400
+#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC             0x0800
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH             0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK             0x0C00
+#define MDIO_CL73_IEEEB1_AN_ADV2                0x01
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M             0x0000
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX          0x0020
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4           0x0040
 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR            0x0080
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1             0x03
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE               0x0400
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC          0x0800
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH          0x0C00
+#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK          0x0C00
 
 #define MDIO_REG_BANK_RX0                               0x80b0
 #define MDIO_RX0_RX_STATUS                              0x10