diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 03:36:55 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:31:24 -0500 |
commit | 589abe3a0f594a7707a15674ca9e80370c972832 (patch) | |
tree | a7930047ca7f5340b9053948fcba98128de4d588 /drivers/net/bnx2x_reg.h | |
parent | 4acac6a53a3c9dfc604a9a8647f16b0242080e93 (diff) |
bnx2x: Supporting BCM8726 PHY
Also adding the ability to recognize the optic module and disable it if it is
not authorized for safety reasons - since this feature might upset some users
which are willing to take the risk, it is optional and can be disabled by
setting an nvram bit (or a trivial driver patch to set this bit).
This dual port PHY requires special handling if the ports are swapped.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
-rw-r--r-- | drivers/net/bnx2x_reg.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 6fc1d0df9789..520bf695864e 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -5800,9 +5800,25 @@ Theotherbitsarereservedandshouldbezero*/ | |||
5800 | #define MDIO_PMA_REG_ROM_VER2 0xca1a | 5800 | #define MDIO_PMA_REG_ROM_VER2 0xca1a |
5801 | #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b | 5801 | #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b |
5802 | #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d | 5802 | #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d |
5803 | #define MDIO_PMA_REG_MISC_CTRL0 0xca23 | ||
5804 | #define MDIO_PMA_REG_LRM_MODE 0xca3f | ||
5803 | #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 | 5805 | #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 |
5804 | #define MDIO_PMA_REG_MISC_CTRL1 0xca85 | 5806 | #define MDIO_PMA_REG_MISC_CTRL1 0xca85 |
5805 | 5807 | ||
5808 | #define MDIO_PMA_REG_8726_TWO_WIRE_CTRL 0x8000 | ||
5809 | #define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK 0x000c | ||
5810 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE 0x0000 | ||
5811 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE 0x0004 | ||
5812 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 | ||
5813 | #define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED 0x000c | ||
5814 | #define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT 0x8002 | ||
5815 | #define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR 0x8003 | ||
5816 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 | ||
5817 | #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff | ||
5818 | #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 | ||
5819 | #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 | ||
5820 | |||
5821 | |||
5806 | #define MDIO_PMA_REG_7101_RESET 0xc000 | 5822 | #define MDIO_PMA_REG_7101_RESET 0xc000 |
5807 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 | 5823 | #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 |
5808 | #define MDIO_PMA_REG_7101_VER1 0xc026 | 5824 | #define MDIO_PMA_REG_7101_VER1 0xc026 |
@@ -5832,6 +5848,12 @@ Theotherbitsarereservedandshouldbezero*/ | |||
5832 | #define MDIO_XS_PLL_SEQUENCER 0x8000 | 5848 | #define MDIO_XS_PLL_SEQUENCER 0x8000 |
5833 | #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a | 5849 | #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a |
5834 | 5850 | ||
5851 | #define MDIO_XS_8706_REG_BANK_RX0 0x80bc | ||
5852 | #define MDIO_XS_8706_REG_BANK_RX1 0x80cc | ||
5853 | #define MDIO_XS_8706_REG_BANK_RX2 0x80dc | ||
5854 | #define MDIO_XS_8706_REG_BANK_RX3 0x80ec | ||
5855 | #define MDIO_XS_8706_REG_BANK_RXA 0x80fc | ||
5856 | |||
5835 | #define MDIO_AN_DEVAD 0x7 | 5857 | #define MDIO_AN_DEVAD 0x7 |
5836 | /*ieee*/ | 5858 | /*ieee*/ |
5837 | #define MDIO_AN_REG_CTRL 0x0000 | 5859 | #define MDIO_AN_REG_CTRL 0x0000 |