bnx2x: MSI support

Enabling MSI on top of MSI-X and INTA. Also changing the module parameter to
allow choosing INTA or MSI even when MSI-X is available. The default status
block should not be reversed for endianity. Since MSI can issue
re-configuration, the interrupt disable function now requires mmiowb

Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 20 insertions, 0 deletions

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index fc957fa5c249..0be77c5bcefa 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -745,6 +745,7 @@
 #define DORQ_REG_SHRT_CMHEAD                                     0x170054
 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0                            (0x1<<4)
 #define HC_CONFIG_0_REG_INT_LINE_EN_0                            (0x1<<3)
+#define HC_CONFIG_0_REG_MSI_ATTN_EN_0                            (0x1<<7)
 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0                        (0x1<<2)
 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                          (0x1<<1)
 #define HC_REG_AGG_INT_0                                         0x108050
@@ -5359,9 +5360,28 @@
 #define PCICFG_PM_CSR_STATE                     (0x3<<0)
 #define PCICFG_PM_CSR_PME_ENABLE                (1<<8)
 #define PCICFG_PM_CSR_PME_STATUS                (1<<15)
+#define PCICFG_MSI_CAP_ID                               0x58
+#define PCICFG_MSI_CONTROL_ENABLE               (0x1<<16)
+#define PCICFG_MSI_CONTROL_MCAP                 (0x7<<17)
+#define PCICFG_MSI_CONTROL_MENA                 (0x7<<20)
+#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP      (0x1<<23)
+#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE   (0x1<<24)
 #define PCICFG_GRC_ADDRESS                              0x78
 #define PCICFG_GRC_DATA                                 0x80
+#define PCICFG_MSIX_CAP_ID                              0xa0
+#define PCICFG_MSIX_CONTROL_TABLE_SIZE          (0x7ff<<16)
+#define PCICFG_MSIX_CONTROL_RESERVED            (0x7<<27)
+#define PCICFG_MSIX_CONTROL_FUNC_MASK           (0x1<<30)
+#define PCICFG_MSIX_CONTROL_MSIX_ENABLE         (0x1<<31)
+
 #define PCICFG_DEVICE_CONTROL                           0xb4
+#define PCICFG_DEVICE_STATUS                            0xb6
+#define PCICFG_DEVICE_STATUS_CORR_ERR_DET       (1<<0)
+#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET  (1<<1)
+#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET      (1<<2)
+#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET      (1<<3)
+#define PCICFG_DEVICE_STATUS_AUX_PWR_DET        (1<<4)
+#define PCICFG_DEVICE_STATUS_NO_PEND            (1<<5)
 #define PCICFG_LINK_CONTROL                             0xbc