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authorEilon Greenstein <eilong@broadcom.com>2008-08-13 18:49:35 -0400
committerDavid S. Miller <davem@davemloft.net>2008-08-13 19:01:48 -0400
commit471de716b782fb55ae0fdc040cf2722caffeeb94 (patch)
tree81d7f5086f1f68d919090e0aa81af1fcd20f2bd3 /drivers/net/bnx2x_main.c
parent66e855f3f5197fec1162c5235fdb5f92b956d618 (diff)
bnx2x: FW Internal Memory structure
FW Internal Memory structure The FW uses data structures on the chip internal memory to aggregate the connections when TPA is enabled. The driver was clearing the wrong offsets and therefore one function could cause another function to loose packets. Changing the initialization of the chip internal memory to clear only the relevant memory for each function which is being loaded Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x_main.c100
1 files changed, 51 insertions, 49 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index ac46228cc9d0..6115161334a7 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -2975,37 +2975,6 @@ static inline long bnx2x_hilo(u32 *hiref)
2975 * Init service functions 2975 * Init service functions
2976 */ 2976 */
2977 2977
2978static void bnx2x_storm_stats_init(struct bnx2x *bp)
2979{
2980 int func = BP_FUNC(bp);
2981
2982 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func), 1);
2983 REG_WR(bp, BAR_XSTRORM_INTMEM +
2984 XSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2985
2986 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func), 1);
2987 REG_WR(bp, BAR_TSTRORM_INTMEM +
2988 TSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2989
2990 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func), 0);
2991 REG_WR(bp, BAR_CSTRORM_INTMEM +
2992 CSTORM_STATS_FLAGS_OFFSET(func) + 4, 0);
2993
2994 REG_WR(bp, BAR_XSTRORM_INTMEM +
2995 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
2996 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
2997 REG_WR(bp, BAR_XSTRORM_INTMEM +
2998 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
2999 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3000
3001 REG_WR(bp, BAR_TSTRORM_INTMEM +
3002 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
3003 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
3004 REG_WR(bp, BAR_TSTRORM_INTMEM +
3005 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
3006 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
3007}
3008
3009static void bnx2x_storm_stats_post(struct bnx2x *bp) 2978static void bnx2x_storm_stats_post(struct bnx2x *bp)
3010{ 2979{
3011 if (!bp->stats_pending) { 2980 if (!bp->stats_pending) {
@@ -4632,13 +4601,35 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4632 bnx2x_set_client_config(bp); 4601 bnx2x_set_client_config(bp);
4633} 4602}
4634 4603
4635static void bnx2x_init_internal(struct bnx2x *bp) 4604static void bnx2x_init_internal_common(struct bnx2x *bp)
4605{
4606 int i;
4607
4608 /* Zero this manually as its initialization is
4609 currently missing in the initTool */
4610 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4611 REG_WR(bp, BAR_USTRORM_INTMEM +
4612 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4613}
4614
4615static void bnx2x_init_internal_port(struct bnx2x *bp)
4616{
4617 int port = BP_PORT(bp);
4618
4619 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4620 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4621 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4622 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4623}
4624
4625static void bnx2x_init_internal_func(struct bnx2x *bp)
4636{ 4626{
4637 struct tstorm_eth_function_common_config tstorm_config = {0}; 4627 struct tstorm_eth_function_common_config tstorm_config = {0};
4638 struct stats_indication_flags stats_flags = {0}; 4628 struct stats_indication_flags stats_flags = {0};
4639 int port = BP_PORT(bp); 4629 int port = BP_PORT(bp);
4640 int func = BP_FUNC(bp); 4630 int func = BP_FUNC(bp);
4641 int i; 4631 int i;
4632 u16 max_agg_size;
4642 4633
4643 if (is_multi(bp)) { 4634 if (is_multi(bp)) {
4644 tstorm_config.config_flags = MULTI_FLAGS; 4635 tstorm_config.config_flags = MULTI_FLAGS;
@@ -4651,9 +4642,6 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4651 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func), 4642 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4652 (*(u32 *)&tstorm_config)); 4643 (*(u32 *)&tstorm_config));
4653 4644
4654/* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n",
4655 (*(u32 *)&tstorm_config)); */
4656
4657 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ 4645 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4658 bnx2x_set_storm_rx_mode(bp); 4646 bnx2x_set_storm_rx_mode(bp);
4659 4647
@@ -4716,15 +4704,12 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4716 bp->e1hov); 4704 bp->e1hov);
4717 } 4705 }
4718 4706
4719 /* Zero this manualy as its initialization is 4707 /* Init CQ ring mapping and aggregation size */
4720 currently missing in the initTool */ 4708 max_agg_size = min((u32)(bp->rx_buf_use_size +
4721 for (i = 0; i < USTORM_AGG_DATA_SIZE >> 2; i++) 4709 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4722 REG_WR(bp, BAR_USTRORM_INTMEM + 4710 (u32)0xffff);
4723 USTORM_AGG_DATA_OFFSET + 4*i, 0);
4724
4725 for_each_queue(bp, i) { 4711 for_each_queue(bp, i) {
4726 struct bnx2x_fastpath *fp = &bp->fp[i]; 4712 struct bnx2x_fastpath *fp = &bp->fp[i];
4727 u16 max_agg_size;
4728 4713
4729 REG_WR(bp, BAR_USTRORM_INTMEM + 4714 REG_WR(bp, BAR_USTRORM_INTMEM +
4730 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)), 4715 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
@@ -4733,16 +4718,34 @@ static void bnx2x_init_internal(struct bnx2x *bp)
4733 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4, 4718 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4734 U64_HI(fp->rx_comp_mapping)); 4719 U64_HI(fp->rx_comp_mapping));
4735 4720
4736 max_agg_size = min((u32)(bp->rx_buf_use_size +
4737 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4738 (u32)0xffff);
4739 REG_WR16(bp, BAR_USTRORM_INTMEM + 4721 REG_WR16(bp, BAR_USTRORM_INTMEM +
4740 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)), 4722 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4741 max_agg_size); 4723 max_agg_size);
4742 } 4724 }
4743} 4725}
4744 4726
4745static void bnx2x_nic_init(struct bnx2x *bp) 4727static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4728{
4729 switch (load_code) {
4730 case FW_MSG_CODE_DRV_LOAD_COMMON:
4731 bnx2x_init_internal_common(bp);
4732 /* no break */
4733
4734 case FW_MSG_CODE_DRV_LOAD_PORT:
4735 bnx2x_init_internal_port(bp);
4736 /* no break */
4737
4738 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4739 bnx2x_init_internal_func(bp);
4740 break;
4741
4742 default:
4743 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4744 break;
4745 }
4746}
4747
4748static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4746{ 4749{
4747 int i; 4750 int i;
4748 4751
@@ -4768,8 +4771,7 @@ static void bnx2x_nic_init(struct bnx2x *bp)
4768 bnx2x_init_tx_ring(bp); 4771 bnx2x_init_tx_ring(bp);
4769 bnx2x_init_sp_ring(bp); 4772 bnx2x_init_sp_ring(bp);
4770 bnx2x_init_context(bp); 4773 bnx2x_init_context(bp);
4771 bnx2x_init_internal(bp); 4774 bnx2x_init_internal(bp, load_code);
4772 bnx2x_storm_stats_init(bp);
4773 bnx2x_init_ind_table(bp); 4775 bnx2x_init_ind_table(bp);
4774 bnx2x_int_enable(bp); 4776 bnx2x_int_enable(bp);
4775} 4777}
@@ -6325,7 +6327,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6325 atomic_set(&bp->intr_sem, 0); 6327 atomic_set(&bp->intr_sem, 0);
6326 6328
6327 /* Setup NIC internals and enable interrupts */ 6329 /* Setup NIC internals and enable interrupts */
6328 bnx2x_nic_init(bp); 6330 bnx2x_nic_init(bp, load_code);
6329 6331
6330 /* Send LOAD_DONE command to MCP */ 6332 /* Send LOAD_DONE command to MCP */
6331 if (!BP_NOMCP(bp)) { 6333 if (!BP_NOMCP(bp)) {