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authorEilon Greenstein <eilong@broadcom.com>2009-03-02 02:59:52 -0500
committerDavid S. Miller <davem@davemloft.net>2009-03-03 01:32:41 -0500
commit490c3c9bf986545bdd99dcd4b0045c747564be39 (patch)
tree85da6e9765fc60794208d001d2a9c477decc7b4d /drivers/net/bnx2x_main.c
parent2059aba7e40afb18e578ce57cc48fc3c782a531b (diff)
bnx2x: Using DMA engine
Using DMA engine (DMAE) to initialize large consecutive memories in the chip Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x_main.c51
1 files changed, 12 insertions, 39 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 46e2492fc9d0..3ef24b9eab3e 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -4223,10 +4223,10 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
4223{ 4223{
4224 int port = BP_PORT(bp); 4224 int port = BP_PORT(bp);
4225 4225
4226 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 4226 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4227 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 4227 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4228 sizeof(struct ustorm_status_block)/4); 4228 sizeof(struct ustorm_status_block)/4);
4229 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 4229 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4230 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, 4230 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
4231 sizeof(struct cstorm_status_block)/4); 4231 sizeof(struct cstorm_status_block)/4);
4232} 4232}
@@ -4280,18 +4280,18 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp)
4280{ 4280{
4281 int func = BP_FUNC(bp); 4281 int func = BP_FUNC(bp);
4282 4282
4283 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + 4283 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR +
4284 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4285 sizeof(struct tstorm_def_status_block)/4);
4286 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR +
4284 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4287 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4285 sizeof(struct ustorm_def_status_block)/4); 4288 sizeof(struct ustorm_def_status_block)/4);
4286 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + 4289 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR +
4287 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4290 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4288 sizeof(struct cstorm_def_status_block)/4); 4291 sizeof(struct cstorm_def_status_block)/4);
4289 bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM + 4292 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR +
4290 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, 4293 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4291 sizeof(struct xstorm_def_status_block)/4); 4294 sizeof(struct xstorm_def_status_block)/4);
4292 bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4293 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4294 sizeof(struct tstorm_def_status_block)/4);
4295} 4295}
4296 4296
4297static void bnx2x_init_def_sb(struct bnx2x *bp, 4297static void bnx2x_init_def_sb(struct bnx2x *bp,
@@ -5615,37 +5615,10 @@ static int bnx2x_init_common(struct bnx2x *bp)
5615 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END); 5615 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5616 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END); 5616 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5617 5617
5618 if (CHIP_IS_E1H(bp)) { 5618 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5619 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, 5619 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5620 STORM_INTMEM_SIZE_E1H/2); 5620 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5621 bnx2x_init_fill(bp, 5621 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE(bp));
5622 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5623 0, STORM_INTMEM_SIZE_E1H/2);
5624 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5625 STORM_INTMEM_SIZE_E1H/2);
5626 bnx2x_init_fill(bp,
5627 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5628 0, STORM_INTMEM_SIZE_E1H/2);
5629 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5630 STORM_INTMEM_SIZE_E1H/2);
5631 bnx2x_init_fill(bp,
5632 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5633 0, STORM_INTMEM_SIZE_E1H/2);
5634 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5635 STORM_INTMEM_SIZE_E1H/2);
5636 bnx2x_init_fill(bp,
5637 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5638 0, STORM_INTMEM_SIZE_E1H/2);
5639 } else { /* E1 */
5640 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5641 STORM_INTMEM_SIZE_E1);
5642 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5643 STORM_INTMEM_SIZE_E1);
5644 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5645 STORM_INTMEM_SIZE_E1);
5646 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5647 STORM_INTMEM_SIZE_E1);
5648 }
5649 5622
5650 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END); 5623 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5651 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END); 5624 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);