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authorMichael Chan <mchan@broadcom.com>2009-10-10 09:46:54 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-12 02:30:11 -0400
commite665bfda5b8fea586ddd028b26a6e2ed9e987c6b (patch)
tree799c503f5e2855871e7a7547b07e5e42cabc6d7c /drivers/net/bnx2x_main.c
parent2891290219d8a28a923560d53d24c00fa96fa09f (diff)
bnx2x: Refactor MAC address setup code.
For iSCSI MAC address setup in later patches. Signed-off-by: Shmulik Ravid - Rabinovitz <shmulikr@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Acked-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x_main.c162
1 files changed, 112 insertions, 50 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 713d66939383..02ce3b31050c 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -1026,12 +1026,15 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1026 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): 1026 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
1027 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG): 1027 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
1028 DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); 1028 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
1029 bp->set_mac_pending = 0; 1029 bp->set_mac_pending--;
1030 smp_wmb();
1030 break; 1031 break;
1031 1032
1032 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT): 1033 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
1033 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED): 1034 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DISABLED):
1034 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n"); 1035 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
1036 bp->set_mac_pending--;
1037 smp_wmb();
1035 break; 1038 break;
1036 1039
1037 default: 1040 default:
@@ -2530,7 +2533,7 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
2530} 2533}
2531 2534
2532static void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 2535static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
2533static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set); 2536static void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set);
2534static void bnx2x_set_rx_mode(struct net_device *dev); 2537static void bnx2x_set_rx_mode(struct net_device *dev);
2535 2538
2536static void bnx2x_e1h_disable(struct bnx2x *bp) 2539static void bnx2x_e1h_disable(struct bnx2x *bp)
@@ -2546,7 +2549,7 @@ static void bnx2x_e1h_disable(struct bnx2x *bp)
2546 2549
2547 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 2550 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2548 2551
2549 bnx2x_set_mac_addr_e1h(bp, 0); 2552 bnx2x_set_eth_mac_addr_e1h(bp, 0);
2550 2553
2551 for (i = 0; i < MC_HASH_SIZE; i++) 2554 for (i = 0; i < MC_HASH_SIZE; i++)
2552 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); 2555 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
@@ -2560,7 +2563,7 @@ static void bnx2x_e1h_enable(struct bnx2x *bp)
2560 2563
2561 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1); 2564 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2562 2565
2563 bnx2x_set_mac_addr_e1h(bp, 1); 2566 bnx2x_set_eth_mac_addr_e1h(bp, 1);
2564 2567
2565 /* Tx queue should be only reenabled */ 2568 /* Tx queue should be only reenabled */
2566 netif_tx_wake_all_queues(bp->dev); 2569 netif_tx_wake_all_queues(bp->dev);
@@ -7036,7 +7039,19 @@ static void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
7036 * Init service functions 7039 * Init service functions
7037 */ 7040 */
7038 7041
7039static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set) 7042/**
7043 * Sets a MAC in a CAM for a few L2 Clients for E1 chip
7044 *
7045 * @param bp driver descriptor
7046 * @param set set or clear an entry (1 or 0)
7047 * @param mac pointer to a buffer containing a MAC
7048 * @param cl_bit_vec bit vector of clients to register a MAC for
7049 * @param cam_offset offset in a CAM to use
7050 * @param with_bcast set broadcast MAC as well
7051 */
7052static void bnx2x_set_mac_addr_e1_gen(struct bnx2x *bp, int set, u8 *mac,
7053 u32 cl_bit_vec, u8 cam_offset,
7054 u8 with_bcast)
7040{ 7055{
7041 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config); 7056 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
7042 int port = BP_PORT(bp); 7057 int port = BP_PORT(bp);
@@ -7045,25 +7060,25 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
7045 * unicasts 0-31:port0 32-63:port1 7060 * unicasts 0-31:port0 32-63:port1
7046 * multicast 64-127:port0 128-191:port1 7061 * multicast 64-127:port0 128-191:port1
7047 */ 7062 */
7048 config->hdr.length = 2; 7063 config->hdr.length = 1 + (with_bcast ? 1 : 0);
7049 config->hdr.offset = port ? 32 : 0; 7064 config->hdr.offset = cam_offset;
7050 config->hdr.client_id = bp->fp->cl_id; 7065 config->hdr.client_id = 0xff;
7051 config->hdr.reserved1 = 0; 7066 config->hdr.reserved1 = 0;
7052 7067
7053 /* primary MAC */ 7068 /* primary MAC */
7054 config->config_table[0].cam_entry.msb_mac_addr = 7069 config->config_table[0].cam_entry.msb_mac_addr =
7055 swab16(*(u16 *)&bp->dev->dev_addr[0]); 7070 swab16(*(u16 *)&mac[0]);
7056 config->config_table[0].cam_entry.middle_mac_addr = 7071 config->config_table[0].cam_entry.middle_mac_addr =
7057 swab16(*(u16 *)&bp->dev->dev_addr[2]); 7072 swab16(*(u16 *)&mac[2]);
7058 config->config_table[0].cam_entry.lsb_mac_addr = 7073 config->config_table[0].cam_entry.lsb_mac_addr =
7059 swab16(*(u16 *)&bp->dev->dev_addr[4]); 7074 swab16(*(u16 *)&mac[4]);
7060 config->config_table[0].cam_entry.flags = cpu_to_le16(port); 7075 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
7061 if (set) 7076 if (set)
7062 config->config_table[0].target_table_entry.flags = 0; 7077 config->config_table[0].target_table_entry.flags = 0;
7063 else 7078 else
7064 CAM_INVALIDATE(config->config_table[0]); 7079 CAM_INVALIDATE(config->config_table[0]);
7065 config->config_table[0].target_table_entry.clients_bit_vector = 7080 config->config_table[0].target_table_entry.clients_bit_vector =
7066 cpu_to_le32(1 << BP_L_ID(bp)); 7081 cpu_to_le32(cl_bit_vec);
7067 config->config_table[0].target_table_entry.vlan_id = 0; 7082 config->config_table[0].target_table_entry.vlan_id = 0;
7068 7083
7069 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n", 7084 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
@@ -7073,47 +7088,58 @@ static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
7073 config->config_table[0].cam_entry.lsb_mac_addr); 7088 config->config_table[0].cam_entry.lsb_mac_addr);
7074 7089
7075 /* broadcast */ 7090 /* broadcast */
7076 config->config_table[1].cam_entry.msb_mac_addr = cpu_to_le16(0xffff); 7091 if (with_bcast) {
7077 config->config_table[1].cam_entry.middle_mac_addr = cpu_to_le16(0xffff); 7092 config->config_table[1].cam_entry.msb_mac_addr =
7078 config->config_table[1].cam_entry.lsb_mac_addr = cpu_to_le16(0xffff); 7093 cpu_to_le16(0xffff);
7079 config->config_table[1].cam_entry.flags = cpu_to_le16(port); 7094 config->config_table[1].cam_entry.middle_mac_addr =
7080 if (set) 7095 cpu_to_le16(0xffff);
7081 config->config_table[1].target_table_entry.flags = 7096 config->config_table[1].cam_entry.lsb_mac_addr =
7082 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST; 7097 cpu_to_le16(0xffff);
7083 else 7098 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
7084 CAM_INVALIDATE(config->config_table[1]); 7099 if (set)
7085 config->config_table[1].target_table_entry.clients_bit_vector = 7100 config->config_table[1].target_table_entry.flags =
7086 cpu_to_le32(1 << BP_L_ID(bp)); 7101 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
7087 config->config_table[1].target_table_entry.vlan_id = 0; 7102 else
7103 CAM_INVALIDATE(config->config_table[1]);
7104 config->config_table[1].target_table_entry.clients_bit_vector =
7105 cpu_to_le32(cl_bit_vec);
7106 config->config_table[1].target_table_entry.vlan_id = 0;
7107 }
7088 7108
7089 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 7109 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7090 U64_HI(bnx2x_sp_mapping(bp, mac_config)), 7110 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
7091 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 7111 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
7092} 7112}
7093 7113
7094static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set) 7114/**
7115 * Sets a MAC in a CAM for a few L2 Clients for E1H chip
7116 *
7117 * @param bp driver descriptor
7118 * @param set set or clear an entry (1 or 0)
7119 * @param mac pointer to a buffer containing a MAC
7120 * @param cl_bit_vec bit vector of clients to register a MAC for
7121 * @param cam_offset offset in a CAM to use
7122 */
7123static void bnx2x_set_mac_addr_e1h_gen(struct bnx2x *bp, int set, u8 *mac,
7124 u32 cl_bit_vec, u8 cam_offset)
7095{ 7125{
7096 struct mac_configuration_cmd_e1h *config = 7126 struct mac_configuration_cmd_e1h *config =
7097 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config); 7127 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
7098 7128
7099 /* CAM allocation for E1H
7100 * unicasts: by func number
7101 * multicast: 20+FUNC*20, 20 each
7102 */
7103 config->hdr.length = 1; 7129 config->hdr.length = 1;
7104 config->hdr.offset = BP_FUNC(bp); 7130 config->hdr.offset = cam_offset;
7105 config->hdr.client_id = bp->fp->cl_id; 7131 config->hdr.client_id = 0xff;
7106 config->hdr.reserved1 = 0; 7132 config->hdr.reserved1 = 0;
7107 7133
7108 /* primary MAC */ 7134 /* primary MAC */
7109 config->config_table[0].msb_mac_addr = 7135 config->config_table[0].msb_mac_addr =
7110 swab16(*(u16 *)&bp->dev->dev_addr[0]); 7136 swab16(*(u16 *)&mac[0]);
7111 config->config_table[0].middle_mac_addr = 7137 config->config_table[0].middle_mac_addr =
7112 swab16(*(u16 *)&bp->dev->dev_addr[2]); 7138 swab16(*(u16 *)&mac[2]);
7113 config->config_table[0].lsb_mac_addr = 7139 config->config_table[0].lsb_mac_addr =
7114 swab16(*(u16 *)&bp->dev->dev_addr[4]); 7140 swab16(*(u16 *)&mac[4]);
7115 config->config_table[0].clients_bit_vector = 7141 config->config_table[0].clients_bit_vector =
7116 cpu_to_le32(1 << BP_L_ID(bp)); 7142 cpu_to_le32(cl_bit_vec);
7117 config->config_table[0].vlan_id = 0; 7143 config->config_table[0].vlan_id = 0;
7118 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov); 7144 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
7119 if (set) 7145 if (set)
@@ -7122,11 +7148,11 @@ static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
7122 config->config_table[0].flags = 7148 config->config_table[0].flags =
7123 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE; 7149 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
7124 7150
7125 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n", 7151 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID mask %d\n",
7126 (set ? "setting" : "clearing"), 7152 (set ? "setting" : "clearing"),
7127 config->config_table[0].msb_mac_addr, 7153 config->config_table[0].msb_mac_addr,
7128 config->config_table[0].middle_mac_addr, 7154 config->config_table[0].middle_mac_addr,
7129 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp)); 7155 config->config_table[0].lsb_mac_addr, bp->e1hov, cl_bit_vec);
7130 7156
7131 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 7157 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7132 U64_HI(bnx2x_sp_mapping(bp, mac_config)), 7158 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
@@ -7178,6 +7204,31 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
7178 return -EBUSY; 7204 return -EBUSY;
7179} 7205}
7180 7206
7207static void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set)
7208{
7209 bp->set_mac_pending++;
7210 smp_wmb();
7211
7212 bnx2x_set_mac_addr_e1h_gen(bp, set, bp->dev->dev_addr,
7213 (1 << bp->fp->cl_id), BP_FUNC(bp));
7214
7215 /* Wait for a completion */
7216 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
7217}
7218
7219static void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set)
7220{
7221 bp->set_mac_pending++;
7222 smp_wmb();
7223
7224 bnx2x_set_mac_addr_e1_gen(bp, set, bp->dev->dev_addr,
7225 (1 << bp->fp->cl_id), (BP_PORT(bp) ? 32 : 0),
7226 1);
7227
7228 /* Wait for a completion */
7229 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
7230}
7231
7181static int bnx2x_setup_leading(struct bnx2x *bp) 7232static int bnx2x_setup_leading(struct bnx2x *bp)
7182{ 7233{
7183 int rc; 7234 int rc;
@@ -7452,9 +7503,9 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
7452 } 7503 }
7453 7504
7454 if (CHIP_IS_E1(bp)) 7505 if (CHIP_IS_E1(bp))
7455 bnx2x_set_mac_addr_e1(bp, 1); 7506 bnx2x_set_eth_mac_addr_e1(bp, 1);
7456 else 7507 else
7457 bnx2x_set_mac_addr_e1h(bp, 1); 7508 bnx2x_set_eth_mac_addr_e1h(bp, 1);
7458 } 7509 }
7459 7510
7460 if (bp->port.pmf) 7511 if (bp->port.pmf)
@@ -7717,7 +7768,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
7717 struct mac_configuration_cmd *config = 7768 struct mac_configuration_cmd *config =
7718 bnx2x_sp(bp, mcast_config); 7769 bnx2x_sp(bp, mcast_config);
7719 7770
7720 bnx2x_set_mac_addr_e1(bp, 0); 7771 bnx2x_set_eth_mac_addr_e1(bp, 0);
7721 7772
7722 for (i = 0; i < config->hdr.length; i++) 7773 for (i = 0; i < config->hdr.length; i++)
7723 CAM_INVALIDATE(config->config_table[i]); 7774 CAM_INVALIDATE(config->config_table[i]);
@@ -7730,6 +7781,9 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
7730 config->hdr.client_id = bp->fp->cl_id; 7781 config->hdr.client_id = bp->fp->cl_id;
7731 config->hdr.reserved1 = 0; 7782 config->hdr.reserved1 = 0;
7732 7783
7784 bp->set_mac_pending++;
7785 smp_wmb();
7786
7733 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 7787 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
7734 U64_HI(bnx2x_sp_mapping(bp, mcast_config)), 7788 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
7735 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0); 7789 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
@@ -7737,7 +7791,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
7737 } else { /* E1H */ 7791 } else { /* E1H */
7738 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7792 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7739 7793
7740 bnx2x_set_mac_addr_e1h(bp, 0); 7794 bnx2x_set_eth_mac_addr_e1h(bp, 0);
7741 7795
7742 for (i = 0; i < MC_HASH_SIZE; i++) 7796 for (i = 0; i < MC_HASH_SIZE; i++)
7743 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0); 7797 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
@@ -8520,6 +8574,14 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8520 bp->link_params.req_flow_ctrl, bp->port.advertising); 8574 bp->link_params.req_flow_ctrl, bp->port.advertising);
8521} 8575}
8522 8576
8577static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8578{
8579 mac_hi = cpu_to_be16(mac_hi);
8580 mac_lo = cpu_to_be32(mac_lo);
8581 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8582 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8583}
8584
8523static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp) 8585static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8524{ 8586{
8525 int port = BP_PORT(bp); 8587 int port = BP_PORT(bp);
@@ -8601,12 +8663,7 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8601 8663
8602 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 8664 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8603 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 8665 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8604 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff); 8666 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8605 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
8606 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
8607 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
8608 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
8609 bp->dev->dev_addr[5] = (u8)(val & 0xff);
8610 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 8667 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8611 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN); 8668 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8612} 8669}
@@ -10232,14 +10289,16 @@ static int bnx2x_test_intr(struct bnx2x *bp)
10232 config->hdr.client_id = bp->fp->cl_id; 10289 config->hdr.client_id = bp->fp->cl_id;
10233 config->hdr.reserved1 = 0; 10290 config->hdr.reserved1 = 0;
10234 10291
10292 bp->set_mac_pending++;
10293 smp_wmb();
10235 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 10294 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
10236 U64_HI(bnx2x_sp_mapping(bp, mac_config)), 10295 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
10237 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0); 10296 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
10238 if (rc == 0) { 10297 if (rc == 0) {
10239 bp->set_mac_pending++;
10240 for (i = 0; i < 10; i++) { 10298 for (i = 0; i < 10; i++) {
10241 if (!bp->set_mac_pending) 10299 if (!bp->set_mac_pending)
10242 break; 10300 break;
10301 smp_rmb();
10243 msleep_interruptible(10); 10302 msleep_interruptible(10);
10244 } 10303 }
10245 if (i == 10) 10304 if (i == 10)
@@ -11337,6 +11396,9 @@ static void bnx2x_set_rx_mode(struct net_device *dev)
11337 config->hdr.client_id = bp->fp->cl_id; 11396 config->hdr.client_id = bp->fp->cl_id;
11338 config->hdr.reserved1 = 0; 11397 config->hdr.reserved1 = 0;
11339 11398
11399 bp->set_mac_pending++;
11400 smp_wmb();
11401
11340 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0, 11402 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
11341 U64_HI(bnx2x_sp_mapping(bp, mcast_config)), 11403 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
11342 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 11404 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
@@ -11386,9 +11448,9 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
11386 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 11448 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
11387 if (netif_running(dev)) { 11449 if (netif_running(dev)) {
11388 if (CHIP_IS_E1(bp)) 11450 if (CHIP_IS_E1(bp))
11389 bnx2x_set_mac_addr_e1(bp, 1); 11451 bnx2x_set_eth_mac_addr_e1(bp, 1);
11390 else 11452 else
11391 bnx2x_set_mac_addr_e1h(bp, 1); 11453 bnx2x_set_eth_mac_addr_e1h(bp, 1);
11392 } 11454 }
11393 11455
11394 return 0; 11456 return 0;