aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/bnx2x_main.c
diff options
context:
space:
mode:
authorEilon Greenstein <eilong@broadcom.com>2009-07-21 01:47:33 -0400
committerDavid S. Miller <davem@davemloft.net>2009-07-21 14:18:28 -0400
commit37dbbf32a0d45f0ed88f92cb6d0c35f4809e3a8e (patch)
treeab2deec056ed0117e024d4706f76a09fa53aba78 /drivers/net/bnx2x_main.c
parenteb8da205a6cac953a46a247b8dd19505eba944e2 (diff)
bnx2x: Adding some mmiowb
Signed-off-by: Vlad Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r--drivers/net/bnx2x_main.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index d946c9ea3f29..f20df6d7dcb5 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -652,6 +652,11 @@ static void bnx2x_int_enable(struct bnx2x *bp)
652 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 652 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
653 653
654 REG_WR(bp, addr, val); 654 REG_WR(bp, addr, val);
655 /*
656 * Ensure that HC_CONFIG is written before leading/trailing edge config
657 */
658 mmiowb();
659 barrier();
655 660
656 if (CHIP_IS_E1H(bp)) { 661 if (CHIP_IS_E1H(bp)) {
657 /* init leading/trailing edge */ 662 /* init leading/trailing edge */
@@ -666,6 +671,9 @@ static void bnx2x_int_enable(struct bnx2x *bp)
666 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 671 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
667 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 672 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
668 } 673 }
674
675 /* Make sure that interrupts are indeed enabled from here on */
676 mmiowb();
669} 677}
670 678
671static void bnx2x_int_disable(struct bnx2x *bp) 679static void bnx2x_int_disable(struct bnx2x *bp)
@@ -739,6 +747,10 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
739 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", 747 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
740 (*(u32 *)&igu_ack), hc_addr); 748 (*(u32 *)&igu_ack), hc_addr);
741 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 749 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
750
751 /* Make sure that ACK is written */
752 mmiowb();
753 barrier();
742} 754}
743 755
744static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 756static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
@@ -2429,9 +2441,14 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2429 bp->spq_prod_idx++; 2441 bp->spq_prod_idx++;
2430 } 2442 }
2431 2443
2444 /* Make sure that BD data is updated before writing the producer */
2445 wmb();
2446
2432 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 2447 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2433 bp->spq_prod_idx); 2448 bp->spq_prod_idx);
2434 2449
2450 mmiowb();
2451
2435 spin_unlock_bh(&bp->spq_lock); 2452 spin_unlock_bh(&bp->spq_lock);
2436 return 0; 2453 return 0;
2437} 2454}