diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 03:36:52 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:31:20 -0500 |
commit | 4acac6a53a3c9dfc604a9a8647f16b0242080e93 (patch) | |
tree | d21f2687f4d580f22e0aa018dc9eccaaa56de005 /drivers/net/bnx2x_main.c | |
parent | 87942b467880fb65381af87a5ff61fdb7ede5eb3 (diff) |
bnx2x: GPIO accessories
A GPIO is used with the 8726 PHY. Adding the GPIO related functions in this
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_main.c')
-rw-r--r-- | drivers/net/bnx2x_main.c | 80 |
1 files changed, 78 insertions, 2 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index 9c40b02b65f6..95f8e58e73b4 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
@@ -626,8 +626,8 @@ static void bnx2x_int_enable(struct bnx2x *bp) | |||
626 | if (IS_E1HMF(bp)) { | 626 | if (IS_E1HMF(bp)) { |
627 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | 627 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); |
628 | if (bp->port.pmf) | 628 | if (bp->port.pmf) |
629 | /* enable nig attention */ | 629 | /* enable nig and gpio3 attention */ |
630 | val |= 0x0100; | 630 | val |= 0x1100; |
631 | } else | 631 | } else |
632 | val = 0xffff; | 632 | val = 0xffff; |
633 | 633 | ||
@@ -1836,6 +1836,36 @@ static void bnx2x_release_phy_lock(struct bnx2x *bp) | |||
1836 | mutex_unlock(&bp->port.phy_mutex); | 1836 | mutex_unlock(&bp->port.phy_mutex); |
1837 | } | 1837 | } |
1838 | 1838 | ||
1839 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) | ||
1840 | { | ||
1841 | /* The GPIO should be swapped if swap register is set and active */ | ||
1842 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | ||
1843 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | ||
1844 | int gpio_shift = gpio_num + | ||
1845 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | ||
1846 | u32 gpio_mask = (1 << gpio_shift); | ||
1847 | u32 gpio_reg; | ||
1848 | int value; | ||
1849 | |||
1850 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | ||
1851 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | ||
1852 | return -EINVAL; | ||
1853 | } | ||
1854 | |||
1855 | /* read GPIO value */ | ||
1856 | gpio_reg = REG_RD(bp, MISC_REG_GPIO); | ||
1857 | |||
1858 | /* get the requested pin value */ | ||
1859 | if ((gpio_reg & gpio_mask) == gpio_mask) | ||
1860 | value = 1; | ||
1861 | else | ||
1862 | value = 0; | ||
1863 | |||
1864 | DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value); | ||
1865 | |||
1866 | return value; | ||
1867 | } | ||
1868 | |||
1839 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) | 1869 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) |
1840 | { | 1870 | { |
1841 | /* The GPIO should be swapped if swap register is set and active */ | 1871 | /* The GPIO should be swapped if swap register is set and active */ |
@@ -1889,6 +1919,52 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) | |||
1889 | return 0; | 1919 | return 0; |
1890 | } | 1920 | } |
1891 | 1921 | ||
1922 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) | ||
1923 | { | ||
1924 | /* The GPIO should be swapped if swap register is set and active */ | ||
1925 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | ||
1926 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; | ||
1927 | int gpio_shift = gpio_num + | ||
1928 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | ||
1929 | u32 gpio_mask = (1 << gpio_shift); | ||
1930 | u32 gpio_reg; | ||
1931 | |||
1932 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | ||
1933 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | ||
1934 | return -EINVAL; | ||
1935 | } | ||
1936 | |||
1937 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | ||
1938 | /* read GPIO int */ | ||
1939 | gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); | ||
1940 | |||
1941 | switch (mode) { | ||
1942 | case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: | ||
1943 | DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " | ||
1944 | "output low\n", gpio_num, gpio_shift); | ||
1945 | /* clear SET and set CLR */ | ||
1946 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | ||
1947 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | ||
1948 | break; | ||
1949 | |||
1950 | case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: | ||
1951 | DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " | ||
1952 | "output high\n", gpio_num, gpio_shift); | ||
1953 | /* clear CLR and set SET */ | ||
1954 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); | ||
1955 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); | ||
1956 | break; | ||
1957 | |||
1958 | default: | ||
1959 | break; | ||
1960 | } | ||
1961 | |||
1962 | REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); | ||
1963 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | ||
1964 | |||
1965 | return 0; | ||
1966 | } | ||
1967 | |||
1892 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) | 1968 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) |
1893 | { | 1969 | { |
1894 | u32 spio_mask = (1 << spio_num); | 1970 | u32 spio_mask = (1 << spio_num); |