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authorEilon Greenstein <eilong@broadcom.com>2009-02-12 03:37:09 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-16 02:31:39 -0500
commit3a36f2efbf9ac5da1d08cb44d237ba35ec354888 (patch)
tree587d2c7429130345830c60092afacfad6c3c9cdf /drivers/net/bnx2x_link.c
parentc1b7399027254a45a4036c548c13eb97c7d0d8fa (diff)
bnx2x: Removing CL73 code
This code is disabled, so removing it to avoid confusion Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x_link.c111
1 files changed, 19 insertions, 92 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index 2463de8fe862..526072bb8087 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -29,7 +29,6 @@
29#include "bnx2x.h" 29#include "bnx2x.h"
30 30
31/********************************************************/ 31/********************************************************/
32#define SUPPORT_CL73 0 /* Currently no */
33#define ETH_HLEN 14 32#define ETH_HLEN 14
34#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/ 33#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
35#define ETH_MIN_PACKET_SIZE 60 34#define ETH_MIN_PACKET_SIZE 60
@@ -1208,62 +1207,9 @@ static void bnx2x_set_autoneg(struct link_params *params,
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 1207 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1209 reg_val); 1208 reg_val);
1210 1209
1211 /* Enable Clause 73 Aneg */ 1210 /* CL73 Autoneg Disabled */
1212 if ((vars->line_speed == SPEED_AUTO_NEG) && 1211 reg_val = 0;
1213 (SUPPORT_CL73)) {
1214 /* Enable BAM Station Manager */
1215 1212
1216 CL45_WR_OVER_CL22(bp, params->port,
1217 params->phy_addr,
1218 MDIO_REG_BANK_CL73_USERB0,
1219 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1220 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1221 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1222 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
1223
1224 /* Merge CL73 and CL37 aneg resolution */
1225 CL45_RD_OVER_CL22(bp, params->port,
1226 params->phy_addr,
1227 MDIO_REG_BANK_CL73_USERB0,
1228 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1229 &reg_val);
1230
1231 CL45_WR_OVER_CL22(bp, params->port,
1232 params->phy_addr,
1233 MDIO_REG_BANK_CL73_USERB0,
1234 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1235 (reg_val |
1236 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
1237
1238 /* Set the CL73 AN speed */
1239
1240 CL45_RD_OVER_CL22(bp, params->port,
1241 params->phy_addr,
1242 MDIO_REG_BANK_CL73_IEEEB1,
1243 MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
1244 /* In the SerDes we support only the 1G.
1245 In the XGXS we support the 10G KX4
1246 but we currently do not support the KR */
1247 if (vars->phy_flags & PHY_XGXS_FLAG) {
1248 DP(NETIF_MSG_LINK, "XGXS\n");
1249 /* 10G KX4 */
1250 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1251 } else {
1252 DP(NETIF_MSG_LINK, "SerDes\n");
1253 /* 1000M KX */
1254 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1255 }
1256 CL45_WR_OVER_CL22(bp, params->port,
1257 params->phy_addr,
1258 MDIO_REG_BANK_CL73_IEEEB1,
1259 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
1260
1261 /* CL73 Autoneg Enabled */
1262 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1263 } else {
1264 /* CL73 Autoneg Disabled */
1265 reg_val = 0;
1266 }
1267 CL45_WR_OVER_CL22(bp, params->port, 1213 CL45_WR_OVER_CL22(bp, params->port,
1268 params->phy_addr, 1214 params->phy_addr,
1269 MDIO_REG_BANK_CL73_IEEEB0, 1215 MDIO_REG_BANK_CL73_IEEEB0,
@@ -1396,44 +1342,25 @@ static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1396static void bnx2x_restart_autoneg(struct link_params *params) 1342static void bnx2x_restart_autoneg(struct link_params *params)
1397{ 1343{
1398 struct bnx2x *bp = params->bp; 1344 struct bnx2x *bp = params->bp;
1345 u16 mii_control;
1399 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); 1346 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1400 if (SUPPORT_CL73) { 1347 /* Enable and restart BAM/CL37 aneg */
1401 /* enable and restart clause 73 aneg */
1402 u16 an_ctrl;
1403
1404 CL45_RD_OVER_CL22(bp, params->port,
1405 params->phy_addr,
1406 MDIO_REG_BANK_CL73_IEEEB0,
1407 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1408 &an_ctrl);
1409 CL45_WR_OVER_CL22(bp, params->port,
1410 params->phy_addr,
1411 MDIO_REG_BANK_CL73_IEEEB0,
1412 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1413 (an_ctrl |
1414 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1416 1348
1417 } else { 1349 CL45_RD_OVER_CL22(bp, params->port,
1418 /* Enable and restart BAM/CL37 aneg */ 1350 params->phy_addr,
1419 u16 mii_control; 1351 MDIO_REG_BANK_COMBO_IEEE0,
1420 1352 MDIO_COMBO_IEEE0_MII_CONTROL,
1421 CL45_RD_OVER_CL22(bp, params->port, 1353 &mii_control);
1422 params->phy_addr, 1354 DP(NETIF_MSG_LINK,
1423 MDIO_REG_BANK_COMBO_IEEE0, 1355 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1424 MDIO_COMBO_IEEE0_MII_CONTROL, 1356 mii_control);
1425 &mii_control); 1357 CL45_WR_OVER_CL22(bp, params->port,
1426 DP(NETIF_MSG_LINK, 1358 params->phy_addr,
1427 "bnx2x_restart_autoneg mii_control before = 0x%x\n", 1359 MDIO_REG_BANK_COMBO_IEEE0,
1428 mii_control); 1360 MDIO_COMBO_IEEE0_MII_CONTROL,
1429 CL45_WR_OVER_CL22(bp, params->port, 1361 (mii_control |
1430 params->phy_addr, 1362 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1431 MDIO_REG_BANK_COMBO_IEEE0, 1363 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1432 MDIO_COMBO_IEEE0_MII_CONTROL,
1433 (mii_control |
1434 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1435 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1436 }
1437} 1364}
1438 1365
1439static void bnx2x_initialize_sgmii_process(struct link_params *params, 1366static void bnx2x_initialize_sgmii_process(struct link_params *params,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 19:52:23 -0500