diff options
author | David S. Miller <davem@davemloft.net> | 2008-12-17 02:53:20 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-12-17 02:54:24 -0500 |
commit | c0700f90e5300c63d01c70e157e75e4510dd2981 (patch) | |
tree | f4889b62ab770b943eb5c2bd0778eab3b5118a91 /drivers/net/bnx2x_link.c | |
parent | f6d52432a4bc6da5de2a0bbb350f735db3206aa5 (diff) |
bnx2x: Fix namespace collision with FLOW_CTRL_{TX,RX}
These are now defined in linux/mii.h and the bnx2x driver
defines different values which are shared with hardware
data structures.
So add a "BNX2X_" prefix to these macro names.
Based upon a report from Stephen Rothwell.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r-- | drivers/net/bnx2x_link.c | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index 4ce7fe9c5251..67de94f1f30e 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c | |||
@@ -289,7 +289,7 @@ static u8 bnx2x_emac_enable(struct link_params *params, | |||
289 | /* pause enable/disable */ | 289 | /* pause enable/disable */ |
290 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | 290 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
291 | EMAC_RX_MODE_FLOW_EN); | 291 | EMAC_RX_MODE_FLOW_EN); |
292 | if (vars->flow_ctrl & FLOW_CTRL_RX) | 292 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
293 | bnx2x_bits_en(bp, emac_base + | 293 | bnx2x_bits_en(bp, emac_base + |
294 | EMAC_REG_EMAC_RX_MODE, | 294 | EMAC_REG_EMAC_RX_MODE, |
295 | EMAC_RX_MODE_FLOW_EN); | 295 | EMAC_RX_MODE_FLOW_EN); |
@@ -297,7 +297,7 @@ static u8 bnx2x_emac_enable(struct link_params *params, | |||
297 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | 297 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
298 | (EMAC_TX_MODE_EXT_PAUSE_EN | | 298 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
299 | EMAC_TX_MODE_FLOW_EN)); | 299 | EMAC_TX_MODE_FLOW_EN)); |
300 | if (vars->flow_ctrl & FLOW_CTRL_TX) | 300 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
301 | bnx2x_bits_en(bp, emac_base + | 301 | bnx2x_bits_en(bp, emac_base + |
302 | EMAC_REG_EMAC_TX_MODE, | 302 | EMAC_REG_EMAC_TX_MODE, |
303 | (EMAC_TX_MODE_EXT_PAUSE_EN | | 303 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
@@ -333,7 +333,7 @@ static u8 bnx2x_emac_enable(struct link_params *params, | |||
333 | /* enable the NIG in/out to the emac */ | 333 | /* enable the NIG in/out to the emac */ |
334 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); | 334 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); |
335 | val = 0; | 335 | val = 0; |
336 | if (vars->flow_ctrl & FLOW_CTRL_TX) | 336 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
337 | val = 1; | 337 | val = 1; |
338 | 338 | ||
339 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | 339 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); |
@@ -396,7 +396,7 @@ static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars, | |||
396 | 396 | ||
397 | /* tx control */ | 397 | /* tx control */ |
398 | val = 0xc0; | 398 | val = 0xc0; |
399 | if (vars->flow_ctrl & FLOW_CTRL_TX) | 399 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
400 | val |= 0x800000; | 400 | val |= 0x800000; |
401 | wb_data[0] = val; | 401 | wb_data[0] = val; |
402 | wb_data[1] = 0; | 402 | wb_data[1] = 0; |
@@ -423,7 +423,7 @@ static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars, | |||
423 | 423 | ||
424 | /* rx control set to don't strip crc */ | 424 | /* rx control set to don't strip crc */ |
425 | val = 0x14; | 425 | val = 0x14; |
426 | if (vars->flow_ctrl & FLOW_CTRL_RX) | 426 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
427 | val |= 0x20; | 427 | val |= 0x20; |
428 | wb_data[0] = val; | 428 | wb_data[0] = val; |
429 | wb_data[1] = 0; | 429 | wb_data[1] = 0; |
@@ -460,7 +460,7 @@ static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars, | |||
460 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | 460 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); |
461 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | 461 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); |
462 | val = 0; | 462 | val = 0; |
463 | if (vars->flow_ctrl & FLOW_CTRL_TX) | 463 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
464 | val = 1; | 464 | val = 1; |
465 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | 465 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); |
466 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | 466 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); |
@@ -580,14 +580,14 @@ void bnx2x_link_status_update(struct link_params *params, | |||
580 | } | 580 | } |
581 | 581 | ||
582 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | 582 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) |
583 | vars->flow_ctrl |= FLOW_CTRL_TX; | 583 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; |
584 | else | 584 | else |
585 | vars->flow_ctrl &= ~FLOW_CTRL_TX; | 585 | vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX; |
586 | 586 | ||
587 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | 587 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) |
588 | vars->flow_ctrl |= FLOW_CTRL_RX; | 588 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; |
589 | else | 589 | else |
590 | vars->flow_ctrl &= ~FLOW_CTRL_RX; | 590 | vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX; |
591 | 591 | ||
592 | if (vars->phy_flags & PHY_XGXS_FLAG) { | 592 | if (vars->phy_flags & PHY_XGXS_FLAG) { |
593 | if (vars->line_speed && | 593 | if (vars->line_speed && |
@@ -618,7 +618,7 @@ void bnx2x_link_status_update(struct link_params *params, | |||
618 | 618 | ||
619 | vars->line_speed = 0; | 619 | vars->line_speed = 0; |
620 | vars->duplex = DUPLEX_FULL; | 620 | vars->duplex = DUPLEX_FULL; |
621 | vars->flow_ctrl = FLOW_CTRL_NONE; | 621 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
622 | 622 | ||
623 | /* indicate no mac active */ | 623 | /* indicate no mac active */ |
624 | vars->mac_type = MAC_TYPE_NONE; | 624 | vars->mac_type = MAC_TYPE_NONE; |
@@ -691,7 +691,7 @@ static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, | |||
691 | return -EINVAL; | 691 | return -EINVAL; |
692 | } | 692 | } |
693 | 693 | ||
694 | if (flow_ctrl & FLOW_CTRL_RX || | 694 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
695 | line_speed == SPEED_10 || | 695 | line_speed == SPEED_10 || |
696 | line_speed == SPEED_100 || | 696 | line_speed == SPEED_100 || |
697 | line_speed == SPEED_1000 || | 697 | line_speed == SPEED_1000 || |
@@ -1300,8 +1300,8 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc) | |||
1300 | * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ | 1300 | * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ |
1301 | 1301 | ||
1302 | switch (params->req_flow_ctrl) { | 1302 | switch (params->req_flow_ctrl) { |
1303 | case FLOW_CTRL_AUTO: | 1303 | case BNX2X_FLOW_CTRL_AUTO: |
1304 | if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) { | 1304 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { |
1305 | *ieee_fc |= | 1305 | *ieee_fc |= |
1306 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | 1306 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
1307 | } else { | 1307 | } else { |
@@ -1309,17 +1309,17 @@ static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc) | |||
1309 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | 1309 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
1310 | } | 1310 | } |
1311 | break; | 1311 | break; |
1312 | case FLOW_CTRL_TX: | 1312 | case BNX2X_FLOW_CTRL_TX: |
1313 | *ieee_fc |= | 1313 | *ieee_fc |= |
1314 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | 1314 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
1315 | break; | 1315 | break; |
1316 | 1316 | ||
1317 | case FLOW_CTRL_RX: | 1317 | case BNX2X_FLOW_CTRL_RX: |
1318 | case FLOW_CTRL_BOTH: | 1318 | case BNX2X_FLOW_CTRL_BOTH: |
1319 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | 1319 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
1320 | break; | 1320 | break; |
1321 | 1321 | ||
1322 | case FLOW_CTRL_NONE: | 1322 | case BNX2X_FLOW_CTRL_NONE: |
1323 | default: | 1323 | default: |
1324 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | 1324 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; |
1325 | break; | 1325 | break; |
@@ -1463,18 +1463,18 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |||
1463 | { /* LD LP */ | 1463 | { /* LD LP */ |
1464 | switch (pause_result) { /* ASYM P ASYM P */ | 1464 | switch (pause_result) { /* ASYM P ASYM P */ |
1465 | case 0xb: /* 1 0 1 1 */ | 1465 | case 0xb: /* 1 0 1 1 */ |
1466 | vars->flow_ctrl = FLOW_CTRL_TX; | 1466 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; |
1467 | break; | 1467 | break; |
1468 | 1468 | ||
1469 | case 0xe: /* 1 1 1 0 */ | 1469 | case 0xe: /* 1 1 1 0 */ |
1470 | vars->flow_ctrl = FLOW_CTRL_RX; | 1470 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; |
1471 | break; | 1471 | break; |
1472 | 1472 | ||
1473 | case 0x5: /* 0 1 0 1 */ | 1473 | case 0x5: /* 0 1 0 1 */ |
1474 | case 0x7: /* 0 1 1 1 */ | 1474 | case 0x7: /* 0 1 1 1 */ |
1475 | case 0xd: /* 1 1 0 1 */ | 1475 | case 0xd: /* 1 1 0 1 */ |
1476 | case 0xf: /* 1 1 1 1 */ | 1476 | case 0xf: /* 1 1 1 1 */ |
1477 | vars->flow_ctrl = FLOW_CTRL_BOTH; | 1477 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; |
1478 | break; | 1478 | break; |
1479 | 1479 | ||
1480 | default: | 1480 | default: |
@@ -1531,7 +1531,7 @@ static u8 bnx2x_ext_phy_resove_fc(struct link_params *params, | |||
1531 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", | 1531 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", |
1532 | pause_result); | 1532 | pause_result); |
1533 | bnx2x_pause_resolve(vars, pause_result); | 1533 | bnx2x_pause_resolve(vars, pause_result); |
1534 | if (vars->flow_ctrl == FLOW_CTRL_NONE && | 1534 | if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE && |
1535 | ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { | 1535 | ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) { |
1536 | bnx2x_cl45_read(bp, port, | 1536 | bnx2x_cl45_read(bp, port, |
1537 | ext_phy_type, | 1537 | ext_phy_type, |
@@ -1567,10 +1567,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params, | |||
1567 | u16 lp_pause; /* link partner */ | 1567 | u16 lp_pause; /* link partner */ |
1568 | u16 pause_result; | 1568 | u16 pause_result; |
1569 | 1569 | ||
1570 | vars->flow_ctrl = FLOW_CTRL_NONE; | 1570 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
1571 | 1571 | ||
1572 | /* resolve from gp_status in case of AN complete and not sgmii */ | 1572 | /* resolve from gp_status in case of AN complete and not sgmii */ |
1573 | if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) && | 1573 | if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && |
1574 | (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | 1574 | (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && |
1575 | (!(vars->phy_flags & PHY_SGMII_FLAG)) && | 1575 | (!(vars->phy_flags & PHY_SGMII_FLAG)) && |
1576 | (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == | 1576 | (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == |
@@ -1591,11 +1591,11 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params, | |||
1591 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | 1591 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; |
1592 | DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); | 1592 | DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); |
1593 | bnx2x_pause_resolve(vars, pause_result); | 1593 | bnx2x_pause_resolve(vars, pause_result); |
1594 | } else if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) && | 1594 | } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) && |
1595 | (bnx2x_ext_phy_resove_fc(params, vars))) { | 1595 | (bnx2x_ext_phy_resove_fc(params, vars))) { |
1596 | return; | 1596 | return; |
1597 | } else { | 1597 | } else { |
1598 | if (params->req_flow_ctrl == FLOW_CTRL_AUTO) | 1598 | if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) |
1599 | vars->flow_ctrl = params->req_fc_auto_adv; | 1599 | vars->flow_ctrl = params->req_fc_auto_adv; |
1600 | else | 1600 | else |
1601 | vars->flow_ctrl = params->req_flow_ctrl; | 1601 | vars->flow_ctrl = params->req_flow_ctrl; |
@@ -1728,11 +1728,11 @@ static u8 bnx2x_link_settings_status(struct link_params *params, | |||
1728 | LINK_STATUS_PARALLEL_DETECTION_USED; | 1728 | LINK_STATUS_PARALLEL_DETECTION_USED; |
1729 | 1729 | ||
1730 | } | 1730 | } |
1731 | if (vars->flow_ctrl & FLOW_CTRL_TX) | 1731 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
1732 | vars->link_status |= | 1732 | vars->link_status |= |
1733 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | 1733 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; |
1734 | 1734 | ||
1735 | if (vars->flow_ctrl & FLOW_CTRL_RX) | 1735 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
1736 | vars->link_status |= | 1736 | vars->link_status |= |
1737 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | 1737 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; |
1738 | 1738 | ||
@@ -1742,7 +1742,7 @@ static u8 bnx2x_link_settings_status(struct link_params *params, | |||
1742 | vars->phy_link_up = 0; | 1742 | vars->phy_link_up = 0; |
1743 | 1743 | ||
1744 | vars->duplex = DUPLEX_FULL; | 1744 | vars->duplex = DUPLEX_FULL; |
1745 | vars->flow_ctrl = FLOW_CTRL_NONE; | 1745 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
1746 | vars->autoneg = AUTO_NEG_DISABLED; | 1746 | vars->autoneg = AUTO_NEG_DISABLED; |
1747 | vars->mac_type = MAC_TYPE_NONE; | 1747 | vars->mac_type = MAC_TYPE_NONE; |
1748 | } | 1748 | } |
@@ -3924,7 +3924,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
3924 | vars->link_up = 0; | 3924 | vars->link_up = 0; |
3925 | vars->line_speed = 0; | 3925 | vars->line_speed = 0; |
3926 | vars->duplex = DUPLEX_FULL; | 3926 | vars->duplex = DUPLEX_FULL; |
3927 | vars->flow_ctrl = FLOW_CTRL_NONE; | 3927 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
3928 | vars->mac_type = MAC_TYPE_NONE; | 3928 | vars->mac_type = MAC_TYPE_NONE; |
3929 | 3929 | ||
3930 | if (params->switch_cfg == SWITCH_CFG_1G) | 3930 | if (params->switch_cfg == SWITCH_CFG_1G) |
@@ -3946,12 +3946,12 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
3946 | vars->link_up = 1; | 3946 | vars->link_up = 1; |
3947 | vars->line_speed = SPEED_10000; | 3947 | vars->line_speed = SPEED_10000; |
3948 | vars->duplex = DUPLEX_FULL; | 3948 | vars->duplex = DUPLEX_FULL; |
3949 | vars->flow_ctrl = FLOW_CTRL_NONE; | 3949 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
3950 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | 3950 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); |
3951 | /* enable on E1.5 FPGA */ | 3951 | /* enable on E1.5 FPGA */ |
3952 | if (CHIP_IS_E1H(bp)) { | 3952 | if (CHIP_IS_E1H(bp)) { |
3953 | vars->flow_ctrl |= | 3953 | vars->flow_ctrl |= |
3954 | (FLOW_CTRL_TX | FLOW_CTRL_RX); | 3954 | (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX); |
3955 | vars->link_status |= | 3955 | vars->link_status |= |
3956 | (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | | 3956 | (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | |
3957 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED); | 3957 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED); |
@@ -3974,7 +3974,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
3974 | vars->link_up = 1; | 3974 | vars->link_up = 1; |
3975 | vars->line_speed = SPEED_10000; | 3975 | vars->line_speed = SPEED_10000; |
3976 | vars->duplex = DUPLEX_FULL; | 3976 | vars->duplex = DUPLEX_FULL; |
3977 | vars->flow_ctrl = FLOW_CTRL_NONE; | 3977 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
3978 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | 3978 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); |
3979 | 3979 | ||
3980 | bnx2x_bmac_enable(params, vars, 0); | 3980 | bnx2x_bmac_enable(params, vars, 0); |
@@ -3994,7 +3994,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
3994 | vars->link_up = 1; | 3994 | vars->link_up = 1; |
3995 | vars->line_speed = SPEED_10000; | 3995 | vars->line_speed = SPEED_10000; |
3996 | vars->duplex = DUPLEX_FULL; | 3996 | vars->duplex = DUPLEX_FULL; |
3997 | vars->flow_ctrl = FLOW_CTRL_NONE; | 3997 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
3998 | vars->mac_type = MAC_TYPE_BMAC; | 3998 | vars->mac_type = MAC_TYPE_BMAC; |
3999 | 3999 | ||
4000 | vars->phy_flags = PHY_XGXS_FLAG; | 4000 | vars->phy_flags = PHY_XGXS_FLAG; |
@@ -4009,7 +4009,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
4009 | vars->link_up = 1; | 4009 | vars->link_up = 1; |
4010 | vars->line_speed = SPEED_1000; | 4010 | vars->line_speed = SPEED_1000; |
4011 | vars->duplex = DUPLEX_FULL; | 4011 | vars->duplex = DUPLEX_FULL; |
4012 | vars->flow_ctrl = FLOW_CTRL_NONE; | 4012 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
4013 | vars->mac_type = MAC_TYPE_EMAC; | 4013 | vars->mac_type = MAC_TYPE_EMAC; |
4014 | 4014 | ||
4015 | vars->phy_flags = PHY_XGXS_FLAG; | 4015 | vars->phy_flags = PHY_XGXS_FLAG; |
@@ -4026,7 +4026,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |||
4026 | vars->link_up = 1; | 4026 | vars->link_up = 1; |
4027 | vars->line_speed = SPEED_10000; | 4027 | vars->line_speed = SPEED_10000; |
4028 | vars->duplex = DUPLEX_FULL; | 4028 | vars->duplex = DUPLEX_FULL; |
4029 | vars->flow_ctrl = FLOW_CTRL_NONE; | 4029 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
4030 | 4030 | ||
4031 | vars->phy_flags = PHY_XGXS_FLAG; | 4031 | vars->phy_flags = PHY_XGXS_FLAG; |
4032 | 4032 | ||