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authorEilon Greenstein <eilong@broadcom.com>2009-02-12 03:37:07 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-16 02:31:36 -0500
commitc1b7399027254a45a4036c548c13eb97c7d0d8fa (patch)
treee4c6b5d2b9964174e003dcc51795ea519b8efb18 /drivers/net/bnx2x_link.c
parent811a2f2d3be9a39bd4e0930501fda8630857748d (diff)
bnx2x: Using the HW 5th lane
This 1G interface (on top of the 4 lanes 10G interface) requires additional setting to work in CL45 Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_link.c')
-rw-r--r--drivers/net/bnx2x_link.c35
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index f4c699ecfb41..2463de8fe862 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -174,13 +174,34 @@
174 (_bank + (_addr & 0xf)), \ 174 (_bank + (_addr & 0xf)), \
175 _val) 175 _val)
176 176
177static void bnx2x_set_phy_mdio(struct link_params *params) 177static void bnx2x_set_serdes_access(struct link_params *params)
178{ 178{
179 struct bnx2x *bp = params->bp; 179 struct bnx2x *bp = params->bp;
180 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + 180 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
181 params->port*0x18, 0); 181 /* Set Clause 22 */
182 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 182 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
183 DEFAULT_PHY_DEV_ADDR); 183 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
184 udelay(500);
185 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
186 udelay(500);
187 /* Set Clause 45 */
188 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
189}
190static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
191{
192 struct bnx2x *bp = params->bp;
193 if (phy_flags & PHY_XGXS_FLAG) {
194 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
195 params->port*0x18, 0);
196 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
197 DEFAULT_PHY_DEV_ADDR);
198 } else {
199 bnx2x_set_serdes_access(params);
200
201 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
202 params->port*0x10,
203 DEFAULT_PHY_DEV_ADDR);
204 }
184} 205}
185 206
186static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) 207static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
@@ -520,7 +541,7 @@ static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
520 udelay(500); 541 udelay(500);
521 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, 542 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
522 val); 543 val);
523 bnx2x_set_phy_mdio(params); 544 bnx2x_set_phy_mdio(params, phy_flags);
524} 545}
525 546
526void bnx2x_link_status_update(struct link_params *params, 547void bnx2x_link_status_update(struct link_params *params,
@@ -996,6 +1017,8 @@ static u8 bnx2x_reset_unicore(struct link_params *params)
996 (mii_control | 1017 (mii_control |
997 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 1018 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
998 1019
1020 bnx2x_set_serdes_access(params);
1021
999 /* wait for the reset to self clear */ 1022 /* wait for the reset to self clear */
1000 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { 1023 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1001 udelay(5); 1024 udelay(5);