diff options
| author | Eilon Greenstein <eilong@broadcom.com> | 2009-02-12 03:38:01 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:31:48 -0500 |
| commit | 26e029752c8f8671b1de83fe86906fc29f9eda92 (patch) | |
| tree | 8da95cc8436301235013ab52334a99ae11c13acc /drivers/net/bnx2x_init.h | |
| parent | cfb18c5cb7ef5506a2864f9ec360cbb2ca6e8d28 (diff) | |
bnx2x: Optimize chip MPS configuration
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_init.h')
| -rw-r--r-- | drivers/net/bnx2x_init.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 021438f81341..6fcd1dc51d97 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h | |||
| @@ -655,17 +655,18 @@ static void bnx2x_init_pxp(struct bnx2x *bp) | |||
| 655 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); | 655 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); |
| 656 | 656 | ||
| 657 | if (CHIP_IS_E1H(bp)) { | 657 | if (CHIP_IS_E1H(bp)) { |
| 658 | REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1); | 658 | val = ((w_order == 0) ? 2 : 3); |
| 659 | REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1); | 659 | REG_WR(bp, PXP2_REG_WR_HC_MPS, val); |
| 660 | REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1); | 660 | REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); |
| 661 | REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1); | 661 | REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); |
| 662 | REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1); | 662 | REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); |
| 663 | REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1); | 663 | REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); |
| 664 | REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1); | 664 | REG_WR(bp, PXP2_REG_WR_QM_MPS, val); |
| 665 | REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1); | 665 | REG_WR(bp, PXP2_REG_WR_TM_MPS, val); |
| 666 | REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1); | 666 | REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); |
| 667 | REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); | ||
| 667 | REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ | 668 | REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ |
| 668 | REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1); | 669 | REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); |
| 669 | } | 670 | } |
| 670 | } | 671 | } |
| 671 | 672 | ||